1; RUN: llc -march=hexagon -enable-pipeliner < %s
2; REQUIRES: asserts
3
4; This test caused an assert because there was a use of an instruction
5; that was scheduled at stage 0, but no phi were added in the epilog.
6
7%s.0 = type <{ i8*, i8*, i16, i8, i8, i8 }>
8%s.1 = type { [4 x i16], [4 x i16], [4 x i16], [4 x i16], i32, i32, i32, i8, [10 x i32], [10 x [3 x i32]], [4 x i64], i8 }
9%s.2 = type { [3 x i16], [4 x i8], i32, [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [6 x %s.3], [6 x %s.3], [6 x %s.3], i8, [3 x [3 x i16]], [3 x [3 x i16]], [3 x i16], [3 x i16], [6 x i16], [2 x i32], [10 x i32], [2 x i32], [2 x i32], [2 x [3 x i32]], [2 x i32], [2 x [3 x i64]], [2 x [3 x [3 x i32]]], [2 x [3 x i32]] }
10%s.3 = type { i8, i8, i8, i8 }
11
12@g0 = external constant %s.0, align 1
13
14define void @f0(i8 zeroext %a0, i32 %a1, i32 %a2, i8 zeroext %a3, %s.1* nocapture %a4, %s.2* %a5, i8 zeroext %a6) #0 {
15b0:
16  br i1 undef, label %b1, label %b7
17
18b1:                                               ; preds = %b0
19  br i1 undef, label %b2, label %b3
20
21b2:                                               ; preds = %b1
22  unreachable
23
24b3:                                               ; preds = %b1
25  %v0 = select i1 undef, i32 2, i32 4
26  %v1 = load i8, i8* undef, align 1
27  %v2 = zext i8 %v1 to i32
28  %v3 = icmp uge i32 %v2, %v0
29  br label %b4
30
31b4:                                               ; preds = %b4, %b3
32  br i1 undef, label %b4, label %b8
33
34b5:                                               ; preds = %b10
35  unreachable
36
37b6:                                               ; preds = %b10
38  call void @f1(%s.0* @g0, i32 undef, i32 %v21, i32 undef, i32 undef)
39  unreachable
40
41b7:                                               ; preds = %b0
42  ret void
43
44b8:                                               ; preds = %b8, %b4
45  %v4 = phi i32 [ %v11, %b8 ], [ undef, %b4 ]
46  %v5 = phi i32 [ %v12, %b8 ], [ 0, %b4 ]
47  %v6 = xor i1 false, %v3
48  %v7 = zext i1 %v6 to i32
49  %v8 = shl nuw nsw i32 %v7, 1
50  %v9 = shl i32 %v4, 2
51  %v10 = or i32 0, %v9
52  %v11 = or i32 %v10, %v8
53  %v12 = add i32 %v5, 1
54  %v13 = icmp ult i32 %v12, %v0
55  br i1 %v13, label %b8, label %b9
56
57b9:                                               ; preds = %b9, %b8
58  %v14 = phi i32 [ %v21, %b9 ], [ %v11, %b8 ]
59  %v15 = icmp ne i32 undef, 1
60  %v16 = xor i1 %v15, %v3
61  %v17 = zext i1 %v16 to i32
62  %v18 = shl nuw nsw i32 %v17, 1
63  %v19 = shl i32 %v14, 2
64  %v20 = or i32 0, %v19
65  %v21 = or i32 %v20, %v18
66  br i1 undef, label %b9, label %b10
67
68b10:                                              ; preds = %b9
69  br i1 undef, label %b6, label %b5
70}
71
72declare void @f1(%s.0*, i32, i32, i32, i32)
73
74attributes #0 = { nounwind "target-cpu"="hexagonv55" }
75