1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4
5define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
6; CHECK-LABEL: build_var0_v4i1:
7; CHECK:       @ %bb.0: @ %entry
8; CHECK-NEXT:    cmp r0, r1
9; CHECK-NEXT:    mov.w r1, #0
10; CHECK-NEXT:    csetm r0, lo
11; CHECK-NEXT:    bfi r1, r0, #0, #4
12; CHECK-NEXT:    vmsr p0, r1
13; CHECK-NEXT:    vpsel q0, q0, q1
14; CHECK-NEXT:    bx lr
15entry:
16  %c = icmp ult i32 %s, %t
17  %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 0
18  %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b
19  ret <4 x i32> %r
20}
21
22define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
23; CHECK-LABEL: build_var3_v4i1:
24; CHECK:       @ %bb.0: @ %entry
25; CHECK-NEXT:    cmp r0, r1
26; CHECK-NEXT:    mov.w r1, #0
27; CHECK-NEXT:    csetm r0, lo
28; CHECK-NEXT:    bfi r1, r0, #12, #4
29; CHECK-NEXT:    vmsr p0, r1
30; CHECK-NEXT:    vpsel q0, q0, q1
31; CHECK-NEXT:    bx lr
32entry:
33  %c = icmp ult i32 %s, %t
34  %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 3
35  %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b
36  ret <4 x i32> %r
37}
38
39define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
40; CHECK-LABEL: build_varN_v4i1:
41; CHECK:       @ %bb.0: @ %entry
42; CHECK-NEXT:    cmp r0, r1
43; CHECK-NEXT:    csetm r0, lo
44; CHECK-NEXT:    vmsr p0, r0
45; CHECK-NEXT:    vpsel q0, q0, q1
46; CHECK-NEXT:    bx lr
47entry:
48  %c = icmp ult i32 %s, %t
49  %vc1 = insertelement <4 x i1> undef, i1 %c, i64 0
50  %vc4 = shufflevector <4 x i1> %vc1, <4 x i1> undef, <4 x i32> zeroinitializer
51  %r = select <4 x i1> %vc4, <4 x i32> %a, <4 x i32> %b
52  ret <4 x i32> %r
53}
54
55
56define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
57; CHECK-LABEL: build_var0_v8i1:
58; CHECK:       @ %bb.0: @ %entry
59; CHECK-NEXT:    cmp r0, r1
60; CHECK-NEXT:    mov.w r1, #0
61; CHECK-NEXT:    csetm r0, lo
62; CHECK-NEXT:    bfi r1, r0, #0, #2
63; CHECK-NEXT:    vmsr p0, r1
64; CHECK-NEXT:    vpsel q0, q0, q1
65; CHECK-NEXT:    bx lr
66entry:
67  %c = icmp ult i32 %s, %t
68  %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 0
69  %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b
70  ret <8 x i16> %r
71}
72
73define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
74; CHECK-LABEL: build_var3_v8i1:
75; CHECK:       @ %bb.0: @ %entry
76; CHECK-NEXT:    cmp r0, r1
77; CHECK-NEXT:    mov.w r1, #0
78; CHECK-NEXT:    csetm r0, lo
79; CHECK-NEXT:    bfi r1, r0, #6, #2
80; CHECK-NEXT:    vmsr p0, r1
81; CHECK-NEXT:    vpsel q0, q0, q1
82; CHECK-NEXT:    bx lr
83entry:
84  %c = icmp ult i32 %s, %t
85  %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 3
86  %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b
87  ret <8 x i16> %r
88}
89
90define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
91; CHECK-LABEL: build_varN_v8i1:
92; CHECK:       @ %bb.0: @ %entry
93; CHECK-NEXT:    cmp r0, r1
94; CHECK-NEXT:    csetm r0, lo
95; CHECK-NEXT:    vmsr p0, r0
96; CHECK-NEXT:    vpsel q0, q0, q1
97; CHECK-NEXT:    bx lr
98entry:
99  %c = icmp ult i32 %s, %t
100  %vc1 = insertelement <8 x i1> undef, i1 %c, i64 0
101  %vc4 = shufflevector <8 x i1> %vc1, <8 x i1> undef, <8 x i32> zeroinitializer
102  %r = select <8 x i1> %vc4, <8 x i16> %a, <8 x i16> %b
103  ret <8 x i16> %r
104}
105
106
107define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
108; CHECK-LABEL: build_var0_v16i1:
109; CHECK:       @ %bb.0: @ %entry
110; CHECK-NEXT:    cmp r0, r1
111; CHECK-NEXT:    mov.w r1, #0
112; CHECK-NEXT:    csetm r0, lo
113; CHECK-NEXT:    bfi r1, r0, #0, #1
114; CHECK-NEXT:    vmsr p0, r1
115; CHECK-NEXT:    vpsel q0, q0, q1
116; CHECK-NEXT:    bx lr
117entry:
118  %c = icmp ult i32 %s, %t
119  %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 0
120  %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b
121  ret <16 x i8> %r
122}
123
124define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
125; CHECK-LABEL: build_var3_v16i1:
126; CHECK:       @ %bb.0: @ %entry
127; CHECK-NEXT:    cmp r0, r1
128; CHECK-NEXT:    mov.w r1, #0
129; CHECK-NEXT:    csetm r0, lo
130; CHECK-NEXT:    bfi r1, r0, #3, #1
131; CHECK-NEXT:    vmsr p0, r1
132; CHECK-NEXT:    vpsel q0, q0, q1
133; CHECK-NEXT:    bx lr
134entry:
135  %c = icmp ult i32 %s, %t
136  %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 3
137  %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b
138  ret <16 x i8> %r
139}
140
141define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
142; CHECK-LABEL: build_varN_v16i1:
143; CHECK:       @ %bb.0: @ %entry
144; CHECK-NEXT:    cmp r0, r1
145; CHECK-NEXT:    csetm r0, lo
146; CHECK-NEXT:    vmsr p0, r0
147; CHECK-NEXT:    vpsel q0, q0, q1
148; CHECK-NEXT:    bx lr
149entry:
150  %c = icmp ult i32 %s, %t
151  %vc1 = insertelement <16 x i1> undef, i1 %c, i64 0
152  %vc4 = shufflevector <16 x i1> %vc1, <16 x i1> undef, <16 x i32> zeroinitializer
153  %r = select <16 x i1> %vc4, <16 x i8> %a, <16 x i8> %b
154  ret <16 x i8> %r
155}
156
157
158define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
159; CHECK-LABEL: build_var0_v2i1:
160; CHECK:       @ %bb.0: @ %entry
161; CHECK-NEXT:    cmp r0, r1
162; CHECK-NEXT:    csetm r0, lo
163; CHECK-NEXT:    vmov s8, r0
164; CHECK-NEXT:    vldr s10, .LCPI9_0
165; CHECK-NEXT:    vmov.f32 s9, s8
166; CHECK-NEXT:    vmov.f32 s11, s10
167; CHECK-NEXT:    vbic q1, q1, q2
168; CHECK-NEXT:    vand q0, q0, q2
169; CHECK-NEXT:    vorr q0, q0, q1
170; CHECK-NEXT:    bx lr
171; CHECK-NEXT:    .p2align 2
172; CHECK-NEXT:  @ %bb.1:
173; CHECK-NEXT:  .LCPI9_0:
174; CHECK-NEXT:    .long 0x00000000 @ float 0
175entry:
176  %c = icmp ult i32 %s, %t
177  %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 0
178  %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
179  ret <2 x i64> %r
180}
181
182define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
183; CHECK-LABEL: build_var1_v2i1:
184; CHECK:       @ %bb.0: @ %entry
185; CHECK-NEXT:    cmp r0, r1
186; CHECK-NEXT:    csetm r0, lo
187; CHECK-NEXT:    vmov s10, r0
188; CHECK-NEXT:    vldr s8, .LCPI10_0
189; CHECK-NEXT:    vmov.f32 s9, s8
190; CHECK-NEXT:    vmov.f32 s11, s10
191; CHECK-NEXT:    vbic q1, q1, q2
192; CHECK-NEXT:    vand q0, q0, q2
193; CHECK-NEXT:    vorr q0, q0, q1
194; CHECK-NEXT:    bx lr
195; CHECK-NEXT:    .p2align 2
196; CHECK-NEXT:  @ %bb.1:
197; CHECK-NEXT:  .LCPI10_0:
198; CHECK-NEXT:    .long 0x00000000 @ float 0
199entry:
200  %c = icmp ult i32 %s, %t
201  %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 1
202  %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
203  ret <2 x i64> %r
204}
205
206define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
207; CHECK-LABEL: build_varN_v2i1:
208; CHECK:       @ %bb.0: @ %entry
209; CHECK-NEXT:    cmp r0, r1
210; CHECK-NEXT:    csetm r0, lo
211; CHECK-NEXT:    vdup.32 q2, r0
212; CHECK-NEXT:    vbic q1, q1, q2
213; CHECK-NEXT:    vand q0, q0, q2
214; CHECK-NEXT:    vorr q0, q0, q1
215; CHECK-NEXT:    bx lr
216entry:
217  %c = icmp ult i32 %s, %t
218  %vc1 = insertelement <2 x i1> undef, i1 %c, i64 0
219  %vc4 = shufflevector <2 x i1> %vc1, <2 x i1> undef, <2 x i32> zeroinitializer
220  %r = select <2 x i1> %vc4, <2 x i64> %a, <2 x i64> %b
221  ret <2 x i64> %r
222}
223