1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3;;; Test extract intrinsic instructions
4;;;
5;;; Note:
6;;;   We test extract_vm512u and extract_vm512l pseudo instructions.
7
8; Function Attrs: nounwind readnone
9define fastcc <256 x i1> @extract_vm512u(<512 x i1> %0) {
10; CHECK-LABEL: extract_vm512u:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    andm %vm1, %vm0, %vm2
13; CHECK-NEXT:    b.l.t (, %s10)
14  %2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1> %0)
15  ret <256 x i1> %2
16}
17
18; Function Attrs: nounwind readnone
19declare <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1>)
20
21; Function Attrs: nounwind readnone
22define fastcc <256 x i1> @extract_vm512l(<512 x i1> %0) {
23; CHECK-LABEL: extract_vm512l:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    andm %vm0, %vm0, %vm2
26; CHECK-NEXT:    andm %vm1, %vm0, %vm3
27; CHECK-NEXT:    b.l.t (, %s10)
28  %2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1> %0)
29  ret <256 x i1> %2
30}
31
32; Function Attrs: nounwind readnone
33declare <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1>)
34