1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3;;; Test vector minimum intrinsic instructions
4;;;
5;;; Note:
6;;;   We test VRMIN*vl and VRMIN*vl_v instructions.
7
8; Function Attrs: nounwind readnone
9define fastcc <256 x double> @vrminswfstsx_vvl(<256 x double> %0) {
10; CHECK-LABEL: vrminswfstsx_vvl:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    lea %s0, 256
13; CHECK-NEXT:    lvl %s0
14; CHECK-NEXT:    vrmins.w.fst.sx %v0, %v0
15; CHECK-NEXT:    b.l.t (, %s10)
16  %2 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstsx.vvl(<256 x double> %0, i32 256)
17  ret <256 x double> %2
18}
19
20; Function Attrs: nounwind readnone
21declare <256 x double> @llvm.ve.vl.vrminswfstsx.vvl(<256 x double>, i32)
22
23; Function Attrs: nounwind readnone
24define fastcc <256 x double> @vrminswfstsx_vvvl(<256 x double> %0, <256 x double> %1) {
25; CHECK-LABEL: vrminswfstsx_vvvl:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    lea %s0, 128
28; CHECK-NEXT:    lvl %s0
29; CHECK-NEXT:    vrmins.w.fst.sx %v1, %v0
30; CHECK-NEXT:    lea %s16, 256
31; CHECK-NEXT:    lvl %s16
32; CHECK-NEXT:    vor %v0, (0)1, %v1
33; CHECK-NEXT:    b.l.t (, %s10)
34  %3 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstsx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
35  ret <256 x double> %3
36}
37
38; Function Attrs: nounwind readnone
39declare <256 x double> @llvm.ve.vl.vrminswfstsx.vvvl(<256 x double>, <256 x double>, i32)
40
41; Function Attrs: nounwind readnone
42define fastcc <256 x double> @vrminswlstsx_vvl(<256 x double> %0) {
43; CHECK-LABEL: vrminswlstsx_vvl:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    lea %s0, 256
46; CHECK-NEXT:    lvl %s0
47; CHECK-NEXT:    vrmins.w.lst.sx %v0, %v0
48; CHECK-NEXT:    b.l.t (, %s10)
49  %2 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstsx.vvl(<256 x double> %0, i32 256)
50  ret <256 x double> %2
51}
52
53; Function Attrs: nounwind readnone
54declare <256 x double> @llvm.ve.vl.vrminswlstsx.vvl(<256 x double>, i32)
55
56; Function Attrs: nounwind readnone
57define fastcc <256 x double> @vrminswlstsx_vvvl(<256 x double> %0, <256 x double> %1) {
58; CHECK-LABEL: vrminswlstsx_vvvl:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    lea %s0, 128
61; CHECK-NEXT:    lvl %s0
62; CHECK-NEXT:    vrmins.w.lst.sx %v1, %v0
63; CHECK-NEXT:    lea %s16, 256
64; CHECK-NEXT:    lvl %s16
65; CHECK-NEXT:    vor %v0, (0)1, %v1
66; CHECK-NEXT:    b.l.t (, %s10)
67  %3 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstsx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
68  ret <256 x double> %3
69}
70
71; Function Attrs: nounwind readnone
72declare <256 x double> @llvm.ve.vl.vrminswlstsx.vvvl(<256 x double>, <256 x double>, i32)
73
74; Function Attrs: nounwind readnone
75define fastcc <256 x double> @vrminswfstzx_vvl(<256 x double> %0) {
76; CHECK-LABEL: vrminswfstzx_vvl:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    lea %s0, 256
79; CHECK-NEXT:    lvl %s0
80; CHECK-NEXT:    vrmins.w.fst.zx %v0, %v0
81; CHECK-NEXT:    b.l.t (, %s10)
82  %2 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstzx.vvl(<256 x double> %0, i32 256)
83  ret <256 x double> %2
84}
85
86; Function Attrs: nounwind readnone
87declare <256 x double> @llvm.ve.vl.vrminswfstzx.vvl(<256 x double>, i32)
88
89; Function Attrs: nounwind readnone
90define fastcc <256 x double> @vrminswfstzx_vvvl(<256 x double> %0, <256 x double> %1) {
91; CHECK-LABEL: vrminswfstzx_vvvl:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    lea %s0, 128
94; CHECK-NEXT:    lvl %s0
95; CHECK-NEXT:    vrmins.w.fst.zx %v1, %v0
96; CHECK-NEXT:    lea %s16, 256
97; CHECK-NEXT:    lvl %s16
98; CHECK-NEXT:    vor %v0, (0)1, %v1
99; CHECK-NEXT:    b.l.t (, %s10)
100  %3 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstzx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
101  ret <256 x double> %3
102}
103
104; Function Attrs: nounwind readnone
105declare <256 x double> @llvm.ve.vl.vrminswfstzx.vvvl(<256 x double>, <256 x double>, i32)
106
107; Function Attrs: nounwind readnone
108define fastcc <256 x double> @vrminswlstzx_vvl(<256 x double> %0) {
109; CHECK-LABEL: vrminswlstzx_vvl:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    lea %s0, 256
112; CHECK-NEXT:    lvl %s0
113; CHECK-NEXT:    vrmins.w.lst.zx %v0, %v0
114; CHECK-NEXT:    b.l.t (, %s10)
115  %2 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstzx.vvl(<256 x double> %0, i32 256)
116  ret <256 x double> %2
117}
118
119; Function Attrs: nounwind readnone
120declare <256 x double> @llvm.ve.vl.vrminswlstzx.vvl(<256 x double>, i32)
121
122; Function Attrs: nounwind readnone
123define fastcc <256 x double> @vrminswlstzx_vvvl(<256 x double> %0, <256 x double> %1) {
124; CHECK-LABEL: vrminswlstzx_vvvl:
125; CHECK:       # %bb.0:
126; CHECK-NEXT:    lea %s0, 128
127; CHECK-NEXT:    lvl %s0
128; CHECK-NEXT:    vrmins.w.lst.zx %v1, %v0
129; CHECK-NEXT:    lea %s16, 256
130; CHECK-NEXT:    lvl %s16
131; CHECK-NEXT:    vor %v0, (0)1, %v1
132; CHECK-NEXT:    b.l.t (, %s10)
133  %3 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstzx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
134  ret <256 x double> %3
135}
136
137; Function Attrs: nounwind readnone
138declare <256 x double> @llvm.ve.vl.vrminswlstzx.vvvl(<256 x double>, <256 x double>, i32)
139
140; Function Attrs: nounwind readnone
141define fastcc <256 x double> @vrminslfst_vvl(<256 x double> %0) {
142; CHECK-LABEL: vrminslfst_vvl:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    lea %s0, 256
145; CHECK-NEXT:    lvl %s0
146; CHECK-NEXT:    vrmins.l.fst %v0, %v0
147; CHECK-NEXT:    b.l.t (, %s10)
148  %2 = tail call fast <256 x double> @llvm.ve.vl.vrminslfst.vvl(<256 x double> %0, i32 256)
149  ret <256 x double> %2
150}
151
152; Function Attrs: nounwind readnone
153declare <256 x double> @llvm.ve.vl.vrminslfst.vvl(<256 x double>, i32)
154
155; Function Attrs: nounwind readnone
156define fastcc <256 x double> @vrminslfst_vvvl(<256 x double> %0, <256 x double> %1) {
157; CHECK-LABEL: vrminslfst_vvvl:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    lea %s0, 128
160; CHECK-NEXT:    lvl %s0
161; CHECK-NEXT:    vrmins.l.fst %v1, %v0
162; CHECK-NEXT:    lea %s16, 256
163; CHECK-NEXT:    lvl %s16
164; CHECK-NEXT:    vor %v0, (0)1, %v1
165; CHECK-NEXT:    b.l.t (, %s10)
166  %3 = tail call fast <256 x double> @llvm.ve.vl.vrminslfst.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
167  ret <256 x double> %3
168}
169
170; Function Attrs: nounwind readnone
171declare <256 x double> @llvm.ve.vl.vrminslfst.vvvl(<256 x double>, <256 x double>, i32)
172
173; Function Attrs: nounwind readnone
174define fastcc <256 x double> @vrminsllst_vvl(<256 x double> %0) {
175; CHECK-LABEL: vrminsllst_vvl:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    lea %s0, 256
178; CHECK-NEXT:    lvl %s0
179; CHECK-NEXT:    vrmins.l.lst %v0, %v0
180; CHECK-NEXT:    b.l.t (, %s10)
181  %2 = tail call fast <256 x double> @llvm.ve.vl.vrminsllst.vvl(<256 x double> %0, i32 256)
182  ret <256 x double> %2
183}
184
185; Function Attrs: nounwind readnone
186declare <256 x double> @llvm.ve.vl.vrminsllst.vvl(<256 x double>, i32)
187
188; Function Attrs: nounwind readnone
189define fastcc <256 x double> @vrminsllst_vvvl(<256 x double> %0, <256 x double> %1) {
190; CHECK-LABEL: vrminsllst_vvvl:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    lea %s0, 128
193; CHECK-NEXT:    lvl %s0
194; CHECK-NEXT:    vrmins.l.lst %v1, %v0
195; CHECK-NEXT:    lea %s16, 256
196; CHECK-NEXT:    lvl %s16
197; CHECK-NEXT:    vor %v0, (0)1, %v1
198; CHECK-NEXT:    b.l.t (, %s10)
199  %3 = tail call fast <256 x double> @llvm.ve.vl.vrminsllst.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
200  ret <256 x double> %3
201}
202
203; Function Attrs: nounwind readnone
204declare <256 x double> @llvm.ve.vl.vrminsllst.vvvl(<256 x double>, <256 x double>, i32)
205