1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 2 3;;; Test vector sequential number intrinsic instructions 4;;; 5;;; Note: 6;;; We test VSEQ*l, VSEQ*l_v, PVSEQ*l, and PVSEQ*l_v instructions. 7 8; Function Attrs: nounwind readnone 9define fastcc <256 x double> @vseq_vl() { 10; CHECK-LABEL: vseq_vl: 11; CHECK: # %bb.0: 12; CHECK-NEXT: lea %s0, 256 13; CHECK-NEXT: lvl %s0 14; CHECK-NEXT: vseq %v0 15; CHECK-NEXT: b.l.t (, %s10) 16 %1 = tail call fast <256 x double> @llvm.ve.vl.vseq.vl(i32 256) 17 ret <256 x double> %1 18} 19 20; Function Attrs: nounwind readnone 21declare <256 x double> @llvm.ve.vl.vseq.vl(i32) 22 23; Function Attrs: nounwind readnone 24define fastcc <256 x double> @vseq_vvl(<256 x double> %0) { 25; CHECK-LABEL: vseq_vvl: 26; CHECK: # %bb.0: 27; CHECK-NEXT: lea %s0, 256 28; CHECK-NEXT: lvl %s0 29; CHECK-NEXT: vseq %v0 30; CHECK-NEXT: b.l.t (, %s10) 31 %2 = tail call fast <256 x double> @llvm.ve.vl.vseq.vvl(<256 x double> %0, i32 256) 32 ret <256 x double> %2 33} 34 35; Function Attrs: nounwind readnone 36declare <256 x double> @llvm.ve.vl.vseq.vvl(<256 x double>, i32) 37 38; Function Attrs: nounwind readnone 39define fastcc <256 x double> @pvseqlo_vl() { 40; CHECK-LABEL: pvseqlo_vl: 41; CHECK: # %bb.0: 42; CHECK-NEXT: lea %s0, 256 43; CHECK-NEXT: lvl %s0 44; CHECK-NEXT: pvseq.lo %v0 45; CHECK-NEXT: b.l.t (, %s10) 46 %1 = tail call fast <256 x double> @llvm.ve.vl.pvseqlo.vl(i32 256) 47 ret <256 x double> %1 48} 49 50; Function Attrs: nounwind readnone 51declare <256 x double> @llvm.ve.vl.pvseqlo.vl(i32) 52 53; Function Attrs: nounwind readnone 54define fastcc <256 x double> @pvseqlo_vvl(<256 x double> %0) { 55; CHECK-LABEL: pvseqlo_vvl: 56; CHECK: # %bb.0: 57; CHECK-NEXT: lea %s0, 256 58; CHECK-NEXT: lvl %s0 59; CHECK-NEXT: pvseq.lo %v0 60; CHECK-NEXT: b.l.t (, %s10) 61 %2 = tail call fast <256 x double> @llvm.ve.vl.pvseqlo.vvl(<256 x double> %0, i32 256) 62 ret <256 x double> %2 63} 64 65; Function Attrs: nounwind readnone 66declare <256 x double> @llvm.ve.vl.pvseqlo.vvl(<256 x double>, i32) 67 68; Function Attrs: nounwind readnone 69define fastcc <256 x double> @pvsequp_vl() { 70; CHECK-LABEL: pvsequp_vl: 71; CHECK: # %bb.0: 72; CHECK-NEXT: lea %s0, 256 73; CHECK-NEXT: lvl %s0 74; CHECK-NEXT: pvseq.up %v0 75; CHECK-NEXT: b.l.t (, %s10) 76 %1 = tail call fast <256 x double> @llvm.ve.vl.pvsequp.vl(i32 256) 77 ret <256 x double> %1 78} 79 80; Function Attrs: nounwind readnone 81declare <256 x double> @llvm.ve.vl.pvsequp.vl(i32) 82 83; Function Attrs: nounwind readnone 84define fastcc <256 x double> @pvsequp_vvl(<256 x double> %0) { 85; CHECK-LABEL: pvsequp_vvl: 86; CHECK: # %bb.0: 87; CHECK-NEXT: lea %s0, 256 88; CHECK-NEXT: lvl %s0 89; CHECK-NEXT: pvseq.up %v0 90; CHECK-NEXT: b.l.t (, %s10) 91 %2 = tail call fast <256 x double> @llvm.ve.vl.pvsequp.vvl(<256 x double> %0, i32 256) 92 ret <256 x double> %2 93} 94 95; Function Attrs: nounwind readnone 96declare <256 x double> @llvm.ve.vl.pvsequp.vvl(<256 x double>, i32) 97 98; Function Attrs: nounwind readnone 99define fastcc <256 x double> @pvseq_vl() { 100; CHECK-LABEL: pvseq_vl: 101; CHECK: # %bb.0: 102; CHECK-NEXT: lea %s0, 256 103; CHECK-NEXT: lvl %s0 104; CHECK-NEXT: pvseq %v0 105; CHECK-NEXT: b.l.t (, %s10) 106 %1 = tail call fast <256 x double> @llvm.ve.vl.pvseq.vl(i32 256) 107 ret <256 x double> %1 108} 109 110; Function Attrs: nounwind readnone 111declare <256 x double> @llvm.ve.vl.pvseq.vl(i32) 112 113; Function Attrs: nounwind readnone 114define fastcc <256 x double> @pvseq_vvl(<256 x double> %0) { 115; CHECK-LABEL: pvseq_vvl: 116; CHECK: # %bb.0: 117; CHECK-NEXT: lea %s0, 256 118; CHECK-NEXT: lvl %s0 119; CHECK-NEXT: pvseq %v0 120; CHECK-NEXT: b.l.t (, %s10) 121 %2 = tail call fast <256 x double> @llvm.ve.vl.pvseq.vvl(<256 x double> %0, i32 256) 122 ret <256 x double> %2 123} 124 125; Function Attrs: nounwind readnone 126declare <256 x double> @llvm.ve.vl.pvseq.vvl(<256 x double>, i32) 127