1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26 #include <xf86drm.h>
27 #include <nouveau_drm.h>
28 #include "util/format/u_format.h"
29 #include "util/format/u_format_s3tc.h"
30 #include "util/u_screen.h"
31
32 #include "nv_object.xml.h"
33 #include "nv_m2mf.xml.h"
34 #include "nv30/nv30-40_3d.xml.h"
35 #include "nv30/nv01_2d.xml.h"
36
37 #include "nouveau_fence.h"
38 #include "nv30/nv30_screen.h"
39 #include "nv30/nv30_context.h"
40 #include "nv30/nv30_resource.h"
41 #include "nv30/nv30_format.h"
42
43 #define RANKINE_0397_CHIPSET 0x00000003
44 #define RANKINE_0497_CHIPSET 0x000001e0
45 #define RANKINE_0697_CHIPSET 0x00000010
46 #define CURIE_4097_CHIPSET 0x00000baf
47 #define CURIE_4497_CHIPSET 0x00005450
48 #define CURIE_4497_CHIPSET6X 0x00000088
49
50 static int
nv30_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)51 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
52 {
53 struct nv30_screen *screen = nv30_screen(pscreen);
54 struct nouveau_object *eng3d = screen->eng3d;
55 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
56
57 switch (param) {
58 /* non-boolean capabilities */
59 case PIPE_CAP_MAX_RENDER_TARGETS:
60 return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
61 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
62 return 4096;
63 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
64 return 10;
65 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
66 return 13;
67 case PIPE_CAP_GLSL_FEATURE_LEVEL:
68 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
69 return 120;
70 case PIPE_CAP_ENDIANNESS:
71 return PIPE_ENDIAN_LITTLE;
72 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
73 return 16;
74 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
75 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
76 case PIPE_CAP_MAX_VIEWPORTS:
77 return 1;
78 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
79 return 2048;
80 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
81 return 8 * 1024 * 1024;
82 case PIPE_CAP_MAX_VARYINGS:
83 return 8;
84
85 /* supported capabilities */
86 case PIPE_CAP_ANISOTROPIC_FILTER:
87 case PIPE_CAP_POINT_SPRITE:
88 case PIPE_CAP_OCCLUSION_QUERY:
89 case PIPE_CAP_QUERY_TIME_ELAPSED:
90 case PIPE_CAP_QUERY_TIMESTAMP:
91 case PIPE_CAP_TEXTURE_SWIZZLE:
92 case PIPE_CAP_DEPTH_CLIP_DISABLE:
93 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
94 case PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT:
95 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
96 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
97 case PIPE_CAP_TGSI_TEXCOORD:
98 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
99 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
100 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
101 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
102 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
103 return 1;
104 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
105 return PIPE_TEXTURE_TRANSFER_BLIT;
106 /* nv35 capabilities */
107 case PIPE_CAP_DEPTH_BOUNDS_TEST:
108 return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
109 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
110 case PIPE_CAP_SUPPORTED_PRIM_MODES:
111 return BITFIELD_MASK(PIPE_PRIM_MAX);
112 /* nv4x capabilities */
113 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
114 case PIPE_CAP_NPOT_TEXTURES:
115 case PIPE_CAP_CONDITIONAL_RENDER:
116 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
117 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
118 case PIPE_CAP_PRIMITIVE_RESTART:
119 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
120 return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
121 /* unsupported */
122 case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
123 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
124 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
125 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
126 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
127 case PIPE_CAP_VERTEX_SHADER_SATURATE:
128 case PIPE_CAP_INDEP_BLEND_ENABLE:
129 case PIPE_CAP_INDEP_BLEND_FUNC:
130 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
131 case PIPE_CAP_SHADER_STENCIL_EXPORT:
132 case PIPE_CAP_VS_INSTANCEID:
133 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
134 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
135 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
136 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
137 case PIPE_CAP_MIN_TEXEL_OFFSET:
138 case PIPE_CAP_MAX_TEXEL_OFFSET:
139 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
140 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
141 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
142 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
143 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
144 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
145 case PIPE_CAP_MAX_VERTEX_STREAMS:
146 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
147 case PIPE_CAP_TEXTURE_BARRIER:
148 case PIPE_CAP_SEAMLESS_CUBE_MAP:
149 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
150 case PIPE_CAP_CUBE_MAP_ARRAY:
151 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
152 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
153 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
154 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
155 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
156 case PIPE_CAP_START_INSTANCE:
157 case PIPE_CAP_TEXTURE_MULTISAMPLE:
158 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
159 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
160 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
161 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
162 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
163 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
164 case PIPE_CAP_VS_LAYER_VIEWPORT:
165 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
166 case PIPE_CAP_TEXTURE_GATHER_SM5:
167 case PIPE_CAP_FAKE_SW_MSAA:
168 case PIPE_CAP_TEXTURE_QUERY_LOD:
169 case PIPE_CAP_SAMPLE_SHADING:
170 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
171 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
172 case PIPE_CAP_USER_VERTEX_BUFFERS:
173 case PIPE_CAP_COMPUTE:
174 case PIPE_CAP_DRAW_INDIRECT:
175 case PIPE_CAP_MULTI_DRAW_INDIRECT:
176 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
177 case PIPE_CAP_FS_FINE_DERIVATIVE:
178 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
179 case PIPE_CAP_SAMPLER_VIEW_TARGET:
180 case PIPE_CAP_CLIP_HALFZ:
181 case PIPE_CAP_VERTEXID_NOBASE:
182 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
183 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
184 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
185 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
186 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
187 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
188 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
189 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
190 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
191 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
192 case PIPE_CAP_SHAREABLE_SHADERS:
193 case PIPE_CAP_CLEAR_TEXTURE:
194 case PIPE_CAP_DRAW_PARAMETERS:
195 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
196 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
197 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
198 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
199 case PIPE_CAP_INVALIDATE_BUFFER:
200 case PIPE_CAP_GENERATE_MIPMAP:
201 case PIPE_CAP_STRING_MARKER:
202 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
203 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
204 case PIPE_CAP_QUERY_BUFFER_OBJECT:
205 case PIPE_CAP_QUERY_MEMORY_INFO:
206 case PIPE_CAP_PCI_GROUP:
207 case PIPE_CAP_PCI_BUS:
208 case PIPE_CAP_PCI_DEVICE:
209 case PIPE_CAP_PCI_FUNCTION:
210 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
211 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
212 case PIPE_CAP_CULL_DISTANCE:
213 case PIPE_CAP_SHADER_GROUP_VOTE:
214 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
215 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
216 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
217 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
218 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
219 case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
220 case PIPE_CAP_NATIVE_FENCE_FD:
221 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
222 case PIPE_CAP_FBFETCH:
223 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
224 case PIPE_CAP_DOUBLES:
225 case PIPE_CAP_INT64:
226 case PIPE_CAP_INT64_DIVMOD:
227 case PIPE_CAP_TGSI_TEX_TXF_LZ:
228 case PIPE_CAP_SHADER_CLOCK:
229 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
230 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
231 case PIPE_CAP_SHADER_BALLOT:
232 case PIPE_CAP_TES_LAYER_VIEWPORT:
233 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
234 case PIPE_CAP_POST_DEPTH_COVERAGE:
235 case PIPE_CAP_BINDLESS_TEXTURE:
236 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
237 case PIPE_CAP_QUERY_SO_OVERFLOW:
238 case PIPE_CAP_MEMOBJ:
239 case PIPE_CAP_LOAD_CONSTBUF:
240 case PIPE_CAP_TILE_RASTER_ORDER:
241 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
242 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
243 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
244 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
245 case PIPE_CAP_FENCE_SIGNAL:
246 case PIPE_CAP_CONSTBUF0_FLAGS:
247 case PIPE_CAP_PACKED_UNIFORMS:
248 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
249 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
250 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
251 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
252 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
253 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
254 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
255 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
256 case PIPE_CAP_TGSI_DIV:
257 case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP:
258 case PIPE_CAP_IMAGE_STORE_FORMATTED:
259 return 0;
260
261 case PIPE_CAP_MAX_GS_INVOCATIONS:
262 return 32;
263 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
264 return 1 << 27;
265 case PIPE_CAP_VENDOR_ID:
266 return 0x10de;
267 case PIPE_CAP_DEVICE_ID: {
268 uint64_t device_id;
269 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
270 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
271 return -1;
272 }
273 return device_id;
274 }
275 case PIPE_CAP_ACCELERATED:
276 return 1;
277 case PIPE_CAP_VIDEO_MEMORY:
278 return dev->vram_size >> 20;
279 case PIPE_CAP_UMA:
280 return 0;
281 default:
282 return u_pipe_screen_get_param_defaults(pscreen, param);
283 }
284 }
285
286 static float
nv30_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)287 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
288 {
289 struct nv30_screen *screen = nv30_screen(pscreen);
290 struct nouveau_object *eng3d = screen->eng3d;
291
292 switch (param) {
293 case PIPE_CAPF_MIN_LINE_WIDTH:
294 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
295 case PIPE_CAPF_MIN_POINT_SIZE:
296 case PIPE_CAPF_MIN_POINT_SIZE_AA:
297 return 1;
298 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
299 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
300 return 0.1;
301 case PIPE_CAPF_MAX_LINE_WIDTH:
302 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
303 return 10.0;
304 case PIPE_CAPF_MAX_POINT_SIZE:
305 case PIPE_CAPF_MAX_POINT_SIZE_AA:
306 return 64.0;
307 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
308 return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
309 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
310 return 15.0;
311 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
312 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
313 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
314 return 0.0;
315 default:
316 debug_printf("unknown paramf %d\n", param);
317 return 0;
318 }
319 }
320
321 static int
nv30_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)322 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
323 enum pipe_shader_type shader,
324 enum pipe_shader_cap param)
325 {
326 struct nv30_screen *screen = nv30_screen(pscreen);
327 struct nouveau_object *eng3d = screen->eng3d;
328
329 switch (shader) {
330 case PIPE_SHADER_VERTEX:
331 switch (param) {
332 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
333 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
334 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
335 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
336 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
337 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
338 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
339 return 0;
340 case PIPE_SHADER_CAP_MAX_INPUTS:
341 case PIPE_SHADER_CAP_MAX_OUTPUTS:
342 return 16;
343 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
344 return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
345 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
346 return 1;
347 case PIPE_SHADER_CAP_MAX_TEMPS:
348 return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
349 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
350 return 32;
351 case PIPE_SHADER_CAP_PREFERRED_IR:
352 return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
353 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
354 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
355 return 0;
356 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
357 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
358 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
359 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
360 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
361 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
362 case PIPE_SHADER_CAP_SUBROUTINES:
363 case PIPE_SHADER_CAP_INTEGERS:
364 case PIPE_SHADER_CAP_INT64_ATOMICS:
365 case PIPE_SHADER_CAP_FP16:
366 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
367 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
368 case PIPE_SHADER_CAP_INT16:
369 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
370 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
371 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
372 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
373 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
374 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
375 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
376 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
377 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
378 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
379 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
380 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
381 return 0;
382 case PIPE_SHADER_CAP_SUPPORTED_IRS:
383 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
384 default:
385 debug_printf("unknown vertex shader param %d\n", param);
386 return 0;
387 }
388 break;
389 case PIPE_SHADER_FRAGMENT:
390 switch (param) {
391 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
392 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
393 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
394 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
395 return 4096;
396 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
397 return 0;
398 case PIPE_SHADER_CAP_MAX_INPUTS:
399 return 8; /* should be possible to do 10 with nv4x */
400 case PIPE_SHADER_CAP_MAX_OUTPUTS:
401 return 4;
402 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
403 return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
404 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
405 return 1;
406 case PIPE_SHADER_CAP_MAX_TEMPS:
407 return 32;
408 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
409 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
410 return 16;
411 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
412 return 32;
413 case PIPE_SHADER_CAP_PREFERRED_IR:
414 return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
415 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
416 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
417 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
418 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
419 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
420 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
421 case PIPE_SHADER_CAP_SUBROUTINES:
422 case PIPE_SHADER_CAP_INTEGERS:
423 case PIPE_SHADER_CAP_FP16:
424 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
425 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
426 case PIPE_SHADER_CAP_INT16:
427 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
428 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
429 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
430 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
431 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
432 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
433 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
434 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
435 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
436 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
437 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
438 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
439 return 0;
440 case PIPE_SHADER_CAP_SUPPORTED_IRS:
441 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
442 default:
443 debug_printf("unknown fragment shader param %d\n", param);
444 return 0;
445 }
446 break;
447 default:
448 return 0;
449 }
450 }
451
452 static bool
nv30_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)453 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
454 enum pipe_format format,
455 enum pipe_texture_target target,
456 unsigned sample_count,
457 unsigned storage_sample_count,
458 unsigned bindings)
459 {
460 if (sample_count > nv30_screen(pscreen)->max_sample_count)
461 return false;
462
463 if (!(0x00000017 & (1 << sample_count)))
464 return false;
465
466 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
467 return false;
468
469 /* No way to render to a swizzled 3d texture. We don't necessarily know if
470 * it's swizzled or not here, but we have to assume anyways.
471 */
472 if (target == PIPE_TEXTURE_3D && (bindings & PIPE_BIND_RENDER_TARGET))
473 return false;
474
475 /* shared is always supported */
476 bindings &= ~PIPE_BIND_SHARED;
477
478 if (bindings & PIPE_BIND_INDEX_BUFFER) {
479 if (format != PIPE_FORMAT_R8_UINT &&
480 format != PIPE_FORMAT_R16_UINT &&
481 format != PIPE_FORMAT_R32_UINT)
482 return false;
483 bindings &= ~PIPE_BIND_INDEX_BUFFER;
484 }
485
486 return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
487 }
488
489 static const nir_shader_compiler_options nv30_base_compiler_options = {
490 .fuse_ffma32 = true,
491 .fuse_ffma64 = true,
492 .lower_bitops = true,
493 .lower_extract_byte = true,
494 .lower_extract_word = true,
495 .lower_fdiv = true,
496 .lower_insert_byte = true,
497 .lower_insert_word = true,
498 .lower_fdph = true,
499 .lower_flrp32 = true,
500 .lower_flrp64 = true,
501 .lower_fmod = true,
502 .lower_fpow = true, /* In hardware as of nv40 FS */
503 .lower_rotate = true,
504 .lower_uniforms_to_ubo = true,
505 .lower_vector_cmp = true,
506 .max_unroll_iterations = 32,
507
508 .use_interpolated_input_intrinsics = true,
509 };
510
511 static const void *
nv30_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)512 nv30_screen_get_compiler_options(struct pipe_screen *pscreen,
513 enum pipe_shader_ir ir,
514 enum pipe_shader_type shader)
515 {
516 struct nv30_screen *screen = nv30_screen(pscreen);
517 assert(ir == PIPE_SHADER_IR_NIR);
518
519 /* The FS compiler options are different between nv30 and nv40, and are set
520 * up at screen creation time.
521 */
522 if (shader == PIPE_SHADER_FRAGMENT)
523 return &screen->fs_compiler_options;
524
525 return &nv30_base_compiler_options;
526 }
527
528 static void
nv30_screen_fence_emit(struct pipe_screen * pscreen,uint32_t * sequence)529 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
530 {
531 struct nv30_screen *screen = nv30_screen(pscreen);
532 struct nouveau_pushbuf *push = screen->base.pushbuf;
533
534 *sequence = ++screen->base.fence.sequence;
535
536 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
537 PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
538 (2 /* size */ << 18) | (7 /* subchan */ << 13));
539 PUSH_DATA (push, 0);
540 PUSH_DATA (push, *sequence);
541 }
542
543 static uint32_t
nv30_screen_fence_update(struct pipe_screen * pscreen)544 nv30_screen_fence_update(struct pipe_screen *pscreen)
545 {
546 struct nv30_screen *screen = nv30_screen(pscreen);
547 struct nv04_notify *fence = screen->fence->data;
548 return *(uint32_t *)((char *)screen->notify->map + fence->offset);
549 }
550
551 static void
nv30_screen_destroy(struct pipe_screen * pscreen)552 nv30_screen_destroy(struct pipe_screen *pscreen)
553 {
554 struct nv30_screen *screen = nv30_screen(pscreen);
555
556 if (!nouveau_drm_screen_unref(&screen->base))
557 return;
558
559 nouveau_fence_cleanup(&screen->base);
560
561 nouveau_bo_ref(NULL, &screen->notify);
562
563 nouveau_heap_destroy(&screen->query_heap);
564 nouveau_heap_destroy(&screen->vp_exec_heap);
565 nouveau_heap_destroy(&screen->vp_data_heap);
566
567 nouveau_object_del(&screen->query);
568 nouveau_object_del(&screen->fence);
569 nouveau_object_del(&screen->ntfy);
570
571 nouveau_object_del(&screen->sifm);
572 nouveau_object_del(&screen->swzsurf);
573 nouveau_object_del(&screen->surf2d);
574 nouveau_object_del(&screen->m2mf);
575 nouveau_object_del(&screen->eng3d);
576 nouveau_object_del(&screen->null);
577
578 nouveau_screen_fini(&screen->base);
579 FREE(screen);
580 }
581
582 #define FAIL_SCREEN_INIT(str, err) \
583 do { \
584 NOUVEAU_ERR(str, err); \
585 screen->base.base.context_create = NULL; \
586 return &screen->base; \
587 } while(0)
588
589 struct nouveau_screen *
nv30_screen_create(struct nouveau_device * dev)590 nv30_screen_create(struct nouveau_device *dev)
591 {
592 struct nv30_screen *screen;
593 struct pipe_screen *pscreen;
594 struct nouveau_pushbuf *push;
595 struct nv04_fifo *fifo;
596 unsigned oclass = 0;
597 int ret, i;
598
599 switch (dev->chipset & 0xf0) {
600 case 0x30:
601 if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
602 oclass = NV30_3D_CLASS;
603 else
604 if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
605 oclass = NV34_3D_CLASS;
606 else
607 if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
608 oclass = NV35_3D_CLASS;
609 break;
610 case 0x40:
611 if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
612 oclass = NV40_3D_CLASS;
613 else
614 if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
615 oclass = NV44_3D_CLASS;
616 break;
617 case 0x60:
618 if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
619 oclass = NV44_3D_CLASS;
620 break;
621 default:
622 break;
623 }
624
625 if (!oclass) {
626 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
627 return NULL;
628 }
629
630 screen = CALLOC_STRUCT(nv30_screen);
631 if (!screen)
632 return NULL;
633
634 pscreen = &screen->base.base;
635 pscreen->destroy = nv30_screen_destroy;
636
637 /*
638 * Some modern apps try to use msaa without keeping in mind the
639 * restrictions on videomem of older cards. Resulting in dmesg saying:
640 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
641 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
642 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
643 *
644 * Because we are running out of video memory, after which the program
645 * using the msaa visual freezes, and eventually the entire system freezes.
646 *
647 * To work around this we do not allow msaa visauls by default and allow
648 * the user to override this via NV30_MAX_MSAA.
649 */
650 screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
651 if (screen->max_sample_count > 4)
652 screen->max_sample_count = 4;
653
654 pscreen->get_param = nv30_screen_get_param;
655 pscreen->get_paramf = nv30_screen_get_paramf;
656 pscreen->get_shader_param = nv30_screen_get_shader_param;
657 pscreen->context_create = nv30_context_create;
658 pscreen->is_format_supported = nv30_screen_is_format_supported;
659 pscreen->get_compiler_options = nv30_screen_get_compiler_options;
660
661 nv30_resource_screen_init(pscreen);
662 nouveau_screen_init_vdec(&screen->base);
663
664 screen->base.fence.emit = nv30_screen_fence_emit;
665 screen->base.fence.update = nv30_screen_fence_update;
666
667 ret = nouveau_screen_init(&screen->base, dev);
668 if (ret)
669 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
670
671 screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
672 screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
673 if (oclass == NV40_3D_CLASS) {
674 screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
675 screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
676 }
677
678 screen->fs_compiler_options = nv30_base_compiler_options;
679 if (oclass >= NV40_3D_CLASS)
680 screen->fs_compiler_options.lower_fpow = false;
681
682 fifo = screen->base.channel->data;
683 push = screen->base.pushbuf;
684 push->rsvd_kick = 16;
685
686 ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
687 NULL, 0, &screen->null);
688 if (ret)
689 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
690
691 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
692 * this means that the address pointed at by the DMA object must
693 * be 4KiB aligned, which means this object needs to be the first
694 * one allocated on the channel.
695 */
696 ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
697 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
698 .length = 32 }, sizeof(struct nv04_notify),
699 &screen->fence);
700 if (ret)
701 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
702
703 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
704 ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
705 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
706 .length = 32 }, sizeof(struct nv04_notify),
707 &screen->ntfy);
708 if (ret)
709 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
710
711 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
712 * the remainder of the "notifier block" assigned by the kernel for
713 * use as query objects
714 */
715 ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
716 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
717 .length = 4096 - 128 }, sizeof(struct nv04_notify),
718 &screen->query);
719 if (ret)
720 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
721
722 ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
723 if (ret)
724 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
725
726 list_inithead(&screen->queries);
727
728 /* Vertex program resources (code/data), currently 6 of the constant
729 * slots are reserved to implement user clipping planes
730 */
731 if (oclass < NV40_3D_CLASS) {
732 nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
733 nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
734 } else {
735 nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
736 nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
737 }
738
739 ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
740 if (ret == 0)
741 ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
742 if (ret)
743 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
744
745 ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
746 NULL, 0, &screen->eng3d);
747 if (ret)
748 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
749
750 BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
751 PUSH_DATA (push, screen->eng3d->handle);
752 BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
753 PUSH_DATA (push, screen->ntfy->handle);
754 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */
755 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */
756 PUSH_DATA (push, fifo->vram); /* COLOR1 */
757 PUSH_DATA (push, screen->null->handle); /* UNK190 */
758 PUSH_DATA (push, fifo->vram); /* COLOR0 */
759 PUSH_DATA (push, fifo->vram); /* ZETA */
760 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */
761 PUSH_DATA (push, fifo->gart); /* VTXBUF1 */
762 PUSH_DATA (push, screen->fence->handle); /* FENCE */
763 PUSH_DATA (push, screen->query->handle); /* QUERY - intr 0x80 if nullobj */
764 PUSH_DATA (push, screen->null->handle); /* UNK1AC */
765 PUSH_DATA (push, screen->null->handle); /* UNK1B0 */
766 if (screen->eng3d->oclass < NV40_3D_CLASS) {
767 BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
768 PUSH_DATA (push, 0x00100000);
769 BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
770 PUSH_DATA (push, 3);
771
772 BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
773 PUSH_DATA (push, 0);
774 BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
775 PUSH_DATA (push, fui(0.0));
776 PUSH_DATA (push, fui(0.0));
777 PUSH_DATA (push, fui(1.0));
778 BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
779 for (i = 0; i < 16; i++)
780 PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
781
782 BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
783 PUSH_DATA (push, 0);
784 } else {
785 BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
786 PUSH_DATA (push, fifo->vram);
787 PUSH_DATA (push, fifo->vram); /* COLOR3 */
788
789 BEGIN_NV04(push, SUBC_3D(0x1450), 1);
790 PUSH_DATA (push, 0x00000004);
791
792 BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
793 PUSH_DATA (push, 0x00000010);
794 PUSH_DATA (push, 0x01000100);
795 PUSH_DATA (push, 0xff800006);
796
797 /* vtxprog output routing */
798 BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
799 PUSH_DATA (push, 0x06144321);
800 BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
801 PUSH_DATA (push, 0xedcba987);
802 PUSH_DATA (push, 0x0000006f);
803 BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
804 PUSH_DATA (push, 0x00171615);
805 BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
806 PUSH_DATA (push, 0x001b1a19);
807
808 BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
809 PUSH_DATA (push, 0x0020ffff);
810 BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
811 PUSH_DATA (push, 0x01d300d4);
812
813 BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
814 PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
815 }
816
817 ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
818 NULL, 0, &screen->m2mf);
819 if (ret)
820 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
821
822 BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
823 PUSH_DATA (push, screen->m2mf->handle);
824 BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
825 PUSH_DATA (push, screen->ntfy->handle);
826
827 ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
828 NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
829 if (ret)
830 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
831
832 BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
833 PUSH_DATA (push, screen->surf2d->handle);
834 BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
835 PUSH_DATA (push, screen->ntfy->handle);
836
837 if (dev->chipset < 0x40)
838 oclass = NV30_SURFACE_SWZ_CLASS;
839 else
840 oclass = NV40_SURFACE_SWZ_CLASS;
841
842 ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
843 NULL, 0, &screen->swzsurf);
844 if (ret)
845 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
846
847 BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
848 PUSH_DATA (push, screen->swzsurf->handle);
849 BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
850 PUSH_DATA (push, screen->ntfy->handle);
851
852 if (dev->chipset < 0x40)
853 oclass = NV30_SIFM_CLASS;
854 else
855 oclass = NV40_SIFM_CLASS;
856
857 ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
858 NULL, 0, &screen->sifm);
859 if (ret)
860 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
861
862 BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
863 PUSH_DATA (push, screen->sifm->handle);
864 BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
865 PUSH_DATA (push, screen->ntfy->handle);
866 BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
867 PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
868
869 nouveau_pushbuf_kick(push, push->channel);
870
871 nouveau_fence_new(&screen->base, &screen->base.fence.current);
872 return &screen->base;
873 }
874