1 /*
2  * Copyright 2010 Christoph Bumiller
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28 #include "util/format_srgb.h"
29 
30 #include "tgsi/tgsi_parse.h"
31 #include "compiler/nir/nir.h"
32 
33 #include "nv50/nv50_stateobj.h"
34 #include "nv50/nv50_context.h"
35 #include "nv50/nv50_query_hw.h"
36 
37 #include "nv50/nv50_3d.xml.h"
38 #include "nv50/g80_texture.xml.h"
39 
40 #include "nouveau_gldefs.h"
41 
42 /* Caveats:
43  *  ! pipe_sampler_state.normalized_coords is ignored - rectangle textures will
44  *     use non-normalized coordinates, everything else won't
45  *    (The relevant bit is in the TIC entry and not the TSC entry.)
46  *
47  *  ! pipe_sampler_state.seamless_cube_map is ignored - seamless filtering is
48  *     always activated on NVA0 +
49  *    (Give me the global bit, otherwise it's not worth the CPU work.)
50  *
51  *  ! pipe_sampler_state.border_color is not swizzled according to the texture
52  *     swizzle in pipe_sampler_view
53  *    (This will be ugly with indirect independent texture/sampler access,
54  *     we'd have to emulate the logic in the shader. GL doesn't have that,
55  *     D3D doesn't have swizzle, if we knew what we were implementing we'd be
56  *     good.)
57  *
58  *  ! pipe_rasterizer_state.line_last_pixel is ignored - it is never drawn
59  *
60  *  ! pipe_rasterizer_state.flatshade_first also applies to QUADS
61  *    (There's a GL query for that, forcing an exception is just ridiculous.)
62  *
63  *  ! pipe_rasterizer_state.sprite_coord_enable is masked with 0xff on NVC0
64  *    (The hardware only has 8 slots meant for TexCoord and we have to assign
65  *     in advance to maintain elegant separate shader objects.)
66  */
67 
68 static inline uint32_t
nv50_colormask(unsigned mask)69 nv50_colormask(unsigned mask)
70 {
71    uint32_t ret = 0;
72 
73    if (mask & PIPE_MASK_R)
74       ret |= 0x0001;
75    if (mask & PIPE_MASK_G)
76       ret |= 0x0010;
77    if (mask & PIPE_MASK_B)
78       ret |= 0x0100;
79    if (mask & PIPE_MASK_A)
80       ret |= 0x1000;
81 
82    return ret;
83 }
84 
85 #define NV50_BLEND_FACTOR_CASE(a, b) \
86    case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
87 
88 static inline uint32_t
nv50_blend_fac(unsigned factor)89 nv50_blend_fac(unsigned factor)
90 {
91    switch (factor) {
92    NV50_BLEND_FACTOR_CASE(ONE, ONE);
93    NV50_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
94    NV50_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
95    NV50_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
96    NV50_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
97    NV50_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
98    NV50_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
99    NV50_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
100    NV50_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
101    NV50_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
102    NV50_BLEND_FACTOR_CASE(ZERO, ZERO);
103    NV50_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
104    NV50_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
105    NV50_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
106    NV50_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
107    NV50_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
108    NV50_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
109    NV50_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
110    NV50_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
111    default:
112       return NV50_BLEND_FACTOR_ZERO;
113    }
114 }
115 
116 static void *
nv50_blend_state_create(struct pipe_context * pipe,const struct pipe_blend_state * cso)117 nv50_blend_state_create(struct pipe_context *pipe,
118                         const struct pipe_blend_state *cso)
119 {
120    struct nv50_blend_stateobj *so = CALLOC_STRUCT(nv50_blend_stateobj);
121    int i;
122    bool emit_common_func = cso->rt[0].blend_enable;
123    uint32_t ms;
124 
125    if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
126       SB_BEGIN_3D(so, BLEND_INDEPENDENT, 1);
127       SB_DATA    (so, cso->independent_blend_enable);
128    }
129 
130    so->pipe = *cso;
131 
132    SB_BEGIN_3D(so, COLOR_MASK_COMMON, 1);
133    SB_DATA    (so, !cso->independent_blend_enable);
134 
135    SB_BEGIN_3D(so, BLEND_ENABLE_COMMON, 1);
136    SB_DATA    (so, !cso->independent_blend_enable);
137 
138    if (cso->independent_blend_enable) {
139       SB_BEGIN_3D(so, BLEND_ENABLE(0), 8);
140       for (i = 0; i < 8; ++i) {
141          SB_DATA(so, cso->rt[i].blend_enable);
142          if (cso->rt[i].blend_enable)
143             emit_common_func = true;
144       }
145 
146       if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
147          emit_common_func = false;
148 
149          for (i = 0; i < 8; ++i) {
150             if (!cso->rt[i].blend_enable)
151                continue;
152             SB_BEGIN_3D_(so, NVA3_3D_IBLEND_EQUATION_RGB(i), 6);
153             SB_DATA     (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
154             SB_DATA     (so, nv50_blend_fac(cso->rt[i].rgb_src_factor));
155             SB_DATA     (so, nv50_blend_fac(cso->rt[i].rgb_dst_factor));
156             SB_DATA     (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
157             SB_DATA     (so, nv50_blend_fac(cso->rt[i].alpha_src_factor));
158             SB_DATA     (so, nv50_blend_fac(cso->rt[i].alpha_dst_factor));
159          }
160       }
161    } else {
162       SB_BEGIN_3D(so, BLEND_ENABLE(0), 1);
163       SB_DATA    (so, cso->rt[0].blend_enable);
164    }
165 
166    if (emit_common_func) {
167       SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
168       SB_DATA    (so, nvgl_blend_eqn(cso->rt[0].rgb_func));
169       SB_DATA    (so, nv50_blend_fac(cso->rt[0].rgb_src_factor));
170       SB_DATA    (so, nv50_blend_fac(cso->rt[0].rgb_dst_factor));
171       SB_DATA    (so, nvgl_blend_eqn(cso->rt[0].alpha_func));
172       SB_DATA    (so, nv50_blend_fac(cso->rt[0].alpha_src_factor));
173       SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
174       SB_DATA    (so, nv50_blend_fac(cso->rt[0].alpha_dst_factor));
175    }
176 
177    if (cso->logicop_enable) {
178       SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
179       SB_DATA    (so, 1);
180       SB_DATA    (so, nvgl_logicop_func(cso->logicop_func));
181    } else {
182       SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 1);
183       SB_DATA    (so, 0);
184    }
185 
186    if (cso->independent_blend_enable) {
187       SB_BEGIN_3D(so, COLOR_MASK(0), 8);
188       for (i = 0; i < 8; ++i)
189          SB_DATA(so, nv50_colormask(cso->rt[i].colormask));
190    } else {
191       SB_BEGIN_3D(so, COLOR_MASK(0), 1);
192       SB_DATA    (so, nv50_colormask(cso->rt[0].colormask));
193    }
194 
195    ms = 0;
196    if (cso->alpha_to_coverage)
197       ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
198    if (cso->alpha_to_one)
199       ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
200 
201    SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
202    SB_DATA    (so, ms);
203 
204    assert(so->size <= ARRAY_SIZE(so->state));
205    return so;
206 }
207 
208 static void
nv50_blend_state_bind(struct pipe_context * pipe,void * hwcso)209 nv50_blend_state_bind(struct pipe_context *pipe, void *hwcso)
210 {
211    struct nv50_context *nv50 = nv50_context(pipe);
212 
213    nv50->blend = hwcso;
214    nv50->dirty_3d |= NV50_NEW_3D_BLEND;
215 }
216 
217 static void
nv50_blend_state_delete(struct pipe_context * pipe,void * hwcso)218 nv50_blend_state_delete(struct pipe_context *pipe, void *hwcso)
219 {
220    FREE(hwcso);
221 }
222 
223 /* NOTE: ignoring line_last_pixel */
224 static void *
nv50_rasterizer_state_create(struct pipe_context * pipe,const struct pipe_rasterizer_state * cso)225 nv50_rasterizer_state_create(struct pipe_context *pipe,
226                              const struct pipe_rasterizer_state *cso)
227 {
228    struct nv50_rasterizer_stateobj *so;
229    uint32_t reg;
230 
231    so = CALLOC_STRUCT(nv50_rasterizer_stateobj);
232    if (!so)
233       return NULL;
234    so->pipe = *cso;
235 
236 #ifndef NV50_SCISSORS_CLIPPING
237    for (int i = 0; i < NV50_MAX_VIEWPORTS; i++) {
238       SB_BEGIN_3D(so, SCISSOR_ENABLE(i), 1);
239       SB_DATA    (so, cso->scissor);
240    }
241 #endif
242 
243    SB_BEGIN_3D(so, SHADE_MODEL, 1);
244    SB_DATA    (so, cso->flatshade ? NV50_3D_SHADE_MODEL_FLAT :
245                                     NV50_3D_SHADE_MODEL_SMOOTH);
246    SB_BEGIN_3D(so, PROVOKING_VERTEX_LAST, 1);
247    SB_DATA    (so, !cso->flatshade_first);
248    SB_BEGIN_3D(so, VERTEX_TWO_SIDE_ENABLE, 1);
249    SB_DATA    (so, cso->light_twoside);
250 
251    SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
252    SB_DATA    (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
253 
254    SB_BEGIN_3D(so, MULTISAMPLE_ENABLE, 1);
255    SB_DATA    (so, cso->multisample);
256 
257    SB_BEGIN_3D(so, LINE_WIDTH, 1);
258    SB_DATA    (so, fui(cso->line_width));
259    SB_BEGIN_3D(so, LINE_SMOOTH_ENABLE, 1);
260    SB_DATA    (so, cso->line_smooth);
261 
262    SB_BEGIN_3D(so, LINE_STIPPLE_ENABLE, 1);
263    if (cso->line_stipple_enable) {
264       SB_DATA    (so, 1);
265       SB_BEGIN_3D(so, LINE_STIPPLE, 1);
266       SB_DATA    (so, (cso->line_stipple_pattern << 8) |
267                   cso->line_stipple_factor);
268    } else {
269       SB_DATA    (so, 0);
270    }
271 
272    if (!cso->point_size_per_vertex) {
273       SB_BEGIN_3D(so, POINT_SIZE, 1);
274       SB_DATA    (so, fui(cso->point_size));
275    }
276    SB_BEGIN_3D(so, POINT_SPRITE_ENABLE, 1);
277    SB_DATA    (so, cso->point_quad_rasterization);
278    SB_BEGIN_3D(so, POINT_SMOOTH_ENABLE, 1);
279    SB_DATA    (so, cso->point_smooth);
280 
281    SB_BEGIN_3D(so, POLYGON_MODE_FRONT, 3);
282    SB_DATA    (so, nvgl_polygon_mode(cso->fill_front));
283    SB_DATA    (so, nvgl_polygon_mode(cso->fill_back));
284    SB_DATA    (so, cso->poly_smooth);
285 
286    SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
287    SB_DATA    (so, cso->cull_face != PIPE_FACE_NONE);
288    SB_DATA    (so, cso->front_ccw ? NV50_3D_FRONT_FACE_CCW :
289                                     NV50_3D_FRONT_FACE_CW);
290    switch (cso->cull_face) {
291    case PIPE_FACE_FRONT_AND_BACK:
292       SB_DATA(so, NV50_3D_CULL_FACE_FRONT_AND_BACK);
293       break;
294    case PIPE_FACE_FRONT:
295       SB_DATA(so, NV50_3D_CULL_FACE_FRONT);
296       break;
297    case PIPE_FACE_BACK:
298    default:
299      SB_DATA(so, NV50_3D_CULL_FACE_BACK);
300      break;
301    }
302 
303    SB_BEGIN_3D(so, POLYGON_STIPPLE_ENABLE, 1);
304    SB_DATA    (so, cso->poly_stipple_enable);
305    SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
306    SB_DATA    (so, cso->offset_point);
307    SB_DATA    (so, cso->offset_line);
308    SB_DATA    (so, cso->offset_tri);
309 
310    if (cso->offset_point || cso->offset_line || cso->offset_tri) {
311       SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
312       SB_DATA    (so, fui(cso->offset_scale));
313       SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
314       SB_DATA    (so, fui(cso->offset_units * 2.0f));
315       SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
316       SB_DATA    (so, fui(cso->offset_clamp));
317    }
318 
319    if (cso->depth_clip_near) {
320       reg = 0;
321    } else {
322       reg =
323          NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
324          NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
325          NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
326    }
327 #ifndef NV50_SCISSORS_CLIPPING
328    reg |=
329       NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK7 |
330       NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
331 #endif
332    SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
333    SB_DATA    (so, reg);
334 
335    SB_BEGIN_3D(so, DEPTH_CLIP_NEGATIVE_Z, 1);
336    SB_DATA    (so, cso->clip_halfz);
337 
338    SB_BEGIN_3D(so, PIXEL_CENTER_INTEGER, 1);
339    SB_DATA    (so, !cso->half_pixel_center);
340 
341    assert(so->size <= ARRAY_SIZE(so->state));
342    return (void *)so;
343 }
344 
345 static void
nv50_rasterizer_state_bind(struct pipe_context * pipe,void * hwcso)346 nv50_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
347 {
348    struct nv50_context *nv50 = nv50_context(pipe);
349 
350    nv50->rast = hwcso;
351    nv50->dirty_3d |= NV50_NEW_3D_RASTERIZER;
352 }
353 
354 static void
nv50_rasterizer_state_delete(struct pipe_context * pipe,void * hwcso)355 nv50_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
356 {
357    FREE(hwcso);
358 }
359 
360 static void *
nv50_zsa_state_create(struct pipe_context * pipe,const struct pipe_depth_stencil_alpha_state * cso)361 nv50_zsa_state_create(struct pipe_context *pipe,
362                       const struct pipe_depth_stencil_alpha_state *cso)
363 {
364    struct nv50_zsa_stateobj *so = CALLOC_STRUCT(nv50_zsa_stateobj);
365 
366    so->pipe = *cso;
367 
368    SB_BEGIN_3D(so, DEPTH_WRITE_ENABLE, 1);
369    SB_DATA    (so, cso->depth.writemask);
370    SB_BEGIN_3D(so, DEPTH_TEST_ENABLE, 1);
371    if (cso->depth.enabled) {
372       SB_DATA    (so, 1);
373       SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
374       SB_DATA    (so, nvgl_comparison_op(cso->depth.func));
375    } else {
376       SB_DATA    (so, 0);
377    }
378 
379    SB_BEGIN_3D(so, DEPTH_BOUNDS_EN, 1);
380    if (cso->depth.bounds_test) {
381       SB_DATA    (so, 1);
382       SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
383       SB_DATA    (so, fui(cso->depth.bounds_min));
384       SB_DATA    (so, fui(cso->depth.bounds_max));
385    } else {
386       SB_DATA    (so, 0);
387    }
388 
389    if (cso->stencil[0].enabled) {
390       SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
391       SB_DATA    (so, 1);
392       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].fail_op));
393       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
394       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
395       SB_DATA    (so, nvgl_comparison_op(cso->stencil[0].func));
396       SB_BEGIN_3D(so, STENCIL_FRONT_MASK, 2);
397       SB_DATA    (so, cso->stencil[0].writemask);
398       SB_DATA    (so, cso->stencil[0].valuemask);
399    } else {
400       SB_BEGIN_3D(so, STENCIL_ENABLE, 1);
401       SB_DATA    (so, 0);
402    }
403 
404    if (cso->stencil[1].enabled) {
405       assert(cso->stencil[0].enabled);
406       SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
407       SB_DATA    (so, 1);
408       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].fail_op));
409       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
410       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
411       SB_DATA    (so, nvgl_comparison_op(cso->stencil[1].func));
412       SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
413       SB_DATA    (so, cso->stencil[1].writemask);
414       SB_DATA    (so, cso->stencil[1].valuemask);
415    } else {
416       SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 1);
417       SB_DATA    (so, 0);
418    }
419 
420    SB_BEGIN_3D(so, ALPHA_TEST_ENABLE, 1);
421    if (cso->alpha.enabled) {
422       SB_DATA    (so, 1);
423       SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
424       SB_DATA    (so, fui(cso->alpha.ref_value));
425       SB_DATA    (so, nvgl_comparison_op(cso->alpha.func));
426    } else {
427       SB_DATA    (so, 0);
428    }
429 
430    SB_BEGIN_3D(so, CB_ADDR, 1);
431    SB_DATA    (so, NV50_CB_AUX_ALPHATEST_OFFSET << (8 - 2) | NV50_CB_AUX);
432    SB_BEGIN_3D(so, CB_DATA(0), 1);
433    SB_DATA    (so, fui(cso->alpha.ref_value));
434 
435    assert(so->size <= ARRAY_SIZE(so->state));
436    return (void *)so;
437 }
438 
439 static void
nv50_zsa_state_bind(struct pipe_context * pipe,void * hwcso)440 nv50_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
441 {
442    struct nv50_context *nv50 = nv50_context(pipe);
443 
444    nv50->zsa = hwcso;
445    nv50->dirty_3d |= NV50_NEW_3D_ZSA;
446 }
447 
448 static void
nv50_zsa_state_delete(struct pipe_context * pipe,void * hwcso)449 nv50_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
450 {
451    FREE(hwcso);
452 }
453 
454 /* ====================== SAMPLERS AND TEXTURES ================================
455  */
456 
457 static inline unsigned
nv50_tsc_wrap_mode(unsigned wrap)458 nv50_tsc_wrap_mode(unsigned wrap)
459 {
460    switch (wrap) {
461    case PIPE_TEX_WRAP_REPEAT:
462       return G80_TSC_WRAP_WRAP;
463    case PIPE_TEX_WRAP_MIRROR_REPEAT:
464       return G80_TSC_WRAP_MIRROR;
465    case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
466       return G80_TSC_WRAP_CLAMP_TO_EDGE;
467    case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
468       return G80_TSC_WRAP_BORDER;
469    case PIPE_TEX_WRAP_CLAMP:
470       return G80_TSC_WRAP_CLAMP_OGL;
471    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
472       return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_TO_EDGE;
473    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
474       return G80_TSC_WRAP_MIRROR_ONCE_BORDER;
475    case PIPE_TEX_WRAP_MIRROR_CLAMP:
476       return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_OGL;
477    default:
478        NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
479        return G80_TSC_WRAP_WRAP;
480    }
481 }
482 
483 void *
nv50_sampler_state_create(struct pipe_context * pipe,const struct pipe_sampler_state * cso)484 nv50_sampler_state_create(struct pipe_context *pipe,
485                           const struct pipe_sampler_state *cso)
486 {
487    struct nv50_tsc_entry *so = MALLOC_STRUCT(nv50_tsc_entry);
488    float f[2];
489 
490    so->id = -1;
491 
492    so->tsc[0] = (0x00026000 |
493                  (nv50_tsc_wrap_mode(cso->wrap_s) << 0) |
494                  (nv50_tsc_wrap_mode(cso->wrap_t) << 3) |
495                  (nv50_tsc_wrap_mode(cso->wrap_r) << 6));
496 
497    switch (cso->mag_img_filter) {
498    case PIPE_TEX_FILTER_LINEAR:
499       so->tsc[1] = G80_TSC_1_MAG_FILTER_LINEAR;
500       break;
501    case PIPE_TEX_FILTER_NEAREST:
502    default:
503       so->tsc[1] = G80_TSC_1_MAG_FILTER_NEAREST;
504       break;
505    }
506 
507    switch (cso->min_img_filter) {
508    case PIPE_TEX_FILTER_LINEAR:
509       so->tsc[1] |= G80_TSC_1_MIN_FILTER_LINEAR;
510       break;
511    case PIPE_TEX_FILTER_NEAREST:
512    default:
513       so->tsc[1] |= G80_TSC_1_MIN_FILTER_NEAREST;
514       break;
515    }
516 
517    switch (cso->min_mip_filter) {
518    case PIPE_TEX_MIPFILTER_LINEAR:
519       so->tsc[1] |= G80_TSC_1_MIP_FILTER_LINEAR;
520       break;
521    case PIPE_TEX_MIPFILTER_NEAREST:
522       so->tsc[1] |= G80_TSC_1_MIP_FILTER_NEAREST;
523       break;
524    case PIPE_TEX_MIPFILTER_NONE:
525    default:
526       so->tsc[1] |= G80_TSC_1_MIP_FILTER_NONE;
527       break;
528    }
529 
530    if (nouveau_screen(pipe->screen)->class_3d >= NVE4_3D_CLASS) {
531       if (cso->seamless_cube_map)
532          so->tsc[1] |= GK104_TSC_1_CUBEMAP_INTERFACE_FILTERING;
533       if (!cso->normalized_coords)
534          so->tsc[1] |= GK104_TSC_1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS;
535    } else {
536       so->seamless_cube_map = cso->seamless_cube_map;
537    }
538 
539    if (cso->max_anisotropy >= 16)
540       so->tsc[0] |= (7 << 20);
541    else
542    if (cso->max_anisotropy >= 12)
543       so->tsc[0] |= (6 << 20);
544    else {
545       so->tsc[0] |= (cso->max_anisotropy >> 1) << 20;
546 
547       if (cso->max_anisotropy >= 4)
548          so->tsc[1] |= 6 << G80_TSC_1_TRILIN_OPT__SHIFT;
549       else
550       if (cso->max_anisotropy >= 2)
551          so->tsc[1] |= 4 << G80_TSC_1_TRILIN_OPT__SHIFT;
552    }
553 
554    if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
555       /* NOTE: must be deactivated for non-shadow textures */
556       so->tsc[0] |= (1 << 9);
557       so->tsc[0] |= (nvgl_comparison_op(cso->compare_func) & 0x7) << 10;
558    }
559 
560    f[0] = CLAMP(cso->lod_bias, -16.0f, 15.0f);
561    so->tsc[1] |= ((int)(f[0] * 256.0f) & 0x1fff) << 12;
562 
563    f[0] = CLAMP(cso->min_lod, 0.0f, 15.0f);
564    f[1] = CLAMP(cso->max_lod, 0.0f, 15.0f);
565    so->tsc[2] =
566       (((int)(f[1] * 256.0f) & 0xfff) << 12) | ((int)(f[0] * 256.0f) & 0xfff);
567 
568    so->tsc[2] |=
569       util_format_linear_float_to_srgb_8unorm(cso->border_color.f[0]) << 24;
570    so->tsc[3] =
571       util_format_linear_float_to_srgb_8unorm(cso->border_color.f[1]) << 12;
572    so->tsc[3] |=
573       util_format_linear_float_to_srgb_8unorm(cso->border_color.f[2]) << 20;
574 
575    so->tsc[4] = fui(cso->border_color.f[0]);
576    so->tsc[5] = fui(cso->border_color.f[1]);
577    so->tsc[6] = fui(cso->border_color.f[2]);
578    so->tsc[7] = fui(cso->border_color.f[3]);
579 
580    return (void *)so;
581 }
582 
583 static void
nv50_sampler_state_delete(struct pipe_context * pipe,void * hwcso)584 nv50_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
585 {
586    unsigned s, i;
587 
588    for (s = 0; s < 3; ++s) {
589       assert(nv50_context(pipe)->num_samplers[s] <= PIPE_MAX_SAMPLERS);
590       for (i = 0; i < nv50_context(pipe)->num_samplers[s]; ++i)
591          if (nv50_context(pipe)->samplers[s][i] == hwcso)
592             nv50_context(pipe)->samplers[s][i] = NULL;
593    }
594 
595    nv50_screen_tsc_free(nv50_context(pipe)->screen, nv50_tsc_entry(hwcso));
596 
597    FREE(hwcso);
598 }
599 
600 static inline void
nv50_stage_sampler_states_bind(struct nv50_context * nv50,int s,unsigned nr,void ** hwcsos)601 nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
602                                unsigned nr, void **hwcsos)
603 {
604    unsigned highest_found = 0;
605    unsigned i;
606 
607    assert(nr <= PIPE_MAX_SAMPLERS);
608    for (i = 0; i < nr; ++i) {
609       struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
610       struct nv50_tsc_entry *old = nv50->samplers[s][i];
611 
612       if (hwcso)
613          highest_found = i;
614 
615       nv50->samplers[s][i] = hwcso;
616       if (old)
617          nv50_screen_tsc_unlock(nv50->screen, old);
618    }
619    assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
620    if (nr >= nv50->num_samplers[s])
621       nv50->num_samplers[s] = highest_found + 1;
622 
623    nv50->dirty_3d |= NV50_NEW_3D_SAMPLERS;
624 }
625 
626 static void
nv50_vp_sampler_states_bind(struct pipe_context * pipe,unsigned nr,void ** s)627 nv50_vp_sampler_states_bind(struct pipe_context *pipe, unsigned nr, void **s)
628 {
629    nv50_stage_sampler_states_bind(nv50_context(pipe), 0, nr, s);
630 }
631 
632 static void
nv50_fp_sampler_states_bind(struct pipe_context * pipe,unsigned nr,void ** s)633 nv50_fp_sampler_states_bind(struct pipe_context *pipe, unsigned nr, void **s)
634 {
635    nv50_stage_sampler_states_bind(nv50_context(pipe), 2, nr, s);
636 }
637 
638 static void
nv50_gp_sampler_states_bind(struct pipe_context * pipe,unsigned nr,void ** s)639 nv50_gp_sampler_states_bind(struct pipe_context *pipe, unsigned nr, void **s)
640 {
641    nv50_stage_sampler_states_bind(nv50_context(pipe), 1, nr, s);
642 }
643 
644 static void
nv50_bind_sampler_states(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned num_samplers,void ** samplers)645 nv50_bind_sampler_states(struct pipe_context *pipe,
646                          enum pipe_shader_type shader, unsigned start,
647                          unsigned num_samplers, void **samplers)
648 {
649    assert(start == 0);
650    switch (shader) {
651    case PIPE_SHADER_VERTEX:
652       nv50_vp_sampler_states_bind(pipe, num_samplers, samplers);
653       break;
654    case PIPE_SHADER_GEOMETRY:
655       nv50_gp_sampler_states_bind(pipe, num_samplers, samplers);
656       break;
657    case PIPE_SHADER_FRAGMENT:
658       nv50_fp_sampler_states_bind(pipe, num_samplers, samplers);
659       break;
660    default:
661       assert(!"unexpected shader type");
662       break;
663    }
664 }
665 
666 
667 
668 /* NOTE: only called when not referenced anywhere, won't be bound */
669 static void
nv50_sampler_view_destroy(struct pipe_context * pipe,struct pipe_sampler_view * view)670 nv50_sampler_view_destroy(struct pipe_context *pipe,
671                           struct pipe_sampler_view *view)
672 {
673    pipe_resource_reference(&view->texture, NULL);
674 
675    nv50_screen_tic_free(nv50_context(pipe)->screen, nv50_tic_entry(view));
676 
677    FREE(nv50_tic_entry(view));
678 }
679 
680 static inline void
nv50_stage_set_sampler_views(struct nv50_context * nv50,int s,unsigned nr,struct pipe_sampler_view ** views)681 nv50_stage_set_sampler_views(struct nv50_context *nv50, int s,
682                              unsigned nr,
683                              struct pipe_sampler_view **views)
684 {
685    unsigned i;
686 
687    assert(nr <= PIPE_MAX_SAMPLERS);
688    for (i = 0; i < nr; ++i) {
689       struct pipe_sampler_view *view = views ? views[i] : NULL;
690       struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
691       if (old)
692          nv50_screen_tic_unlock(nv50->screen, old);
693 
694       if (view && view->texture) {
695          struct pipe_resource *res = view->texture;
696          if (res->target == PIPE_BUFFER &&
697              (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
698             nv50->textures_coherent[s] |= 1 << i;
699          else
700             nv50->textures_coherent[s] &= ~(1 << i);
701       } else {
702          nv50->textures_coherent[s] &= ~(1 << i);
703       }
704 
705       pipe_sampler_view_reference(&nv50->textures[s][i], view);
706    }
707 
708    assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS);
709    for (i = nr; i < nv50->num_textures[s]; ++i) {
710       struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
711       if (!old)
712          continue;
713       nv50_screen_tic_unlock(nv50->screen, old);
714 
715       pipe_sampler_view_reference(&nv50->textures[s][i], NULL);
716    }
717 
718    nv50->num_textures[s] = nr;
719 
720    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
721 
722    nv50->dirty_3d |= NV50_NEW_3D_TEXTURES;
723 }
724 
725 static void
nv50_set_sampler_views(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,struct pipe_sampler_view ** views)726 nv50_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
727                        unsigned start, unsigned nr,
728                        struct pipe_sampler_view **views)
729 {
730    assert(start == 0);
731    switch (shader) {
732    case PIPE_SHADER_VERTEX:
733       nv50_stage_set_sampler_views(nv50_context(pipe), 0, nr, views);
734       break;
735    case PIPE_SHADER_GEOMETRY:
736       nv50_stage_set_sampler_views(nv50_context(pipe), 1, nr, views);
737       break;
738    case PIPE_SHADER_FRAGMENT:
739       nv50_stage_set_sampler_views(nv50_context(pipe), 2, nr, views);
740       break;
741    default:
742       ;
743    }
744 }
745 
746 
747 
748 /* ============================= SHADERS =======================================
749  */
750 
751 static void *
nv50_sp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso,unsigned type)752 nv50_sp_state_create(struct pipe_context *pipe,
753                      const struct pipe_shader_state *cso, unsigned type)
754 {
755    struct nv50_program *prog;
756 
757    prog = CALLOC_STRUCT(nv50_program);
758    if (!prog)
759       return NULL;
760 
761    prog->type = type;
762    prog->pipe.type = cso->type;
763 
764    switch (cso->type) {
765    case PIPE_SHADER_IR_TGSI:
766       prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
767       break;
768    case PIPE_SHADER_IR_NIR:
769       prog->pipe.ir.nir = cso->ir.nir;
770       break;
771    default:
772       assert(!"unsupported IR!");
773       free(prog);
774       return NULL;
775    }
776 
777    if (cso->stream_output.num_outputs)
778       prog->pipe.stream_output = cso->stream_output;
779 
780    prog->translated = nv50_program_translate(
781          prog, nv50_context(pipe)->screen->base.device->chipset,
782          &nouveau_context(pipe)->debug);
783 
784    return (void *)prog;
785 }
786 
787 static void
nv50_sp_state_delete(struct pipe_context * pipe,void * hwcso)788 nv50_sp_state_delete(struct pipe_context *pipe, void *hwcso)
789 {
790    struct nv50_program *prog = (struct nv50_program *)hwcso;
791 
792    nv50_program_destroy(nv50_context(pipe), prog);
793 
794    if (prog->pipe.type == PIPE_SHADER_IR_TGSI)
795       FREE((void *)prog->pipe.tokens);
796    else if (prog->pipe.type == PIPE_SHADER_IR_NIR)
797       ralloc_free(prog->pipe.ir.nir);
798    FREE(prog);
799 }
800 
801 static void *
nv50_vp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)802 nv50_vp_state_create(struct pipe_context *pipe,
803                      const struct pipe_shader_state *cso)
804 {
805    return nv50_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
806 }
807 
808 static void
nv50_vp_state_bind(struct pipe_context * pipe,void * hwcso)809 nv50_vp_state_bind(struct pipe_context *pipe, void *hwcso)
810 {
811     struct nv50_context *nv50 = nv50_context(pipe);
812 
813     nv50->vertprog = hwcso;
814     nv50->dirty_3d |= NV50_NEW_3D_VERTPROG;
815 }
816 
817 static void *
nv50_fp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)818 nv50_fp_state_create(struct pipe_context *pipe,
819                      const struct pipe_shader_state *cso)
820 {
821    return nv50_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
822 }
823 
824 static void
nv50_fp_state_bind(struct pipe_context * pipe,void * hwcso)825 nv50_fp_state_bind(struct pipe_context *pipe, void *hwcso)
826 {
827     struct nv50_context *nv50 = nv50_context(pipe);
828 
829     nv50->fragprog = hwcso;
830     nv50->dirty_3d |= NV50_NEW_3D_FRAGPROG;
831 }
832 
833 static void *
nv50_gp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)834 nv50_gp_state_create(struct pipe_context *pipe,
835                      const struct pipe_shader_state *cso)
836 {
837    return nv50_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
838 }
839 
840 static void
nv50_gp_state_bind(struct pipe_context * pipe,void * hwcso)841 nv50_gp_state_bind(struct pipe_context *pipe, void *hwcso)
842 {
843     struct nv50_context *nv50 = nv50_context(pipe);
844 
845     nv50->gmtyprog = hwcso;
846     nv50->dirty_3d |= NV50_NEW_3D_GMTYPROG;
847 }
848 
849 static void *
nv50_cp_state_create(struct pipe_context * pipe,const struct pipe_compute_state * cso)850 nv50_cp_state_create(struct pipe_context *pipe,
851                      const struct pipe_compute_state *cso)
852 {
853    struct nv50_program *prog;
854 
855    prog = CALLOC_STRUCT(nv50_program);
856    if (!prog)
857       return NULL;
858    prog->type = PIPE_SHADER_COMPUTE;
859    prog->pipe.type = cso->ir_type;
860 
861    switch(cso->ir_type) {
862    case PIPE_SHADER_IR_TGSI:
863       prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
864       break;
865    case PIPE_SHADER_IR_NIR:
866       prog->pipe.ir.nir = (nir_shader *)cso->prog;
867       break;
868    default:
869       assert(!"unsupported IR!");
870       free(prog);
871       return NULL;
872    }
873 
874    prog->cp.smem_size = cso->req_local_mem;
875    prog->cp.lmem_size = cso->req_private_mem;
876    prog->parm_size = cso->req_input_mem;
877 
878    return (void *)prog;
879 }
880 
881 static void
nv50_cp_state_bind(struct pipe_context * pipe,void * hwcso)882 nv50_cp_state_bind(struct pipe_context *pipe, void *hwcso)
883 {
884    struct nv50_context *nv50 = nv50_context(pipe);
885 
886    nv50->compprog = hwcso;
887    nv50->dirty_cp |= NV50_NEW_CP_PROGRAM;
888 }
889 
890 static void
nv50_set_constant_buffer(struct pipe_context * pipe,enum pipe_shader_type shader,uint index,const struct pipe_constant_buffer * cb)891 nv50_set_constant_buffer(struct pipe_context *pipe,
892                          enum pipe_shader_type shader, uint index,
893                          const struct pipe_constant_buffer *cb)
894 {
895    struct nv50_context *nv50 = nv50_context(pipe);
896    struct pipe_resource *res = cb ? cb->buffer : NULL;
897    const unsigned s = nv50_context_shader_stage(shader);
898    const unsigned i = index;
899 
900    if (shader == PIPE_SHADER_COMPUTE)
901       return;
902 
903    assert(i < NV50_MAX_PIPE_CONSTBUFS);
904    if (nv50->constbuf[s][i].user)
905       nv50->constbuf[s][i].u.buf = NULL;
906    else
907    if (nv50->constbuf[s][i].u.buf) {
908       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_CB(s, i));
909       nv04_resource(nv50->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
910    }
911    pipe_resource_reference(&nv50->constbuf[s][i].u.buf, res);
912 
913    nv50->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
914    if (nv50->constbuf[s][i].user) {
915       nv50->constbuf[s][i].u.data = cb->user_buffer;
916       nv50->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
917       nv50->constbuf_valid[s] |= 1 << i;
918       nv50->constbuf_coherent[s] &= ~(1 << i);
919    } else
920    if (res) {
921       nv50->constbuf[s][i].offset = cb->buffer_offset;
922       nv50->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
923       nv50->constbuf_valid[s] |= 1 << i;
924       if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
925          nv50->constbuf_coherent[s] |= 1 << i;
926       else
927          nv50->constbuf_coherent[s] &= ~(1 << i);
928    } else {
929       nv50->constbuf_valid[s] &= ~(1 << i);
930       nv50->constbuf_coherent[s] &= ~(1 << i);
931    }
932    nv50->constbuf_dirty[s] |= 1 << i;
933 
934    nv50->dirty_3d |= NV50_NEW_3D_CONSTBUF;
935 }
936 
937 /* =============================================================================
938  */
939 
940 static void
nv50_set_blend_color(struct pipe_context * pipe,const struct pipe_blend_color * bcol)941 nv50_set_blend_color(struct pipe_context *pipe,
942                      const struct pipe_blend_color *bcol)
943 {
944    struct nv50_context *nv50 = nv50_context(pipe);
945 
946    nv50->blend_colour = *bcol;
947    nv50->dirty_3d |= NV50_NEW_3D_BLEND_COLOUR;
948 }
949 
950 static void
nv50_set_stencil_ref(struct pipe_context * pipe,const struct pipe_stencil_ref * sr)951 nv50_set_stencil_ref(struct pipe_context *pipe,
952                      const struct pipe_stencil_ref *sr)
953 {
954    struct nv50_context *nv50 = nv50_context(pipe);
955 
956    nv50->stencil_ref = *sr;
957    nv50->dirty_3d |= NV50_NEW_3D_STENCIL_REF;
958 }
959 
960 static void
nv50_set_clip_state(struct pipe_context * pipe,const struct pipe_clip_state * clip)961 nv50_set_clip_state(struct pipe_context *pipe,
962                     const struct pipe_clip_state *clip)
963 {
964    struct nv50_context *nv50 = nv50_context(pipe);
965 
966    memcpy(nv50->clip.ucp, clip->ucp, sizeof(clip->ucp));
967 
968    nv50->dirty_3d |= NV50_NEW_3D_CLIP;
969 }
970 
971 static void
nv50_set_sample_mask(struct pipe_context * pipe,unsigned sample_mask)972 nv50_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
973 {
974    struct nv50_context *nv50 = nv50_context(pipe);
975 
976    nv50->sample_mask = sample_mask;
977    nv50->dirty_3d |= NV50_NEW_3D_SAMPLE_MASK;
978 }
979 
980 static void
nv50_set_min_samples(struct pipe_context * pipe,unsigned min_samples)981 nv50_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
982 {
983    struct nv50_context *nv50 = nv50_context(pipe);
984 
985    if (nv50->min_samples != min_samples) {
986       nv50->min_samples = min_samples;
987       nv50->dirty_3d |= NV50_NEW_3D_MIN_SAMPLES;
988    }
989 }
990 
991 static void
nv50_set_framebuffer_state(struct pipe_context * pipe,const struct pipe_framebuffer_state * fb)992 nv50_set_framebuffer_state(struct pipe_context *pipe,
993                            const struct pipe_framebuffer_state *fb)
994 {
995    struct nv50_context *nv50 = nv50_context(pipe);
996 
997    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
998 
999    util_copy_framebuffer_state(&nv50->framebuffer, fb);
1000 
1001    nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_TEXTURES;
1002 }
1003 
1004 static void
nv50_set_polygon_stipple(struct pipe_context * pipe,const struct pipe_poly_stipple * stipple)1005 nv50_set_polygon_stipple(struct pipe_context *pipe,
1006                          const struct pipe_poly_stipple *stipple)
1007 {
1008    struct nv50_context *nv50 = nv50_context(pipe);
1009 
1010    nv50->stipple = *stipple;
1011    nv50->dirty_3d |= NV50_NEW_3D_STIPPLE;
1012 }
1013 
1014 static void
nv50_set_scissor_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_scissors,const struct pipe_scissor_state * scissor)1015 nv50_set_scissor_states(struct pipe_context *pipe,
1016                         unsigned start_slot,
1017                         unsigned num_scissors,
1018                         const struct pipe_scissor_state *scissor)
1019 {
1020    struct nv50_context *nv50 = nv50_context(pipe);
1021    int i;
1022 
1023    assert(start_slot + num_scissors <= NV50_MAX_VIEWPORTS);
1024    for (i = 0; i < num_scissors; i++) {
1025       if (!memcmp(&nv50->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
1026          continue;
1027       nv50->scissors[start_slot + i] = scissor[i];
1028       nv50->scissors_dirty |= 1 << (start_slot + i);
1029       nv50->dirty_3d |= NV50_NEW_3D_SCISSOR;
1030    }
1031 }
1032 
1033 static void
nv50_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt)1034 nv50_set_viewport_states(struct pipe_context *pipe,
1035                          unsigned start_slot,
1036                          unsigned num_viewports,
1037                          const struct pipe_viewport_state *vpt)
1038 {
1039    struct nv50_context *nv50 = nv50_context(pipe);
1040    int i;
1041 
1042    assert(start_slot + num_viewports <= NV50_MAX_VIEWPORTS);
1043    for (i = 0; i < num_viewports; i++) {
1044       if (!memcmp(&nv50->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
1045          continue;
1046       nv50->viewports[start_slot + i] = vpt[i];
1047       nv50->viewports_dirty |= 1 << (start_slot + i);
1048       nv50->dirty_3d |= NV50_NEW_3D_VIEWPORT;
1049    }
1050 }
1051 
1052 static void
nv50_set_window_rectangles(struct pipe_context * pipe,bool include,unsigned num_rectangles,const struct pipe_scissor_state * rectangles)1053 nv50_set_window_rectangles(struct pipe_context *pipe,
1054                            bool include,
1055                            unsigned num_rectangles,
1056                            const struct pipe_scissor_state *rectangles)
1057 {
1058    struct nv50_context *nv50 = nv50_context(pipe);
1059 
1060    nv50->window_rect.inclusive = include;
1061    nv50->window_rect.rects = MIN2(num_rectangles, NV50_MAX_WINDOW_RECTANGLES);
1062    memcpy(nv50->window_rect.rect, rectangles,
1063           sizeof(struct pipe_scissor_state) * nv50->window_rect.rects);
1064 
1065    nv50->dirty_3d |= NV50_NEW_3D_WINDOW_RECTS;
1066 }
1067 
1068 static void
nv50_set_vertex_buffers(struct pipe_context * pipe,unsigned start_slot,unsigned count,const struct pipe_vertex_buffer * vb)1069 nv50_set_vertex_buffers(struct pipe_context *pipe,
1070                         unsigned start_slot, unsigned count,
1071                         const struct pipe_vertex_buffer *vb)
1072 {
1073    struct nv50_context *nv50 = nv50_context(pipe);
1074    unsigned i;
1075 
1076    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX);
1077    nv50->dirty_3d |= NV50_NEW_3D_ARRAYS;
1078 
1079    util_set_vertex_buffers_count(nv50->vtxbuf, &nv50->num_vtxbufs, vb,
1080                                  start_slot, count);
1081 
1082    if (!vb) {
1083       nv50->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1084       nv50->vbo_constant &= ~(((1ull << count) - 1) << start_slot);
1085       nv50->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
1086       return;
1087    }
1088 
1089    for (i = 0; i < count; ++i) {
1090       unsigned dst_index = start_slot + i;
1091 
1092       if (vb[i].is_user_buffer) {
1093          nv50->vbo_user |= 1 << dst_index;
1094          if (!vb[i].stride)
1095             nv50->vbo_constant |= 1 << dst_index;
1096          else
1097             nv50->vbo_constant &= ~(1 << dst_index);
1098          nv50->vtxbufs_coherent &= ~(1 << dst_index);
1099       } else {
1100          nv50->vbo_user &= ~(1 << dst_index);
1101          nv50->vbo_constant &= ~(1 << dst_index);
1102 
1103          if (vb[i].buffer.resource &&
1104              vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1105             nv50->vtxbufs_coherent |= (1 << dst_index);
1106          else
1107             nv50->vtxbufs_coherent &= ~(1 << dst_index);
1108       }
1109    }
1110 }
1111 
1112 static void
nv50_vertex_state_bind(struct pipe_context * pipe,void * hwcso)1113 nv50_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1114 {
1115    struct nv50_context *nv50 = nv50_context(pipe);
1116 
1117    nv50->vertex = hwcso;
1118    nv50->dirty_3d |= NV50_NEW_3D_VERTEX;
1119 }
1120 
1121 static struct pipe_stream_output_target *
nv50_so_target_create(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size)1122 nv50_so_target_create(struct pipe_context *pipe,
1123                       struct pipe_resource *res,
1124                       unsigned offset, unsigned size)
1125 {
1126    struct nv04_resource *buf = (struct nv04_resource *)res;
1127    struct nv50_so_target *targ = MALLOC_STRUCT(nv50_so_target);
1128    if (!targ)
1129       return NULL;
1130 
1131    if (nouveau_context(pipe)->screen->class_3d >= NVA0_3D_CLASS) {
1132       targ->pq = pipe->create_query(pipe,
1133                                     NVA0_HW_QUERY_STREAM_OUTPUT_BUFFER_OFFSET, 0);
1134       if (!targ->pq) {
1135          FREE(targ);
1136          return NULL;
1137       }
1138    } else {
1139       targ->pq = NULL;
1140    }
1141    targ->clean = true;
1142 
1143    targ->pipe.buffer_size = size;
1144    targ->pipe.buffer_offset = offset;
1145    targ->pipe.context = pipe;
1146    targ->pipe.buffer = NULL;
1147    pipe_resource_reference(&targ->pipe.buffer, res);
1148    pipe_reference_init(&targ->pipe.reference, 1);
1149 
1150    assert(buf->base.target == PIPE_BUFFER);
1151    util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
1152 
1153    return &targ->pipe;
1154 }
1155 
1156 static void
nva0_so_target_save_offset(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg,unsigned index,bool serialize)1157 nva0_so_target_save_offset(struct pipe_context *pipe,
1158                            struct pipe_stream_output_target *ptarg,
1159                            unsigned index, bool serialize)
1160 {
1161    struct nv50_so_target *targ = nv50_so_target(ptarg);
1162 
1163    if (serialize) {
1164       struct nouveau_pushbuf *push = nv50_context(pipe)->base.pushbuf;
1165       PUSH_SPACE(push, 2);
1166       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
1167       PUSH_DATA (push, 0);
1168    }
1169 
1170    nv50_query(targ->pq)->index = index;
1171    pipe->end_query(pipe, targ->pq);
1172 }
1173 
1174 static void
nv50_so_target_destroy(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg)1175 nv50_so_target_destroy(struct pipe_context *pipe,
1176                        struct pipe_stream_output_target *ptarg)
1177 {
1178    struct nv50_so_target *targ = nv50_so_target(ptarg);
1179    if (targ->pq)
1180       pipe->destroy_query(pipe, targ->pq);
1181    pipe_resource_reference(&targ->pipe.buffer, NULL);
1182    FREE(targ);
1183 }
1184 
1185 static void
nv50_set_stream_output_targets(struct pipe_context * pipe,unsigned num_targets,struct pipe_stream_output_target ** targets,const unsigned * offsets)1186 nv50_set_stream_output_targets(struct pipe_context *pipe,
1187                                unsigned num_targets,
1188                                struct pipe_stream_output_target **targets,
1189                                const unsigned *offsets)
1190 {
1191    struct nv50_context *nv50 = nv50_context(pipe);
1192    unsigned i;
1193    bool serialize = true;
1194    const bool can_resume = nv50->screen->base.class_3d >= NVA0_3D_CLASS;
1195 
1196    assert(num_targets <= 4);
1197 
1198    for (i = 0; i < num_targets; ++i) {
1199       const bool changed = nv50->so_target[i] != targets[i];
1200       const bool append = (offsets[i] == (unsigned)-1);
1201       if (!changed && append)
1202          continue;
1203       nv50->so_targets_dirty |= 1 << i;
1204 
1205       if (can_resume && changed && nv50->so_target[i]) {
1206          nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1207          serialize = false;
1208       }
1209 
1210       if (targets[i] && !append)
1211          nv50_so_target(targets[i])->clean = true;
1212 
1213       pipe_so_target_reference(&nv50->so_target[i], targets[i]);
1214    }
1215    for (; i < nv50->num_so_targets; ++i) {
1216       if (can_resume && nv50->so_target[i]) {
1217          nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1218          serialize = false;
1219       }
1220       pipe_so_target_reference(&nv50->so_target[i], NULL);
1221       nv50->so_targets_dirty |= 1 << i;
1222    }
1223    nv50->num_so_targets = num_targets;
1224 
1225    if (nv50->so_targets_dirty) {
1226       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_SO);
1227       nv50->dirty_3d |= NV50_NEW_3D_STRMOUT;
1228    }
1229 }
1230 
1231 static void
nv50_set_compute_resources(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_surface ** resources)1232 nv50_set_compute_resources(struct pipe_context *pipe,
1233                            unsigned start, unsigned nr,
1234                            struct pipe_surface **resources)
1235 {
1236    /* TODO: bind surfaces */
1237 }
1238 
1239 static inline void
nv50_set_global_handle(uint32_t * phandle,struct pipe_resource * res)1240 nv50_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1241 {
1242    struct nv04_resource *buf = nv04_resource(res);
1243    if (buf) {
1244       uint64_t limit = (buf->address + buf->base.width0) - 1;
1245       if (limit < (1ULL << 32)) {
1246          *phandle = (uint32_t)buf->address;
1247       } else {
1248          NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1249                      "resource not contained within 32-bit address space !\n");
1250          *phandle = 0;
1251       }
1252    } else {
1253       *phandle = 0;
1254    }
1255 }
1256 
1257 static void
nv50_set_global_bindings(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_resource ** resources,uint32_t ** handles)1258 nv50_set_global_bindings(struct pipe_context *pipe,
1259                          unsigned start, unsigned nr,
1260                          struct pipe_resource **resources,
1261                          uint32_t **handles)
1262 {
1263    struct nv50_context *nv50 = nv50_context(pipe);
1264    struct pipe_resource **ptr;
1265    unsigned i;
1266    const unsigned end = start + nr;
1267 
1268    if (nv50->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1269       const unsigned old_size = nv50->global_residents.size;
1270       if (util_dynarray_resize(&nv50->global_residents, struct pipe_resource *, end)) {
1271          memset((uint8_t *)nv50->global_residents.data + old_size, 0,
1272                 nv50->global_residents.size - old_size);
1273       } else {
1274          NOUVEAU_ERR("Could not resize global residents array\n");
1275          return;
1276       }
1277    }
1278 
1279    if (resources) {
1280       ptr = util_dynarray_element(
1281          &nv50->global_residents, struct pipe_resource *, start);
1282       for (i = 0; i < nr; ++i) {
1283          pipe_resource_reference(&ptr[i], resources[i]);
1284          nv50_set_global_handle(handles[i], resources[i]);
1285       }
1286    } else {
1287       ptr = util_dynarray_element(
1288          &nv50->global_residents, struct pipe_resource *, start);
1289       for (i = 0; i < nr; ++i)
1290          pipe_resource_reference(&ptr[i], NULL);
1291    }
1292 
1293    nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_GLOBAL);
1294 
1295    nv50->dirty_cp |= NV50_NEW_CP_GLOBALS;
1296 }
1297 
1298 void
nv50_init_state_functions(struct nv50_context * nv50)1299 nv50_init_state_functions(struct nv50_context *nv50)
1300 {
1301    struct pipe_context *pipe = &nv50->base.pipe;
1302 
1303    pipe->create_blend_state = nv50_blend_state_create;
1304    pipe->bind_blend_state = nv50_blend_state_bind;
1305    pipe->delete_blend_state = nv50_blend_state_delete;
1306 
1307    pipe->create_rasterizer_state = nv50_rasterizer_state_create;
1308    pipe->bind_rasterizer_state = nv50_rasterizer_state_bind;
1309    pipe->delete_rasterizer_state = nv50_rasterizer_state_delete;
1310 
1311    pipe->create_depth_stencil_alpha_state = nv50_zsa_state_create;
1312    pipe->bind_depth_stencil_alpha_state = nv50_zsa_state_bind;
1313    pipe->delete_depth_stencil_alpha_state = nv50_zsa_state_delete;
1314 
1315    pipe->create_sampler_state = nv50_sampler_state_create;
1316    pipe->delete_sampler_state = nv50_sampler_state_delete;
1317    pipe->bind_sampler_states   = nv50_bind_sampler_states;
1318 
1319    pipe->create_sampler_view = nv50_create_sampler_view;
1320    pipe->sampler_view_destroy = nv50_sampler_view_destroy;
1321    pipe->set_sampler_views = nv50_set_sampler_views;
1322 
1323    pipe->create_vs_state = nv50_vp_state_create;
1324    pipe->create_fs_state = nv50_fp_state_create;
1325    pipe->create_gs_state = nv50_gp_state_create;
1326    pipe->create_compute_state = nv50_cp_state_create;
1327    pipe->bind_vs_state = nv50_vp_state_bind;
1328    pipe->bind_fs_state = nv50_fp_state_bind;
1329    pipe->bind_gs_state = nv50_gp_state_bind;
1330    pipe->bind_compute_state = nv50_cp_state_bind;
1331    pipe->delete_vs_state = nv50_sp_state_delete;
1332    pipe->delete_fs_state = nv50_sp_state_delete;
1333    pipe->delete_gs_state = nv50_sp_state_delete;
1334    pipe->delete_compute_state = nv50_sp_state_delete;
1335 
1336    pipe->set_blend_color = nv50_set_blend_color;
1337    pipe->set_stencil_ref = nv50_set_stencil_ref;
1338    pipe->set_clip_state = nv50_set_clip_state;
1339    pipe->set_sample_mask = nv50_set_sample_mask;
1340    pipe->set_min_samples = nv50_set_min_samples;
1341    pipe->set_constant_buffer = nv50_set_constant_buffer;
1342    pipe->set_framebuffer_state = nv50_set_framebuffer_state;
1343    pipe->set_polygon_stipple = nv50_set_polygon_stipple;
1344    pipe->set_scissor_states = nv50_set_scissor_states;
1345    pipe->set_viewport_states = nv50_set_viewport_states;
1346    pipe->set_window_rectangles = nv50_set_window_rectangles;
1347 
1348    pipe->create_vertex_elements_state = nv50_vertex_state_create;
1349    pipe->delete_vertex_elements_state = nv50_vertex_state_delete;
1350    pipe->bind_vertex_elements_state = nv50_vertex_state_bind;
1351 
1352    pipe->set_vertex_buffers = nv50_set_vertex_buffers;
1353 
1354    pipe->create_stream_output_target = nv50_so_target_create;
1355    pipe->stream_output_target_destroy = nv50_so_target_destroy;
1356    pipe->set_stream_output_targets = nv50_set_stream_output_targets;
1357 
1358    pipe->set_global_binding = nv50_set_global_bindings;
1359    pipe->set_compute_resources = nv50_set_compute_resources;
1360 
1361    nv50->sample_mask = ~0;
1362    nv50->min_samples = 1;
1363 }
1364