1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
29
30 #include "util/u_cpu_detect.h"
31 #include "util/u_debug.h"
32 #include "util/u_memory.h"
33 #include "util/format/u_format.h"
34 #include "util/u_hash_table.h"
35 #include "util/u_screen.h"
36 #include "util/u_transfer_helper.h"
37 #include "util/ralloc.h"
38
39 #include <xf86drm.h>
40 #include "drm-uapi/drm_fourcc.h"
41 #include "drm-uapi/vc4_drm.h"
42 #include "vc4_screen.h"
43 #include "vc4_context.h"
44 #include "vc4_resource.h"
45
46 static const struct debug_named_value debug_options[] = {
47 { "cl", VC4_DEBUG_CL,
48 "Dump command list during creation" },
49 { "surf", VC4_DEBUG_SURFACE,
50 "Dump surface layouts" },
51 { "qpu", VC4_DEBUG_QPU,
52 "Dump generated QPU instructions" },
53 { "qir", VC4_DEBUG_QIR,
54 "Dump QPU IR during program compile" },
55 { "nir", VC4_DEBUG_NIR,
56 "Dump NIR during program compile" },
57 { "tgsi", VC4_DEBUG_TGSI,
58 "Dump TGSI during program compile" },
59 { "shaderdb", VC4_DEBUG_SHADERDB,
60 "Dump program compile information for shader-db analysis" },
61 { "perf", VC4_DEBUG_PERF,
62 "Print during performance-related events" },
63 { "norast", VC4_DEBUG_NORAST,
64 "Skip actual hardware execution of commands" },
65 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
66 "Flush after each draw call" },
67 { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
68 "Wait for finish after each flush" },
69 #ifdef USE_VC4_SIMULATOR
70 { "dump", VC4_DEBUG_DUMP,
71 "Write a GPU command stream trace file" },
72 #endif
73 { NULL }
74 };
75
76 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", debug_options, 0)
77 uint32_t vc4_debug;
78
79 static const char *
vc4_screen_get_name(struct pipe_screen * pscreen)80 vc4_screen_get_name(struct pipe_screen *pscreen)
81 {
82 struct vc4_screen *screen = vc4_screen(pscreen);
83
84 if (!screen->name) {
85 screen->name = ralloc_asprintf(screen,
86 "VC4 V3D %d.%d",
87 screen->v3d_ver / 10,
88 screen->v3d_ver % 10);
89 }
90
91 return screen->name;
92 }
93
94 static const char *
vc4_screen_get_vendor(struct pipe_screen * pscreen)95 vc4_screen_get_vendor(struct pipe_screen *pscreen)
96 {
97 return "Broadcom";
98 }
99
100 static void
vc4_screen_destroy(struct pipe_screen * pscreen)101 vc4_screen_destroy(struct pipe_screen *pscreen)
102 {
103 struct vc4_screen *screen = vc4_screen(pscreen);
104
105 _mesa_hash_table_destroy(screen->bo_handles, NULL);
106 vc4_bufmgr_destroy(pscreen);
107 slab_destroy_parent(&screen->transfer_pool);
108 free(screen->ro);
109
110 #ifdef USE_VC4_SIMULATOR
111 vc4_simulator_destroy(screen);
112 #endif
113
114 u_transfer_helper_destroy(pscreen->transfer_helper);
115
116 close(screen->fd);
117 ralloc_free(pscreen);
118 }
119
120 static bool
vc4_has_feature(struct vc4_screen * screen,uint32_t feature)121 vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
122 {
123 struct drm_vc4_get_param p = {
124 .param = feature,
125 };
126 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
127
128 if (ret != 0)
129 return false;
130
131 return p.value;
132 }
133
134 static int
vc4_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)135 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
136 {
137 struct vc4_screen *screen = vc4_screen(pscreen);
138
139 switch (param) {
140 /* Supported features (boolean caps). */
141 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
142 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
143 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
144 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
145 case PIPE_CAP_NPOT_TEXTURES:
146 case PIPE_CAP_SHAREABLE_SHADERS:
147 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
148 case PIPE_CAP_TEXTURE_MULTISAMPLE:
149 case PIPE_CAP_TEXTURE_SWIZZLE:
150 case PIPE_CAP_TEXTURE_BARRIER:
151 case PIPE_CAP_TGSI_TEXCOORD:
152 return 1;
153
154 case PIPE_CAP_NATIVE_FENCE_FD:
155 return screen->has_syncobj;
156
157 case PIPE_CAP_TILE_RASTER_ORDER:
158 return vc4_has_feature(screen,
159 DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER);
160
161 /* lying for GL 2.0 */
162 case PIPE_CAP_OCCLUSION_QUERY:
163 case PIPE_CAP_POINT_SPRITE:
164 return 1;
165
166 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
167 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
168 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
169 return 1;
170
171 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
172 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
173 return 1;
174
175 /* Texturing. */
176 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
177 return 2048;
178 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
179 return VC4_MAX_MIP_LEVELS;
180 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
181 /* Note: Not supported in hardware, just faking it. */
182 return 5;
183
184 case PIPE_CAP_MAX_VARYINGS:
185 return 8;
186
187 case PIPE_CAP_VENDOR_ID:
188 return 0x14E4;
189 case PIPE_CAP_ACCELERATED:
190 return 1;
191 case PIPE_CAP_VIDEO_MEMORY: {
192 uint64_t system_memory;
193
194 if (!os_get_total_physical_memory(&system_memory))
195 return 0;
196
197 return (int)(system_memory >> 20);
198 }
199 case PIPE_CAP_UMA:
200 return 1;
201
202 default:
203 return u_pipe_screen_get_param_defaults(pscreen, param);
204 }
205 }
206
207 static float
vc4_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)208 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
209 {
210 switch (param) {
211 case PIPE_CAPF_MAX_LINE_WIDTH:
212 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
213 return 32;
214
215 case PIPE_CAPF_MAX_POINT_WIDTH:
216 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
217 return 512.0f;
218
219 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
220 return 0.0f;
221 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
222 return 0.0f;
223
224 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
225 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
226 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
227 return 0.0f;
228 default:
229 fprintf(stderr, "unknown paramf %d\n", param);
230 return 0;
231 }
232 }
233
234 static int
vc4_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)235 vc4_screen_get_shader_param(struct pipe_screen *pscreen,
236 enum pipe_shader_type shader,
237 enum pipe_shader_cap param)
238 {
239 if (shader != PIPE_SHADER_VERTEX &&
240 shader != PIPE_SHADER_FRAGMENT) {
241 return 0;
242 }
243
244 /* this is probably not totally correct.. but it's a start: */
245 switch (param) {
246 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
247 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
248 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
249 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
250 return 16384;
251
252 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
253 return vc4_screen(pscreen)->has_control_flow;
254
255 case PIPE_SHADER_CAP_MAX_INPUTS:
256 return 8;
257 case PIPE_SHADER_CAP_MAX_OUTPUTS:
258 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
259 case PIPE_SHADER_CAP_MAX_TEMPS:
260 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
261 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
262 return 16 * 1024 * sizeof(float);
263 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
264 return 1;
265 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
266 return 0;
267 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
268 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
269 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
270 return 0;
271 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
272 return 1;
273 case PIPE_SHADER_CAP_SUBROUTINES:
274 return 0;
275 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
276 return 0;
277 case PIPE_SHADER_CAP_INTEGERS:
278 return 1;
279 case PIPE_SHADER_CAP_INT64_ATOMICS:
280 case PIPE_SHADER_CAP_FP16:
281 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
282 case PIPE_SHADER_CAP_INT16:
283 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
284 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
285 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
286 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
287 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
288 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
289 return 0;
290 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
291 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
292 return VC4_MAX_TEXTURE_SAMPLERS;
293 case PIPE_SHADER_CAP_PREFERRED_IR:
294 return PIPE_SHADER_IR_NIR;
295 case PIPE_SHADER_CAP_SUPPORTED_IRS:
296 return 0;
297 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
298 return 32;
299 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
300 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
301 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
302 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
303 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
304 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
305 return 0;
306 default:
307 fprintf(stderr, "unknown shader param %d\n", param);
308 return 0;
309 }
310 return 0;
311 }
312
313 static bool
vc4_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)314 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
315 enum pipe_format format,
316 enum pipe_texture_target target,
317 unsigned sample_count,
318 unsigned storage_sample_count,
319 unsigned usage)
320 {
321 struct vc4_screen *screen = vc4_screen(pscreen);
322
323 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
324 return false;
325
326 if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
327 return false;
328
329 if (target >= PIPE_MAX_TEXTURE_TYPES) {
330 return false;
331 }
332
333 if (usage & PIPE_BIND_VERTEX_BUFFER) {
334 switch (format) {
335 case PIPE_FORMAT_R32G32B32A32_FLOAT:
336 case PIPE_FORMAT_R32G32B32_FLOAT:
337 case PIPE_FORMAT_R32G32_FLOAT:
338 case PIPE_FORMAT_R32_FLOAT:
339 case PIPE_FORMAT_R32G32B32A32_SNORM:
340 case PIPE_FORMAT_R32G32B32_SNORM:
341 case PIPE_FORMAT_R32G32_SNORM:
342 case PIPE_FORMAT_R32_SNORM:
343 case PIPE_FORMAT_R32G32B32A32_SSCALED:
344 case PIPE_FORMAT_R32G32B32_SSCALED:
345 case PIPE_FORMAT_R32G32_SSCALED:
346 case PIPE_FORMAT_R32_SSCALED:
347 case PIPE_FORMAT_R16G16B16A16_UNORM:
348 case PIPE_FORMAT_R16G16B16_UNORM:
349 case PIPE_FORMAT_R16G16_UNORM:
350 case PIPE_FORMAT_R16_UNORM:
351 case PIPE_FORMAT_R16G16B16A16_SNORM:
352 case PIPE_FORMAT_R16G16B16_SNORM:
353 case PIPE_FORMAT_R16G16_SNORM:
354 case PIPE_FORMAT_R16_SNORM:
355 case PIPE_FORMAT_R16G16B16A16_USCALED:
356 case PIPE_FORMAT_R16G16B16_USCALED:
357 case PIPE_FORMAT_R16G16_USCALED:
358 case PIPE_FORMAT_R16_USCALED:
359 case PIPE_FORMAT_R16G16B16A16_SSCALED:
360 case PIPE_FORMAT_R16G16B16_SSCALED:
361 case PIPE_FORMAT_R16G16_SSCALED:
362 case PIPE_FORMAT_R16_SSCALED:
363 case PIPE_FORMAT_R8G8B8A8_UNORM:
364 case PIPE_FORMAT_R8G8B8_UNORM:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8_UNORM:
367 case PIPE_FORMAT_R8G8B8A8_SNORM:
368 case PIPE_FORMAT_R8G8B8_SNORM:
369 case PIPE_FORMAT_R8G8_SNORM:
370 case PIPE_FORMAT_R8_SNORM:
371 case PIPE_FORMAT_R8G8B8A8_USCALED:
372 case PIPE_FORMAT_R8G8B8_USCALED:
373 case PIPE_FORMAT_R8G8_USCALED:
374 case PIPE_FORMAT_R8_USCALED:
375 case PIPE_FORMAT_R8G8B8A8_SSCALED:
376 case PIPE_FORMAT_R8G8B8_SSCALED:
377 case PIPE_FORMAT_R8G8_SSCALED:
378 case PIPE_FORMAT_R8_SSCALED:
379 break;
380 default:
381 return false;
382 }
383 }
384
385 if ((usage & PIPE_BIND_RENDER_TARGET) &&
386 !vc4_rt_format_supported(format)) {
387 return false;
388 }
389
390 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
391 (!vc4_tex_format_supported(format) ||
392 (format == PIPE_FORMAT_ETC1_RGB8 && !screen->has_etc1))) {
393 return false;
394 }
395
396 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
397 format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
398 format != PIPE_FORMAT_X8Z24_UNORM) {
399 return false;
400 }
401
402 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
403 format != PIPE_FORMAT_I8_UINT &&
404 format != PIPE_FORMAT_I16_UINT) {
405 return false;
406 }
407
408 return true;
409 }
410
411 static void
vc4_screen_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * count)412 vc4_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
413 enum pipe_format format, int max,
414 uint64_t *modifiers,
415 unsigned int *external_only,
416 int *count)
417 {
418 int m, i;
419 bool tex_will_lower;
420 uint64_t available_modifiers[] = {
421 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
422 DRM_FORMAT_MOD_LINEAR,
423 };
424 struct vc4_screen *screen = vc4_screen(pscreen);
425 int num_modifiers = screen->has_tiling_ioctl ? 2 : 1;
426
427 if (!modifiers) {
428 *count = num_modifiers;
429 return;
430 }
431
432 *count = MIN2(max, num_modifiers);
433 m = screen->has_tiling_ioctl ? 0 : 1;
434 tex_will_lower = !vc4_tex_format_supported(format);
435 /* We support both modifiers (tiled and linear) for all sampler
436 * formats, but if we don't have the DRM_VC4_GET_TILING ioctl
437 * we shouldn't advertise the tiled formats.
438 */
439 for (i = 0; i < *count; i++) {
440 modifiers[i] = available_modifiers[m++];
441 if (external_only)
442 external_only[i] = tex_will_lower;
443 }
444 }
445
446 static bool
vc4_get_chip_info(struct vc4_screen * screen)447 vc4_get_chip_info(struct vc4_screen *screen)
448 {
449 struct drm_vc4_get_param ident0 = {
450 .param = DRM_VC4_PARAM_V3D_IDENT0,
451 };
452 struct drm_vc4_get_param ident1 = {
453 .param = DRM_VC4_PARAM_V3D_IDENT1,
454 };
455 int ret;
456
457 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
458 if (ret != 0) {
459 if (errno == EINVAL) {
460 /* Backwards compatibility with 2835 kernels which
461 * only do V3D 2.1.
462 */
463 screen->v3d_ver = 21;
464 return true;
465 } else {
466 fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
467 strerror(errno));
468 return false;
469 }
470 }
471 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
472 if (ret != 0) {
473 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
474 strerror(errno));
475 return false;
476 }
477
478 uint32_t major = (ident0.value >> 24) & 0xff;
479 uint32_t minor = (ident1.value >> 0) & 0xf;
480 screen->v3d_ver = major * 10 + minor;
481
482 if (screen->v3d_ver != 21 && screen->v3d_ver != 26) {
483 fprintf(stderr,
484 "V3D %d.%d not supported by this version of Mesa.\n",
485 screen->v3d_ver / 10,
486 screen->v3d_ver % 10);
487 return false;
488 }
489
490 return true;
491 }
492
493 struct pipe_screen *
vc4_screen_create(int fd,struct renderonly * ro)494 vc4_screen_create(int fd, struct renderonly *ro)
495 {
496 struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
497 uint64_t syncobj_cap = 0;
498 struct pipe_screen *pscreen;
499 int err;
500
501 pscreen = &screen->base;
502
503 pscreen->destroy = vc4_screen_destroy;
504 pscreen->get_param = vc4_screen_get_param;
505 pscreen->get_paramf = vc4_screen_get_paramf;
506 pscreen->get_shader_param = vc4_screen_get_shader_param;
507 pscreen->context_create = vc4_context_create;
508 pscreen->is_format_supported = vc4_screen_is_format_supported;
509
510 screen->fd = fd;
511 if (ro) {
512 screen->ro = renderonly_dup(ro);
513 if (!screen->ro) {
514 fprintf(stderr, "Failed to dup renderonly object\n");
515 ralloc_free(screen);
516 return NULL;
517 }
518 }
519
520 list_inithead(&screen->bo_cache.time_list);
521 (void) mtx_init(&screen->bo_handles_mutex, mtx_plain);
522 screen->bo_handles = util_hash_table_create_ptr_keys();
523
524 screen->has_control_flow =
525 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
526 screen->has_etc1 =
527 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
528 screen->has_threaded_fs =
529 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
530 screen->has_madvise =
531 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_MADVISE);
532 screen->has_perfmon_ioctl =
533 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_PERFMON);
534
535 err = drmGetCap(fd, DRM_CAP_SYNCOBJ, &syncobj_cap);
536 if (err == 0 && syncobj_cap)
537 screen->has_syncobj = true;
538
539 if (!vc4_get_chip_info(screen))
540 goto fail;
541
542 util_cpu_detect();
543
544 slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
545
546 vc4_fence_screen_init(screen);
547
548 vc4_debug = debug_get_option_vc4_debug();
549 if (vc4_debug & VC4_DEBUG_SHADERDB)
550 vc4_debug |= VC4_DEBUG_NORAST;
551
552 #ifdef USE_VC4_SIMULATOR
553 vc4_simulator_init(screen);
554 #endif
555
556 vc4_resource_screen_init(pscreen);
557
558 pscreen->get_name = vc4_screen_get_name;
559 pscreen->get_vendor = vc4_screen_get_vendor;
560 pscreen->get_device_vendor = vc4_screen_get_vendor;
561 pscreen->get_compiler_options = vc4_screen_get_compiler_options;
562 pscreen->query_dmabuf_modifiers = vc4_screen_query_dmabuf_modifiers;
563
564 if (screen->has_perfmon_ioctl) {
565 pscreen->get_driver_query_group_info = vc4_get_driver_query_group_info;
566 pscreen->get_driver_query_info = vc4_get_driver_query_info;
567 }
568
569 return pscreen;
570
571 fail:
572 close(fd);
573 ralloc_free(pscreen);
574 return NULL;
575 }
576