1 /*
2 * Copyright (C) 2019 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_dump.h"
29 #include "u_tracepoints.h"
30
31 #include "freedreno_resource.h"
32 #include "freedreno_tracepoints.h"
33
34 #include "fd6_compute.h"
35 #include "fd6_const.h"
36 #include "fd6_context.h"
37 #include "fd6_emit.h"
38 #include "fd6_pack.h"
39
40 /* maybe move to fd6_program? */
41 static void
cs_program_emit(struct fd_context * ctx,struct fd_ringbuffer * ring,struct ir3_shader_variant * v)42 cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
43 struct ir3_shader_variant *v) assert_dt
44 {
45 const struct ir3_info *i = &v->info;
46 enum a6xx_threadsize thrsz = i->double_threadsize ? THREAD128 : THREAD64;
47
48 OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true,
49 .ds_state = true, .gs_state = true,
50 .fs_state = true, .cs_state = true,
51 .gfx_ibo = true, .cs_ibo = true, ));
52
53 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1);
54 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(v->constlen) |
55 A6XX_HLSQ_CS_CNTL_ENABLED);
56
57 OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);
58 OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED |
59 A6XX_SP_CS_CONFIG_NIBO(v->shader->nir->info.num_ssbos +
60 v->shader->nir->info.num_images) |
61 A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
62 A6XX_SP_CS_CONFIG_NSAMP(v->num_samp)); /* SP_VS_CONFIG */
63 OUT_RING(ring, v->instrlen); /* SP_VS_INSTRLEN */
64
65 OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1);
66 OUT_RING(ring,
67 A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
68 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
69 A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
70 COND(v->mergedregs, A6XX_SP_CS_CTRL_REG0_MERGEDREGS) |
71 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(v)));
72
73 uint32_t shared_size = MAX2(((int)v->shared_size - 1) / 1024, 1);
74 OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
75 OUT_RING(ring, A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(shared_size) |
76 A6XX_SP_CS_UNKNOWN_A9B1_UNK6);
77
78 if (ctx->screen->info->a6xx.has_lpac) {
79 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_UNKNOWN_B9D0, 1);
80 OUT_RING(ring, A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(shared_size) |
81 A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6);
82 }
83
84 uint32_t local_invocation_id, work_group_id;
85 local_invocation_id =
86 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
87 work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORKGROUP_ID);
88
89 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
90 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
91 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
92 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
93 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
94 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
95 A6XX_HLSQ_CS_CNTL_1_THREADSIZE(thrsz));
96
97 if (ctx->screen->info->a6xx.has_lpac) {
98 OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_0, 2);
99 OUT_RING(ring, A6XX_SP_CS_CNTL_0_WGIDCONSTID(work_group_id) |
100 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
101 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
102 A6XX_SP_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
103 OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
104 A6XX_SP_CS_CNTL_1_THREADSIZE(thrsz));
105 }
106
107 OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
108 OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
109
110 if (v->instrlen > 0)
111 fd6_emit_shader(ctx, ring, v);
112 }
113
114 static void
fd6_launch_grid(struct fd_context * ctx,const struct pipe_grid_info * info)115 fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
116 {
117 struct ir3_shader_key key = {};
118 struct ir3_shader_variant *v;
119 struct fd_ringbuffer *ring = ctx->batch->draw;
120 unsigned nglobal = 0;
121
122 v = ir3_shader_variant(ir3_get_shader(ctx->compute), key, false, &ctx->debug);
123 if (!v)
124 return;
125
126 if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
127 cs_program_emit(ctx, ring, v);
128
129 fd6_emit_cs_state(ctx, ring, v);
130 fd6_emit_cs_consts(v, ring, ctx, info);
131
132 u_foreach_bit (i, ctx->global_bindings.enabled_mask)
133 nglobal++;
134
135 if (nglobal > 0) {
136 /* global resources don't otherwise get an OUT_RELOC(), since
137 * the raw ptr address is emitted in ir3_emit_cs_consts().
138 * So to make the kernel aware that these buffers are referenced
139 * by the batch, emit dummy reloc's as part of a no-op packet
140 * payload:
141 */
142 OUT_PKT7(ring, CP_NOP, 2 * nglobal);
143 u_foreach_bit (i, ctx->global_bindings.enabled_mask) {
144 struct pipe_resource *prsc = ctx->global_bindings.buf[i];
145 OUT_RELOC(ring, fd_resource(prsc)->bo, 0, 0, 0);
146 }
147 }
148
149 OUT_PKT7(ring, CP_SET_MARKER, 1);
150 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
151
152 const unsigned *local_size =
153 info->block; // v->shader->nir->info->workgroup_size;
154 const unsigned *num_groups = info->grid;
155 /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
156 const unsigned work_dim = info->work_dim ? info->work_dim : 3;
157 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
158 OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim) |
159 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
160 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
161 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
162 OUT_RING(ring,
163 A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
164 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
165 OUT_RING(ring,
166 A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
167 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
168 OUT_RING(ring,
169 A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
170 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
171
172 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
173 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_X */
174 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
175 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
176
177 trace_grid_info(&ctx->batch->trace, ring, info);
178 trace_start_compute(&ctx->batch->trace, ring);
179
180 if (info->indirect) {
181 struct fd_resource *rsc = fd_resource(info->indirect);
182
183 OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4);
184 OUT_RING(ring, 0x00000000);
185 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */
186 OUT_RING(ring,
187 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
188 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
189 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
190 } else {
191 OUT_PKT7(ring, CP_EXEC_CS, 4);
192 OUT_RING(ring, 0x00000000);
193 OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0]));
194 OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1]));
195 OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2]));
196 }
197
198 trace_end_compute(&ctx->batch->trace, ring);
199
200 OUT_WFI5(ring);
201
202 fd6_cache_flush(ctx->batch, ring);
203 }
204
205 void
fd6_compute_init(struct pipe_context * pctx)206 fd6_compute_init(struct pipe_context *pctx) disable_thread_safety_analysis
207 {
208 struct fd_context *ctx = fd_context(pctx);
209 ctx->launch_grid = fd6_launch_grid;
210 pctx->create_compute_state = ir3_shader_compute_state_create;
211 pctx->delete_compute_state = ir3_shader_state_delete;
212 }
213