1 /* -*- mesa-c++ -*- 2 * 3 * Copyright (c) 2019 Collabora LTD 4 * 5 * Author: Gert Wollny <gert.wollny@collabora.com> 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * on the rights to use, copy, modify, merge, publish, distribute, sub 11 * license, and/or sell copies of the Software, and to permit persons to whom 12 * the Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27 #ifndef sfn_shader_from_nir_h 28 #define sfn_shader_from_nir_h 29 30 31 #include "gallium/drivers/r600/r600_shader.h" 32 33 #include "compiler/nir/nir.h" 34 #include "compiler/nir_types.h" 35 36 #include "sfn_instruction_block.h" 37 #include "sfn_instruction_export.h" 38 #include "sfn_alu_defines.h" 39 #include "sfn_valuepool.h" 40 #include "sfn_debug.h" 41 #include "sfn_instruction_cf.h" 42 #include "sfn_emittexinstruction.h" 43 #include "sfn_emitaluinstruction.h" 44 #include "sfn_emitssboinstruction.h" 45 46 #include <vector> 47 #include <set> 48 #include <stack> 49 #include <unordered_map> 50 51 struct nir_instr; 52 53 namespace r600 { 54 55 extern SfnLog sfn_log; 56 57 class ShaderFromNirProcessor : public ValuePool { 58 public: 59 ShaderFromNirProcessor(pipe_shader_type ptype, r600_pipe_shader_selector& sel, 60 r600_shader& sh_info, int scratch_size, enum chip_class _chip_class, 61 int atomic_base); 62 virtual ~ShaderFromNirProcessor(); 63 64 void emit_instruction(Instruction *ir); 65 66 PValue from_nir_with_fetch_constant(const nir_src& src, unsigned component, int channel = -1); 67 GPRVector vec_from_nir_with_fetch_constant(const nir_src& src, unsigned mask, 68 const GPRVector::Swizzle& swizzle, bool match = false); 69 70 bool emit_instruction(EAluOp opcode, PValue dest, 71 std::vector<PValue> src0, 72 const std::set<AluModifiers>& m_flags); 73 void emit_export_instruction(WriteoutInstruction *ir); 74 void emit_instruction(AluInstruction *ir); 75 76 void split_constants(nir_alu_instr* instr); 77 void remap_registers(); 78 79 const nir_variable *get_deref_location(const nir_src& src) const; 80 sh_info()81 r600_shader& sh_info() {return m_sh_info;} 82 void add_param_output_reg(int loc, const GPRVector *gpr); 83 void set_output(unsigned pos, int sel); 84 const GPRVector *output_register(unsigned location) const; 85 void evaluate_spi_sid(r600_shader_io &io); 86 87 enum chip_class get_chip_class() const; 88 remap_atomic_base(int base)89 int remap_atomic_base(int base) { 90 return m_atomic_base_map[base]; 91 } 92 93 void get_array_info(r600_shader& shader) const; 94 95 virtual bool scan_inputs_read(const nir_shader *sh); 96 void set_shader_info(const nir_shader *sh); 97 98 protected: 99 100 void set_var_address(nir_deref_instr *instr); 101 void set_input(unsigned pos, PValue var); 102 103 bool scan_instruction(nir_instr *instr); 104 105 virtual bool scan_sysvalue_access(nir_instr *instr) = 0; 106 107 bool emit_if_start(int if_id, nir_if *if_stmt); 108 bool emit_else_start(int if_id); 109 bool emit_ifelse_end(int if_id); 110 111 bool emit_loop_start(int loop_id); 112 bool emit_loop_end(int loop_id); 113 bool emit_jump_instruction(nir_jump_instr *instr); 114 115 bool emit_load_tcs_param_base(nir_intrinsic_instr* instr, int offset); 116 bool emit_load_local_shared(nir_intrinsic_instr* instr); 117 bool emit_store_local_shared(nir_intrinsic_instr* instr); 118 bool emit_atomic_local_shared(nir_intrinsic_instr* instr); 119 120 bool emit_barrier(nir_intrinsic_instr* instr); 121 122 bool load_preloaded_value(const nir_dest& dest, int chan, PValue value, 123 bool as_last = true); 124 125 void inc_atomic_file_count(); 126 127 virtual void do_set_shader_info(const nir_shader *sh); 128 129 enum ESlots { 130 es_face, 131 es_instanceid, 132 es_invocation_id, 133 es_patch_id, 134 es_pos, 135 es_rel_patch_id, 136 es_sample_mask_in, 137 es_sample_id, 138 es_sample_pos, 139 es_tess_factor_base, 140 es_vertexid, 141 es_tess_coord, 142 es_primitive_id, 143 es_helper_invocation, 144 es_last 145 }; 146 147 std::bitset<es_last> m_sv_values; 148 149 bool allocate_reserved_registers(); 150 151 152 private: 153 virtual bool do_allocate_reserved_registers() = 0; 154 155 156 void emit_instruction_internal(Instruction *ir); 157 158 bool emit_alu_instruction(nir_instr *instr); 159 bool emit_deref_instruction(nir_deref_instr* instr); 160 bool emit_intrinsic_instruction(nir_intrinsic_instr* instr); 161 virtual bool emit_intrinsic_instruction_override(nir_intrinsic_instr* instr); 162 bool emit_tex_instruction(nir_instr* instr); 163 bool emit_discard_if(nir_intrinsic_instr* instr); 164 bool emit_load_ubo_vec4(nir_intrinsic_instr* instr); 165 bool emit_ssbo_atomic_add(nir_intrinsic_instr* instr); 166 bool load_uniform_indirect(nir_intrinsic_instr* instr, PValue addr, int offest, int bufid); 167 168 /* Code creating functions */ 169 bool emit_load_function_temp(const nir_variable *var, nir_intrinsic_instr *instr); 170 AluInstruction *emit_load_literal(const nir_load_const_instr *literal, const nir_src& src, unsigned writemask); 171 172 bool load_uniform(nir_intrinsic_instr* instr); 173 bool process_uniforms(nir_variable *uniform); 174 175 void append_block(int nesting_change); 176 177 virtual void emit_shader_start(); 178 virtual bool emit_deref_instruction_override(nir_deref_instr* instr); 179 180 bool emit_store_scratch(nir_intrinsic_instr* instr); 181 bool emit_load_scratch(nir_intrinsic_instr* instr); 182 bool emit_shader_clock(nir_intrinsic_instr* instr); 183 virtual void do_finalize() = 0; 184 185 void finalize(); 186 friend class ShaderFromNir; 187 188 std::set<nir_variable*> m_arrays; 189 190 std::map<unsigned, PValue> m_inputs; 191 std::map<unsigned, int> m_outputs; 192 193 std::map<unsigned, nir_variable*> m_var_derefs; 194 std::map<const nir_variable *, nir_variable_mode> m_var_mode; 195 196 std::map<unsigned, const glsl_type*> m_uniform_type_map; 197 std::map<int, IfElseInstruction *> m_if_block_start_map; 198 std::map<int, LoopBeginInstruction *> m_loop_begin_block_map; 199 200 pipe_shader_type m_processor_type; 201 202 std::vector<InstructionBlock> m_output; 203 unsigned m_nesting_depth; 204 unsigned m_block_number; 205 InstructionBlock m_export_output; 206 r600_shader& m_sh_info; 207 enum chip_class m_chip_class; 208 EmitTexInstruction m_tex_instr; 209 EmitAluInstruction m_alu_instr; 210 EmitSSBOInstruction m_ssbo_instr; 211 OutputRegisterMap m_output_register_map; 212 213 IfElseInstruction *m_pending_else; 214 int m_scratch_size; 215 int m_next_hwatomic_loc; 216 217 r600_pipe_shader_selector& m_sel; 218 int m_atomic_base ; 219 int m_image_count; 220 221 std::unordered_map<int, int> m_atomic_base_map; 222 AluInstruction *last_emitted_alu; 223 }; 224 225 } 226 227 #endif 228