1 /*
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4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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13  * version 2 for more details (a copy is included in the LICENSE file that
14  * accompanied this code).
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25 
26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_INLINE_HPP
27 #define CPU_PPC_VM_ASSEMBLER_PPC_INLINE_HPP
28 
29 #include "asm/assembler.inline.hpp"
30 #include "asm/codeBuffer.hpp"
31 #include "code/codeCache.hpp"
32 
emit_int32(int x)33 inline void Assembler::emit_int32(int x) {
34   AbstractAssembler::emit_int32(x);
35 }
36 
emit_data(int x)37 inline void Assembler::emit_data(int x) {
38   emit_int32(x);
39 }
40 
emit_data(int x,relocInfo::relocType rtype)41 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
42   relocate(rtype);
43   emit_int32(x);
44 }
45 
emit_data(int x,RelocationHolder const & rspec)46 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
47   relocate(rspec);
48   emit_int32(x);
49 }
50 
51 // Emit an address
emit_addr(const address addr)52 inline address Assembler::emit_addr(const address addr) {
53   address start = pc();
54   emit_address(addr);
55   return start;
56 }
57 
58 #if !defined(ABI_ELFv2)
59 // Emit a function descriptor with the specified entry point, TOC, and
60 // ENV. If the entry point is NULL, the descriptor will point just
61 // past the descriptor.
emit_fd(address entry,address toc,address env)62 inline address Assembler::emit_fd(address entry, address toc, address env) {
63   FunctionDescriptor* fd = (FunctionDescriptor*)pc();
64 
65   assert(sizeof(FunctionDescriptor) == 3*sizeof(address), "function descriptor size");
66 
67   (void)emit_addr();
68   (void)emit_addr();
69   (void)emit_addr();
70 
71   fd->set_entry(entry == NULL ? pc() : entry);
72   fd->set_toc(toc);
73   fd->set_env(env);
74 
75   return (address)fd;
76 }
77 #endif
78 
79 // Issue an illegal instruction. 0 is guaranteed to be an illegal instruction.
illtrap()80 inline void Assembler::illtrap() { Assembler::emit_int32(0); }
is_illtrap(int x)81 inline bool Assembler::is_illtrap(int x) { return x == 0; }
82 
83 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
addi(Register d,Register a,int si16)84 inline void Assembler::addi(   Register d, Register a, int si16)   { assert(a != R0, "r0 not allowed"); addi_r0ok( d, a, si16); }
addis(Register d,Register a,int si16)85 inline void Assembler::addis(  Register d, Register a, int si16)   { assert(a != R0, "r0 not allowed"); addis_r0ok(d, a, si16); }
addi_r0ok(Register d,Register a,int si16)86 inline void Assembler::addi_r0ok(Register d,Register a,int si16)   { emit_int32(ADDI_OPCODE   | rt(d) | ra(a) | simm(si16, 16)); }
addis_r0ok(Register d,Register a,int si16)87 inline void Assembler::addis_r0ok(Register d,Register a,int si16)  { emit_int32(ADDIS_OPCODE  | rt(d) | ra(a) | simm(si16, 16)); }
addic_(Register d,Register a,int si16)88 inline void Assembler::addic_( Register d, Register a, int si16)   { emit_int32(ADDIC__OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
subfic(Register d,Register a,int si16)89 inline void Assembler::subfic( Register d, Register a, int si16)   { emit_int32(SUBFIC_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
add(Register d,Register a,Register b)90 inline void Assembler::add(    Register d, Register a, Register b) { emit_int32(ADD_OPCODE    | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
add_(Register d,Register a,Register b)91 inline void Assembler::add_(   Register d, Register a, Register b) { emit_int32(ADD_OPCODE    | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
subf(Register d,Register a,Register b)92 inline void Assembler::subf(   Register d, Register a, Register b) { emit_int32(SUBF_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
sub(Register d,Register a,Register b)93 inline void Assembler::sub(    Register d, Register a, Register b) { subf(d, b, a); }
subf_(Register d,Register a,Register b)94 inline void Assembler::subf_(  Register d, Register a, Register b) { emit_int32(SUBF_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
addc(Register d,Register a,Register b)95 inline void Assembler::addc(   Register d, Register a, Register b) { emit_int32(ADDC_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
addc_(Register d,Register a,Register b)96 inline void Assembler::addc_(  Register d, Register a, Register b) { emit_int32(ADDC_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
subfc(Register d,Register a,Register b)97 inline void Assembler::subfc(  Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE  | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
subfc_(Register d,Register a,Register b)98 inline void Assembler::subfc_( Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE  | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
adde(Register d,Register a,Register b)99 inline void Assembler::adde(   Register d, Register a, Register b) { emit_int32(ADDE_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
adde_(Register d,Register a,Register b)100 inline void Assembler::adde_(  Register d, Register a, Register b) { emit_int32(ADDE_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
subfe(Register d,Register a,Register b)101 inline void Assembler::subfe(  Register d, Register a, Register b) { emit_int32(SUBFE_OPCODE  | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
subfe_(Register d,Register a,Register b)102 inline void Assembler::subfe_( Register d, Register a, Register b) { emit_int32(SUBFE_OPCODE  | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
addme(Register d,Register a)103 inline void Assembler::addme(  Register d, Register a)             { emit_int32(ADDME_OPCODE  | rt(d) | ra(a) |         oe(0) | rc(0)); }
addme_(Register d,Register a)104 inline void Assembler::addme_( Register d, Register a)             { emit_int32(ADDME_OPCODE  | rt(d) | ra(a) |         oe(0) | rc(1)); }
subfme(Register d,Register a)105 inline void Assembler::subfme( Register d, Register a)             { emit_int32(SUBFME_OPCODE | rt(d) | ra(a) |         oe(0) | rc(0)); }
subfme_(Register d,Register a)106 inline void Assembler::subfme_(Register d, Register a)             { emit_int32(SUBFME_OPCODE | rt(d) | ra(a) |         oe(0) | rc(1)); }
addze(Register d,Register a)107 inline void Assembler::addze(  Register d, Register a)             { emit_int32(ADDZE_OPCODE  | rt(d) | ra(a) |         oe(0) | rc(0)); }
addze_(Register d,Register a)108 inline void Assembler::addze_( Register d, Register a)             { emit_int32(ADDZE_OPCODE  | rt(d) | ra(a) |         oe(0) | rc(1)); }
subfze(Register d,Register a)109 inline void Assembler::subfze( Register d, Register a)             { emit_int32(SUBFZE_OPCODE | rt(d) | ra(a) |         oe(0) | rc(0)); }
subfze_(Register d,Register a)110 inline void Assembler::subfze_(Register d, Register a)             { emit_int32(SUBFZE_OPCODE | rt(d) | ra(a) |         oe(0) | rc(1)); }
neg(Register d,Register a)111 inline void Assembler::neg(    Register d, Register a)             { emit_int32(NEG_OPCODE    | rt(d) | ra(a) | oe(0) | rc(0)); }
neg_(Register d,Register a)112 inline void Assembler::neg_(   Register d, Register a)             { emit_int32(NEG_OPCODE    | rt(d) | ra(a) | oe(0) | rc(1)); }
mulli(Register d,Register a,int si16)113 inline void Assembler::mulli(  Register d, Register a, int si16)   { emit_int32(MULLI_OPCODE  | rt(d) | ra(a) | simm(si16, 16)); }
mulld(Register d,Register a,Register b)114 inline void Assembler::mulld(  Register d, Register a, Register b) { emit_int32(MULLD_OPCODE  | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
mulld_(Register d,Register a,Register b)115 inline void Assembler::mulld_( Register d, Register a, Register b) { emit_int32(MULLD_OPCODE  | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
mullw(Register d,Register a,Register b)116 inline void Assembler::mullw(  Register d, Register a, Register b) { emit_int32(MULLW_OPCODE  | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
mullw_(Register d,Register a,Register b)117 inline void Assembler::mullw_( Register d, Register a, Register b) { emit_int32(MULLW_OPCODE  | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
mulhw(Register d,Register a,Register b)118 inline void Assembler::mulhw(  Register d, Register a, Register b) { emit_int32(MULHW_OPCODE  | rt(d) | ra(a) | rb(b) | rc(0)); }
mulhw_(Register d,Register a,Register b)119 inline void Assembler::mulhw_( Register d, Register a, Register b) { emit_int32(MULHW_OPCODE  | rt(d) | ra(a) | rb(b) | rc(1)); }
mulhwu(Register d,Register a,Register b)120 inline void Assembler::mulhwu( Register d, Register a, Register b) { emit_int32(MULHWU_OPCODE | rt(d) | ra(a) | rb(b) | rc(0)); }
mulhwu_(Register d,Register a,Register b)121 inline void Assembler::mulhwu_(Register d, Register a, Register b) { emit_int32(MULHWU_OPCODE | rt(d) | ra(a) | rb(b) | rc(1)); }
mulhd(Register d,Register a,Register b)122 inline void Assembler::mulhd(  Register d, Register a, Register b) { emit_int32(MULHD_OPCODE  | rt(d) | ra(a) | rb(b) | rc(0)); }
mulhd_(Register d,Register a,Register b)123 inline void Assembler::mulhd_( Register d, Register a, Register b) { emit_int32(MULHD_OPCODE  | rt(d) | ra(a) | rb(b) | rc(1)); }
mulhdu(Register d,Register a,Register b)124 inline void Assembler::mulhdu( Register d, Register a, Register b) { emit_int32(MULHDU_OPCODE | rt(d) | ra(a) | rb(b) | rc(0)); }
mulhdu_(Register d,Register a,Register b)125 inline void Assembler::mulhdu_(Register d, Register a, Register b) { emit_int32(MULHDU_OPCODE | rt(d) | ra(a) | rb(b) | rc(1)); }
divd(Register d,Register a,Register b)126 inline void Assembler::divd(   Register d, Register a, Register b) { emit_int32(DIVD_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
divd_(Register d,Register a,Register b)127 inline void Assembler::divd_(  Register d, Register a, Register b) { emit_int32(DIVD_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
divw(Register d,Register a,Register b)128 inline void Assembler::divw(   Register d, Register a, Register b) { emit_int32(DIVW_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
divw_(Register d,Register a,Register b)129 inline void Assembler::divw_(  Register d, Register a, Register b) { emit_int32(DIVW_OPCODE   | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
130 
131 // Fixed-Point Arithmetic Instructions with Overflow detection
addo(Register d,Register a,Register b)132 inline void Assembler::addo(    Register d, Register a, Register b) { emit_int32(ADD_OPCODE    | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
addo_(Register d,Register a,Register b)133 inline void Assembler::addo_(   Register d, Register a, Register b) { emit_int32(ADD_OPCODE    | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
subfo(Register d,Register a,Register b)134 inline void Assembler::subfo(   Register d, Register a, Register b) { emit_int32(SUBF_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
subfo_(Register d,Register a,Register b)135 inline void Assembler::subfo_(  Register d, Register a, Register b) { emit_int32(SUBF_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
addco(Register d,Register a,Register b)136 inline void Assembler::addco(   Register d, Register a, Register b) { emit_int32(ADDC_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
addco_(Register d,Register a,Register b)137 inline void Assembler::addco_(  Register d, Register a, Register b) { emit_int32(ADDC_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
subfco(Register d,Register a,Register b)138 inline void Assembler::subfco(  Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE  | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
subfco_(Register d,Register a,Register b)139 inline void Assembler::subfco_( Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE  | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
addeo(Register d,Register a,Register b)140 inline void Assembler::addeo(   Register d, Register a, Register b) { emit_int32(ADDE_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
addeo_(Register d,Register a,Register b)141 inline void Assembler::addeo_(  Register d, Register a, Register b) { emit_int32(ADDE_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
subfeo(Register d,Register a,Register b)142 inline void Assembler::subfeo(  Register d, Register a, Register b) { emit_int32(SUBFE_OPCODE  | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
subfeo_(Register d,Register a,Register b)143 inline void Assembler::subfeo_( Register d, Register a, Register b) { emit_int32(SUBFE_OPCODE  | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
addmeo(Register d,Register a)144 inline void Assembler::addmeo(  Register d, Register a)             { emit_int32(ADDME_OPCODE  | rt(d) | ra(a) |         oe(1) | rc(0)); }
addmeo_(Register d,Register a)145 inline void Assembler::addmeo_( Register d, Register a)             { emit_int32(ADDME_OPCODE  | rt(d) | ra(a) |         oe(1) | rc(1)); }
subfmeo(Register d,Register a)146 inline void Assembler::subfmeo( Register d, Register a)             { emit_int32(SUBFME_OPCODE | rt(d) | ra(a) |         oe(1) | rc(0)); }
subfmeo_(Register d,Register a)147 inline void Assembler::subfmeo_(Register d, Register a)             { emit_int32(SUBFME_OPCODE | rt(d) | ra(a) |         oe(1) | rc(1)); }
addzeo(Register d,Register a)148 inline void Assembler::addzeo(  Register d, Register a)             { emit_int32(ADDZE_OPCODE  | rt(d) | ra(a) |         oe(1) | rc(0)); }
addzeo_(Register d,Register a)149 inline void Assembler::addzeo_( Register d, Register a)             { emit_int32(ADDZE_OPCODE  | rt(d) | ra(a) |         oe(1) | rc(1)); }
subfzeo(Register d,Register a)150 inline void Assembler::subfzeo( Register d, Register a)             { emit_int32(SUBFZE_OPCODE | rt(d) | ra(a) |         oe(1) | rc(0)); }
subfzeo_(Register d,Register a)151 inline void Assembler::subfzeo_(Register d, Register a)             { emit_int32(SUBFZE_OPCODE | rt(d) | ra(a) |         oe(1) | rc(1)); }
nego(Register d,Register a)152 inline void Assembler::nego(    Register d, Register a)             { emit_int32(NEG_OPCODE    | rt(d) | ra(a) | oe(1) | rc(0)); }
nego_(Register d,Register a)153 inline void Assembler::nego_(   Register d, Register a)             { emit_int32(NEG_OPCODE    | rt(d) | ra(a) | oe(1) | rc(1)); }
mulldo(Register d,Register a,Register b)154 inline void Assembler::mulldo(  Register d, Register a, Register b) { emit_int32(MULLD_OPCODE  | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
mulldo_(Register d,Register a,Register b)155 inline void Assembler::mulldo_( Register d, Register a, Register b) { emit_int32(MULLD_OPCODE  | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
mullwo(Register d,Register a,Register b)156 inline void Assembler::mullwo(  Register d, Register a, Register b) { emit_int32(MULLW_OPCODE  | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
mullwo_(Register d,Register a,Register b)157 inline void Assembler::mullwo_( Register d, Register a, Register b) { emit_int32(MULLW_OPCODE  | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
divdo(Register d,Register a,Register b)158 inline void Assembler::divdo(   Register d, Register a, Register b) { emit_int32(DIVD_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
divdo_(Register d,Register a,Register b)159 inline void Assembler::divdo_(  Register d, Register a, Register b) { emit_int32(DIVD_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
divwo(Register d,Register a,Register b)160 inline void Assembler::divwo(   Register d, Register a, Register b) { emit_int32(DIVW_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
divwo_(Register d,Register a,Register b)161 inline void Assembler::divwo_(  Register d, Register a, Register b) { emit_int32(DIVW_OPCODE   | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
162 
163 // extended mnemonics
li(Register d,int si16)164 inline void Assembler::li(   Register d, int si16)             { Assembler::addi_r0ok( d, R0, si16); }
lis(Register d,int si16)165 inline void Assembler::lis(  Register d, int si16)             { Assembler::addis_r0ok(d, R0, si16); }
addir(Register d,int si16,Register a)166 inline void Assembler::addir(Register d, int si16, Register a) { Assembler::addi(d, a, si16); }
subi(Register d,Register a,int si16)167 inline void Assembler::subi( Register d, Register a, int si16) { Assembler::addi(d, a, -si16); }
168 
169 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
cmpi(ConditionRegister f,int l,Register a,int si16)170 inline void Assembler::cmpi(  ConditionRegister f, int l, Register a, int si16)   { emit_int32( CMPI_OPCODE  | bf(f) | l10(l) | ra(a) | simm(si16,16)); }
cmp(ConditionRegister f,int l,Register a,Register b)171 inline void Assembler::cmp(   ConditionRegister f, int l, Register a, Register b) { emit_int32( CMP_OPCODE   | bf(f) | l10(l) | ra(a) | rb(b)); }
cmpli(ConditionRegister f,int l,Register a,int ui16)172 inline void Assembler::cmpli( ConditionRegister f, int l, Register a, int ui16)   { emit_int32( CMPLI_OPCODE | bf(f) | l10(l) | ra(a) | uimm(ui16,16)); }
cmpl(ConditionRegister f,int l,Register a,Register b)173 inline void Assembler::cmpl(  ConditionRegister f, int l, Register a, Register b) { emit_int32( CMPL_OPCODE  | bf(f) | l10(l) | ra(a) | rb(b)); }
cmprb(ConditionRegister f,int l,Register a,Register b)174 inline void Assembler::cmprb( ConditionRegister f, int l, Register a, Register b) { emit_int32( CMPRB_OPCODE | bf(f) | l10(l) | ra(a) | rb(b)); }
cmpeqb(ConditionRegister f,Register a,Register b)175 inline void Assembler::cmpeqb(ConditionRegister f, Register a, Register b)        { emit_int32( CMPEQB_OPCODE| bf(f) | ra(a)  | rb(b)); }
176 
177 // extended mnemonics of Compare Instructions
cmpwi(ConditionRegister crx,Register a,int si16)178 inline void Assembler::cmpwi( ConditionRegister crx, Register a, int si16)   { Assembler::cmpi( crx, 0, a, si16); }
cmpdi(ConditionRegister crx,Register a,int si16)179 inline void Assembler::cmpdi( ConditionRegister crx, Register a, int si16)   { Assembler::cmpi( crx, 1, a, si16); }
cmpw(ConditionRegister crx,Register a,Register b)180 inline void Assembler::cmpw(  ConditionRegister crx, Register a, Register b) { Assembler::cmp(  crx, 0, a, b); }
cmpd(ConditionRegister crx,Register a,Register b)181 inline void Assembler::cmpd(  ConditionRegister crx, Register a, Register b) { Assembler::cmp(  crx, 1, a, b); }
cmplwi(ConditionRegister crx,Register a,int ui16)182 inline void Assembler::cmplwi(ConditionRegister crx, Register a, int ui16)   { Assembler::cmpli(crx, 0, a, ui16); }
cmpldi(ConditionRegister crx,Register a,int ui16)183 inline void Assembler::cmpldi(ConditionRegister crx, Register a, int ui16)   { Assembler::cmpli(crx, 1, a, ui16); }
cmplw(ConditionRegister crx,Register a,Register b)184 inline void Assembler::cmplw( ConditionRegister crx, Register a, Register b) { Assembler::cmpl( crx, 0, a, b); }
cmpld(ConditionRegister crx,Register a,Register b)185 inline void Assembler::cmpld( ConditionRegister crx, Register a, Register b) { Assembler::cmpl( crx, 1, a, b); }
186 
isel(Register d,Register a,Register b,int c)187 inline void Assembler::isel(Register d, Register a, Register b, int c) { guarantee(VM_Version::has_isel(), "opcode not supported on this hardware");
188                                                                          emit_int32(ISEL_OPCODE    | rt(d)  | ra(a) | rb(b) | bc(c)); }
189 
190 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
andi_(Register a,Register s,int ui16)191 inline void Assembler::andi_(   Register a, Register s, int ui16)      { emit_int32(ANDI_OPCODE    | rta(a) | rs(s) | uimm(ui16, 16)); }
andis_(Register a,Register s,int ui16)192 inline void Assembler::andis_(  Register a, Register s, int ui16)      { emit_int32(ANDIS_OPCODE   | rta(a) | rs(s) | uimm(ui16, 16)); }
ori(Register a,Register s,int ui16)193 inline void Assembler::ori(     Register a, Register s, int ui16)      { emit_int32(ORI_OPCODE     | rta(a) | rs(s) | uimm(ui16, 16)); }
oris(Register a,Register s,int ui16)194 inline void Assembler::oris(    Register a, Register s, int ui16)      { emit_int32(ORIS_OPCODE    | rta(a) | rs(s) | uimm(ui16, 16)); }
xori(Register a,Register s,int ui16)195 inline void Assembler::xori(    Register a, Register s, int ui16)      { emit_int32(XORI_OPCODE    | rta(a) | rs(s) | uimm(ui16, 16)); }
xoris(Register a,Register s,int ui16)196 inline void Assembler::xoris(   Register a, Register s, int ui16)      { emit_int32(XORIS_OPCODE   | rta(a) | rs(s) | uimm(ui16, 16)); }
andr(Register a,Register s,Register b)197 inline void Assembler::andr(    Register a, Register s, Register b)    { emit_int32(AND_OPCODE     | rta(a) | rs(s) | rb(b) | rc(0)); }
and_(Register a,Register s,Register b)198 inline void Assembler::and_(    Register a, Register s, Register b)    { emit_int32(AND_OPCODE     | rta(a) | rs(s) | rb(b) | rc(1)); }
199 
or_unchecked(Register a,Register s,Register b)200 inline void Assembler::or_unchecked(Register a, Register s, Register b){ emit_int32(OR_OPCODE      | rta(a) | rs(s) | rb(b) | rc(0)); }
orr(Register a,Register s,Register b)201 inline void Assembler::orr(     Register a, Register s, Register b)    { if (a==s && s==b) { Assembler::nop(); } else { Assembler::or_unchecked(a,s,b); } }
or_(Register a,Register s,Register b)202 inline void Assembler::or_(     Register a, Register s, Register b)    { emit_int32(OR_OPCODE      | rta(a) | rs(s) | rb(b) | rc(1)); }
xorr(Register a,Register s,Register b)203 inline void Assembler::xorr(    Register a, Register s, Register b)    { emit_int32(XOR_OPCODE     | rta(a) | rs(s) | rb(b) | rc(0)); }
xor_(Register a,Register s,Register b)204 inline void Assembler::xor_(    Register a, Register s, Register b)    { emit_int32(XOR_OPCODE     | rta(a) | rs(s) | rb(b) | rc(1)); }
nand(Register a,Register s,Register b)205 inline void Assembler::nand(    Register a, Register s, Register b)    { emit_int32(NAND_OPCODE    | rta(a) | rs(s) | rb(b) | rc(0)); }
nand_(Register a,Register s,Register b)206 inline void Assembler::nand_(   Register a, Register s, Register b)    { emit_int32(NAND_OPCODE    | rta(a) | rs(s) | rb(b) | rc(1)); }
nor(Register a,Register s,Register b)207 inline void Assembler::nor(     Register a, Register s, Register b)    { emit_int32(NOR_OPCODE     | rta(a) | rs(s) | rb(b) | rc(0)); }
nor_(Register a,Register s,Register b)208 inline void Assembler::nor_(    Register a, Register s, Register b)    { emit_int32(NOR_OPCODE     | rta(a) | rs(s) | rb(b) | rc(1)); }
andc(Register a,Register s,Register b)209 inline void Assembler::andc(    Register a, Register s, Register b)    { emit_int32(ANDC_OPCODE    | rta(a) | rs(s) | rb(b) | rc(0)); }
andc_(Register a,Register s,Register b)210 inline void Assembler::andc_(   Register a, Register s, Register b)    { emit_int32(ANDC_OPCODE    | rta(a) | rs(s) | rb(b) | rc(1)); }
orc(Register a,Register s,Register b)211 inline void Assembler::orc(     Register a, Register s, Register b)    { emit_int32(ORC_OPCODE     | rta(a) | rs(s) | rb(b) | rc(0)); }
orc_(Register a,Register s,Register b)212 inline void Assembler::orc_(    Register a, Register s, Register b)    { emit_int32(ORC_OPCODE     | rta(a) | rs(s) | rb(b) | rc(1)); }
extsb(Register a,Register s)213 inline void Assembler::extsb(   Register a, Register s)                { emit_int32(EXTSB_OPCODE   | rta(a) | rs(s) | rc(0)); }
extsb_(Register a,Register s)214 inline void Assembler::extsb_(  Register a, Register s)                { emit_int32(EXTSB_OPCODE   | rta(a) | rs(s) | rc(1)); }
extsh(Register a,Register s)215 inline void Assembler::extsh(   Register a, Register s)                { emit_int32(EXTSH_OPCODE   | rta(a) | rs(s) | rc(0)); }
extsh_(Register a,Register s)216 inline void Assembler::extsh_(  Register a, Register s)                { emit_int32(EXTSH_OPCODE   | rta(a) | rs(s) | rc(1)); }
extsw(Register a,Register s)217 inline void Assembler::extsw(   Register a, Register s)                { emit_int32(EXTSW_OPCODE   | rta(a) | rs(s) | rc(0)); }
extsw_(Register a,Register s)218 inline void Assembler::extsw_(  Register a, Register s)                { emit_int32(EXTSW_OPCODE   | rta(a) | rs(s) | rc(1)); }
219 
220 // extended mnemonics
nop()221 inline void Assembler::nop()                              { Assembler::ori(R0, R0, 0); }
222 // NOP for FP and BR units (different versions to allow them to be in one group)
fpnop0()223 inline void Assembler::fpnop0()                           { Assembler::fmr(F30, F30); }
fpnop1()224 inline void Assembler::fpnop1()                           { Assembler::fmr(F31, F31); }
brnop0()225 inline void Assembler::brnop0()                           { Assembler::mcrf(CCR2, CCR2); }
brnop1()226 inline void Assembler::brnop1()                           { Assembler::mcrf(CCR3, CCR3); }
brnop2()227 inline void Assembler::brnop2()                           { Assembler::mcrf(CCR4,  CCR4); }
228 
mr(Register d,Register s)229 inline void Assembler::mr(      Register d, Register s)   { Assembler::orr(d, s, s); }
ori_opt(Register d,int ui16)230 inline void Assembler::ori_opt( Register d, int ui16)     { if (ui16!=0) Assembler::ori( d, d, ui16); }
oris_opt(Register d,int ui16)231 inline void Assembler::oris_opt(Register d, int ui16)     { if (ui16!=0) Assembler::oris(d, d, ui16); }
232 
endgroup()233 inline void Assembler::endgroup()                         { Assembler::ori(R1, R1, 0); }
234 
235 // count instructions
cntlzw(Register a,Register s)236 inline void Assembler::cntlzw(  Register a, Register s)              { emit_int32(CNTLZW_OPCODE | rta(a) | rs(s) | rc(0)); }
cntlzw_(Register a,Register s)237 inline void Assembler::cntlzw_( Register a, Register s)              { emit_int32(CNTLZW_OPCODE | rta(a) | rs(s) | rc(1)); }
cntlzd(Register a,Register s)238 inline void Assembler::cntlzd(  Register a, Register s)              { emit_int32(CNTLZD_OPCODE | rta(a) | rs(s) | rc(0)); }
cntlzd_(Register a,Register s)239 inline void Assembler::cntlzd_( Register a, Register s)              { emit_int32(CNTLZD_OPCODE | rta(a) | rs(s) | rc(1)); }
cnttzw(Register a,Register s)240 inline void Assembler::cnttzw(  Register a, Register s)              { emit_int32(CNTTZW_OPCODE | rta(a) | rs(s) | rc(0)); }
cnttzw_(Register a,Register s)241 inline void Assembler::cnttzw_( Register a, Register s)              { emit_int32(CNTTZW_OPCODE | rta(a) | rs(s) | rc(1)); }
cnttzd(Register a,Register s)242 inline void Assembler::cnttzd(  Register a, Register s)              { emit_int32(CNTTZD_OPCODE | rta(a) | rs(s) | rc(0)); }
cnttzd_(Register a,Register s)243 inline void Assembler::cnttzd_( Register a, Register s)              { emit_int32(CNTTZD_OPCODE | rta(a) | rs(s) | rc(1)); }
244 
245 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
sld(Register a,Register s,Register b)246 inline void Assembler::sld(     Register a, Register s, Register b)  { emit_int32(SLD_OPCODE    | rta(a) | rs(s) | rb(b) | rc(0)); }
sld_(Register a,Register s,Register b)247 inline void Assembler::sld_(    Register a, Register s, Register b)  { emit_int32(SLD_OPCODE    | rta(a) | rs(s) | rb(b) | rc(1)); }
slw(Register a,Register s,Register b)248 inline void Assembler::slw(     Register a, Register s, Register b)  { emit_int32(SLW_OPCODE    | rta(a) | rs(s) | rb(b) | rc(0)); }
slw_(Register a,Register s,Register b)249 inline void Assembler::slw_(    Register a, Register s, Register b)  { emit_int32(SLW_OPCODE    | rta(a) | rs(s) | rb(b) | rc(1)); }
srd(Register a,Register s,Register b)250 inline void Assembler::srd(     Register a, Register s, Register b)  { emit_int32(SRD_OPCODE    | rta(a) | rs(s) | rb(b) | rc(0)); }
srd_(Register a,Register s,Register b)251 inline void Assembler::srd_(    Register a, Register s, Register b)  { emit_int32(SRD_OPCODE    | rta(a) | rs(s) | rb(b) | rc(1)); }
srw(Register a,Register s,Register b)252 inline void Assembler::srw(     Register a, Register s, Register b)  { emit_int32(SRW_OPCODE    | rta(a) | rs(s) | rb(b) | rc(0)); }
srw_(Register a,Register s,Register b)253 inline void Assembler::srw_(    Register a, Register s, Register b)  { emit_int32(SRW_OPCODE    | rta(a) | rs(s) | rb(b) | rc(1)); }
srad(Register a,Register s,Register b)254 inline void Assembler::srad(    Register a, Register s, Register b)  { emit_int32(SRAD_OPCODE   | rta(a) | rs(s) | rb(b) | rc(0)); }
srad_(Register a,Register s,Register b)255 inline void Assembler::srad_(   Register a, Register s, Register b)  { emit_int32(SRAD_OPCODE   | rta(a) | rs(s) | rb(b) | rc(1)); }
sraw(Register a,Register s,Register b)256 inline void Assembler::sraw(    Register a, Register s, Register b)  { emit_int32(SRAW_OPCODE   | rta(a) | rs(s) | rb(b) | rc(0)); }
sraw_(Register a,Register s,Register b)257 inline void Assembler::sraw_(   Register a, Register s, Register b)  { emit_int32(SRAW_OPCODE   | rta(a) | rs(s) | rb(b) | rc(1)); }
sradi(Register a,Register s,int sh6)258 inline void Assembler::sradi(   Register a, Register s, int sh6)     { emit_int32(SRADI_OPCODE  | rta(a) | rs(s) | sh162030(sh6) | rc(0)); }
sradi_(Register a,Register s,int sh6)259 inline void Assembler::sradi_(  Register a, Register s, int sh6)     { emit_int32(SRADI_OPCODE  | rta(a) | rs(s) | sh162030(sh6) | rc(1)); }
srawi(Register a,Register s,int sh5)260 inline void Assembler::srawi(   Register a, Register s, int sh5)     { emit_int32(SRAWI_OPCODE  | rta(a) | rs(s) | sh1620(sh5) | rc(0)); }
srawi_(Register a,Register s,int sh5)261 inline void Assembler::srawi_(  Register a, Register s, int sh5)     { emit_int32(SRAWI_OPCODE  | rta(a) | rs(s) | sh1620(sh5) | rc(1)); }
262 
263 // extended mnemonics for Shift Instructions
sldi(Register a,Register s,int sh6)264 inline void Assembler::sldi(    Register a, Register s, int sh6)     { Assembler::rldicr(a, s, sh6, 63-sh6); }
sldi_(Register a,Register s,int sh6)265 inline void Assembler::sldi_(   Register a, Register s, int sh6)     { Assembler::rldicr_(a, s, sh6, 63-sh6); }
slwi(Register a,Register s,int sh5)266 inline void Assembler::slwi(    Register a, Register s, int sh5)     { Assembler::rlwinm(a, s, sh5, 0, 31-sh5); }
slwi_(Register a,Register s,int sh5)267 inline void Assembler::slwi_(   Register a, Register s, int sh5)     { Assembler::rlwinm_(a, s, sh5, 0, 31-sh5); }
srdi(Register a,Register s,int sh6)268 inline void Assembler::srdi(    Register a, Register s, int sh6)     { Assembler::rldicl(a, s, 64-sh6, sh6); }
srdi_(Register a,Register s,int sh6)269 inline void Assembler::srdi_(   Register a, Register s, int sh6)     { Assembler::rldicl_(a, s, 64-sh6, sh6); }
srwi(Register a,Register s,int sh5)270 inline void Assembler::srwi(    Register a, Register s, int sh5)     { Assembler::rlwinm(a, s, 32-sh5, sh5, 31); }
srwi_(Register a,Register s,int sh5)271 inline void Assembler::srwi_(   Register a, Register s, int sh5)     { Assembler::rlwinm_(a, s, 32-sh5, sh5, 31); }
272 
clrrdi(Register a,Register s,int ui6)273 inline void Assembler::clrrdi(  Register a, Register s, int ui6)     { Assembler::rldicr(a, s, 0, 63-ui6); }
clrrdi_(Register a,Register s,int ui6)274 inline void Assembler::clrrdi_( Register a, Register s, int ui6)     { Assembler::rldicr_(a, s, 0, 63-ui6); }
clrldi(Register a,Register s,int ui6)275 inline void Assembler::clrldi(  Register a, Register s, int ui6)     { Assembler::rldicl(a, s, 0, ui6); }
clrldi_(Register a,Register s,int ui6)276 inline void Assembler::clrldi_( Register a, Register s, int ui6)     { Assembler::rldicl_(a, s, 0, ui6); }
clrlsldi(Register a,Register s,int clrl6,int shl6)277 inline void Assembler::clrlsldi( Register a, Register s, int clrl6, int shl6) { Assembler::rldic( a, s, shl6, clrl6-shl6); }
clrlsldi_(Register a,Register s,int clrl6,int shl6)278 inline void Assembler::clrlsldi_(Register a, Register s, int clrl6, int shl6) { Assembler::rldic_(a, s, shl6, clrl6-shl6); }
extrdi(Register a,Register s,int n,int b)279 inline void Assembler::extrdi(  Register a, Register s, int n, int b){ Assembler::rldicl(a, s, b+n, 64-n); }
280 // testbit with condition register.
testbitdi(ConditionRegister cr,Register a,Register s,int ui6)281 inline void Assembler::testbitdi(ConditionRegister cr, Register a, Register s, int ui6) {
282   if (cr == CCR0) {
283     Assembler::rldicr_(a, s, 63-ui6, 0);
284   } else {
285     Assembler::rldicr(a, s, 63-ui6, 0);
286     Assembler::cmpdi(cr, a, 0);
287   }
288 }
289 
290 // Byte reverse instructions (introduced with Power10)
brh(Register a,Register s)291 inline void Assembler::brh(Register a, Register s) { emit_int32(BRH_OPCODE | rta(a) | rs(s)); }
brw(Register a,Register s)292 inline void Assembler::brw(Register a, Register s) { emit_int32(BRW_OPCODE | rta(a) | rs(s)); }
brd(Register a,Register s)293 inline void Assembler::brd(Register a, Register s) { emit_int32(BRD_OPCODE | rta(a) | rs(s)); }
294 
295 // rotate instructions
rotldi(Register a,Register s,int n)296 inline void Assembler::rotldi( Register a, Register s, int n) { Assembler::rldicl(a, s, n, 0); }
rotrdi(Register a,Register s,int n)297 inline void Assembler::rotrdi( Register a, Register s, int n) { Assembler::rldicl(a, s, 64-n, 0); }
rotlwi(Register a,Register s,int n)298 inline void Assembler::rotlwi( Register a, Register s, int n) { Assembler::rlwinm(a, s, n, 0, 31); }
rotrwi(Register a,Register s,int n)299 inline void Assembler::rotrwi( Register a, Register s, int n) { Assembler::rlwinm(a, s, 32-n, 0, 31); }
300 
rldic(Register a,Register s,int sh6,int mb6)301 inline void Assembler::rldic(   Register a, Register s, int sh6, int mb6)         { emit_int32(RLDIC_OPCODE  | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(0)); }
rldic_(Register a,Register s,int sh6,int mb6)302 inline void Assembler::rldic_(  Register a, Register s, int sh6, int mb6)         { emit_int32(RLDIC_OPCODE  | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(1)); }
rldicr(Register a,Register s,int sh6,int mb6)303 inline void Assembler::rldicr(  Register a, Register s, int sh6, int mb6)         { emit_int32(RLDICR_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(0)); }
rldicr_(Register a,Register s,int sh6,int mb6)304 inline void Assembler::rldicr_( Register a, Register s, int sh6, int mb6)         { emit_int32(RLDICR_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(1)); }
rldicl(Register a,Register s,int sh6,int me6)305 inline void Assembler::rldicl(  Register a, Register s, int sh6, int me6)         { emit_int32(RLDICL_OPCODE | rta(a) | rs(s) | sh162030(sh6) | me2126(me6) | rc(0)); }
rldicl_(Register a,Register s,int sh6,int me6)306 inline void Assembler::rldicl_( Register a, Register s, int sh6, int me6)         { emit_int32(RLDICL_OPCODE | rta(a) | rs(s) | sh162030(sh6) | me2126(me6) | rc(1)); }
rlwinm(Register a,Register s,int sh5,int mb5,int me5)307 inline void Assembler::rlwinm(  Register a, Register s, int sh5, int mb5, int me5){ emit_int32(RLWINM_OPCODE | rta(a) | rs(s) | sh1620(sh5) | mb2125(mb5) | me2630(me5) | rc(0)); }
rlwinm_(Register a,Register s,int sh5,int mb5,int me5)308 inline void Assembler::rlwinm_( Register a, Register s, int sh5, int mb5, int me5){ emit_int32(RLWINM_OPCODE | rta(a) | rs(s) | sh1620(sh5) | mb2125(mb5) | me2630(me5) | rc(1)); }
rldimi(Register a,Register s,int sh6,int mb6)309 inline void Assembler::rldimi(  Register a, Register s, int sh6, int mb6)         { emit_int32(RLDIMI_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(0)); }
rlwimi(Register a,Register s,int sh5,int mb5,int me5)310 inline void Assembler::rlwimi(  Register a, Register s, int sh5, int mb5, int me5){ emit_int32(RLWIMI_OPCODE | rta(a) | rs(s) | sh1620(sh5) | mb2125(mb5) | me2630(me5) | rc(0)); }
rldimi_(Register a,Register s,int sh6,int mb6)311 inline void Assembler::rldimi_( Register a, Register s, int sh6, int mb6)         { emit_int32(RLDIMI_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(1)); }
insrdi(Register a,Register s,int n,int b)312 inline void Assembler::insrdi(  Register a, Register s, int n,   int b)           { Assembler::rldimi(a, s, 64-(b+n), b); }
insrwi(Register a,Register s,int n,int b)313 inline void Assembler::insrwi(  Register a, Register s, int n,   int b)           { Assembler::rlwimi(a, s, 32-(b+n), b, b+n-1); }
314 
315 // PPC 1, section 3.3.2 Fixed-Point Load Instructions
lwzx(Register d,Register s1,Register s2)316 inline void Assembler::lwzx( Register d, Register s1, Register s2) { emit_int32(LWZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lwz(Register d,int si16,Register s1)317 inline void Assembler::lwz(  Register d, int si16,    Register s1) { emit_int32(LWZ_OPCODE  | rt(d) | d1(si16)   | ra0mem(s1));}
lwzu(Register d,int si16,Register s1)318 inline void Assembler::lwzu( Register d, int si16,    Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LWZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));}
319 
lwax(Register d,Register s1,Register s2)320 inline void Assembler::lwax( Register d, Register s1, Register s2) { emit_int32(LWAX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lwa(Register d,int si16,Register s1)321 inline void Assembler::lwa(  Register d, int si16,    Register s1) { emit_int32(LWA_OPCODE  | rt(d) | ds(si16)   | ra0mem(s1));}
322 
lwbrx(Register d,Register s1,Register s2)323 inline void Assembler::lwbrx( Register d, Register s1, Register s2) { emit_int32(LWBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
324 
lhzx(Register d,Register s1,Register s2)325 inline void Assembler::lhzx( Register d, Register s1, Register s2) { emit_int32(LHZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lhz(Register d,int si16,Register s1)326 inline void Assembler::lhz(  Register d, int si16,    Register s1) { emit_int32(LHZ_OPCODE  | rt(d) | d1(si16)   | ra0mem(s1));}
lhzu(Register d,int si16,Register s1)327 inline void Assembler::lhzu( Register d, int si16,    Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LHZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));}
328 
lhbrx(Register d,Register s1,Register s2)329 inline void Assembler::lhbrx( Register d, Register s1, Register s2) { emit_int32(LHBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
330 
lhax(Register d,Register s1,Register s2)331 inline void Assembler::lhax( Register d, Register s1, Register s2) { emit_int32(LHAX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lha(Register d,int si16,Register s1)332 inline void Assembler::lha(  Register d, int si16,    Register s1) { emit_int32(LHA_OPCODE  | rt(d) | d1(si16)   | ra0mem(s1));}
lhau(Register d,int si16,Register s1)333 inline void Assembler::lhau( Register d, int si16,    Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LHAU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));}
334 
lbzx(Register d,Register s1,Register s2)335 inline void Assembler::lbzx( Register d, Register s1, Register s2) { emit_int32(LBZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lbz(Register d,int si16,Register s1)336 inline void Assembler::lbz(  Register d, int si16,    Register s1) { emit_int32(LBZ_OPCODE  | rt(d) | d1(si16)   | ra0mem(s1));}
lbzu(Register d,int si16,Register s1)337 inline void Assembler::lbzu( Register d, int si16,    Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LBZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));}
338 
ld(Register d,int si16,Register s1)339 inline void Assembler::ld(   Register d, int si16,    Register s1) { emit_int32(LD_OPCODE  | rt(d) | ds(si16)   | ra0mem(s1));}
ldx(Register d,Register s1,Register s2)340 inline void Assembler::ldx(  Register d, Register s1, Register s2) { emit_int32(LDX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
ldu(Register d,int si16,Register s1)341 inline void Assembler::ldu(  Register d, int si16,    Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LDU_OPCODE | rt(d) | ds(si16) | rta0mem(s1));}
ldbrx(Register d,Register s1,Register s2)342 inline void Assembler::ldbrx( Register d, Register s1, Register s2) { emit_int32(LDBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
343 
ld_ptr(Register d,int b,Register s1)344 inline void Assembler::ld_ptr(Register d, int b, Register s1) { ld(d, b, s1); }
DEBUG_ONLY(inline void Assembler::ld_ptr (Register d,ByteSize b,Register s1){ ld(d, in_bytes(b), s1); })345 DEBUG_ONLY(inline void Assembler::ld_ptr(Register d, ByteSize b, Register s1) { ld(d, in_bytes(b), s1); })
346 
347 //  PPC 1, section 3.3.3 Fixed-Point Store Instructions
348 inline void Assembler::stwx( Register d, Register s1, Register s2) { emit_int32(STWX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
stw(Register d,int si16,Register s1)349 inline void Assembler::stw(  Register d, int si16,    Register s1) { emit_int32(STW_OPCODE  | rs(d) | d1(si16)   | ra0mem(s1));}
stwu(Register d,int si16,Register s1)350 inline void Assembler::stwu( Register d, int si16,    Register s1) { emit_int32(STWU_OPCODE | rs(d) | d1(si16)   | rta0mem(s1));}
stwbrx(Register d,Register s1,Register s2)351 inline void Assembler::stwbrx( Register d, Register s1, Register s2) { emit_int32(STWBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
352 
sthx(Register d,Register s1,Register s2)353 inline void Assembler::sthx( Register d, Register s1, Register s2) { emit_int32(STHX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
sth(Register d,int si16,Register s1)354 inline void Assembler::sth(  Register d, int si16,    Register s1) { emit_int32(STH_OPCODE  | rs(d) | d1(si16)   | ra0mem(s1));}
sthu(Register d,int si16,Register s1)355 inline void Assembler::sthu( Register d, int si16,    Register s1) { emit_int32(STHU_OPCODE | rs(d) | d1(si16)   | rta0mem(s1));}
sthbrx(Register d,Register s1,Register s2)356 inline void Assembler::sthbrx( Register d, Register s1, Register s2) { emit_int32(STHBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
357 
stbx(Register d,Register s1,Register s2)358 inline void Assembler::stbx( Register d, Register s1, Register s2) { emit_int32(STBX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
stb(Register d,int si16,Register s1)359 inline void Assembler::stb(  Register d, int si16,    Register s1) { emit_int32(STB_OPCODE  | rs(d) | d1(si16)   | ra0mem(s1));}
stbu(Register d,int si16,Register s1)360 inline void Assembler::stbu( Register d, int si16,    Register s1) { emit_int32(STBU_OPCODE | rs(d) | d1(si16)   | rta0mem(s1));}
361 
std(Register d,int si16,Register s1)362 inline void Assembler::std(  Register d, int si16,    Register s1) { emit_int32(STD_OPCODE  | rs(d) | ds(si16)   | ra0mem(s1));}
stdx(Register d,Register s1,Register s2)363 inline void Assembler::stdx( Register d, Register s1, Register s2) { emit_int32(STDX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
stdu(Register d,int si16,Register s1)364 inline void Assembler::stdu( Register d, int si16,    Register s1) { emit_int32(STDU_OPCODE | rs(d) | ds(si16)   | rta0mem(s1));}
stdux(Register s,Register a,Register b)365 inline void Assembler::stdux(Register s, Register a,  Register b)  { emit_int32(STDUX_OPCODE| rs(s) | rta0mem(a) | rb(b));}
stdbrx(Register d,Register s1,Register s2)366 inline void Assembler::stdbrx( Register d, Register s1, Register s2) { emit_int32(STDBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
367 
st_ptr(Register d,int b,Register s1)368 inline void Assembler::st_ptr(Register d, int b, Register s1) { std(d, b, s1); }
DEBUG_ONLY(inline void Assembler::st_ptr (Register d,ByteSize b,Register s1){ std(d, in_bytes(b), s1); })369 DEBUG_ONLY(inline void Assembler::st_ptr(Register d, ByteSize b, Register s1) { std(d, in_bytes(b), s1); })
370 
371 // PPC 1, section 3.3.13 Move To/From System Register Instructions
372 inline void Assembler::mtlr( Register s1)         { emit_int32(MTLR_OPCODE  | rs(s1)); }
mflr(Register d)373 inline void Assembler::mflr( Register d )         { emit_int32(MFLR_OPCODE  | rt(d)); }
mtctr(Register s1)374 inline void Assembler::mtctr(Register s1)         { emit_int32(MTCTR_OPCODE | rs(s1)); }
mfctr(Register d)375 inline void Assembler::mfctr(Register d )         { emit_int32(MFCTR_OPCODE | rt(d)); }
mtcrf(int afxm,Register s)376 inline void Assembler::mtcrf(int afxm, Register s){ emit_int32(MTCRF_OPCODE | fxm(afxm) | rs(s)); }
mfcr(Register d)377 inline void Assembler::mfcr( Register d )         { emit_int32(MFCR_OPCODE  | rt(d)); }
mcrf(ConditionRegister crd,ConditionRegister cra)378 inline void Assembler::mcrf( ConditionRegister crd, ConditionRegister cra)
379                                                       { emit_int32(MCRF_OPCODE | bf(crd) | bfa(cra)); }
mtcr(Register s)380 inline void Assembler::mtcr( Register s)          { Assembler::mtcrf(0xff, s); }
setb(Register d,ConditionRegister cra)381 inline void Assembler::setb(Register d, ConditionRegister cra)
382                                                   { emit_int32(SETB_OPCODE | rt(d) | bfa(cra)); }
383 
384 // Special purpose registers
385 // Exception Register
mtxer(Register s1)386 inline void Assembler::mtxer(Register s1)         { emit_int32(MTXER_OPCODE | rs(s1)); }
mfxer(Register d)387 inline void Assembler::mfxer(Register d )         { emit_int32(MFXER_OPCODE | rt(d)); }
388 // Vector Register Save Register
mtvrsave(Register s1)389 inline void Assembler::mtvrsave(Register s1)      { emit_int32(MTVRSAVE_OPCODE | rs(s1)); }
mfvrsave(Register d)390 inline void Assembler::mfvrsave(Register d )      { emit_int32(MFVRSAVE_OPCODE | rt(d)); }
391 // Timebase
mftb(Register d)392 inline void Assembler::mftb(Register d )          { emit_int32(MFTB_OPCODE  | rt(d)); }
393 // Introduced with Power 8:
394 // Data Stream Control Register
mtdscr(Register s1)395 inline void Assembler::mtdscr(Register s1)        { emit_int32(MTDSCR_OPCODE | rs(s1)); }
mfdscr(Register d)396 inline void Assembler::mfdscr(Register d )        { emit_int32(MFDSCR_OPCODE | rt(d)); }
397 // Transactional Memory Registers
mftfhar(Register d)398 inline void Assembler::mftfhar(Register d )       { emit_int32(MFTFHAR_OPCODE   | rt(d)); }
mftfiar(Register d)399 inline void Assembler::mftfiar(Register d )       { emit_int32(MFTFIAR_OPCODE   | rt(d)); }
mftexasr(Register d)400 inline void Assembler::mftexasr(Register d )      { emit_int32(MFTEXASR_OPCODE  | rt(d)); }
mftexasru(Register d)401 inline void Assembler::mftexasru(Register d )     { emit_int32(MFTEXASRU_OPCODE | rt(d)); }
402 
403 // SAP JVM 2006-02-13 PPC branch instruction.
404 // PPC 1, section 2.4.1 Branch Instructions
b(address a,relocInfo::relocType rt)405 inline void Assembler::b( address a, relocInfo::relocType rt) { emit_data(BXX_OPCODE| li(disp( intptr_t(a), intptr_t(pc()))) |aa(0)|lk(0), rt); }
b(Label & L)406 inline void Assembler::b( Label& L)                           { b( target(L)); }
bl(address a,relocInfo::relocType rt)407 inline void Assembler::bl(address a, relocInfo::relocType rt) { emit_data(BXX_OPCODE| li(disp( intptr_t(a), intptr_t(pc()))) |aa(0)|lk(1), rt); }
bl(Label & L)408 inline void Assembler::bl(Label& L)                           { bl(target(L)); }
bc(int boint,int biint,address a,relocInfo::relocType rt)409 inline void Assembler::bc( int boint, int biint, address a, relocInfo::relocType rt) { emit_data(BCXX_OPCODE| bo(boint) | bi(biint) | bd(disp( intptr_t(a), intptr_t(pc()))) | aa(0) | lk(0), rt); }
bc(int boint,int biint,Label & L)410 inline void Assembler::bc( int boint, int biint, Label& L)                           { bc(boint, biint, target(L)); }
bcl(int boint,int biint,address a,relocInfo::relocType rt)411 inline void Assembler::bcl(int boint, int biint, address a, relocInfo::relocType rt) { emit_data(BCXX_OPCODE| bo(boint) | bi(biint) | bd(disp( intptr_t(a), intptr_t(pc()))) | aa(0)|lk(1)); }
bcl(int boint,int biint,Label & L)412 inline void Assembler::bcl(int boint, int biint, Label& L)                           { bcl(boint, biint, target(L)); }
413 
bclr(int boint,int biint,int bhint,relocInfo::relocType rt)414 inline void Assembler::bclr(  int boint, int biint, int bhint, relocInfo::relocType rt) { emit_data(BCLR_OPCODE | bo(boint) | bi(biint) | bh(bhint) | aa(0) | lk(0), rt); }
bclrl(int boint,int biint,int bhint,relocInfo::relocType rt)415 inline void Assembler::bclrl( int boint, int biint, int bhint, relocInfo::relocType rt) { emit_data(BCLR_OPCODE | bo(boint) | bi(biint) | bh(bhint) | aa(0) | lk(1), rt); }
bcctr(int boint,int biint,int bhint,relocInfo::relocType rt)416 inline void Assembler::bcctr( int boint, int biint, int bhint, relocInfo::relocType rt) { emit_data(BCCTR_OPCODE| bo(boint) | bi(biint) | bh(bhint) | aa(0) | lk(0), rt); }
bcctrl(int boint,int biint,int bhint,relocInfo::relocType rt)417 inline void Assembler::bcctrl(int boint, int biint, int bhint, relocInfo::relocType rt) { emit_data(BCCTR_OPCODE| bo(boint) | bi(biint) | bh(bhint) | aa(0) | lk(1), rt); }
418 
419 // helper function for b
is_within_range_of_b(address a,address pc)420 inline bool Assembler::is_within_range_of_b(address a, address pc) {
421   // Guard against illegal branch targets, e.g. -1 (see CompiledStaticCall and ad-file).
422   if ((((uint64_t)a) & 0x3) != 0) return false;
423 
424   const int range = 1 << (29-6); // li field is from bit 6 to bit 29.
425   int value = disp(intptr_t(a), intptr_t(pc));
426   bool result = -range <= value && value < range-1;
427 #ifdef ASSERT
428   if (result) li(value); // Assert that value is in correct range.
429 #endif
430   return result;
431 }
432 
433 // helper functions for bcxx.
is_within_range_of_bcxx(address a,address pc)434 inline bool Assembler::is_within_range_of_bcxx(address a, address pc) {
435   // Guard against illegal branch targets, e.g. -1 (see CompiledStaticCall and ad-file).
436   if ((((uint64_t)a) & 0x3) != 0) return false;
437 
438   const int range = 1 << (29-16); // bd field is from bit 16 to bit 29.
439   int value = disp(intptr_t(a), intptr_t(pc));
440   bool result = -range <= value && value < range-1;
441 #ifdef ASSERT
442   if (result) bd(value); // Assert that value is in correct range.
443 #endif
444   return result;
445 }
446 
447 // Get the destination of a bxx branch (b, bl, ba, bla).
bxx_destination(address baddr)448 address  Assembler::bxx_destination(address baddr) { return bxx_destination(*(int*)baddr, baddr); }
bxx_destination(int instr,address pc)449 address  Assembler::bxx_destination(int instr, address pc) { return (address)bxx_destination_offset(instr, (intptr_t)pc); }
bxx_destination_offset(int instr,intptr_t bxx_pos)450 intptr_t Assembler::bxx_destination_offset(int instr, intptr_t bxx_pos) {
451   intptr_t displ = inv_li_field(instr);
452   return bxx_pos + displ;
453 }
454 
455 // Extended mnemonics for Branch Instructions
blt(ConditionRegister crx,Label & L)456 inline void Assembler::blt(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs1, bi0(crx, less), L); }
bgt(ConditionRegister crx,Label & L)457 inline void Assembler::bgt(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs1, bi0(crx, greater), L); }
beq(ConditionRegister crx,Label & L)458 inline void Assembler::beq(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs1, bi0(crx, equal), L); }
bso(ConditionRegister crx,Label & L)459 inline void Assembler::bso(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs1, bi0(crx, summary_overflow), L); }
bge(ConditionRegister crx,Label & L)460 inline void Assembler::bge(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs0, bi0(crx, less), L); }
ble(ConditionRegister crx,Label & L)461 inline void Assembler::ble(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs0, bi0(crx, greater), L); }
bne(ConditionRegister crx,Label & L)462 inline void Assembler::bne(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs0, bi0(crx, equal), L); }
bns(ConditionRegister crx,Label & L)463 inline void Assembler::bns(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs0, bi0(crx, summary_overflow), L); }
464 
465 // Branch instructions with static prediction hints.
blt_predict_taken(ConditionRegister crx,Label & L)466 inline void Assembler::blt_predict_taken    (ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsTaken,    bi0(crx, less), L); }
bgt_predict_taken(ConditionRegister crx,Label & L)467 inline void Assembler::bgt_predict_taken    (ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsTaken,    bi0(crx, greater), L); }
beq_predict_taken(ConditionRegister crx,Label & L)468 inline void Assembler::beq_predict_taken    (ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsTaken,    bi0(crx, equal), L); }
bso_predict_taken(ConditionRegister crx,Label & L)469 inline void Assembler::bso_predict_taken    (ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsTaken,    bi0(crx, summary_overflow), L); }
bge_predict_taken(ConditionRegister crx,Label & L)470 inline void Assembler::bge_predict_taken    (ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsTaken,    bi0(crx, less), L); }
ble_predict_taken(ConditionRegister crx,Label & L)471 inline void Assembler::ble_predict_taken    (ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsTaken,    bi0(crx, greater), L); }
bne_predict_taken(ConditionRegister crx,Label & L)472 inline void Assembler::bne_predict_taken    (ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsTaken,    bi0(crx, equal), L); }
bns_predict_taken(ConditionRegister crx,Label & L)473 inline void Assembler::bns_predict_taken    (ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsTaken,    bi0(crx, summary_overflow), L); }
blt_predict_not_taken(ConditionRegister crx,Label & L)474 inline void Assembler::blt_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsNotTaken, bi0(crx, less), L); }
bgt_predict_not_taken(ConditionRegister crx,Label & L)475 inline void Assembler::bgt_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsNotTaken, bi0(crx, greater), L); }
beq_predict_not_taken(ConditionRegister crx,Label & L)476 inline void Assembler::beq_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsNotTaken, bi0(crx, equal), L); }
bso_predict_not_taken(ConditionRegister crx,Label & L)477 inline void Assembler::bso_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsNotTaken, bi0(crx, summary_overflow), L); }
bge_predict_not_taken(ConditionRegister crx,Label & L)478 inline void Assembler::bge_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsNotTaken, bi0(crx, less), L); }
ble_predict_not_taken(ConditionRegister crx,Label & L)479 inline void Assembler::ble_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsNotTaken, bi0(crx, greater), L); }
bne_predict_not_taken(ConditionRegister crx,Label & L)480 inline void Assembler::bne_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsNotTaken, bi0(crx, equal), L); }
bns_predict_not_taken(ConditionRegister crx,Label & L)481 inline void Assembler::bns_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsNotTaken, bi0(crx, summary_overflow), L); }
482 
483 // For use in conjunction with testbitdi:
btrue(ConditionRegister crx,Label & L)484 inline void Assembler::btrue( ConditionRegister crx, Label& L) { Assembler::bne(crx, L); }
bfalse(ConditionRegister crx,Label & L)485 inline void Assembler::bfalse(ConditionRegister crx, Label& L) { Assembler::beq(crx, L); }
486 
bltl(ConditionRegister crx,Label & L)487 inline void Assembler::bltl(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs1, bi0(crx, less), L); }
bgtl(ConditionRegister crx,Label & L)488 inline void Assembler::bgtl(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs1, bi0(crx, greater), L); }
beql(ConditionRegister crx,Label & L)489 inline void Assembler::beql(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs1, bi0(crx, equal), L); }
bsol(ConditionRegister crx,Label & L)490 inline void Assembler::bsol(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs1, bi0(crx, summary_overflow), L); }
bgel(ConditionRegister crx,Label & L)491 inline void Assembler::bgel(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs0, bi0(crx, less), L); }
blel(ConditionRegister crx,Label & L)492 inline void Assembler::blel(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs0, bi0(crx, greater), L); }
bnel(ConditionRegister crx,Label & L)493 inline void Assembler::bnel(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs0, bi0(crx, equal), L); }
bnsl(ConditionRegister crx,Label & L)494 inline void Assembler::bnsl(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs0, bi0(crx, summary_overflow), L); }
495 
496 // Extended mnemonics for Branch Instructions via LR.
497 // We use `blr' for returns.
blr(relocInfo::relocType rt)498 inline void Assembler::blr(relocInfo::relocType rt) { Assembler::bclr(bcondAlways, 0, bhintbhBCLRisReturn, rt); }
499 
500 // Extended mnemonics for Branch Instructions with CTR.
501 // Bdnz means `decrement CTR and jump to L if CTR is not zero'.
bdnz(Label & L)502 inline void Assembler::bdnz(Label& L) { Assembler::bc(16, 0, L); }
503 // Decrement and branch if result is zero.
bdz(Label & L)504 inline void Assembler::bdz(Label& L)  { Assembler::bc(18, 0, L); }
505 // We use `bctr[l]' for jumps/calls in function descriptor glue
506 // code, e.g. for calls to runtime functions.
bctr(relocInfo::relocType rt)507 inline void Assembler::bctr( relocInfo::relocType rt) { Assembler::bcctr(bcondAlways, 0, bhintbhBCCTRisNotReturnButSame, rt); }
bctrl(relocInfo::relocType rt)508 inline void Assembler::bctrl(relocInfo::relocType rt) { Assembler::bcctrl(bcondAlways, 0, bhintbhBCCTRisNotReturnButSame, rt); }
509 // Conditional jumps/branches via CTR.
beqctr(ConditionRegister crx,relocInfo::relocType rt)510 inline void Assembler::beqctr( ConditionRegister crx, relocInfo::relocType rt) { Assembler::bcctr( bcondCRbiIs1, bi0(crx, equal), bhintbhBCCTRisNotReturnButSame, rt); }
beqctrl(ConditionRegister crx,relocInfo::relocType rt)511 inline void Assembler::beqctrl(ConditionRegister crx, relocInfo::relocType rt) { Assembler::bcctrl(bcondCRbiIs1, bi0(crx, equal), bhintbhBCCTRisNotReturnButSame, rt); }
bnectr(ConditionRegister crx,relocInfo::relocType rt)512 inline void Assembler::bnectr( ConditionRegister crx, relocInfo::relocType rt) { Assembler::bcctr( bcondCRbiIs0, bi0(crx, equal), bhintbhBCCTRisNotReturnButSame, rt); }
bnectrl(ConditionRegister crx,relocInfo::relocType rt)513 inline void Assembler::bnectrl(ConditionRegister crx, relocInfo::relocType rt) { Assembler::bcctrl(bcondCRbiIs0, bi0(crx, equal), bhintbhBCCTRisNotReturnButSame, rt); }
514 
515 // condition register logic instructions
crand(int d,int s1,int s2)516 inline void Assembler::crand( int d, int s1, int s2) { emit_int32(CRAND_OPCODE  | bt(d) | ba(s1) | bb(s2)); }
crnand(int d,int s1,int s2)517 inline void Assembler::crnand(int d, int s1, int s2) { emit_int32(CRNAND_OPCODE | bt(d) | ba(s1) | bb(s2)); }
cror(int d,int s1,int s2)518 inline void Assembler::cror(  int d, int s1, int s2) { emit_int32(CROR_OPCODE   | bt(d) | ba(s1) | bb(s2)); }
crxor(int d,int s1,int s2)519 inline void Assembler::crxor( int d, int s1, int s2) { emit_int32(CRXOR_OPCODE  | bt(d) | ba(s1) | bb(s2)); }
crnor(int d,int s1,int s2)520 inline void Assembler::crnor( int d, int s1, int s2) { emit_int32(CRNOR_OPCODE  | bt(d) | ba(s1) | bb(s2)); }
creqv(int d,int s1,int s2)521 inline void Assembler::creqv( int d, int s1, int s2) { emit_int32(CREQV_OPCODE  | bt(d) | ba(s1) | bb(s2)); }
crandc(int d,int s1,int s2)522 inline void Assembler::crandc(int d, int s1, int s2) { emit_int32(CRANDC_OPCODE | bt(d) | ba(s1) | bb(s2)); }
crorc(int d,int s1,int s2)523 inline void Assembler::crorc( int d, int s1, int s2) { emit_int32(CRORC_OPCODE  | bt(d) | ba(s1) | bb(s2)); }
524 
525 // More convenient version.
crand(ConditionRegister crdst,Condition cdst,ConditionRegister crsrc,Condition csrc)526 inline void Assembler::crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc) {
527   int dst_bit = condition_register_bit(crdst, cdst),
528       src_bit = condition_register_bit(crsrc, csrc);
529   crand(dst_bit, src_bit, dst_bit);
530 }
crnand(ConditionRegister crdst,Condition cdst,ConditionRegister crsrc,Condition csrc)531 inline void Assembler::crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc) {
532   int dst_bit = condition_register_bit(crdst, cdst),
533       src_bit = condition_register_bit(crsrc, csrc);
534   crnand(dst_bit, src_bit, dst_bit);
535 }
cror(ConditionRegister crdst,Condition cdst,ConditionRegister crsrc,Condition csrc)536 inline void Assembler::cror(  ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc) {
537   int dst_bit = condition_register_bit(crdst, cdst),
538       src_bit = condition_register_bit(crsrc, csrc);
539   cror(dst_bit, src_bit, dst_bit);
540 }
crxor(ConditionRegister crdst,Condition cdst,ConditionRegister crsrc,Condition csrc)541 inline void Assembler::crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc) {
542   int dst_bit = condition_register_bit(crdst, cdst),
543       src_bit = condition_register_bit(crsrc, csrc);
544   crxor(dst_bit, src_bit, dst_bit);
545 }
crnor(ConditionRegister crdst,Condition cdst,ConditionRegister crsrc,Condition csrc)546 inline void Assembler::crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc) {
547   int dst_bit = condition_register_bit(crdst, cdst),
548       src_bit = condition_register_bit(crsrc, csrc);
549   crnor(dst_bit, src_bit, dst_bit);
550 }
creqv(ConditionRegister crdst,Condition cdst,ConditionRegister crsrc,Condition csrc)551 inline void Assembler::creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc) {
552   int dst_bit = condition_register_bit(crdst, cdst),
553       src_bit = condition_register_bit(crsrc, csrc);
554   creqv(dst_bit, src_bit, dst_bit);
555 }
crandc(ConditionRegister crdst,Condition cdst,ConditionRegister crsrc,Condition csrc)556 inline void Assembler::crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc) {
557   int dst_bit = condition_register_bit(crdst, cdst),
558       src_bit = condition_register_bit(crsrc, csrc);
559   crandc(dst_bit, src_bit, dst_bit);
560 }
crorc(ConditionRegister crdst,Condition cdst,ConditionRegister crsrc,Condition csrc)561 inline void Assembler::crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc) {
562   int dst_bit = condition_register_bit(crdst, cdst),
563       src_bit = condition_register_bit(crsrc, csrc);
564   crorc(dst_bit, src_bit, dst_bit);
565 }
566 
567 // Conditional move (>= Power7)
isel(Register d,ConditionRegister cr,Condition cc,bool inv,Register a,Register b)568 inline void Assembler::isel(Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b) {
569   if (b == noreg) {
570     b = d; // Can be omitted if old value should be kept in "else" case.
571   }
572   Register first = a;
573   Register second = b;
574   if (inv) {
575     first = b;
576     second = a; // exchange
577   }
578   assert(first != R0, "r0 not allowed");
579   isel(d, first, second, bi0(cr, cc));
580 }
isel_0(Register d,ConditionRegister cr,Condition cc,Register b)581 inline void Assembler::isel_0(Register d, ConditionRegister cr, Condition cc, Register b) {
582   if (b == noreg) {
583     b = d; // Can be omitted if old value should be kept in "else" case.
584   }
585   isel(d, R0, b, bi0(cr, cc));
586 }
587 
588 // PPC 2, section 3.2.1 Instruction Cache Instructions
icbi(Register s1,Register s2)589 inline void Assembler::icbi(    Register s1, Register s2)         { emit_int32( ICBI_OPCODE   | ra0mem(s1) | rb(s2)           ); }
590 // PPC 2, section 3.2.2 Data Cache Instructions
591 //inline void Assembler::dcba(  Register s1, Register s2)         { emit_int32( DCBA_OPCODE   | ra0mem(s1) | rb(s2)           ); }
dcbz(Register s1,Register s2)592 inline void Assembler::dcbz(    Register s1, Register s2)         { emit_int32( DCBZ_OPCODE   | ra0mem(s1) | rb(s2)           ); }
dcbst(Register s1,Register s2)593 inline void Assembler::dcbst(   Register s1, Register s2)         { emit_int32( DCBST_OPCODE  | ra0mem(s1) | rb(s2)           ); }
dcbf(Register s1,Register s2)594 inline void Assembler::dcbf(    Register s1, Register s2)         { emit_int32( DCBF_OPCODE   | ra0mem(s1) | rb(s2)           ); }
595 // dcache read hint
dcbt(Register s1,Register s2)596 inline void Assembler::dcbt(    Register s1, Register s2)         { emit_int32( DCBT_OPCODE   | ra0mem(s1) | rb(s2)           ); }
dcbtct(Register s1,Register s2,int ct)597 inline void Assembler::dcbtct(  Register s1, Register s2, int ct) { emit_int32( DCBT_OPCODE   | ra0mem(s1) | rb(s2) | thct(ct)); }
dcbtds(Register s1,Register s2,int ds)598 inline void Assembler::dcbtds(  Register s1, Register s2, int ds) { emit_int32( DCBT_OPCODE   | ra0mem(s1) | rb(s2) | thds(ds)); }
599 // dcache write hint
dcbtst(Register s1,Register s2)600 inline void Assembler::dcbtst(  Register s1, Register s2)         { emit_int32( DCBTST_OPCODE | ra0mem(s1) | rb(s2)           ); }
dcbtstct(Register s1,Register s2,int ct)601 inline void Assembler::dcbtstct(Register s1, Register s2, int ct) { emit_int32( DCBTST_OPCODE | ra0mem(s1) | rb(s2) | thct(ct)); }
602 
603 // machine barrier instructions:
sync(int a)604 inline void Assembler::sync(int a) { emit_int32( SYNC_OPCODE | l910(a)); }
sync()605 inline void Assembler::sync()      { Assembler::sync(0); }
lwsync()606 inline void Assembler::lwsync()    { Assembler::sync(1); }
ptesync()607 inline void Assembler::ptesync()   { Assembler::sync(2); }
eieio()608 inline void Assembler::eieio()     { emit_int32( EIEIO_OPCODE); }
isync()609 inline void Assembler::isync()     { emit_int32( ISYNC_OPCODE); }
elemental_membar(int e)610 inline void Assembler::elemental_membar(int e) { assert(0 < e && e < 16, "invalid encoding"); emit_int32( SYNC_OPCODE | e1215(e)); }
611 
612 // Wait instructions for polling.
wait()613 inline void Assembler::wait()    { emit_int32( WAIT_OPCODE); }
waitrsv()614 inline void Assembler::waitrsv() { emit_int32( WAIT_OPCODE | 1<<(31-10)); } // WC=0b01 >=Power7
615 
616 // atomics
617 // Use ra0mem to disallow R0 as base.
lbarx_unchecked(Register d,Register a,Register b,int eh1)618 inline void Assembler::lbarx_unchecked(Register d, Register a, Register b, int eh1)           { emit_int32( LBARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
lharx_unchecked(Register d,Register a,Register b,int eh1)619 inline void Assembler::lharx_unchecked(Register d, Register a, Register b, int eh1)           { emit_int32( LHARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
lwarx_unchecked(Register d,Register a,Register b,int eh1)620 inline void Assembler::lwarx_unchecked(Register d, Register a, Register b, int eh1)           { emit_int32( LWARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
ldarx_unchecked(Register d,Register a,Register b,int eh1)621 inline void Assembler::ldarx_unchecked(Register d, Register a, Register b, int eh1)           { emit_int32( LDARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
lqarx_unchecked(Register d,Register a,Register b,int eh1)622 inline void Assembler::lqarx_unchecked(Register d, Register a, Register b, int eh1)           { emit_int32( LQARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
lxarx_hint_exclusive_access()623 inline bool Assembler::lxarx_hint_exclusive_access()                                          { return VM_Version::has_lxarxeh(); }
lbarx(Register d,Register a,Register b,bool hint_exclusive_access)624 inline void Assembler::lbarx( Register d, Register a, Register b, bool hint_exclusive_access) { lbarx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
lharx(Register d,Register a,Register b,bool hint_exclusive_access)625 inline void Assembler::lharx( Register d, Register a, Register b, bool hint_exclusive_access) { lharx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
lwarx(Register d,Register a,Register b,bool hint_exclusive_access)626 inline void Assembler::lwarx( Register d, Register a, Register b, bool hint_exclusive_access) { lwarx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
ldarx(Register d,Register a,Register b,bool hint_exclusive_access)627 inline void Assembler::ldarx( Register d, Register a, Register b, bool hint_exclusive_access) { ldarx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
lqarx(Register d,Register a,Register b,bool hint_exclusive_access)628 inline void Assembler::lqarx( Register d, Register a, Register b, bool hint_exclusive_access) { lqarx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
stbcx_(Register s,Register a,Register b)629 inline void Assembler::stbcx_(Register s, Register a, Register b)                             { emit_int32( STBCX_OPCODE | rs(s) | ra0mem(a) | rb(b) | rc(1)); }
sthcx_(Register s,Register a,Register b)630 inline void Assembler::sthcx_(Register s, Register a, Register b)                             { emit_int32( STHCX_OPCODE | rs(s) | ra0mem(a) | rb(b) | rc(1)); }
stwcx_(Register s,Register a,Register b)631 inline void Assembler::stwcx_(Register s, Register a, Register b)                             { emit_int32( STWCX_OPCODE | rs(s) | ra0mem(a) | rb(b) | rc(1)); }
stdcx_(Register s,Register a,Register b)632 inline void Assembler::stdcx_(Register s, Register a, Register b)                             { emit_int32( STDCX_OPCODE | rs(s) | ra0mem(a) | rb(b) | rc(1)); }
stqcx_(Register s,Register a,Register b)633 inline void Assembler::stqcx_(Register s, Register a, Register b)                             { emit_int32( STQCX_OPCODE | rs(s) | ra0mem(a) | rb(b) | rc(1)); }
634 
635 // Instructions for adjusting thread priority
636 // for simultaneous multithreading (SMT) on >= POWER5.
smt_prio_very_low()637 inline void Assembler::smt_prio_very_low()    { Assembler::or_unchecked(R31, R31, R31); }
smt_prio_low()638 inline void Assembler::smt_prio_low()         { Assembler::or_unchecked(R1,  R1,  R1); }
smt_prio_medium_low()639 inline void Assembler::smt_prio_medium_low()  { Assembler::or_unchecked(R6,  R6,  R6); }
smt_prio_medium()640 inline void Assembler::smt_prio_medium()      { Assembler::or_unchecked(R2,  R2,  R2); }
smt_prio_medium_high()641 inline void Assembler::smt_prio_medium_high() { Assembler::or_unchecked(R5,  R5,  R5); }
smt_prio_high()642 inline void Assembler::smt_prio_high()        { Assembler::or_unchecked(R3,  R3,  R3); }
643 // >= Power7
smt_yield()644 inline void Assembler::smt_yield()            { Assembler::or_unchecked(R27, R27, R27); } // never actually implemented
smt_mdoio()645 inline void Assembler::smt_mdoio()            { Assembler::or_unchecked(R29, R29, R29); } // never actually implemetned
smt_mdoom()646 inline void Assembler::smt_mdoom()            { Assembler::or_unchecked(R30, R30, R30); } // never actually implemented
647 // Power8
smt_miso()648 inline void Assembler::smt_miso()             { Assembler::or_unchecked(R26, R26, R26); } // never actually implemented
649 
twi_0(Register a)650 inline void Assembler::twi_0(Register a)      { twi_unchecked(0, a, 0);}
651 
652 // trap instructions
tdi_unchecked(int tobits,Register a,int si16)653 inline void Assembler::tdi_unchecked(int tobits, Register a, int si16){                                     emit_int32( TDI_OPCODE | to(tobits) | ra(a) | si(si16)); }
twi_unchecked(int tobits,Register a,int si16)654 inline void Assembler::twi_unchecked(int tobits, Register a, int si16){                                     emit_int32( TWI_OPCODE | to(tobits) | ra(a) | si(si16)); }
tdi(int tobits,Register a,int si16)655 inline void Assembler::tdi(int tobits, Register a, int si16)          { assert(UseSIGTRAP, "precondition"); tdi_unchecked(tobits, a, si16);                      }
twi(int tobits,Register a,int si16)656 inline void Assembler::twi(int tobits, Register a, int si16)          { assert(UseSIGTRAP, "precondition"); twi_unchecked(tobits, a, si16);                      }
td(int tobits,Register a,Register b)657 inline void Assembler::td( int tobits, Register a, Register b)        { assert(UseSIGTRAP, "precondition"); emit_int32( TD_OPCODE  | to(tobits) | ra(a) | rb(b)); }
tw(int tobits,Register a,Register b)658 inline void Assembler::tw( int tobits, Register a, Register b)        { assert(UseSIGTRAP, "precondition"); emit_int32( TW_OPCODE  | to(tobits) | ra(a) | rb(b)); }
659 
660 // FLOATING POINT instructions ppc.
661 // PPC 1, section 4.6.2 Floating-Point Load Instructions
662 // Use ra0mem instead of ra in some instructions below.
lfs(FloatRegister d,int si16,Register a)663 inline void Assembler::lfs( FloatRegister d, int si16, Register a)   { emit_int32( LFS_OPCODE  | frt(d) | ra0mem(a) | simm(si16,16)); }
lfsu(FloatRegister d,int si16,Register a)664 inline void Assembler::lfsu(FloatRegister d, int si16, Register a)   { emit_int32( LFSU_OPCODE | frt(d) | ra(a)     | simm(si16,16)); }
lfsx(FloatRegister d,Register a,Register b)665 inline void Assembler::lfsx(FloatRegister d, Register a, Register b) { emit_int32( LFSX_OPCODE | frt(d) | ra0mem(a) | rb(b)); }
lfd(FloatRegister d,int si16,Register a)666 inline void Assembler::lfd( FloatRegister d, int si16, Register a)   { emit_int32( LFD_OPCODE  | frt(d) | ra0mem(a) | simm(si16,16)); }
lfdu(FloatRegister d,int si16,Register a)667 inline void Assembler::lfdu(FloatRegister d, int si16, Register a)   { emit_int32( LFDU_OPCODE | frt(d) | ra(a)     | simm(si16,16)); }
lfdx(FloatRegister d,Register a,Register b)668 inline void Assembler::lfdx(FloatRegister d, Register a, Register b) { emit_int32( LFDX_OPCODE | frt(d) | ra0mem(a) | rb(b)); }
669 
670 // PPC 1, section 4.6.3 Floating-Point Store Instructions
671 // Use ra0mem instead of ra in some instructions below.
stfs(FloatRegister s,int si16,Register a)672 inline void Assembler::stfs( FloatRegister s, int si16, Register a)  { emit_int32( STFS_OPCODE  | frs(s) | ra0mem(a) | simm(si16,16)); }
stfsu(FloatRegister s,int si16,Register a)673 inline void Assembler::stfsu(FloatRegister s, int si16, Register a)  { emit_int32( STFSU_OPCODE | frs(s) | ra(a)     | simm(si16,16)); }
stfsx(FloatRegister s,Register a,Register b)674 inline void Assembler::stfsx(FloatRegister s, Register a, Register b){ emit_int32( STFSX_OPCODE | frs(s) | ra0mem(a) | rb(b)); }
stfd(FloatRegister s,int si16,Register a)675 inline void Assembler::stfd( FloatRegister s, int si16, Register a)  { emit_int32( STFD_OPCODE  | frs(s) | ra0mem(a) | simm(si16,16)); }
stfdu(FloatRegister s,int si16,Register a)676 inline void Assembler::stfdu(FloatRegister s, int si16, Register a)  { emit_int32( STFDU_OPCODE | frs(s) | ra(a)     | simm(si16,16)); }
stfdx(FloatRegister s,Register a,Register b)677 inline void Assembler::stfdx(FloatRegister s, Register a, Register b){ emit_int32( STFDX_OPCODE | frs(s) | ra0mem(a) | rb(b)); }
678 
679 // PPC 1, section 4.6.4 Floating-Point Move Instructions
fmr(FloatRegister d,FloatRegister b)680 inline void Assembler::fmr( FloatRegister d, FloatRegister b) { emit_int32( FMR_OPCODE | frt(d) | frb(b) | rc(0)); }
fmr_(FloatRegister d,FloatRegister b)681 inline void Assembler::fmr_(FloatRegister d, FloatRegister b) { emit_int32( FMR_OPCODE | frt(d) | frb(b) | rc(1)); }
682 
683 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
684 // on Power7.  Do not use.
685 //inline void Assembler::mffgpr( FloatRegister d, Register b)   { emit_int32( MFFGPR_OPCODE | frt(d) | rb(b) | rc(0)); }
686 //inline void Assembler::mftgpr( Register d, FloatRegister b)   { emit_int32( MFTGPR_OPCODE | rt(d) | frb(b) | rc(0)); }
687 // add cmpb and popcntb to detect ppc power version.
cmpb(Register a,Register s,Register b)688 inline void Assembler::cmpb(   Register a, Register s, Register b) { guarantee(VM_Version::has_cmpb(), "opcode not supported on this hardware");
689                                                                      emit_int32( CMPB_OPCODE    | rta(a) | rs(s) | rb(b) | rc(0)); }
popcntb(Register a,Register s)690 inline void Assembler::popcntb(Register a, Register s)             { guarantee(VM_Version::has_popcntb(), "opcode not supported on this hardware");
691                                                                      emit_int32( POPCNTB_OPCODE | rta(a) | rs(s)); };
popcntw(Register a,Register s)692 inline void Assembler::popcntw(Register a, Register s)             { guarantee(VM_Version::has_popcntw(), "opcode not supported on this hardware");
693                                                                      emit_int32( POPCNTW_OPCODE | rta(a) | rs(s)); };
popcntd(Register a,Register s)694 inline void Assembler::popcntd(Register a, Register s)             { emit_int32( POPCNTD_OPCODE | rta(a) | rs(s)); };
695 
fneg(FloatRegister d,FloatRegister b)696 inline void Assembler::fneg(  FloatRegister d, FloatRegister b) { emit_int32( FNEG_OPCODE  | frt(d) | frb(b) | rc(0)); }
fneg_(FloatRegister d,FloatRegister b)697 inline void Assembler::fneg_( FloatRegister d, FloatRegister b) { emit_int32( FNEG_OPCODE  | frt(d) | frb(b) | rc(1)); }
fabs(FloatRegister d,FloatRegister b)698 inline void Assembler::fabs(  FloatRegister d, FloatRegister b) { emit_int32( FABS_OPCODE  | frt(d) | frb(b) | rc(0)); }
fabs_(FloatRegister d,FloatRegister b)699 inline void Assembler::fabs_( FloatRegister d, FloatRegister b) { emit_int32( FABS_OPCODE  | frt(d) | frb(b) | rc(1)); }
fnabs(FloatRegister d,FloatRegister b)700 inline void Assembler::fnabs( FloatRegister d, FloatRegister b) { emit_int32( FNABS_OPCODE | frt(d) | frb(b) | rc(0)); }
fnabs_(FloatRegister d,FloatRegister b)701 inline void Assembler::fnabs_(FloatRegister d, FloatRegister b) { emit_int32( FNABS_OPCODE | frt(d) | frb(b) | rc(1)); }
702 
703 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
fadd(FloatRegister d,FloatRegister a,FloatRegister b)704 inline void Assembler::fadd(  FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FADD_OPCODE  | frt(d) | fra(a) | frb(b) | rc(0)); }
fadd_(FloatRegister d,FloatRegister a,FloatRegister b)705 inline void Assembler::fadd_( FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FADD_OPCODE  | frt(d) | fra(a) | frb(b) | rc(1)); }
fadds(FloatRegister d,FloatRegister a,FloatRegister b)706 inline void Assembler::fadds( FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FADDS_OPCODE | frt(d) | fra(a) | frb(b) | rc(0)); }
fadds_(FloatRegister d,FloatRegister a,FloatRegister b)707 inline void Assembler::fadds_(FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FADDS_OPCODE | frt(d) | fra(a) | frb(b) | rc(1)); }
fsub(FloatRegister d,FloatRegister a,FloatRegister b)708 inline void Assembler::fsub(  FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FSUB_OPCODE  | frt(d) | fra(a) | frb(b) | rc(0)); }
fsub_(FloatRegister d,FloatRegister a,FloatRegister b)709 inline void Assembler::fsub_( FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FSUB_OPCODE  | frt(d) | fra(a) | frb(b) | rc(1)); }
fsubs(FloatRegister d,FloatRegister a,FloatRegister b)710 inline void Assembler::fsubs( FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FSUBS_OPCODE | frt(d) | fra(a) | frb(b) | rc(0)); }
fsubs_(FloatRegister d,FloatRegister a,FloatRegister b)711 inline void Assembler::fsubs_(FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FSUBS_OPCODE | frt(d) | fra(a) | frb(b) | rc(1)); }
fmul(FloatRegister d,FloatRegister a,FloatRegister c)712 inline void Assembler::fmul(  FloatRegister d, FloatRegister a, FloatRegister c) { emit_int32( FMUL_OPCODE  | frt(d) | fra(a) | frc(c) | rc(0)); }
fmul_(FloatRegister d,FloatRegister a,FloatRegister c)713 inline void Assembler::fmul_( FloatRegister d, FloatRegister a, FloatRegister c) { emit_int32( FMUL_OPCODE  | frt(d) | fra(a) | frc(c) | rc(1)); }
fmuls(FloatRegister d,FloatRegister a,FloatRegister c)714 inline void Assembler::fmuls( FloatRegister d, FloatRegister a, FloatRegister c) { emit_int32( FMULS_OPCODE | frt(d) | fra(a) | frc(c) | rc(0)); }
fmuls_(FloatRegister d,FloatRegister a,FloatRegister c)715 inline void Assembler::fmuls_(FloatRegister d, FloatRegister a, FloatRegister c) { emit_int32( FMULS_OPCODE | frt(d) | fra(a) | frc(c) | rc(1)); }
fdiv(FloatRegister d,FloatRegister a,FloatRegister b)716 inline void Assembler::fdiv(  FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FDIV_OPCODE  | frt(d) | fra(a) | frb(b) | rc(0)); }
fdiv_(FloatRegister d,FloatRegister a,FloatRegister b)717 inline void Assembler::fdiv_( FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FDIV_OPCODE  | frt(d) | fra(a) | frb(b) | rc(1)); }
fdivs(FloatRegister d,FloatRegister a,FloatRegister b)718 inline void Assembler::fdivs( FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FDIVS_OPCODE | frt(d) | fra(a) | frb(b) | rc(0)); }
fdivs_(FloatRegister d,FloatRegister a,FloatRegister b)719 inline void Assembler::fdivs_(FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FDIVS_OPCODE | frt(d) | fra(a) | frb(b) | rc(1)); }
720 
721 // Fused multiply-accumulate instructions.
722 // WARNING: Use only when rounding between the 2 parts is not desired.
723 // Some floating point tck tests will fail if used incorrectly.
fmadd(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)724 inline void Assembler::fmadd(   FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMADD_OPCODE   | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
fmadd_(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)725 inline void Assembler::fmadd_(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMADD_OPCODE   | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
fmadds(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)726 inline void Assembler::fmadds(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMADDS_OPCODE  | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
fmadds_(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)727 inline void Assembler::fmadds_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMADDS_OPCODE  | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
fmsub(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)728 inline void Assembler::fmsub(   FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMSUB_OPCODE   | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
fmsub_(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)729 inline void Assembler::fmsub_(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMSUB_OPCODE   | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
fmsubs(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)730 inline void Assembler::fmsubs(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMSUBS_OPCODE  | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
fmsubs_(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)731 inline void Assembler::fmsubs_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMSUBS_OPCODE  | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
fnmadd(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)732 inline void Assembler::fnmadd(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMADD_OPCODE  | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
fnmadd_(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)733 inline void Assembler::fnmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMADD_OPCODE  | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
fnmadds(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)734 inline void Assembler::fnmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMADDS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
fnmadds_(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)735 inline void Assembler::fnmadds_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMADDS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
fnmsub(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)736 inline void Assembler::fnmsub(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMSUB_OPCODE  | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
fnmsub_(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)737 inline void Assembler::fnmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMSUB_OPCODE  | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
fnmsubs(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)738 inline void Assembler::fnmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMSUBS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
fnmsubs_(FloatRegister d,FloatRegister a,FloatRegister c,FloatRegister b)739 inline void Assembler::fnmsubs_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMSUBS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
740 
741 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
frsp(FloatRegister d,FloatRegister b)742 inline void Assembler::frsp(  FloatRegister d, FloatRegister b) { emit_int32( FRSP_OPCODE   | frt(d) | frb(b) | rc(0)); }
fctid(FloatRegister d,FloatRegister b)743 inline void Assembler::fctid( FloatRegister d, FloatRegister b) { emit_int32( FCTID_OPCODE  | frt(d) | frb(b) | rc(0)); }
fctidz(FloatRegister d,FloatRegister b)744 inline void Assembler::fctidz(FloatRegister d, FloatRegister b) { emit_int32( FCTIDZ_OPCODE | frt(d) | frb(b) | rc(0)); }
fctiw(FloatRegister d,FloatRegister b)745 inline void Assembler::fctiw( FloatRegister d, FloatRegister b) { emit_int32( FCTIW_OPCODE  | frt(d) | frb(b) | rc(0)); }
fctiwz(FloatRegister d,FloatRegister b)746 inline void Assembler::fctiwz(FloatRegister d, FloatRegister b) { emit_int32( FCTIWZ_OPCODE | frt(d) | frb(b) | rc(0)); }
fcfid(FloatRegister d,FloatRegister b)747 inline void Assembler::fcfid( FloatRegister d, FloatRegister b) { emit_int32( FCFID_OPCODE  | frt(d) | frb(b) | rc(0)); }
fcfids(FloatRegister d,FloatRegister b)748 inline void Assembler::fcfids(FloatRegister d, FloatRegister b) { guarantee(VM_Version::has_fcfids(), "opcode not supported on this hardware");
749                                                                   emit_int32( FCFIDS_OPCODE | frt(d) | frb(b) | rc(0)); }
750 
751 // PPC 1, section 4.6.7 Floating-Point Compare Instructions
fcmpu(ConditionRegister crx,FloatRegister a,FloatRegister b)752 inline void Assembler::fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b) { emit_int32( FCMPU_OPCODE | bf(crx) | fra(a) | frb(b)); }
753 
754 // PPC 1, section 5.2.1 Floating-Point Arithmetic Instructions
fsqrt(FloatRegister d,FloatRegister b)755 inline void Assembler::fsqrt( FloatRegister d, FloatRegister b) { guarantee(VM_Version::has_fsqrt(), "opcode not supported on this hardware");
756                                                                   emit_int32( FSQRT_OPCODE  | frt(d) | frb(b) | rc(0)); }
fsqrts(FloatRegister d,FloatRegister b)757 inline void Assembler::fsqrts(FloatRegister d, FloatRegister b) { guarantee(VM_Version::has_fsqrts(), "opcode not supported on this hardware");
758                                                                   emit_int32( FSQRTS_OPCODE | frt(d) | frb(b) | rc(0)); }
759 
760 // Vector instructions for >= Power6.
lvebx(VectorRegister d,Register s1,Register s2)761 inline void Assembler::lvebx( VectorRegister d, Register s1, Register s2) { emit_int32( LVEBX_OPCODE  | vrt(d) | ra0mem(s1) | rb(s2)); }
lvehx(VectorRegister d,Register s1,Register s2)762 inline void Assembler::lvehx( VectorRegister d, Register s1, Register s2) { emit_int32( LVEHX_OPCODE  | vrt(d) | ra0mem(s1) | rb(s2)); }
lvewx(VectorRegister d,Register s1,Register s2)763 inline void Assembler::lvewx( VectorRegister d, Register s1, Register s2) { emit_int32( LVEWX_OPCODE  | vrt(d) | ra0mem(s1) | rb(s2)); }
lvx(VectorRegister d,Register s1,Register s2)764 inline void Assembler::lvx(   VectorRegister d, Register s1, Register s2) { emit_int32( LVX_OPCODE    | vrt(d) | ra0mem(s1) | rb(s2)); }
lvxl(VectorRegister d,Register s1,Register s2)765 inline void Assembler::lvxl(  VectorRegister d, Register s1, Register s2) { emit_int32( LVXL_OPCODE   | vrt(d) | ra0mem(s1) | rb(s2)); }
stvebx(VectorRegister d,Register s1,Register s2)766 inline void Assembler::stvebx(VectorRegister d, Register s1, Register s2) { emit_int32( STVEBX_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); }
stvehx(VectorRegister d,Register s1,Register s2)767 inline void Assembler::stvehx(VectorRegister d, Register s1, Register s2) { emit_int32( STVEHX_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); }
stvewx(VectorRegister d,Register s1,Register s2)768 inline void Assembler::stvewx(VectorRegister d, Register s1, Register s2) { emit_int32( STVEWX_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); }
stvx(VectorRegister d,Register s1,Register s2)769 inline void Assembler::stvx(  VectorRegister d, Register s1, Register s2) { emit_int32( STVX_OPCODE   | vrt(d) | ra0mem(s1) | rb(s2)); }
stvxl(VectorRegister d,Register s1,Register s2)770 inline void Assembler::stvxl( VectorRegister d, Register s1, Register s2) { emit_int32( STVXL_OPCODE  | vrt(d) | ra0mem(s1) | rb(s2)); }
lvsl(VectorRegister d,Register s1,Register s2)771 inline void Assembler::lvsl(  VectorRegister d, Register s1, Register s2) { emit_int32( LVSL_OPCODE   | vrt(d) | ra0mem(s1) | rb(s2)); }
lvsr(VectorRegister d,Register s1,Register s2)772 inline void Assembler::lvsr(  VectorRegister d, Register s1, Register s2) { emit_int32( LVSR_OPCODE   | vrt(d) | ra0mem(s1) | rb(s2)); }
773 
774 // Vector-Scalar (VSX) instructions.
lxvd2x(VectorSRegister d,Register s1)775 inline void Assembler::lxvd2x(  VectorSRegister d, Register s1)              { emit_int32( LXVD2X_OPCODE  | vsrt(d) | ra(0) | rb(s1)); }
lxvd2x(VectorSRegister d,Register s1,Register s2)776 inline void Assembler::lxvd2x(  VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE  | vsrt(d) | ra0mem(s1) | rb(s2)); }
stxvd2x(VectorSRegister d,Register s1)777 inline void Assembler::stxvd2x( VectorSRegister d, Register s1)              { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra(0) | rb(s1)); }
stxvd2x(VectorSRegister d,Register s1,Register s2)778 inline void Assembler::stxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra0mem(s1) | rb(s2)); }
mtvsrd(VectorSRegister d,Register a)779 inline void Assembler::mtvsrd(  VectorSRegister d, Register a)               { emit_int32( MTVSRD_OPCODE  | vsrt(d)  | ra(a)); }
mtvsrwz(VectorSRegister d,Register a)780 inline void Assembler::mtvsrwz( VectorSRegister d, Register a)               { emit_int32( MTVSRWZ_OPCODE | vsrt(d) | ra(a)); }
xxspltw(VectorSRegister d,VectorSRegister b,int ui2)781 inline void Assembler::xxspltw( VectorSRegister d, VectorSRegister b, int ui2)           { emit_int32( XXSPLTW_OPCODE | vsrt(d) | vsrb(b) | xxsplt_uim(uimm(ui2,2))); }
xxlor(VectorSRegister d,VectorSRegister a,VectorSRegister b)782 inline void Assembler::xxlor(   VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLOR_OPCODE  | vsrt(d) | vsra(a) | vsrb(b)); }
xxlxor(VectorSRegister d,VectorSRegister a,VectorSRegister b)783 inline void Assembler::xxlxor(  VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLXOR_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
xxleqv(VectorSRegister d,VectorSRegister a,VectorSRegister b)784 inline void Assembler::xxleqv(  VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLEQV_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
mtvrd(VectorRegister d,Register a)785 inline void Assembler::mtvrd(    VectorRegister d, Register a)               { emit_int32( MTVSRD_OPCODE  | vsrt(d->to_vsr()) | ra(a)); }
mfvrd(Register a,VectorRegister d)786 inline void Assembler::mfvrd(   Register        a, VectorRegister d)         { emit_int32( MFVSRD_OPCODE  | vsrt(d->to_vsr()) | ra(a)); }
mtvrwz(VectorRegister d,Register a)787 inline void Assembler::mtvrwz(  VectorRegister  d, Register a)               { emit_int32( MTVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
mfvrwz(Register a,VectorRegister d)788 inline void Assembler::mfvrwz(  Register        a, VectorRegister d)         { emit_int32( MFVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
xxpermdi(VectorSRegister d,VectorSRegister a,VectorSRegister b,int dm)789 inline void Assembler::xxpermdi(VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm) { emit_int32( XXPERMDI_OPCODE | vsrt(d) | vsra(a) | vsrb(b) | vsdm(dm)); }
xxmrghw(VectorSRegister d,VectorSRegister a,VectorSRegister b)790 inline void Assembler::xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
xxmrglw(VectorSRegister d,VectorSRegister a,VectorSRegister b)791 inline void Assembler::xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
792 
793 // VSX Extended Mnemonics
xxspltd(VectorSRegister d,VectorSRegister a,int x)794 inline void Assembler::xxspltd( VectorSRegister d, VectorSRegister a, int x)             { xxpermdi(d, a, a, x ? 3 : 0); }
xxmrghd(VectorSRegister d,VectorSRegister a,VectorSRegister b)795 inline void Assembler::xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b) { xxpermdi(d, a, b, 0); }
xxmrgld(VectorSRegister d,VectorSRegister a,VectorSRegister b)796 inline void Assembler::xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b) { xxpermdi(d, a, b, 3); }
xxswapd(VectorSRegister d,VectorSRegister a)797 inline void Assembler::xxswapd( VectorSRegister d, VectorSRegister a)                    { xxpermdi(d, a, a, 2); }
798 
799 // Vector-Scalar (VSX) instructions.
mtfprd(FloatRegister d,Register a)800 inline void Assembler::mtfprd(  FloatRegister   d, Register a)      { emit_int32( MTVSRD_OPCODE  | frt(d)  | ra(a)); }
mtfprwa(FloatRegister d,Register a)801 inline void Assembler::mtfprwa( FloatRegister   d, Register a)      { emit_int32( MTVSRWA_OPCODE | frt(d)  | ra(a)); }
mffprd(Register a,FloatRegister d)802 inline void Assembler::mffprd(  Register        a, FloatRegister d) { emit_int32( MFVSRD_OPCODE  | frt(d)  | ra(a)); }
803 
vpkpx(VectorRegister d,VectorRegister a,VectorRegister b)804 inline void Assembler::vpkpx(   VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKPX_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vpkshss(VectorRegister d,VectorRegister a,VectorRegister b)805 inline void Assembler::vpkshss( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKSHSS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpkswss(VectorRegister d,VectorRegister a,VectorRegister b)806 inline void Assembler::vpkswss( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKSWSS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpkshus(VectorRegister d,VectorRegister a,VectorRegister b)807 inline void Assembler::vpkshus( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKSHUS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpkswus(VectorRegister d,VectorRegister a,VectorRegister b)808 inline void Assembler::vpkswus( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKSWUS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpkuhum(VectorRegister d,VectorRegister a,VectorRegister b)809 inline void Assembler::vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKUHUM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpkuwum(VectorRegister d,VectorRegister a,VectorRegister b)810 inline void Assembler::vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKUWUM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpkuhus(VectorRegister d,VectorRegister a,VectorRegister b)811 inline void Assembler::vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKUHUS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpkuwus(VectorRegister d,VectorRegister a,VectorRegister b)812 inline void Assembler::vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKUWUS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vupkhpx(VectorRegister d,VectorRegister b)813 inline void Assembler::vupkhpx( VectorRegister d, VectorRegister b)                   { emit_int32( VUPKHPX_OPCODE | vrt(d) | vrb(b)); }
vupkhsb(VectorRegister d,VectorRegister b)814 inline void Assembler::vupkhsb( VectorRegister d, VectorRegister b)                   { emit_int32( VUPKHSB_OPCODE | vrt(d) | vrb(b)); }
vupkhsh(VectorRegister d,VectorRegister b)815 inline void Assembler::vupkhsh( VectorRegister d, VectorRegister b)                   { emit_int32( VUPKHSH_OPCODE | vrt(d) | vrb(b)); }
vupklpx(VectorRegister d,VectorRegister b)816 inline void Assembler::vupklpx( VectorRegister d, VectorRegister b)                   { emit_int32( VUPKLPX_OPCODE | vrt(d) | vrb(b)); }
vupklsb(VectorRegister d,VectorRegister b)817 inline void Assembler::vupklsb( VectorRegister d, VectorRegister b)                   { emit_int32( VUPKLSB_OPCODE | vrt(d) | vrb(b)); }
vupklsh(VectorRegister d,VectorRegister b)818 inline void Assembler::vupklsh( VectorRegister d, VectorRegister b)                   { emit_int32( VUPKLSH_OPCODE | vrt(d) | vrb(b)); }
vmrghb(VectorRegister d,VectorRegister a,VectorRegister b)819 inline void Assembler::vmrghb(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMRGHB_OPCODE  | vrt(d) | vra(a) | vrb(b)); }
vmrghw(VectorRegister d,VectorRegister a,VectorRegister b)820 inline void Assembler::vmrghw(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMRGHW_OPCODE  | vrt(d) | vra(a) | vrb(b)); }
vmrghh(VectorRegister d,VectorRegister a,VectorRegister b)821 inline void Assembler::vmrghh(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMRGHH_OPCODE  | vrt(d) | vra(a) | vrb(b)); }
vmrglb(VectorRegister d,VectorRegister a,VectorRegister b)822 inline void Assembler::vmrglb(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMRGLB_OPCODE  | vrt(d) | vra(a) | vrb(b)); }
vmrglw(VectorRegister d,VectorRegister a,VectorRegister b)823 inline void Assembler::vmrglw(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMRGLW_OPCODE  | vrt(d) | vra(a) | vrb(b)); }
vmrglh(VectorRegister d,VectorRegister a,VectorRegister b)824 inline void Assembler::vmrglh(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMRGLH_OPCODE  | vrt(d) | vra(a) | vrb(b)); }
vsplt(VectorRegister d,int ui4,VectorRegister b)825 inline void Assembler::vsplt(   VectorRegister d, int ui4,          VectorRegister b) { emit_int32( VSPLT_OPCODE   | vrt(d) | vsplt_uim(uimm(ui4,4)) | vrb(b)); }
vsplth(VectorRegister d,int ui3,VectorRegister b)826 inline void Assembler::vsplth(  VectorRegister d, int ui3,          VectorRegister b) { emit_int32( VSPLTH_OPCODE  | vrt(d) | vsplt_uim(uimm(ui3,3)) | vrb(b)); }
vspltw(VectorRegister d,int ui2,VectorRegister b)827 inline void Assembler::vspltw(  VectorRegister d, int ui2,          VectorRegister b) { emit_int32( VSPLTW_OPCODE  | vrt(d) | vsplt_uim(uimm(ui2,2)) | vrb(b)); }
vspltisb(VectorRegister d,int si5)828 inline void Assembler::vspltisb(VectorRegister d, int si5)                            { emit_int32( VSPLTISB_OPCODE| vrt(d) | vsplti_sim(simm(si5,5))); }
vspltish(VectorRegister d,int si5)829 inline void Assembler::vspltish(VectorRegister d, int si5)                            { emit_int32( VSPLTISH_OPCODE| vrt(d) | vsplti_sim(simm(si5,5))); }
vspltisw(VectorRegister d,int si5)830 inline void Assembler::vspltisw(VectorRegister d, int si5)                            { emit_int32( VSPLTISW_OPCODE| vrt(d) | vsplti_sim(simm(si5,5))); }
vperm(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)831 inline void Assembler::vperm(   VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VPERM_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
vsel(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)832 inline void Assembler::vsel(    VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VSEL_OPCODE  | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
vsl(VectorRegister d,VectorRegister a,VectorRegister b)833 inline void Assembler::vsl(     VectorRegister d, VectorRegister a, VectorRegister b)                  { emit_int32( VSL_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vsldoi(VectorRegister d,VectorRegister a,VectorRegister b,int ui4)834 inline void Assembler::vsldoi(  VectorRegister d, VectorRegister a, VectorRegister b, int ui4)         { emit_int32( VSLDOI_OPCODE| vrt(d) | vra(a) | vrb(b) | vsldoi_shb(uimm(ui4,4))); }
vslo(VectorRegister d,VectorRegister a,VectorRegister b)835 inline void Assembler::vslo(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSLO_OPCODE    | vrt(d) | vra(a) | vrb(b)); }
vsr(VectorRegister d,VectorRegister a,VectorRegister b)836 inline void Assembler::vsr(     VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSR_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vsro(VectorRegister d,VectorRegister a,VectorRegister b)837 inline void Assembler::vsro(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSRO_OPCODE    | vrt(d) | vra(a) | vrb(b)); }
vaddcuw(VectorRegister d,VectorRegister a,VectorRegister b)838 inline void Assembler::vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDCUW_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vaddshs(VectorRegister d,VectorRegister a,VectorRegister b)839 inline void Assembler::vaddshs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDSHS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vaddsbs(VectorRegister d,VectorRegister a,VectorRegister b)840 inline void Assembler::vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDSBS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vaddsws(VectorRegister d,VectorRegister a,VectorRegister b)841 inline void Assembler::vaddsws( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDSWS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vaddubm(VectorRegister d,VectorRegister a,VectorRegister b)842 inline void Assembler::vaddubm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUBM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vadduwm(VectorRegister d,VectorRegister a,VectorRegister b)843 inline void Assembler::vadduwm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUWM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vadduhm(VectorRegister d,VectorRegister a,VectorRegister b)844 inline void Assembler::vadduhm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUHM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vaddudm(VectorRegister d,VectorRegister a,VectorRegister b)845 inline void Assembler::vaddudm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUDM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vaddubs(VectorRegister d,VectorRegister a,VectorRegister b)846 inline void Assembler::vaddubs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUBS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vadduws(VectorRegister d,VectorRegister a,VectorRegister b)847 inline void Assembler::vadduws( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUWS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vadduhs(VectorRegister d,VectorRegister a,VectorRegister b)848 inline void Assembler::vadduhs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUHS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsubcuw(VectorRegister d,VectorRegister a,VectorRegister b)849 inline void Assembler::vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBCUW_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsubshs(VectorRegister d,VectorRegister a,VectorRegister b)850 inline void Assembler::vsubshs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBSHS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsubsbs(VectorRegister d,VectorRegister a,VectorRegister b)851 inline void Assembler::vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBSBS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsubsws(VectorRegister d,VectorRegister a,VectorRegister b)852 inline void Assembler::vsubsws( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBSWS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsububm(VectorRegister d,VectorRegister a,VectorRegister b)853 inline void Assembler::vsububm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBUBM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsubuwm(VectorRegister d,VectorRegister a,VectorRegister b)854 inline void Assembler::vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBUWM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsubuhm(VectorRegister d,VectorRegister a,VectorRegister b)855 inline void Assembler::vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBUHM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsububs(VectorRegister d,VectorRegister a,VectorRegister b)856 inline void Assembler::vsububs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBUBS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsubuws(VectorRegister d,VectorRegister a,VectorRegister b)857 inline void Assembler::vsubuws( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBUWS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsubuhs(VectorRegister d,VectorRegister a,VectorRegister b)858 inline void Assembler::vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUBUHS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vmulesb(VectorRegister d,VectorRegister a,VectorRegister b)859 inline void Assembler::vmulesb( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMULESB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vmuleub(VectorRegister d,VectorRegister a,VectorRegister b)860 inline void Assembler::vmuleub( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMULEUB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vmulesh(VectorRegister d,VectorRegister a,VectorRegister b)861 inline void Assembler::vmulesh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMULESH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vmuleuh(VectorRegister d,VectorRegister a,VectorRegister b)862 inline void Assembler::vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMULEUH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vmulosb(VectorRegister d,VectorRegister a,VectorRegister b)863 inline void Assembler::vmulosb( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMULOSB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vmuloub(VectorRegister d,VectorRegister a,VectorRegister b)864 inline void Assembler::vmuloub( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMULOUB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vmulosh(VectorRegister d,VectorRegister a,VectorRegister b)865 inline void Assembler::vmulosh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMULOSH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vmulouh(VectorRegister d,VectorRegister a,VectorRegister b)866 inline void Assembler::vmulouh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMULOUH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vmhaddshs(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)867 inline void Assembler::vmhaddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VMHADDSHS_OPCODE | vrt(d) | vra(a) | vrb(b)| vrc(c)); }
vmhraddshs(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)868 inline void Assembler::vmhraddshs(VectorRegister d,VectorRegister a,VectorRegister b, VectorRegister c) { emit_int32( VMHRADDSHS_OPCODE| vrt(d) | vra(a) | vrb(b)| vrc(c)); }
vmladduhm(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)869 inline void Assembler::vmladduhm(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VMLADDUHM_OPCODE | vrt(d) | vra(a) | vrb(b)| vrc(c)); }
vmsubuhm(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)870 inline void Assembler::vmsubuhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VMSUBUHM_OPCODE  | vrt(d) | vra(a) | vrb(b)| vrc(c)); }
vmsummbm(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)871 inline void Assembler::vmsummbm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VMSUMMBM_OPCODE  | vrt(d) | vra(a) | vrb(b)| vrc(c)); }
vmsumshm(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)872 inline void Assembler::vmsumshm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VMSUMSHM_OPCODE  | vrt(d) | vra(a) | vrb(b)| vrc(c)); }
vmsumshs(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)873 inline void Assembler::vmsumshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VMSUMSHS_OPCODE  | vrt(d) | vra(a) | vrb(b)| vrc(c)); }
vmsumuhm(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)874 inline void Assembler::vmsumuhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VMSUMUHM_OPCODE  | vrt(d) | vra(a) | vrb(b)| vrc(c)); }
vmsumuhs(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)875 inline void Assembler::vmsumuhs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VMSUMUHS_OPCODE  | vrt(d) | vra(a) | vrb(b)| vrc(c)); }
vsumsws(VectorRegister d,VectorRegister a,VectorRegister b)876 inline void Assembler::vsumsws( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUMSWS_OPCODE  | vrt(d) | vra(a) | vrb(b)); }
vsum2sws(VectorRegister d,VectorRegister a,VectorRegister b)877 inline void Assembler::vsum2sws(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUM2SWS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsum4sbs(VectorRegister d,VectorRegister a,VectorRegister b)878 inline void Assembler::vsum4sbs(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUM4SBS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsum4ubs(VectorRegister d,VectorRegister a,VectorRegister b)879 inline void Assembler::vsum4ubs(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUM4UBS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsum4shs(VectorRegister d,VectorRegister a,VectorRegister b)880 inline void Assembler::vsum4shs(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSUM4SHS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vavgsb(VectorRegister d,VectorRegister a,VectorRegister b)881 inline void Assembler::vavgsb(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VAVGSB_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vavgsw(VectorRegister d,VectorRegister a,VectorRegister b)882 inline void Assembler::vavgsw(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VAVGSW_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vavgsh(VectorRegister d,VectorRegister a,VectorRegister b)883 inline void Assembler::vavgsh(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VAVGSH_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vavgub(VectorRegister d,VectorRegister a,VectorRegister b)884 inline void Assembler::vavgub(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VAVGUB_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vavguw(VectorRegister d,VectorRegister a,VectorRegister b)885 inline void Assembler::vavguw(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VAVGUW_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vavguh(VectorRegister d,VectorRegister a,VectorRegister b)886 inline void Assembler::vavguh(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VAVGUH_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vmaxsb(VectorRegister d,VectorRegister a,VectorRegister b)887 inline void Assembler::vmaxsb(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXSB_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vmaxsw(VectorRegister d,VectorRegister a,VectorRegister b)888 inline void Assembler::vmaxsw(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXSW_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vmaxsh(VectorRegister d,VectorRegister a,VectorRegister b)889 inline void Assembler::vmaxsh(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXSH_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vmaxub(VectorRegister d,VectorRegister a,VectorRegister b)890 inline void Assembler::vmaxub(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXUB_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vmaxuw(VectorRegister d,VectorRegister a,VectorRegister b)891 inline void Assembler::vmaxuw(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXUW_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vmaxuh(VectorRegister d,VectorRegister a,VectorRegister b)892 inline void Assembler::vmaxuh(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXUH_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vminsb(VectorRegister d,VectorRegister a,VectorRegister b)893 inline void Assembler::vminsb(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINSB_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vminsw(VectorRegister d,VectorRegister a,VectorRegister b)894 inline void Assembler::vminsw(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINSW_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vminsh(VectorRegister d,VectorRegister a,VectorRegister b)895 inline void Assembler::vminsh(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINSH_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vminub(VectorRegister d,VectorRegister a,VectorRegister b)896 inline void Assembler::vminub(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINUB_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vminuw(VectorRegister d,VectorRegister a,VectorRegister b)897 inline void Assembler::vminuw(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINUW_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vminuh(VectorRegister d,VectorRegister a,VectorRegister b)898 inline void Assembler::vminuh(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINUH_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
vcmpequb(VectorRegister d,VectorRegister a,VectorRegister b)899 inline void Assembler::vcmpequb(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPEQUB_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
vcmpequh(VectorRegister d,VectorRegister a,VectorRegister b)900 inline void Assembler::vcmpequh(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPEQUH_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
vcmpequw(VectorRegister d,VectorRegister a,VectorRegister b)901 inline void Assembler::vcmpequw(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPEQUW_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
vcmpgtsh(VectorRegister d,VectorRegister a,VectorRegister b)902 inline void Assembler::vcmpgtsh(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPGTSH_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
vcmpgtsb(VectorRegister d,VectorRegister a,VectorRegister b)903 inline void Assembler::vcmpgtsb(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPGTSB_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
vcmpgtsw(VectorRegister d,VectorRegister a,VectorRegister b)904 inline void Assembler::vcmpgtsw(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPGTSW_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
vcmpgtub(VectorRegister d,VectorRegister a,VectorRegister b)905 inline void Assembler::vcmpgtub(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUB_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
vcmpgtuh(VectorRegister d,VectorRegister a,VectorRegister b)906 inline void Assembler::vcmpgtuh(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUH_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
vcmpgtuw(VectorRegister d,VectorRegister a,VectorRegister b)907 inline void Assembler::vcmpgtuw(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUW_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
vcmpequb_(VectorRegister d,VectorRegister a,VectorRegister b)908 inline void Assembler::vcmpequb_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPEQUB_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
vcmpequh_(VectorRegister d,VectorRegister a,VectorRegister b)909 inline void Assembler::vcmpequh_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPEQUH_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
vcmpequw_(VectorRegister d,VectorRegister a,VectorRegister b)910 inline void Assembler::vcmpequw_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPEQUW_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
vcmpgtsh_(VectorRegister d,VectorRegister a,VectorRegister b)911 inline void Assembler::vcmpgtsh_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTSH_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
vcmpgtsb_(VectorRegister d,VectorRegister a,VectorRegister b)912 inline void Assembler::vcmpgtsb_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTSB_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
vcmpgtsw_(VectorRegister d,VectorRegister a,VectorRegister b)913 inline void Assembler::vcmpgtsw_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTSW_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
vcmpgtub_(VectorRegister d,VectorRegister a,VectorRegister b)914 inline void Assembler::vcmpgtub_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUB_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
vcmpgtuh_(VectorRegister d,VectorRegister a,VectorRegister b)915 inline void Assembler::vcmpgtuh_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUH_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
vcmpgtuw_(VectorRegister d,VectorRegister a,VectorRegister b)916 inline void Assembler::vcmpgtuw_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUW_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
vand(VectorRegister d,VectorRegister a,VectorRegister b)917 inline void Assembler::vand(    VectorRegister d, VectorRegister a, VectorRegister b) { guarantee(VM_Version::has_vand(), "opcode not supported on this hardware");
918                                                                                         emit_int32( VAND_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vandc(VectorRegister d,VectorRegister a,VectorRegister b)919 inline void Assembler::vandc(   VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VANDC_OPCODE    | vrt(d) | vra(a) | vrb(b)); }
vnor(VectorRegister d,VectorRegister a,VectorRegister b)920 inline void Assembler::vnor(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNOR_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vor(VectorRegister d,VectorRegister a,VectorRegister b)921 inline void Assembler::vor(     VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VOR_OPCODE      | vrt(d) | vra(a) | vrb(b)); }
vmr(VectorRegister d,VectorRegister a)922 inline void Assembler::vmr(     VectorRegister d, VectorRegister a)                   { emit_int32( VOR_OPCODE      | vrt(d) | vra(a) | vrb(a)); }
vxor(VectorRegister d,VectorRegister a,VectorRegister b)923 inline void Assembler::vxor(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VXOR_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vrld(VectorRegister d,VectorRegister a,VectorRegister b)924 inline void Assembler::vrld(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VRLD_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vrlb(VectorRegister d,VectorRegister a,VectorRegister b)925 inline void Assembler::vrlb(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VRLB_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vrlw(VectorRegister d,VectorRegister a,VectorRegister b)926 inline void Assembler::vrlw(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VRLW_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vrlh(VectorRegister d,VectorRegister a,VectorRegister b)927 inline void Assembler::vrlh(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VRLH_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vslb(VectorRegister d,VectorRegister a,VectorRegister b)928 inline void Assembler::vslb(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSLB_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vskw(VectorRegister d,VectorRegister a,VectorRegister b)929 inline void Assembler::vskw(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSKW_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vslh(VectorRegister d,VectorRegister a,VectorRegister b)930 inline void Assembler::vslh(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSLH_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vsrb(VectorRegister d,VectorRegister a,VectorRegister b)931 inline void Assembler::vsrb(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSRB_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vsrw(VectorRegister d,VectorRegister a,VectorRegister b)932 inline void Assembler::vsrw(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSRW_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vsrh(VectorRegister d,VectorRegister a,VectorRegister b)933 inline void Assembler::vsrh(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSRH_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vsrab(VectorRegister d,VectorRegister a,VectorRegister b)934 inline void Assembler::vsrab(   VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSRAB_OPCODE    | vrt(d) | vra(a) | vrb(b)); }
vsraw(VectorRegister d,VectorRegister a,VectorRegister b)935 inline void Assembler::vsraw(   VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSRAW_OPCODE    | vrt(d) | vra(a) | vrb(b)); }
vsrah(VectorRegister d,VectorRegister a,VectorRegister b)936 inline void Assembler::vsrah(   VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSRAH_OPCODE    | vrt(d) | vra(a) | vrb(b)); }
mtvscr(VectorRegister b)937 inline void Assembler::mtvscr(  VectorRegister b)                                     { emit_int32( MTVSCR_OPCODE   | vrb(b)); }
mfvscr(VectorRegister d)938 inline void Assembler::mfvscr(  VectorRegister d)                                     { emit_int32( MFVSCR_OPCODE   | vrt(d)); }
939 
940 // AES (introduced with Power 8)
vcipher(VectorRegister d,VectorRegister a,VectorRegister b)941 inline void Assembler::vcipher(     VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCIPHER_OPCODE      | vrt(d) | vra(a) | vrb(b)); }
vcipherlast(VectorRegister d,VectorRegister a,VectorRegister b)942 inline void Assembler::vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCIPHERLAST_OPCODE  | vrt(d) | vra(a) | vrb(b)); }
vncipher(VectorRegister d,VectorRegister a,VectorRegister b)943 inline void Assembler::vncipher(    VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNCIPHER_OPCODE     | vrt(d) | vra(a) | vrb(b)); }
vncipherlast(VectorRegister d,VectorRegister a,VectorRegister b)944 inline void Assembler::vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNCIPHERLAST_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vsbox(VectorRegister d,VectorRegister a)945 inline void Assembler::vsbox(       VectorRegister d, VectorRegister a)                   { emit_int32( VSBOX_OPCODE        | vrt(d) | vra(a)         ); }
946 
947 // SHA (introduced with Power 8)
vshasigmad(VectorRegister d,VectorRegister a,bool st,int six)948 inline void Assembler::vshasigmad(VectorRegister d, VectorRegister a, bool st, int six) { emit_int32( VSHASIGMAD_OPCODE | vrt(d) | vra(a) | vst(st) | vsix(six)); }
vshasigmaw(VectorRegister d,VectorRegister a,bool st,int six)949 inline void Assembler::vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six) { emit_int32( VSHASIGMAW_OPCODE | vrt(d) | vra(a) | vst(st) | vsix(six)); }
950 
951 // Vector Binary Polynomial Multiplication (introduced with Power 8)
vpmsumb(VectorRegister d,VectorRegister a,VectorRegister b)952 inline void Assembler::vpmsumb(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpmsumd(VectorRegister d,VectorRegister a,VectorRegister b)953 inline void Assembler::vpmsumd(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMD_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpmsumh(VectorRegister d,VectorRegister a,VectorRegister b)954 inline void Assembler::vpmsumh(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
vpmsumw(VectorRegister d,VectorRegister a,VectorRegister b)955 inline void Assembler::vpmsumw(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMW_OPCODE | vrt(d) | vra(a) | vrb(b)); }
956 
957 // Vector Permute and Xor (introduced with Power 8)
vpermxor(VectorRegister d,VectorRegister a,VectorRegister b,VectorRegister c)958 inline void Assembler::vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VPERMXOR_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
959 
960 // Transactional Memory instructions (introduced with Power 8)
tbegin_()961 inline void Assembler::tbegin_()                                { emit_int32( TBEGIN_OPCODE | rc(1)); }
tbeginrot_()962 inline void Assembler::tbeginrot_()                             { emit_int32( TBEGIN_OPCODE | /*R=1*/ 1u << (31-10) | rc(1)); }
tend_()963 inline void Assembler::tend_()                                  { emit_int32( TEND_OPCODE | rc(1)); }
tendall_()964 inline void Assembler::tendall_()                               { emit_int32( TEND_OPCODE | /*A=1*/ 1u << (31-6) | rc(1)); }
tabort_()965 inline void Assembler::tabort_()                                { emit_int32( TABORT_OPCODE | rc(1)); }
tabort_(Register a)966 inline void Assembler::tabort_(Register a)                      { assert(a != R0, "r0 not allowed"); emit_int32( TABORT_OPCODE | ra(a) | rc(1)); }
tabortwc_(int t,Register a,Register b)967 inline void Assembler::tabortwc_(int t, Register a, Register b) { emit_int32( TABORTWC_OPCODE | to(t) | ra(a) | rb(b) | rc(1)); }
tabortwci_(int t,Register a,int si)968 inline void Assembler::tabortwci_(int t, Register a, int si)    { emit_int32( TABORTWCI_OPCODE | to(t) | ra(a) | sh1620(si) | rc(1)); }
tabortdc_(int t,Register a,Register b)969 inline void Assembler::tabortdc_(int t, Register a, Register b) { emit_int32( TABORTDC_OPCODE | to(t) | ra(a) | rb(b) | rc(1)); }
tabortdci_(int t,Register a,int si)970 inline void Assembler::tabortdci_(int t, Register a, int si)    { emit_int32( TABORTDCI_OPCODE | to(t) | ra(a) | sh1620(si) | rc(1)); }
tsuspend_()971 inline void Assembler::tsuspend_()                              { emit_int32( TSR_OPCODE | rc(1)); }
tresume_()972 inline void Assembler::tresume_()                               { emit_int32( TSR_OPCODE | /*L=1*/ 1u << (31-10) | rc(1)); }
tcheck(int f)973 inline void Assembler::tcheck(int f)                            { emit_int32( TCHECK_OPCODE | bf(f)); }
974 
975 // Deliver A Random Number (introduced with POWER9)
darn(Register d,int l)976 inline void Assembler::darn(Register d, int l /* =1 */) { emit_int32( DARN_OPCODE | rt(d) | l14(l)); }
977 
978 // ra0 version
lwzx(Register d,Register s2)979 inline void Assembler::lwzx( Register d, Register s2) { emit_int32( LWZX_OPCODE | rt(d) | rb(s2));}
lwz(Register d,int si16)980 inline void Assembler::lwz(  Register d, int si16   ) { emit_int32( LWZ_OPCODE  | rt(d) | d1(si16));}
lwax(Register d,Register s2)981 inline void Assembler::lwax( Register d, Register s2) { emit_int32( LWAX_OPCODE | rt(d) | rb(s2));}
lwa(Register d,int si16)982 inline void Assembler::lwa(  Register d, int si16   ) { emit_int32( LWA_OPCODE  | rt(d) | ds(si16));}
lwbrx(Register d,Register s2)983 inline void Assembler::lwbrx(Register d, Register s2) { emit_int32( LWBRX_OPCODE| rt(d) | rb(s2));}
lhzx(Register d,Register s2)984 inline void Assembler::lhzx( Register d, Register s2) { emit_int32( LHZX_OPCODE | rt(d) | rb(s2));}
lhz(Register d,int si16)985 inline void Assembler::lhz(  Register d, int si16   ) { emit_int32( LHZ_OPCODE  | rt(d) | d1(si16));}
lhax(Register d,Register s2)986 inline void Assembler::lhax( Register d, Register s2) { emit_int32( LHAX_OPCODE | rt(d) | rb(s2));}
lha(Register d,int si16)987 inline void Assembler::lha(  Register d, int si16   ) { emit_int32( LHA_OPCODE  | rt(d) | d1(si16));}
lhbrx(Register d,Register s2)988 inline void Assembler::lhbrx(Register d, Register s2) { emit_int32( LHBRX_OPCODE| rt(d) | rb(s2));}
lbzx(Register d,Register s2)989 inline void Assembler::lbzx( Register d, Register s2) { emit_int32( LBZX_OPCODE | rt(d) | rb(s2));}
lbz(Register d,int si16)990 inline void Assembler::lbz(  Register d, int si16   ) { emit_int32( LBZ_OPCODE  | rt(d) | d1(si16));}
ld(Register d,int si16)991 inline void Assembler::ld(   Register d, int si16   ) { emit_int32( LD_OPCODE   | rt(d) | ds(si16));}
ldx(Register d,Register s2)992 inline void Assembler::ldx(  Register d, Register s2) { emit_int32( LDX_OPCODE  | rt(d) | rb(s2));}
ldbrx(Register d,Register s2)993 inline void Assembler::ldbrx(Register d, Register s2) { emit_int32( LDBRX_OPCODE| rt(d) | rb(s2));}
stwx(Register d,Register s2)994 inline void Assembler::stwx( Register d, Register s2) { emit_int32( STWX_OPCODE | rs(d) | rb(s2));}
stw(Register d,int si16)995 inline void Assembler::stw(  Register d, int si16   ) { emit_int32( STW_OPCODE  | rs(d) | d1(si16));}
stwbrx(Register d,Register s2)996 inline void Assembler::stwbrx(Register d, Register s2){ emit_int32(STWBRX_OPCODE| rs(d) | rb(s2));}
sthx(Register d,Register s2)997 inline void Assembler::sthx( Register d, Register s2) { emit_int32( STHX_OPCODE | rs(d) | rb(s2));}
sth(Register d,int si16)998 inline void Assembler::sth(  Register d, int si16   ) { emit_int32( STH_OPCODE  | rs(d) | d1(si16));}
sthbrx(Register d,Register s2)999 inline void Assembler::sthbrx(Register d, Register s2){ emit_int32(STHBRX_OPCODE| rs(d) | rb(s2));}
stbx(Register d,Register s2)1000 inline void Assembler::stbx( Register d, Register s2) { emit_int32( STBX_OPCODE | rs(d) | rb(s2));}
stb(Register d,int si16)1001 inline void Assembler::stb(  Register d, int si16   ) { emit_int32( STB_OPCODE  | rs(d) | d1(si16));}
std(Register d,int si16)1002 inline void Assembler::std(  Register d, int si16   ) { emit_int32( STD_OPCODE  | rs(d) | ds(si16));}
stdx(Register d,Register s2)1003 inline void Assembler::stdx( Register d, Register s2) { emit_int32( STDX_OPCODE | rs(d) | rb(s2));}
stdbrx(Register d,Register s2)1004 inline void Assembler::stdbrx(Register d, Register s2){ emit_int32(STDBRX_OPCODE| rs(d) | rb(s2));}
1005 
1006 // ra0 version
icbi(Register s2)1007 inline void Assembler::icbi(    Register s2)          { emit_int32( ICBI_OPCODE   | rb(s2)           ); }
1008 //inline void Assembler::dcba(  Register s2)          { emit_int32( DCBA_OPCODE   | rb(s2)           ); }
dcbz(Register s2)1009 inline void Assembler::dcbz(    Register s2)          { emit_int32( DCBZ_OPCODE   | rb(s2)           ); }
dcbst(Register s2)1010 inline void Assembler::dcbst(   Register s2)          { emit_int32( DCBST_OPCODE  | rb(s2)           ); }
dcbf(Register s2)1011 inline void Assembler::dcbf(    Register s2)          { emit_int32( DCBF_OPCODE   | rb(s2)           ); }
dcbt(Register s2)1012 inline void Assembler::dcbt(    Register s2)          { emit_int32( DCBT_OPCODE   | rb(s2)           ); }
dcbtct(Register s2,int ct)1013 inline void Assembler::dcbtct(  Register s2, int ct)  { emit_int32( DCBT_OPCODE   | rb(s2) | thct(ct)); }
dcbtds(Register s2,int ds)1014 inline void Assembler::dcbtds(  Register s2, int ds)  { emit_int32( DCBT_OPCODE   | rb(s2) | thds(ds)); }
dcbtst(Register s2)1015 inline void Assembler::dcbtst(  Register s2)          { emit_int32( DCBTST_OPCODE | rb(s2)           ); }
dcbtstct(Register s2,int ct)1016 inline void Assembler::dcbtstct(Register s2, int ct)  { emit_int32( DCBTST_OPCODE | rb(s2) | thct(ct)); }
1017 
1018 // ra0 version
lbarx_unchecked(Register d,Register b,int eh1)1019 inline void Assembler::lbarx_unchecked(Register d, Register b, int eh1)          { emit_int32( LBARX_OPCODE | rt(d) | rb(b) | eh(eh1)); }
lharx_unchecked(Register d,Register b,int eh1)1020 inline void Assembler::lharx_unchecked(Register d, Register b, int eh1)          { emit_int32( LHARX_OPCODE | rt(d) | rb(b) | eh(eh1)); }
lwarx_unchecked(Register d,Register b,int eh1)1021 inline void Assembler::lwarx_unchecked(Register d, Register b, int eh1)          { emit_int32( LWARX_OPCODE | rt(d) | rb(b) | eh(eh1)); }
ldarx_unchecked(Register d,Register b,int eh1)1022 inline void Assembler::ldarx_unchecked(Register d, Register b, int eh1)          { emit_int32( LDARX_OPCODE | rt(d) | rb(b) | eh(eh1)); }
lqarx_unchecked(Register d,Register b,int eh1)1023 inline void Assembler::lqarx_unchecked(Register d, Register b, int eh1)          { emit_int32( LQARX_OPCODE | rt(d) | rb(b) | eh(eh1)); }
lbarx(Register d,Register b,bool hint_exclusive_access)1024 inline void Assembler::lbarx( Register d, Register b, bool hint_exclusive_access){ lbarx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
lharx(Register d,Register b,bool hint_exclusive_access)1025 inline void Assembler::lharx( Register d, Register b, bool hint_exclusive_access){ lharx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
lwarx(Register d,Register b,bool hint_exclusive_access)1026 inline void Assembler::lwarx( Register d, Register b, bool hint_exclusive_access){ lwarx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
ldarx(Register d,Register b,bool hint_exclusive_access)1027 inline void Assembler::ldarx( Register d, Register b, bool hint_exclusive_access){ ldarx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
lqarx(Register d,Register b,bool hint_exclusive_access)1028 inline void Assembler::lqarx( Register d, Register b, bool hint_exclusive_access){ lqarx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
stbcx_(Register s,Register b)1029 inline void Assembler::stbcx_(Register s, Register b)                            { emit_int32( STBCX_OPCODE | rs(s) | rb(b) | rc(1)); }
sthcx_(Register s,Register b)1030 inline void Assembler::sthcx_(Register s, Register b)                            { emit_int32( STHCX_OPCODE | rs(s) | rb(b) | rc(1)); }
stwcx_(Register s,Register b)1031 inline void Assembler::stwcx_(Register s, Register b)                            { emit_int32( STWCX_OPCODE | rs(s) | rb(b) | rc(1)); }
stdcx_(Register s,Register b)1032 inline void Assembler::stdcx_(Register s, Register b)                            { emit_int32( STDCX_OPCODE | rs(s) | rb(b) | rc(1)); }
stqcx_(Register s,Register b)1033 inline void Assembler::stqcx_(Register s, Register b)                            { emit_int32( STQCX_OPCODE | rs(s) | rb(b) | rc(1)); }
1034 
1035 // ra0 version
lfs(FloatRegister d,int si16)1036 inline void Assembler::lfs( FloatRegister d, int si16)   { emit_int32( LFS_OPCODE  | frt(d) | simm(si16,16)); }
lfsx(FloatRegister d,Register b)1037 inline void Assembler::lfsx(FloatRegister d, Register b) { emit_int32( LFSX_OPCODE | frt(d) | rb(b)); }
lfd(FloatRegister d,int si16)1038 inline void Assembler::lfd( FloatRegister d, int si16)   { emit_int32( LFD_OPCODE  | frt(d) | simm(si16,16)); }
lfdx(FloatRegister d,Register b)1039 inline void Assembler::lfdx(FloatRegister d, Register b) { emit_int32( LFDX_OPCODE | frt(d) | rb(b)); }
1040 
1041 // ra0 version
stfs(FloatRegister s,int si16)1042 inline void Assembler::stfs( FloatRegister s, int si16)   { emit_int32( STFS_OPCODE  | frs(s) | simm(si16, 16)); }
stfsx(FloatRegister s,Register b)1043 inline void Assembler::stfsx(FloatRegister s, Register b) { emit_int32( STFSX_OPCODE | frs(s) | rb(b)); }
stfd(FloatRegister s,int si16)1044 inline void Assembler::stfd( FloatRegister s, int si16)   { emit_int32( STFD_OPCODE  | frs(s) | simm(si16, 16)); }
stfdx(FloatRegister s,Register b)1045 inline void Assembler::stfdx(FloatRegister s, Register b) { emit_int32( STFDX_OPCODE | frs(s) | rb(b)); }
1046 
1047 // ra0 version
lvebx(VectorRegister d,Register s2)1048 inline void Assembler::lvebx( VectorRegister d, Register s2) { emit_int32( LVEBX_OPCODE  | vrt(d) | rb(s2)); }
lvehx(VectorRegister d,Register s2)1049 inline void Assembler::lvehx( VectorRegister d, Register s2) { emit_int32( LVEHX_OPCODE  | vrt(d) | rb(s2)); }
lvewx(VectorRegister d,Register s2)1050 inline void Assembler::lvewx( VectorRegister d, Register s2) { emit_int32( LVEWX_OPCODE  | vrt(d) | rb(s2)); }
lvx(VectorRegister d,Register s2)1051 inline void Assembler::lvx(   VectorRegister d, Register s2) { emit_int32( LVX_OPCODE    | vrt(d) | rb(s2)); }
lvxl(VectorRegister d,Register s2)1052 inline void Assembler::lvxl(  VectorRegister d, Register s2) { emit_int32( LVXL_OPCODE   | vrt(d) | rb(s2)); }
stvebx(VectorRegister d,Register s2)1053 inline void Assembler::stvebx(VectorRegister d, Register s2) { emit_int32( STVEBX_OPCODE | vrt(d) | rb(s2)); }
stvehx(VectorRegister d,Register s2)1054 inline void Assembler::stvehx(VectorRegister d, Register s2) { emit_int32( STVEHX_OPCODE | vrt(d) | rb(s2)); }
stvewx(VectorRegister d,Register s2)1055 inline void Assembler::stvewx(VectorRegister d, Register s2) { emit_int32( STVEWX_OPCODE | vrt(d) | rb(s2)); }
stvx(VectorRegister d,Register s2)1056 inline void Assembler::stvx(  VectorRegister d, Register s2) { emit_int32( STVX_OPCODE   | vrt(d) | rb(s2)); }
stvxl(VectorRegister d,Register s2)1057 inline void Assembler::stvxl( VectorRegister d, Register s2) { emit_int32( STVXL_OPCODE  | vrt(d) | rb(s2)); }
lvsl(VectorRegister d,Register s2)1058 inline void Assembler::lvsl(  VectorRegister d, Register s2) { emit_int32( LVSL_OPCODE   | vrt(d) | rb(s2)); }
lvsr(VectorRegister d,Register s2)1059 inline void Assembler::lvsr(  VectorRegister d, Register s2) { emit_int32( LVSR_OPCODE   | vrt(d) | rb(s2)); }
1060 
load_perm(VectorRegister perm,Register addr)1061 inline void Assembler::load_perm(VectorRegister perm, Register addr) {
1062 #if defined(VM_LITTLE_ENDIAN)
1063   lvsr(perm, addr);
1064 #else
1065   lvsl(perm, addr);
1066 #endif
1067 }
1068 
vec_perm(VectorRegister first_dest,VectorRegister second,VectorRegister perm)1069 inline void Assembler::vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm) {
1070 #if defined(VM_LITTLE_ENDIAN)
1071   vperm(first_dest, second, first_dest, perm);
1072 #else
1073   vperm(first_dest, first_dest, second, perm);
1074 #endif
1075 }
1076 
vec_perm(VectorRegister dest,VectorRegister first,VectorRegister second,VectorRegister perm)1077 inline void Assembler::vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm) {
1078 #if defined(VM_LITTLE_ENDIAN)
1079   vperm(dest, second, first, perm);
1080 #else
1081   vperm(dest, first, second, perm);
1082 #endif
1083 }
1084 
load_const(Register d,void * x,Register tmp)1085 inline void Assembler::load_const(Register d, void* x, Register tmp) {
1086    load_const(d, (long)x, tmp);
1087 }
1088 
1089 // Load a 64 bit constant encoded by a `Label'. This works for bound
1090 // labels as well as unbound ones. For unbound labels, the code will
1091 // be patched as soon as the label gets bound.
load_const(Register d,Label & L,Register tmp)1092 inline void Assembler::load_const(Register d, Label& L, Register tmp) {
1093   load_const(d, target(L), tmp);
1094 }
1095 
1096 // Load a 64 bit constant encoded by an AddressLiteral. patchable.
load_const(Register d,AddressLiteral & a,Register tmp)1097 inline void Assembler::load_const(Register d, AddressLiteral& a, Register tmp) {
1098   // First relocate (we don't change the offset in the RelocationHolder,
1099   // just pass a.rspec()), then delegate to load_const(Register, long).
1100   relocate(a.rspec());
1101   load_const(d, (long)a.value(), tmp);
1102 }
1103 
load_const32(Register d,int i)1104 inline void Assembler::load_const32(Register d, int i) {
1105   lis(d, i >> 16);
1106   ori(d, d, i & 0xFFFF);
1107 }
1108 
1109 #endif // CPU_PPC_VM_ASSEMBLER_PPC_INLINE_HPP
1110