1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2020 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "jvm.h"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/align.hpp"
37 #include "utilities/defaultStream.hpp"
38 #include "utilities/globalDefinitions.hpp"
39
40 #ifndef _ALLBSD_SOURCE
41 #include <sys/sysinfo.h>
42 #endif
43
44 #if defined(_AIX)
45 #include <libperfstat.h>
46 #endif
47
48 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
49 #include <sys/auxv.h>
50
51 #ifndef PPC_FEATURE2_HTM_NOSC
52 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
53 #endif
54 #endif
55
56 bool VM_Version::_is_determine_features_test_running = false;
57 uint64_t VM_Version::_dscr_val = 0;
58
59 #define MSG(flag) \
60 if (flag && !FLAG_IS_DEFAULT(flag)) \
61 jio_fprintf(defaultStream::error_stream(), \
62 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
63 " -XX:+" #flag " will be disabled!\n");
64
initialize()65 void VM_Version::initialize() {
66
67 // Test which instructions are supported and measure cache line size.
68 determine_features();
69
70 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
71 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
72 if (VM_Version::has_brw()) {
73 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 10);
74 } else if (VM_Version::has_darn()) {
75 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 9);
76 } else if (VM_Version::has_lqarx()) {
77 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
78 } else if (VM_Version::has_popcntw()) {
79 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
80 } else if (VM_Version::has_cmpb()) {
81 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
82 } else if (VM_Version::has_popcntb()) {
83 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
84 } else {
85 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
86 }
87 }
88
89 bool PowerArchitecturePPC64_ok = false;
90 switch (PowerArchitecturePPC64) {
91 case 10: if (!VM_Version::has_brw() ) break;
92 case 9: if (!VM_Version::has_darn() ) break;
93 case 8: if (!VM_Version::has_lqarx() ) break;
94 case 7: if (!VM_Version::has_popcntw()) break;
95 case 6: if (!VM_Version::has_cmpb() ) break;
96 case 5: if (!VM_Version::has_popcntb()) break;
97 case 0: PowerArchitecturePPC64_ok = true; break;
98 default: break;
99 }
100 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
101 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
102
103 // Power 8: Configure Data Stream Control Register.
104 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
105 config_dscr();
106 }
107
108 if (!UseSIGTRAP) {
109 MSG(TrapBasedICMissChecks);
110 MSG(TrapBasedNotEntrantChecks);
111 MSG(TrapBasedNullChecks);
112 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
113 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
114 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
115 }
116
117 #ifdef COMPILER2
118 if (!UseSIGTRAP) {
119 MSG(TrapBasedRangeChecks);
120 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
121 }
122
123 // On Power6 test for section size.
124 if (PowerArchitecturePPC64 == 6) {
125 determine_section_size();
126 // TODO: PPC port } else {
127 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
128 }
129
130 if (PowerArchitecturePPC64 >= 8) {
131 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
132 FLAG_SET_ERGO(bool, SuperwordUseVSX, true);
133 }
134 } else {
135 if (SuperwordUseVSX) {
136 warning("SuperwordUseVSX specified, but needs at least Power8.");
137 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
138 }
139 }
140 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
141
142 if (PowerArchitecturePPC64 >= 9) {
143 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionsPPC64)) {
144 FLAG_SET_ERGO(bool, UseCountTrailingZerosInstructionsPPC64, true);
145 }
146 if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
147 FLAG_SET_ERGO(bool, UseCharacterCompareIntrinsics, true);
148 }
149 } else {
150 if (UseCountTrailingZerosInstructionsPPC64) {
151 warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
152 FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionsPPC64, false);
153 }
154 if (UseCharacterCompareIntrinsics) {
155 warning("UseCharacterCompareIntrinsics specified, but needs at least Power9.");
156 FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false);
157 }
158 }
159
160 if (PowerArchitecturePPC64 >= 10) {
161 if (FLAG_IS_DEFAULT(UseByteReverseInstructions)) {
162 FLAG_SET_ERGO(bool, UseByteReverseInstructions, true);
163 }
164 } else {
165 if (UseByteReverseInstructions) {
166 warning("UseByteReverseInstructions specified, but needs at least Power10.");
167 FLAG_SET_DEFAULT(UseByteReverseInstructions, false);
168 }
169 }
170 #endif
171
172 // Create and print feature-string.
173 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
174 jio_snprintf(buf, sizeof(buf),
175 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
176 (has_fsqrt() ? " fsqrt" : ""),
177 (has_isel() ? " isel" : ""),
178 (has_lxarxeh() ? " lxarxeh" : ""),
179 (has_cmpb() ? " cmpb" : ""),
180 (has_popcntb() ? " popcntb" : ""),
181 (has_popcntw() ? " popcntw" : ""),
182 (has_fcfids() ? " fcfids" : ""),
183 (has_vand() ? " vand" : ""),
184 (has_lqarx() ? " lqarx" : ""),
185 (has_vcipher() ? " aes" : ""),
186 (has_vpmsumb() ? " vpmsumb" : ""),
187 (has_mfdscr() ? " mfdscr" : ""),
188 (has_vsx() ? " vsx" : ""),
189 (has_ldbrx() ? " ldbrx" : ""),
190 (has_stdbrx() ? " stdbrx" : ""),
191 (has_vshasig() ? " sha" : ""),
192 (has_tm() ? " rtm" : ""),
193 (has_darn() ? " darn" : ""),
194 (has_brw() ? " brw" : "")
195 // Make sure number of %s matches num_features!
196 );
197 _features_string = os::strdup(buf);
198 if (Verbose) {
199 print_features();
200 }
201
202 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
203 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
204 _supports_cx8 = true;
205
206 // Used by C1.
207 _supports_atomic_getset4 = true;
208 _supports_atomic_getadd4 = true;
209 _supports_atomic_getset8 = true;
210 _supports_atomic_getadd8 = true;
211
212 UseSSE = 0; // Only on x86 and x64
213
214 intx cache_line_size = L1_data_cache_line_size();
215
216 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
217
218 if (AllocatePrefetchStyle == 4) {
219 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
220 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
221 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
222 } else {
223 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
224 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
225 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
226 }
227
228 assert(AllocatePrefetchLines > 0, "invalid value");
229 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
230 AllocatePrefetchLines = 1; // Conservative value.
231 }
232
233 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
234 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
235 }
236
237 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
238
239 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (cache_line_size > ContendedPaddingWidth)) {
240 ContendedPaddingWidth = cache_line_size;
241 }
242
243 // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
244 // In all other cases, the implementation uses only generally available instructions.
245 if (!UseCRC32Intrinsics) {
246 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
247 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
248 }
249 }
250
251 // Implementation does not use any of the vector instructions available with Power8.
252 // Their exploitation is still pending (aka "work in progress").
253 if (!UseCRC32CIntrinsics) {
254 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
255 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
256 }
257 }
258
259 // TODO: Provide implementation.
260 if (UseAdler32Intrinsics) {
261 warning("Adler32Intrinsics not available on this CPU.");
262 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
263 }
264
265 // The AES intrinsic stubs require AES instruction support.
266 if (has_vcipher()) {
267 if (FLAG_IS_DEFAULT(UseAES)) {
268 UseAES = true;
269 }
270 } else if (UseAES) {
271 if (!FLAG_IS_DEFAULT(UseAES))
272 warning("AES instructions are not available on this CPU");
273 FLAG_SET_DEFAULT(UseAES, false);
274 }
275
276 if (UseAES && has_vcipher()) {
277 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
278 UseAESIntrinsics = true;
279 }
280 } else if (UseAESIntrinsics) {
281 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
282 warning("AES intrinsics are not available on this CPU");
283 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
284 }
285
286 if (UseAESCTRIntrinsics) {
287 warning("AES/CTR intrinsics are not available on this CPU");
288 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
289 }
290
291 if (UseGHASHIntrinsics) {
292 warning("GHASH intrinsics are not available on this CPU");
293 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
294 }
295
296 if (FLAG_IS_DEFAULT(UseFMA)) {
297 FLAG_SET_DEFAULT(UseFMA, true);
298 }
299
300 if (has_vshasig()) {
301 if (FLAG_IS_DEFAULT(UseSHA)) {
302 UseSHA = true;
303 }
304 } else if (UseSHA) {
305 if (!FLAG_IS_DEFAULT(UseSHA))
306 warning("SHA instructions are not available on this CPU");
307 FLAG_SET_DEFAULT(UseSHA, false);
308 }
309
310 if (UseSHA1Intrinsics) {
311 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
312 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
313 }
314
315 if (UseSHA && has_vshasig()) {
316 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
317 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
318 }
319 } else if (UseSHA256Intrinsics) {
320 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
321 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
322 }
323
324 if (UseSHA && has_vshasig()) {
325 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
326 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
327 }
328 } else if (UseSHA512Intrinsics) {
329 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
330 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
331 }
332
333 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
334 FLAG_SET_DEFAULT(UseSHA, false);
335 }
336
337 #ifdef COMPILER2
338 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
339 UseSquareToLenIntrinsic = true;
340 }
341 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
342 UseMulAddIntrinsic = true;
343 }
344 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
345 UseMultiplyToLenIntrinsic = true;
346 }
347 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
348 UseMontgomeryMultiplyIntrinsic = true;
349 }
350 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
351 UseMontgomerySquareIntrinsic = true;
352 }
353 #endif
354
355 if (UseVectorizedMismatchIntrinsic) {
356 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
357 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
358 }
359
360
361 // Adjust RTM (Restricted Transactional Memory) flags.
362 if (UseRTMLocking) {
363 // If CPU or OS do not support TM:
364 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
365 // setting during arguments processing. See use_biased_locking().
366 // VM_Version_init() is executed after UseBiasedLocking is used
367 // in Thread::allocate().
368 if (PowerArchitecturePPC64 < 8) {
369 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
370 }
371
372 if (!has_tm()) {
373 vm_exit_during_initialization("RTM is not supported on this OS version.");
374 }
375 }
376
377 if (UseRTMLocking) {
378 #if INCLUDE_RTM_OPT
379 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
380 // RTM locking should be used only for applications with
381 // high lock contention. For now we do not use it by default.
382 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
383 }
384 #else
385 // Only C2 does RTM locking optimization.
386 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
387 // setting during arguments processing. See use_biased_locking().
388 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
389 #endif
390 } else { // !UseRTMLocking
391 if (UseRTMForStackLocks) {
392 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
393 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
394 }
395 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
396 }
397 if (UseRTMDeopt) {
398 FLAG_SET_DEFAULT(UseRTMDeopt, false);
399 }
400 #ifdef COMPILER2
401 if (PrintPreciseRTMLockingStatistics) {
402 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
403 }
404 #endif
405 }
406
407 // This machine allows unaligned memory accesses
408 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
409 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
410 }
411
412 check_virtualizations();
413 }
414
check_virtualizations()415 void VM_Version::check_virtualizations() {
416 #if defined(_AIX)
417 int rc = 0;
418 perfstat_partition_total_t pinfo;
419 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
420 if (rc == 1) {
421 Abstract_VM_Version::_detected_virtualization = PowerVM;
422 }
423 #else
424 const char* info_file = "/proc/ppc64/lparcfg";
425 // system_type=...qemu indicates PowerKVM
426 // e.g. system_type=IBM pSeries (emulated by qemu)
427 char line[500];
428 FILE* fp = fopen(info_file, "r");
429 if (fp == NULL) {
430 return;
431 }
432 const char* system_type="system_type="; // in case this line contains qemu, it is KVM
433 const char* num_lpars="NumLpars="; // in case of non-KVM : if this line is found it is PowerVM
434 bool num_lpars_found = false;
435
436 while (fgets(line, sizeof(line), fp) != NULL) {
437 if (strncmp(line, system_type, strlen(system_type)) == 0) {
438 if (strstr(line, "qemu") != 0) {
439 Abstract_VM_Version::_detected_virtualization = PowerKVM;
440 fclose(fp);
441 return;
442 }
443 }
444 if (strncmp(line, num_lpars, strlen(num_lpars)) == 0) {
445 num_lpars_found = true;
446 }
447 }
448 if (num_lpars_found) {
449 Abstract_VM_Version::_detected_virtualization = PowerVM;
450 } else {
451 Abstract_VM_Version::_detected_virtualization = PowerFullPartitionMode;
452 }
453 fclose(fp);
454 #endif
455 }
456
print_platform_virtualization_info(outputStream * st)457 void VM_Version::print_platform_virtualization_info(outputStream* st) {
458 #if defined(_AIX)
459 // more info about perfstat API see
460 // https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.prftools/idprftools_perfstat_glob_partition.htm
461 int rc = 0;
462 perfstat_partition_total_t pinfo;
463 memset(&pinfo, 0, sizeof(perfstat_partition_total_t));
464 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
465 if (rc != 1) {
466 return;
467 } else {
468 st->print_cr("Virtualization type : PowerVM");
469 }
470 // CPU information
471 perfstat_cpu_total_t cpuinfo;
472 memset(&cpuinfo, 0, sizeof(perfstat_cpu_total_t));
473 rc = perfstat_cpu_total(NULL, &cpuinfo, sizeof(perfstat_cpu_total_t), 1);
474 if (rc != 1) {
475 return;
476 }
477
478 st->print_cr("Processor description : %s", cpuinfo.description);
479 st->print_cr("Processor speed : %llu Hz", cpuinfo.processorHZ);
480
481 st->print_cr("LPAR partition name : %s", pinfo.name);
482 st->print_cr("LPAR partition number : %u", pinfo.lpar_id);
483 st->print_cr("LPAR partition type : %s", pinfo.type.b.shared_enabled ? "shared" : "dedicated");
484 st->print_cr("LPAR mode : %s", pinfo.type.b.donate_enabled ? "donating" : pinfo.type.b.capped ? "capped" : "uncapped");
485 st->print_cr("LPAR partition group ID : %u", pinfo.group_id);
486 st->print_cr("LPAR shared pool ID : %u", pinfo.pool_id);
487
488 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_capable ? "capable" : "not capable");
489 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_enabled ? "on" : "off");
490 st->print_cr("AME (active memory expansion) : %s", pinfo.type.b.ame_enabled ? "on" : "off");
491
492 if (pinfo.type.b.ame_enabled) {
493 st->print_cr("AME true memory in bytes : %llu", pinfo.true_memory);
494 st->print_cr("AME expanded memory in bytes : %llu", pinfo.expanded_memory);
495 }
496
497 st->print_cr("SMT : %s", pinfo.type.b.smt_capable ? "capable" : "not capable");
498 st->print_cr("SMT : %s", pinfo.type.b.smt_enabled ? "on" : "off");
499 int ocpus = pinfo.online_cpus > 0 ? pinfo.online_cpus : 1;
500 st->print_cr("LPAR threads : %d", cpuinfo.ncpus/ocpus);
501 st->print_cr("LPAR online virtual cpus : %d", pinfo.online_cpus);
502 st->print_cr("LPAR logical cpus : %d", cpuinfo.ncpus);
503 st->print_cr("LPAR maximum virtual cpus : %u", pinfo.max_cpus);
504 st->print_cr("LPAR minimum virtual cpus : %u", pinfo.min_cpus);
505 st->print_cr("LPAR entitled capacity : %4.2f", (double) (pinfo.entitled_proc_capacity/100.0));
506 st->print_cr("LPAR online memory : %llu MB", pinfo.online_memory);
507 st->print_cr("LPAR maximum memory : %llu MB", pinfo.max_memory);
508 st->print_cr("LPAR minimum memory : %llu MB", pinfo.min_memory);
509 #else
510 const char* info_file = "/proc/ppc64/lparcfg";
511 const char* kw[] = { "system_type=", // qemu indicates PowerKVM
512 "partition_entitled_capacity=", // entitled processor capacity percentage
513 "partition_max_entitled_capacity=",
514 "capacity_weight=", // partition CPU weight
515 "partition_active_processors=",
516 "partition_potential_processors=",
517 "entitled_proc_capacity_available=",
518 "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage
519 "shared_processor_mode=", // (non)dedicated partition
520 "system_potential_processors=",
521 "pool=", // CPU-pool number
522 "pool_capacity=",
523 "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines
524 NULL };
525 if (!print_matching_lines_from_file(info_file, st, kw)) {
526 st->print_cr(" <%s Not Available>", info_file);
527 }
528 #endif
529 }
530
use_biased_locking()531 bool VM_Version::use_biased_locking() {
532 #if INCLUDE_RTM_OPT
533 // RTM locking is most useful when there is high lock contention and
534 // low data contention. With high lock contention the lock is usually
535 // inflated and biased locking is not suitable for that case.
536 // RTM locking code requires that biased locking is off.
537 // Note: we can't switch off UseBiasedLocking in get_processor_features()
538 // because it is used by Thread::allocate() which is called before
539 // VM_Version::initialize().
540 if (UseRTMLocking && UseBiasedLocking) {
541 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
542 FLAG_SET_DEFAULT(UseBiasedLocking, false);
543 } else {
544 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
545 UseBiasedLocking = false;
546 }
547 }
548 #endif
549 return UseBiasedLocking;
550 }
551
print_features()552 void VM_Version::print_features() {
553 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
554
555 if (Verbose) {
556 if (ContendedPaddingWidth > 0) {
557 tty->cr();
558 tty->print_cr("ContendedPaddingWidth " INTX_FORMAT, ContendedPaddingWidth);
559 }
560 }
561 }
562
563 #ifdef COMPILER2
564 // Determine section size on power6: If section size is 8 instructions,
565 // there should be a difference between the two testloops of ~15 %. If
566 // no difference is detected the section is assumed to be 32 instructions.
determine_section_size()567 void VM_Version::determine_section_size() {
568
569 int unroll = 80;
570
571 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
572
573 // Allocate space for the code.
574 ResourceMark rm;
575 CodeBuffer cb("detect_section_size", code_size, 0);
576 MacroAssembler* a = new MacroAssembler(&cb);
577
578 uint32_t *code = (uint32_t *)a->pc();
579 // Emit code.
580 void (*test1)() = (void(*)())(void *)a->function_entry();
581
582 Label l1;
583
584 a->li(R4, 1);
585 a->sldi(R4, R4, 28);
586 a->b(l1);
587 a->align(CodeEntryAlignment);
588
589 a->bind(l1);
590
591 for (int i = 0; i < unroll; i++) {
592 // Schleife 1
593 // ------- sector 0 ------------
594 // ;; 0
595 a->nop(); // 1
596 a->fpnop0(); // 2
597 a->fpnop1(); // 3
598 a->addi(R4,R4, -1); // 4
599
600 // ;; 1
601 a->nop(); // 5
602 a->fmr(F6, F6); // 6
603 a->fmr(F7, F7); // 7
604 a->endgroup(); // 8
605 // ------- sector 8 ------------
606
607 // ;; 2
608 a->nop(); // 9
609 a->nop(); // 10
610 a->fmr(F8, F8); // 11
611 a->fmr(F9, F9); // 12
612
613 // ;; 3
614 a->nop(); // 13
615 a->fmr(F10, F10); // 14
616 a->fmr(F11, F11); // 15
617 a->endgroup(); // 16
618 // -------- sector 16 -------------
619
620 // ;; 4
621 a->nop(); // 17
622 a->nop(); // 18
623 a->fmr(F15, F15); // 19
624 a->fmr(F16, F16); // 20
625
626 // ;; 5
627 a->nop(); // 21
628 a->fmr(F17, F17); // 22
629 a->fmr(F18, F18); // 23
630 a->endgroup(); // 24
631 // ------- sector 24 ------------
632
633 // ;; 6
634 a->nop(); // 25
635 a->nop(); // 26
636 a->fmr(F19, F19); // 27
637 a->fmr(F20, F20); // 28
638
639 // ;; 7
640 a->nop(); // 29
641 a->fmr(F21, F21); // 30
642 a->fmr(F22, F22); // 31
643 a->brnop0(); // 32
644
645 // ------- sector 32 ------------
646 }
647
648 // ;; 8
649 a->cmpdi(CCR0, R4, unroll); // 33
650 a->bge(CCR0, l1); // 34
651 a->blr();
652
653 // Emit code.
654 void (*test2)() = (void(*)())(void *)a->function_entry();
655 // uint32_t *code = (uint32_t *)a->pc();
656
657 Label l2;
658
659 a->li(R4, 1);
660 a->sldi(R4, R4, 28);
661 a->b(l2);
662 a->align(CodeEntryAlignment);
663
664 a->bind(l2);
665
666 for (int i = 0; i < unroll; i++) {
667 // Schleife 2
668 // ------- sector 0 ------------
669 // ;; 0
670 a->brnop0(); // 1
671 a->nop(); // 2
672 //a->cmpdi(CCR0, R4, unroll);
673 a->fpnop0(); // 3
674 a->fpnop1(); // 4
675 a->addi(R4,R4, -1); // 5
676
677 // ;; 1
678
679 a->nop(); // 6
680 a->fmr(F6, F6); // 7
681 a->fmr(F7, F7); // 8
682 // ------- sector 8 ---------------
683
684 // ;; 2
685 a->endgroup(); // 9
686
687 // ;; 3
688 a->nop(); // 10
689 a->nop(); // 11
690 a->fmr(F8, F8); // 12
691
692 // ;; 4
693 a->fmr(F9, F9); // 13
694 a->nop(); // 14
695 a->fmr(F10, F10); // 15
696
697 // ;; 5
698 a->fmr(F11, F11); // 16
699 // -------- sector 16 -------------
700
701 // ;; 6
702 a->endgroup(); // 17
703
704 // ;; 7
705 a->nop(); // 18
706 a->nop(); // 19
707 a->fmr(F15, F15); // 20
708
709 // ;; 8
710 a->fmr(F16, F16); // 21
711 a->nop(); // 22
712 a->fmr(F17, F17); // 23
713
714 // ;; 9
715 a->fmr(F18, F18); // 24
716 // -------- sector 24 -------------
717
718 // ;; 10
719 a->endgroup(); // 25
720
721 // ;; 11
722 a->nop(); // 26
723 a->nop(); // 27
724 a->fmr(F19, F19); // 28
725
726 // ;; 12
727 a->fmr(F20, F20); // 29
728 a->nop(); // 30
729 a->fmr(F21, F21); // 31
730
731 // ;; 13
732 a->fmr(F22, F22); // 32
733 }
734
735 // -------- sector 32 -------------
736 // ;; 14
737 a->cmpdi(CCR0, R4, unroll); // 33
738 a->bge(CCR0, l2); // 34
739
740 a->blr();
741 uint32_t *code_end = (uint32_t *)a->pc();
742 a->flush();
743
744 double loop1_seconds,loop2_seconds, rel_diff;
745 uint64_t start1, stop1;
746
747 start1 = os::current_thread_cpu_time(false);
748 (*test1)();
749 stop1 = os::current_thread_cpu_time(false);
750 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
751
752
753 start1 = os::current_thread_cpu_time(false);
754 (*test2)();
755 stop1 = os::current_thread_cpu_time(false);
756
757 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
758
759 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
760
761 if (PrintAssembly) {
762 ttyLocker ttyl;
763 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
764 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
765 tty->print_cr("Time loop1 :%f", loop1_seconds);
766 tty->print_cr("Time loop2 :%f", loop2_seconds);
767 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
768
769 if (rel_diff > 12.0) {
770 tty->print_cr("Section Size 8 Instructions");
771 } else{
772 tty->print_cr("Section Size 32 Instructions or Power5");
773 }
774 }
775
776 #if 0 // TODO: PPC port
777 // Set sector size (if not set explicitly).
778 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
779 if (rel_diff > 12.0) {
780 PdScheduling::power6SectorSize = 0x20;
781 } else {
782 PdScheduling::power6SectorSize = 0x80;
783 }
784 } else if (Power6SectorSize128PPC64) {
785 PdScheduling::power6SectorSize = 0x80;
786 } else {
787 PdScheduling::power6SectorSize = 0x20;
788 }
789 #endif
790 if (UsePower6SchedulerPPC64) Unimplemented();
791 }
792 #endif // COMPILER2
793
determine_features()794 void VM_Version::determine_features() {
795 #if defined(ABI_ELFv2)
796 // 1 InstWord per call for the blr instruction.
797 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
798 #else
799 // 7 InstWords for each call (function descriptor + blr instruction).
800 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
801 #endif
802 int features = 0;
803
804 // create test area
805 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
806 char test_area[BUFFER_SIZE];
807 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
808
809 // Allocate space for the code.
810 ResourceMark rm;
811 CodeBuffer cb("detect_cpu_features", code_size, 0);
812 MacroAssembler* a = new MacroAssembler(&cb);
813
814 // Must be set to true so we can generate the test code.
815 _features = VM_Version::all_features_m;
816
817 // Emit code.
818 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
819 uint32_t *code = (uint32_t *)a->pc();
820 // Don't use R0 in ldarx.
821 // Keep R3_ARG1 unmodified, it contains &field (see below).
822 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
823 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
824 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
825 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
826 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
827 a->cmpb(R7, R5, R6); // code[4] -> cmpb
828 a->popcntb(R7, R5); // code[5] -> popcntb
829 a->popcntw(R7, R5); // code[6] -> popcntw
830 a->fcfids(F3, F4); // code[7] -> fcfids
831 a->vand(VR0, VR0, VR0); // code[8] -> vand
832 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
833 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
834 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
835 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
836 a->mfdscr(R0); // code[12] -> mfdscr
837 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
838 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
839 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
840 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
841 // rtm is determined by OS
842 a->darn(R7); // code[17] -> darn
843 a->brw(R5, R6); // code[18] -> brw
844 a->blr();
845
846 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
847 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
848 a->dcbz(R3_ARG1); // R3_ARG1 = addr
849 a->blr();
850
851 uint32_t *code_end = (uint32_t *)a->pc();
852 a->flush();
853 _features = VM_Version::unknown_m;
854
855 // Print the detection code.
856 if (PrintAssembly) {
857 ttyLocker ttyl;
858 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
859 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
860 }
861
862 // Measure cache line size.
863 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
864 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
865 int count = 0; // count zeroed bytes
866 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
867 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
868 _L1_data_cache_line_size = count;
869
870 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
871 VM_Version::_is_determine_features_test_running = true;
872 // We must align the first argument to 16 bytes because of the lqarx check.
873 (*test)(align_up((address)mid_of_test_area, 16), 0);
874 VM_Version::_is_determine_features_test_running = false;
875
876 // determine which instructions are legal.
877 int feature_cntr = 0;
878 if (code[feature_cntr++]) features |= fsqrt_m;
879 if (code[feature_cntr++]) features |= fsqrts_m;
880 if (code[feature_cntr++]) features |= isel_m;
881 if (code[feature_cntr++]) features |= lxarxeh_m;
882 if (code[feature_cntr++]) features |= cmpb_m;
883 if (code[feature_cntr++]) features |= popcntb_m;
884 if (code[feature_cntr++]) features |= popcntw_m;
885 if (code[feature_cntr++]) features |= fcfids_m;
886 if (code[feature_cntr++]) features |= vand_m;
887 if (code[feature_cntr++]) features |= lqarx_m;
888 if (code[feature_cntr++]) features |= vcipher_m;
889 if (code[feature_cntr++]) features |= vpmsumb_m;
890 if (code[feature_cntr++]) features |= mfdscr_m;
891 if (code[feature_cntr++]) features |= vsx_m;
892 if (code[feature_cntr++]) features |= ldbrx_m;
893 if (code[feature_cntr++]) features |= stdbrx_m;
894 if (code[feature_cntr++]) features |= vshasig_m;
895 // feature rtm_m is determined by OS
896 if (code[feature_cntr++]) features |= darn_m;
897 if (code[feature_cntr++]) features |= brw_m;
898
899 // Print the detection code.
900 if (PrintAssembly) {
901 ttyLocker ttyl;
902 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
903 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
904 }
905
906 _features = features;
907
908 #ifdef AIX
909 // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
910 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
911 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
912 // The Java property os.version, which is used in RTM tests to decide
913 // whether the feature is available, only knows major and minor versions.
914 // We don't want to change this property, as user code might depend on it.
915 // So the tests can not check on subversion 3.30, and we only enable RTM
916 // with AIX 7.2.
917 if (has_lqarx()) { // POWER8 or above
918 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
919 _features |= rtm_m;
920 }
921 }
922 #endif
923 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
924 unsigned long auxv = getauxval(AT_HWCAP2);
925
926 if (auxv & PPC_FEATURE2_HTM_NOSC) {
927 if (auxv & PPC_FEATURE2_HAS_HTM) {
928 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
929 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
930 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
931 // and kernel workarounds, so there is a new mode only supported
932 // on non-virtualized P9 machines called HTM with no Suspend Mode).
933 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
934 _features |= rtm_m;
935 }
936 }
937 #endif
938 }
939
940 // Power 8: Configure Data Stream Control Register.
config_dscr()941 void VM_Version::config_dscr() {
942 // 7 InstWords for each call (function descriptor + blr instruction).
943 const int code_size = (2+2*7)*BytesPerInstWord;
944
945 // Allocate space for the code.
946 ResourceMark rm;
947 CodeBuffer cb("config_dscr", code_size, 0);
948 MacroAssembler* a = new MacroAssembler(&cb);
949
950 // Emit code.
951 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
952 uint32_t *code = (uint32_t *)a->pc();
953 a->mfdscr(R3);
954 a->blr();
955
956 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
957 a->mtdscr(R3);
958 a->blr();
959
960 uint32_t *code_end = (uint32_t *)a->pc();
961 a->flush();
962
963 // Print the detection code.
964 if (PrintAssembly) {
965 ttyLocker ttyl;
966 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
967 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
968 }
969
970 // Apply the configuration if needed.
971 _dscr_val = (*get_dscr)();
972 if (Verbose) {
973 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
974 }
975 bool change_requested = false;
976 if (DSCR_PPC64 != (uintx)-1) {
977 _dscr_val = DSCR_PPC64;
978 change_requested = true;
979 }
980 if (DSCR_DPFD_PPC64 <= 7) {
981 uint64_t mask = 0x7;
982 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
983 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
984 change_requested = true;
985 }
986 }
987 if (DSCR_URG_PPC64 <= 7) {
988 uint64_t mask = 0x7 << 6;
989 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
990 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
991 change_requested = true;
992 }
993 }
994 if (change_requested) {
995 (*set_dscr)(_dscr_val);
996 if (Verbose) {
997 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
998 }
999 }
1000 }
1001
1002 static uint64_t saved_features = 0;
1003
allow_all()1004 void VM_Version::allow_all() {
1005 saved_features = _features;
1006 _features = all_features_m;
1007 }
1008
revert()1009 void VM_Version::revert() {
1010 _features = saved_features;
1011 }
1012