1 /* 2 * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_S390_VM_C1_FRAMEMAP_S390_HPP 27 #define CPU_S390_VM_C1_FRAMEMAP_S390_HPP 28 29 public: 30 31 enum { 32 nof_reg_args = 5, // Registers Z_ARG1 - Z_ARG5 are available for parameter passing. 33 first_available_sp_in_frame = frame::z_abi_16_size, 34 frame_pad_in_bytes = 0 35 }; 36 37 static const int pd_c_runtime_reserved_arg_size; 38 39 static LIR_Opr Z_R0_opr; 40 static LIR_Opr Z_R1_opr; 41 static LIR_Opr Z_R2_opr; 42 static LIR_Opr Z_R3_opr; 43 static LIR_Opr Z_R4_opr; 44 static LIR_Opr Z_R5_opr; 45 static LIR_Opr Z_R6_opr; 46 static LIR_Opr Z_R7_opr; 47 static LIR_Opr Z_R8_opr; 48 static LIR_Opr Z_R9_opr; 49 static LIR_Opr Z_R10_opr; 50 static LIR_Opr Z_R11_opr; 51 static LIR_Opr Z_R12_opr; 52 static LIR_Opr Z_R13_opr; 53 static LIR_Opr Z_R14_opr; 54 static LIR_Opr Z_R15_opr; 55 56 static LIR_Opr Z_R0_oop_opr; 57 static LIR_Opr Z_R1_oop_opr; 58 static LIR_Opr Z_R2_oop_opr; 59 static LIR_Opr Z_R3_oop_opr; 60 static LIR_Opr Z_R4_oop_opr; 61 static LIR_Opr Z_R5_oop_opr; 62 static LIR_Opr Z_R6_oop_opr; 63 static LIR_Opr Z_R7_oop_opr; 64 static LIR_Opr Z_R8_oop_opr; 65 static LIR_Opr Z_R9_oop_opr; 66 static LIR_Opr Z_R10_oop_opr; 67 static LIR_Opr Z_R11_oop_opr; 68 static LIR_Opr Z_R12_oop_opr; 69 static LIR_Opr Z_R13_oop_opr; 70 static LIR_Opr Z_R14_oop_opr; 71 static LIR_Opr Z_R15_oop_opr; 72 73 static LIR_Opr Z_R0_metadata_opr; 74 static LIR_Opr Z_R1_metadata_opr; 75 static LIR_Opr Z_R2_metadata_opr; 76 static LIR_Opr Z_R3_metadata_opr; 77 static LIR_Opr Z_R4_metadata_opr; 78 static LIR_Opr Z_R5_metadata_opr; 79 static LIR_Opr Z_R6_metadata_opr; 80 static LIR_Opr Z_R7_metadata_opr; 81 static LIR_Opr Z_R8_metadata_opr; 82 static LIR_Opr Z_R9_metadata_opr; 83 static LIR_Opr Z_R10_metadata_opr; 84 static LIR_Opr Z_R11_metadata_opr; 85 static LIR_Opr Z_R12_metadata_opr; 86 static LIR_Opr Z_R13_metadata_opr; 87 static LIR_Opr Z_R14_metadata_opr; 88 static LIR_Opr Z_R15_metadata_opr; 89 90 static LIR_Opr Z_SP_opr; 91 static LIR_Opr Z_FP_opr; 92 93 static LIR_Opr Z_R2_long_opr; 94 static LIR_Opr Z_R10_long_opr; 95 static LIR_Opr Z_R11_long_opr; 96 97 static LIR_Opr Z_F0_opr; 98 static LIR_Opr Z_F0_double_opr; 99 100 private: 101 static FloatRegister _fpu_rnr2reg [FrameMap::nof_fpu_regs]; // mapping c1 regnr. -> FloatRegister 102 static int _fpu_reg2rnr [FrameMap::nof_fpu_regs]; // mapping assembler encoding -> c1 regnr. 103 104 static void map_float_register(int rnr, FloatRegister reg); 105 106 // FloatRegister -> c1 rnr fpu_reg2rnr(FloatRegister reg)107 static int fpu_reg2rnr (FloatRegister reg) { 108 assert(_init_done, "tables not initialized"); 109 int c1rnr = _fpu_reg2rnr[reg->encoding()]; 110 debug_only(fpu_range_check(c1rnr);) 111 return c1rnr; 112 } 113 114 public: 115 116 static LIR_Opr as_long_opr(Register r) { 117 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); 118 } as_pointer_opr(Register r)119 static LIR_Opr as_pointer_opr(Register r) { 120 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); 121 } 122 as_float_opr(FloatRegister r)123 static LIR_Opr as_float_opr(FloatRegister r) { 124 return LIR_OprFact::single_fpu(fpu_reg2rnr(r)); 125 } as_double_opr(FloatRegister r)126 static LIR_Opr as_double_opr(FloatRegister r) { 127 return LIR_OprFact::double_fpu(fpu_reg2rnr(r)); 128 } 129 130 static FloatRegister nr2floatreg (int rnr); 131 132 static VMReg fpu_regname (int n); 133 134 // No callee saved registers (saved values are not accessible if callee is in runtime). is_caller_save_register(LIR_Opr opr)135 static bool is_caller_save_register (LIR_Opr opr) { return true; } is_caller_save_register(Register r)136 static bool is_caller_save_register (Register r) { return true; } 137 nof_caller_save_cpu_regs()138 static int nof_caller_save_cpu_regs() { return pd_nof_caller_save_cpu_regs_frame_map; } last_cpu_reg()139 static int last_cpu_reg() { return pd_last_cpu_reg; } 140 141 #endif // CPU_S390_VM_C1_FRAMEMAP_S390_HPP 142