1// 2// Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved. 3// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4// 5// This code is free software; you can redistribute it and/or modify it 6// under the terms of the GNU General Public License version 2 only, as 7// published by the Free Software Foundation. 8// 9// This code is distributed in the hope that it will be useful, but WITHOUT 10// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12// version 2 for more details (a copy is included in the LICENSE file that 13// accompanied this code). 14// 15// You should have received a copy of the GNU General Public License version 16// 2 along with this work; if not, write to the Free Software Foundation, 17// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18// 19// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20// or visit www.oracle.com if you need additional information or have any 21// questions. 22// 23// 24 25// AMD64 Architecture Description File 26 27//----------REGISTER DEFINITION BLOCK------------------------------------------ 28// This information is used by the matcher and the register allocator to 29// describe individual registers and classes of registers within the target 30// archtecture. 31 32register %{ 33//----------Architecture Description Register Definitions---------------------- 34// General Registers 35// "reg_def" name ( register save type, C convention save type, 36// ideal register type, encoding ); 37// Register Save Types: 38// 39// NS = No-Save: The register allocator assumes that these registers 40// can be used without saving upon entry to the method, & 41// that they do not need to be saved at call sites. 42// 43// SOC = Save-On-Call: The register allocator assumes that these registers 44// can be used without saving upon entry to the method, 45// but that they must be saved at call sites. 46// 47// SOE = Save-On-Entry: The register allocator assumes that these registers 48// must be saved before using them upon entry to the 49// method, but they do not need to be saved at call 50// sites. 51// 52// AS = Always-Save: The register allocator assumes that these registers 53// must be saved before using them upon entry to the 54// method, & that they must be saved at call sites. 55// 56// Ideal Register Type is used to determine how to save & restore a 57// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 58// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 59// 60// The encoding number is the actual bit-pattern placed into the opcodes. 61 62// General Registers 63// R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when 64// used as byte registers) 65 66// Previously set RBX, RSI, and RDI as save-on-entry for java code 67// Turn off SOE in java-code due to frequent use of uncommon-traps. 68// Now that allocator is better, turn on RSI and RDI as SOE registers. 69 70reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); 71reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); 72 73reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); 74reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); 75 76reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); 77reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); 78 79reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); 80reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); 81 82reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); 83reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); 84 85// now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code 86reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); 87reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); 88 89#ifdef _WIN64 90 91reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); 92reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); 93 94reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); 95reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); 96 97#else 98 99reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); 100reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); 101 102reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); 103reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); 104 105#endif 106 107reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); 108reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); 109 110reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); 111reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); 112 113reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); 114reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); 115 116reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); 117reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); 118 119reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); 120reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); 121 122reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); 123reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); 124 125reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); 126reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); 127 128reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); 129reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); 130 131 132// Floating Point Registers 133 134// Specify priority of register selection within phases of register 135// allocation. Highest priority is first. A useful heuristic is to 136// give registers a low priority when they are required by machine 137// instructions, like EAX and EDX on I486, and choose no-save registers 138// before save-on-call, & save-on-call before save-on-entry. Registers 139// which participate in fixed calling sequences should come last. 140// Registers which are used as pairs must fall on an even boundary. 141 142alloc_class chunk0(R10, R10_H, 143 R11, R11_H, 144 R8, R8_H, 145 R9, R9_H, 146 R12, R12_H, 147 RCX, RCX_H, 148 RBX, RBX_H, 149 RDI, RDI_H, 150 RDX, RDX_H, 151 RSI, RSI_H, 152 RAX, RAX_H, 153 RBP, RBP_H, 154 R13, R13_H, 155 R14, R14_H, 156 R15, R15_H, 157 RSP, RSP_H); 158 159 160//----------Architecture Description Register Classes-------------------------- 161// Several register classes are automatically defined based upon information in 162// this architecture description. 163// 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) 164// 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) 165// 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) 166// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 167// 168 169// Empty register class. 170reg_class no_reg(); 171 172// Class for all pointer/long registers 173reg_class all_reg(RAX, RAX_H, 174 RDX, RDX_H, 175 RBP, RBP_H, 176 RDI, RDI_H, 177 RSI, RSI_H, 178 RCX, RCX_H, 179 RBX, RBX_H, 180 RSP, RSP_H, 181 R8, R8_H, 182 R9, R9_H, 183 R10, R10_H, 184 R11, R11_H, 185 R12, R12_H, 186 R13, R13_H, 187 R14, R14_H, 188 R15, R15_H); 189 190// Class for all int registers 191reg_class all_int_reg(RAX 192 RDX, 193 RBP, 194 RDI, 195 RSI, 196 RCX, 197 RBX, 198 R8, 199 R9, 200 R10, 201 R11, 202 R12, 203 R13, 204 R14); 205 206// Class for all pointer registers 207reg_class any_reg %{ 208 return _ANY_REG_mask; 209%} 210 211// Class for all pointer registers (excluding RSP) 212reg_class ptr_reg %{ 213 return _PTR_REG_mask; 214%} 215 216// Class for all pointer registers (excluding RSP and RBP) 217reg_class ptr_reg_no_rbp %{ 218 return _PTR_REG_NO_RBP_mask; 219%} 220 221// Class for all pointer registers (excluding RAX and RSP) 222reg_class ptr_no_rax_reg %{ 223 return _PTR_NO_RAX_REG_mask; 224%} 225 226// Class for all pointer registers (excluding RAX, RBX, and RSP) 227reg_class ptr_no_rax_rbx_reg %{ 228 return _PTR_NO_RAX_RBX_REG_mask; 229%} 230 231// Class for all long registers (excluding RSP) 232reg_class long_reg %{ 233 return _LONG_REG_mask; 234%} 235 236// Class for all long registers (excluding RAX, RDX and RSP) 237reg_class long_no_rax_rdx_reg %{ 238 return _LONG_NO_RAX_RDX_REG_mask; 239%} 240 241// Class for all long registers (excluding RCX and RSP) 242reg_class long_no_rcx_reg %{ 243 return _LONG_NO_RCX_REG_mask; 244%} 245 246// Class for all int registers (excluding RSP) 247reg_class int_reg %{ 248 return _INT_REG_mask; 249%} 250 251// Class for all int registers (excluding RAX, RDX, and RSP) 252reg_class int_no_rax_rdx_reg %{ 253 return _INT_NO_RAX_RDX_REG_mask; 254%} 255 256// Class for all int registers (excluding RCX and RSP) 257reg_class int_no_rcx_reg %{ 258 return _INT_NO_RCX_REG_mask; 259%} 260 261// Singleton class for RAX pointer register 262reg_class ptr_rax_reg(RAX, RAX_H); 263 264// Singleton class for RBX pointer register 265reg_class ptr_rbx_reg(RBX, RBX_H); 266 267// Singleton class for RSI pointer register 268reg_class ptr_rsi_reg(RSI, RSI_H); 269 270// Singleton class for RDI pointer register 271reg_class ptr_rdi_reg(RDI, RDI_H); 272 273// Singleton class for stack pointer 274reg_class ptr_rsp_reg(RSP, RSP_H); 275 276// Singleton class for TLS pointer 277reg_class ptr_r15_reg(R15, R15_H); 278 279// Singleton class for RAX long register 280reg_class long_rax_reg(RAX, RAX_H); 281 282// Singleton class for RCX long register 283reg_class long_rcx_reg(RCX, RCX_H); 284 285// Singleton class for RDX long register 286reg_class long_rdx_reg(RDX, RDX_H); 287 288// Singleton class for RAX int register 289reg_class int_rax_reg(RAX); 290 291// Singleton class for RBX int register 292reg_class int_rbx_reg(RBX); 293 294// Singleton class for RCX int register 295reg_class int_rcx_reg(RCX); 296 297// Singleton class for RCX int register 298reg_class int_rdx_reg(RDX); 299 300// Singleton class for RCX int register 301reg_class int_rdi_reg(RDI); 302 303// Singleton class for instruction pointer 304// reg_class ip_reg(RIP); 305 306%} 307 308//----------SOURCE BLOCK------------------------------------------------------- 309// This is a block of C++ code which provides values, functions, and 310// definitions necessary in the rest of the architecture description 311source_hpp %{ 312 313extern RegMask _ANY_REG_mask; 314extern RegMask _PTR_REG_mask; 315extern RegMask _PTR_REG_NO_RBP_mask; 316extern RegMask _PTR_NO_RAX_REG_mask; 317extern RegMask _PTR_NO_RAX_RBX_REG_mask; 318extern RegMask _LONG_REG_mask; 319extern RegMask _LONG_NO_RAX_RDX_REG_mask; 320extern RegMask _LONG_NO_RCX_REG_mask; 321extern RegMask _INT_REG_mask; 322extern RegMask _INT_NO_RAX_RDX_REG_mask; 323extern RegMask _INT_NO_RCX_REG_mask; 324 325extern RegMask _STACK_OR_PTR_REG_mask; 326extern RegMask _STACK_OR_LONG_REG_mask; 327extern RegMask _STACK_OR_INT_REG_mask; 328 329inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; } 330inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; } 331inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; } 332 333%} 334 335source %{ 336#define RELOC_IMM64 Assembler::imm_operand 337#define RELOC_DISP32 Assembler::disp32_operand 338 339#define __ _masm. 340 341RegMask _ANY_REG_mask; 342RegMask _PTR_REG_mask; 343RegMask _PTR_REG_NO_RBP_mask; 344RegMask _PTR_NO_RAX_REG_mask; 345RegMask _PTR_NO_RAX_RBX_REG_mask; 346RegMask _LONG_REG_mask; 347RegMask _LONG_NO_RAX_RDX_REG_mask; 348RegMask _LONG_NO_RCX_REG_mask; 349RegMask _INT_REG_mask; 350RegMask _INT_NO_RAX_RDX_REG_mask; 351RegMask _INT_NO_RCX_REG_mask; 352RegMask _STACK_OR_PTR_REG_mask; 353RegMask _STACK_OR_LONG_REG_mask; 354RegMask _STACK_OR_INT_REG_mask; 355 356static bool need_r12_heapbase() { 357 return UseCompressedOops || UseCompressedClassPointers; 358} 359 360void reg_mask_init() { 361 // _ALL_REG_mask is generated by adlc from the all_reg register class below. 362 // We derive a number of subsets from it. 363 _ANY_REG_mask = _ALL_REG_mask; 364 365 if (PreserveFramePointer) { 366 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg())); 367 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next())); 368 } 369 if (need_r12_heapbase()) { 370 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg())); 371 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next())); 372 } 373 374 _PTR_REG_mask = _ANY_REG_mask; 375 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg())); 376 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next())); 377 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg())); 378 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next())); 379 380 _STACK_OR_PTR_REG_mask = _PTR_REG_mask; 381 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask()); 382 383 _PTR_REG_NO_RBP_mask = _PTR_REG_mask; 384 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg())); 385 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next())); 386 387 _PTR_NO_RAX_REG_mask = _PTR_REG_mask; 388 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg())); 389 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next())); 390 391 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask; 392 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg())); 393 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next())); 394 395 _LONG_REG_mask = _PTR_REG_mask; 396 _STACK_OR_LONG_REG_mask = _LONG_REG_mask; 397 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask()); 398 399 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask; 400 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg())); 401 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next())); 402 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg())); 403 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next())); 404 405 _LONG_NO_RCX_REG_mask = _LONG_REG_mask; 406 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg())); 407 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next())); 408 409 _INT_REG_mask = _ALL_INT_REG_mask; 410 if (PreserveFramePointer) { 411 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg())); 412 } 413 if (need_r12_heapbase()) { 414 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg())); 415 } 416 417 _STACK_OR_INT_REG_mask = _INT_REG_mask; 418 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask()); 419 420 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask; 421 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg())); 422 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg())); 423 424 _INT_NO_RCX_REG_mask = _INT_REG_mask; 425 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg())); 426} 427 428static bool generate_vzeroupper(Compile* C) { 429 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper 430} 431 432static int clear_avx_size() { 433 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper 434} 435 436// !!!!! Special hack to get all types of calls to specify the byte offset 437// from the start of the call to the point where the return address 438// will point. 439int MachCallStaticJavaNode::ret_addr_offset() 440{ 441 int offset = 5; // 5 bytes from start of call to where return address points 442 offset += clear_avx_size(); 443 return offset; 444} 445 446int MachCallDynamicJavaNode::ret_addr_offset() 447{ 448 int offset = 15; // 15 bytes from start of call to where return address points 449 offset += clear_avx_size(); 450 return offset; 451} 452 453int MachCallRuntimeNode::ret_addr_offset() { 454 int offset = 13; // movq r10,#addr; callq (r10) 455 offset += clear_avx_size(); 456 return offset; 457} 458 459// Indicate if the safepoint node needs the polling page as an input, 460// it does if the polling page is more than disp32 away. 461bool SafePointNode::needs_polling_address_input() 462{ 463 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far(); 464} 465 466// 467// Compute padding required for nodes which need alignment 468// 469 470// The address of the call instruction needs to be 4-byte aligned to 471// ensure that it does not span a cache line so that it can be patched. 472int CallStaticJavaDirectNode::compute_padding(int current_offset) const 473{ 474 current_offset += clear_avx_size(); // skip vzeroupper 475 current_offset += 1; // skip call opcode byte 476 return align_up(current_offset, alignment_required()) - current_offset; 477} 478 479// The address of the call instruction needs to be 4-byte aligned to 480// ensure that it does not span a cache line so that it can be patched. 481int CallDynamicJavaDirectNode::compute_padding(int current_offset) const 482{ 483 current_offset += clear_avx_size(); // skip vzeroupper 484 current_offset += 11; // skip movq instruction + call opcode byte 485 return align_up(current_offset, alignment_required()) - current_offset; 486} 487 488// EMIT_RM() 489void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { 490 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); 491 cbuf.insts()->emit_int8(c); 492} 493 494// EMIT_CC() 495void emit_cc(CodeBuffer &cbuf, int f1, int f2) { 496 unsigned char c = (unsigned char) (f1 | f2); 497 cbuf.insts()->emit_int8(c); 498} 499 500// EMIT_OPCODE() 501void emit_opcode(CodeBuffer &cbuf, int code) { 502 cbuf.insts()->emit_int8((unsigned char) code); 503} 504 505// EMIT_OPCODE() w/ relocation information 506void emit_opcode(CodeBuffer &cbuf, 507 int code, relocInfo::relocType reloc, int offset, int format) 508{ 509 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); 510 emit_opcode(cbuf, code); 511} 512 513// EMIT_D8() 514void emit_d8(CodeBuffer &cbuf, int d8) { 515 cbuf.insts()->emit_int8((unsigned char) d8); 516} 517 518// EMIT_D16() 519void emit_d16(CodeBuffer &cbuf, int d16) { 520 cbuf.insts()->emit_int16(d16); 521} 522 523// EMIT_D32() 524void emit_d32(CodeBuffer &cbuf, int d32) { 525 cbuf.insts()->emit_int32(d32); 526} 527 528// EMIT_D64() 529void emit_d64(CodeBuffer &cbuf, int64_t d64) { 530 cbuf.insts()->emit_int64(d64); 531} 532 533// emit 32 bit value and construct relocation entry from relocInfo::relocType 534void emit_d32_reloc(CodeBuffer& cbuf, 535 int d32, 536 relocInfo::relocType reloc, 537 int format) 538{ 539 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); 540 cbuf.relocate(cbuf.insts_mark(), reloc, format); 541 cbuf.insts()->emit_int32(d32); 542} 543 544// emit 32 bit value and construct relocation entry from RelocationHolder 545void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { 546#ifdef ASSERT 547 if (rspec.reloc()->type() == relocInfo::oop_type && 548 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { 549 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); 550 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code"); 551 } 552#endif 553 cbuf.relocate(cbuf.insts_mark(), rspec, format); 554 cbuf.insts()->emit_int32(d32); 555} 556 557void emit_d32_reloc(CodeBuffer& cbuf, address addr) { 558 address next_ip = cbuf.insts_end() + 4; 559 emit_d32_reloc(cbuf, (int) (addr - next_ip), 560 external_word_Relocation::spec(addr), 561 RELOC_DISP32); 562} 563 564 565// emit 64 bit value and construct relocation entry from relocInfo::relocType 566void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { 567 cbuf.relocate(cbuf.insts_mark(), reloc, format); 568 cbuf.insts()->emit_int64(d64); 569} 570 571// emit 64 bit value and construct relocation entry from RelocationHolder 572void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { 573#ifdef ASSERT 574 if (rspec.reloc()->type() == relocInfo::oop_type && 575 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { 576 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); 577 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code"); 578 } 579#endif 580 cbuf.relocate(cbuf.insts_mark(), rspec, format); 581 cbuf.insts()->emit_int64(d64); 582} 583 584// Access stack slot for load or store 585void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) 586{ 587 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) 588 if (-0x80 <= disp && disp < 0x80) { 589 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte 590 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte 591 emit_d8(cbuf, disp); // Displacement // R/M byte 592 } else { 593 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte 594 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte 595 emit_d32(cbuf, disp); // Displacement // R/M byte 596 } 597} 598 599 // rRegI ereg, memory mem) %{ // emit_reg_mem 600void encode_RegMem(CodeBuffer &cbuf, 601 int reg, 602 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) 603{ 604 assert(disp_reloc == relocInfo::none, "cannot have disp"); 605 int regenc = reg & 7; 606 int baseenc = base & 7; 607 int indexenc = index & 7; 608 609 // There is no index & no scale, use form without SIB byte 610 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { 611 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] 612 if (disp == 0 && base != RBP_enc && base != R13_enc) { 613 emit_rm(cbuf, 0x0, regenc, baseenc); // * 614 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { 615 // If 8-bit displacement, mode 0x1 616 emit_rm(cbuf, 0x1, regenc, baseenc); // * 617 emit_d8(cbuf, disp); 618 } else { 619 // If 32-bit displacement 620 if (base == -1) { // Special flag for absolute address 621 emit_rm(cbuf, 0x0, regenc, 0x5); // * 622 if (disp_reloc != relocInfo::none) { 623 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); 624 } else { 625 emit_d32(cbuf, disp); 626 } 627 } else { 628 // Normal base + offset 629 emit_rm(cbuf, 0x2, regenc, baseenc); // * 630 if (disp_reloc != relocInfo::none) { 631 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); 632 } else { 633 emit_d32(cbuf, disp); 634 } 635 } 636 } 637 } else { 638 // Else, encode with the SIB byte 639 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] 640 if (disp == 0 && base != RBP_enc && base != R13_enc) { 641 // If no displacement 642 emit_rm(cbuf, 0x0, regenc, 0x4); // * 643 emit_rm(cbuf, scale, indexenc, baseenc); 644 } else { 645 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { 646 // If 8-bit displacement, mode 0x1 647 emit_rm(cbuf, 0x1, regenc, 0x4); // * 648 emit_rm(cbuf, scale, indexenc, baseenc); 649 emit_d8(cbuf, disp); 650 } else { 651 // If 32-bit displacement 652 if (base == 0x04 ) { 653 emit_rm(cbuf, 0x2, regenc, 0x4); 654 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? 655 } else { 656 emit_rm(cbuf, 0x2, regenc, 0x4); 657 emit_rm(cbuf, scale, indexenc, baseenc); // * 658 } 659 if (disp_reloc != relocInfo::none) { 660 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); 661 } else { 662 emit_d32(cbuf, disp); 663 } 664 } 665 } 666 } 667} 668 669// This could be in MacroAssembler but it's fairly C2 specific 670void emit_cmpfp_fixup(MacroAssembler& _masm) { 671 Label exit; 672 __ jccb(Assembler::noParity, exit); 673 __ pushf(); 674 // 675 // comiss/ucomiss instructions set ZF,PF,CF flags and 676 // zero OF,AF,SF for NaN values. 677 // Fixup flags by zeroing ZF,PF so that compare of NaN 678 // values returns 'less than' result (CF is set). 679 // Leave the rest of flags unchanged. 680 // 681 // 7 6 5 4 3 2 1 0 682 // |S|Z|r|A|r|P|r|C| (r - reserved bit) 683 // 0 0 1 0 1 0 1 1 (0x2B) 684 // 685 __ andq(Address(rsp, 0), 0xffffff2b); 686 __ popf(); 687 __ bind(exit); 688} 689 690void emit_cmpfp3(MacroAssembler& _masm, Register dst) { 691 Label done; 692 __ movl(dst, -1); 693 __ jcc(Assembler::parity, done); 694 __ jcc(Assembler::below, done); 695 __ setb(Assembler::notEqual, dst); 696 __ movzbl(dst, dst); 697 __ bind(done); 698} 699 700// Math.min() # Math.max() 701// -------------------------- 702// ucomis[s/d] # 703// ja -> b # a 704// jp -> NaN # NaN 705// jb -> a # b 706// je # 707// |-jz -> a | b # a & b 708// | -> a # 709void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst, 710 XMMRegister a, XMMRegister b, 711 XMMRegister xmmt, Register rt, 712 bool min, bool single) { 713 714 Label nan, zero, below, above, done; 715 716 if (single) 717 __ ucomiss(a, b); 718 else 719 __ ucomisd(a, b); 720 721 if (dst->encoding() != (min ? b : a)->encoding()) 722 __ jccb(Assembler::above, above); // CF=0 & ZF=0 723 else 724 __ jccb(Assembler::above, done); 725 726 __ jccb(Assembler::parity, nan); // PF=1 727 __ jccb(Assembler::below, below); // CF=1 728 729 // equal 730 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit); 731 if (single) { 732 __ ucomiss(a, xmmt); 733 __ jccb(Assembler::equal, zero); 734 735 __ movflt(dst, a); 736 __ jmp(done); 737 } 738 else { 739 __ ucomisd(a, xmmt); 740 __ jccb(Assembler::equal, zero); 741 742 __ movdbl(dst, a); 743 __ jmp(done); 744 } 745 746 __ bind(zero); 747 if (min) 748 __ vpor(dst, a, b, Assembler::AVX_128bit); 749 else 750 __ vpand(dst, a, b, Assembler::AVX_128bit); 751 752 __ jmp(done); 753 754 __ bind(above); 755 if (single) 756 __ movflt(dst, min ? b : a); 757 else 758 __ movdbl(dst, min ? b : a); 759 760 __ jmp(done); 761 762 __ bind(nan); 763 if (single) { 764 __ movl(rt, 0x7fc00000); // Float.NaN 765 __ movdl(dst, rt); 766 } 767 else { 768 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN 769 __ movdq(dst, rt); 770 } 771 __ jmp(done); 772 773 __ bind(below); 774 if (single) 775 __ movflt(dst, min ? a : b); 776 else 777 __ movdbl(dst, min ? a : b); 778 779 __ bind(done); 780} 781 782//============================================================================= 783const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; 784 785int Compile::ConstantTable::calculate_table_base_offset() const { 786 return 0; // absolute addressing, no offset 787} 788 789bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 790void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 791 ShouldNotReachHere(); 792} 793 794void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 795 // Empty encoding 796} 797 798uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 799 return 0; 800} 801 802#ifndef PRODUCT 803void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 804 st->print("# MachConstantBaseNode (empty encoding)"); 805} 806#endif 807 808 809//============================================================================= 810#ifndef PRODUCT 811void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 812 Compile* C = ra_->C; 813 814 int framesize = C->frame_size_in_bytes(); 815 int bangsize = C->bang_size_in_bytes(); 816 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 817 // Remove wordSize for return addr which is already pushed. 818 framesize -= wordSize; 819 820 if (C->need_stack_bang(bangsize)) { 821 framesize -= wordSize; 822 st->print("# stack bang (%d bytes)", bangsize); 823 st->print("\n\t"); 824 st->print("pushq rbp\t# Save rbp"); 825 if (PreserveFramePointer) { 826 st->print("\n\t"); 827 st->print("movq rbp, rsp\t# Save the caller's SP into rbp"); 828 } 829 if (framesize) { 830 st->print("\n\t"); 831 st->print("subq rsp, #%d\t# Create frame",framesize); 832 } 833 } else { 834 st->print("subq rsp, #%d\t# Create frame",framesize); 835 st->print("\n\t"); 836 framesize -= wordSize; 837 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize); 838 if (PreserveFramePointer) { 839 st->print("\n\t"); 840 st->print("movq rbp, rsp\t# Save the caller's SP into rbp"); 841 if (framesize > 0) { 842 st->print("\n\t"); 843 st->print("addq rbp, #%d", framesize); 844 } 845 } 846 } 847 848 if (VerifyStackAtCalls) { 849 st->print("\n\t"); 850 framesize -= wordSize; 851 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize); 852#ifdef ASSERT 853 st->print("\n\t"); 854 st->print("# stack alignment check"); 855#endif 856 } 857 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) { 858 st->print("\n\t"); 859 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t"); 860 st->print("\n\t"); 861 st->print("je fast_entry\t"); 862 st->print("\n\t"); 863 st->print("call #nmethod_entry_barrier_stub\t"); 864 st->print("\n\tfast_entry:"); 865 } 866 st->cr(); 867} 868#endif 869 870void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 871 Compile* C = ra_->C; 872 MacroAssembler _masm(&cbuf); 873 874 int framesize = C->frame_size_in_bytes(); 875 int bangsize = C->bang_size_in_bytes(); 876 877 if (C->clinit_barrier_on_entry()) { 878 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); 879 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started"); 880 881 Label L_skip_barrier; 882 Register klass = rscratch1; 883 884 __ mov_metadata(klass, C->method()->holder()->constant_encoding()); 885 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/); 886 887 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path 888 889 __ bind(L_skip_barrier); 890 } 891 892 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL); 893 894 C->set_frame_complete(cbuf.insts_size()); 895 896 if (C->has_mach_constant_base_node()) { 897 // NOTE: We set the table base offset here because users might be 898 // emitted before MachConstantBaseNode. 899 Compile::ConstantTable& constant_table = C->constant_table(); 900 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 901 } 902} 903 904uint MachPrologNode::size(PhaseRegAlloc* ra_) const 905{ 906 return MachNode::size(ra_); // too many variables; just compute it 907 // the hard way 908} 909 910int MachPrologNode::reloc() const 911{ 912 return 0; // a large enough number 913} 914 915//============================================================================= 916#ifndef PRODUCT 917void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const 918{ 919 Compile* C = ra_->C; 920 if (generate_vzeroupper(C)) { 921 st->print("vzeroupper"); 922 st->cr(); st->print("\t"); 923 } 924 925 int framesize = C->frame_size_in_bytes(); 926 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 927 // Remove word for return adr already pushed 928 // and RBP 929 framesize -= 2*wordSize; 930 931 if (framesize) { 932 st->print_cr("addq rsp, %d\t# Destroy frame", framesize); 933 st->print("\t"); 934 } 935 936 st->print_cr("popq rbp"); 937 if (do_polling() && C->is_method_compilation()) { 938 st->print("\t"); 939 if (SafepointMechanism::uses_thread_local_poll()) { 940 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t" 941 "testl rax, [rscratch1]\t" 942 "# Safepoint: poll for GC"); 943 } else if (Assembler::is_polling_page_far()) { 944 st->print_cr("movq rscratch1, #polling_page_address\n\t" 945 "testl rax, [rscratch1]\t" 946 "# Safepoint: poll for GC"); 947 } else { 948 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t" 949 "# Safepoint: poll for GC"); 950 } 951 } 952} 953#endif 954 955void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const 956{ 957 Compile* C = ra_->C; 958 MacroAssembler _masm(&cbuf); 959 960 if (generate_vzeroupper(C)) { 961 // Clear upper bits of YMM registers when current compiled code uses 962 // wide vectors to avoid AVX <-> SSE transition penalty during call. 963 __ vzeroupper(); 964 } 965 966 int framesize = C->frame_size_in_bytes(); 967 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 968 // Remove word for return adr already pushed 969 // and RBP 970 framesize -= 2*wordSize; 971 972 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here 973 974 if (framesize) { 975 emit_opcode(cbuf, Assembler::REX_W); 976 if (framesize < 0x80) { 977 emit_opcode(cbuf, 0x83); // addq rsp, #framesize 978 emit_rm(cbuf, 0x3, 0x00, RSP_enc); 979 emit_d8(cbuf, framesize); 980 } else { 981 emit_opcode(cbuf, 0x81); // addq rsp, #framesize 982 emit_rm(cbuf, 0x3, 0x00, RSP_enc); 983 emit_d32(cbuf, framesize); 984 } 985 } 986 987 // popq rbp 988 emit_opcode(cbuf, 0x58 | RBP_enc); 989 990 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 991 __ reserved_stack_check(); 992 } 993 994 if (do_polling() && C->is_method_compilation()) { 995 MacroAssembler _masm(&cbuf); 996 if (SafepointMechanism::uses_thread_local_poll()) { 997 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset())); 998 __ relocate(relocInfo::poll_return_type); 999 __ testl(rax, Address(rscratch1, 0)); 1000 } else { 1001 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 1002 if (Assembler::is_polling_page_far()) { 1003 __ lea(rscratch1, polling_page); 1004 __ relocate(relocInfo::poll_return_type); 1005 __ testl(rax, Address(rscratch1, 0)); 1006 } else { 1007 __ testl(rax, polling_page); 1008 } 1009 } 1010 } 1011} 1012 1013uint MachEpilogNode::size(PhaseRegAlloc* ra_) const 1014{ 1015 return MachNode::size(ra_); // too many variables; just compute it 1016 // the hard way 1017} 1018 1019int MachEpilogNode::reloc() const 1020{ 1021 return 2; // a large enough number 1022} 1023 1024const Pipeline* MachEpilogNode::pipeline() const 1025{ 1026 return MachNode::pipeline_class(); 1027} 1028 1029int MachEpilogNode::safepoint_offset() const 1030{ 1031 return 0; 1032} 1033 1034//============================================================================= 1035 1036enum RC { 1037 rc_bad, 1038 rc_int, 1039 rc_float, 1040 rc_stack 1041}; 1042 1043static enum RC rc_class(OptoReg::Name reg) 1044{ 1045 if( !OptoReg::is_valid(reg) ) return rc_bad; 1046 1047 if (OptoReg::is_stack(reg)) return rc_stack; 1048 1049 VMReg r = OptoReg::as_VMReg(reg); 1050 1051 if (r->is_Register()) return rc_int; 1052 1053 assert(r->is_XMMRegister(), "must be"); 1054 return rc_float; 1055} 1056 1057// Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. 1058static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 1059 int src_hi, int dst_hi, uint ireg, outputStream* st); 1060 1061int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, 1062 int stack_offset, int reg, uint ireg, outputStream* st); 1063 1064static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, 1065 int dst_offset, uint ireg, outputStream* st) { 1066 if (cbuf) { 1067 MacroAssembler _masm(cbuf); 1068 switch (ireg) { 1069 case Op_VecS: 1070 __ movq(Address(rsp, -8), rax); 1071 __ movl(rax, Address(rsp, src_offset)); 1072 __ movl(Address(rsp, dst_offset), rax); 1073 __ movq(rax, Address(rsp, -8)); 1074 break; 1075 case Op_VecD: 1076 __ pushq(Address(rsp, src_offset)); 1077 __ popq (Address(rsp, dst_offset)); 1078 break; 1079 case Op_VecX: 1080 __ pushq(Address(rsp, src_offset)); 1081 __ popq (Address(rsp, dst_offset)); 1082 __ pushq(Address(rsp, src_offset+8)); 1083 __ popq (Address(rsp, dst_offset+8)); 1084 break; 1085 case Op_VecY: 1086 __ vmovdqu(Address(rsp, -32), xmm0); 1087 __ vmovdqu(xmm0, Address(rsp, src_offset)); 1088 __ vmovdqu(Address(rsp, dst_offset), xmm0); 1089 __ vmovdqu(xmm0, Address(rsp, -32)); 1090 break; 1091 case Op_VecZ: 1092 __ evmovdquq(Address(rsp, -64), xmm0, 2); 1093 __ evmovdquq(xmm0, Address(rsp, src_offset), 2); 1094 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2); 1095 __ evmovdquq(xmm0, Address(rsp, -64), 2); 1096 break; 1097 default: 1098 ShouldNotReachHere(); 1099 } 1100#ifndef PRODUCT 1101 } else { 1102 switch (ireg) { 1103 case Op_VecS: 1104 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" 1105 "movl rax, [rsp + #%d]\n\t" 1106 "movl [rsp + #%d], rax\n\t" 1107 "movq rax, [rsp - #8]", 1108 src_offset, dst_offset); 1109 break; 1110 case Op_VecD: 1111 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" 1112 "popq [rsp + #%d]", 1113 src_offset, dst_offset); 1114 break; 1115 case Op_VecX: 1116 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t" 1117 "popq [rsp + #%d]\n\t" 1118 "pushq [rsp + #%d]\n\t" 1119 "popq [rsp + #%d]", 1120 src_offset, dst_offset, src_offset+8, dst_offset+8); 1121 break; 1122 case Op_VecY: 1123 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" 1124 "vmovdqu xmm0, [rsp + #%d]\n\t" 1125 "vmovdqu [rsp + #%d], xmm0\n\t" 1126 "vmovdqu xmm0, [rsp - #32]", 1127 src_offset, dst_offset); 1128 break; 1129 case Op_VecZ: 1130 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t" 1131 "vmovdqu xmm0, [rsp + #%d]\n\t" 1132 "vmovdqu [rsp + #%d], xmm0\n\t" 1133 "vmovdqu xmm0, [rsp - #64]", 1134 src_offset, dst_offset); 1135 break; 1136 default: 1137 ShouldNotReachHere(); 1138 } 1139#endif 1140 } 1141} 1142 1143uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, 1144 PhaseRegAlloc* ra_, 1145 bool do_size, 1146 outputStream* st) const { 1147 assert(cbuf != NULL || st != NULL, "sanity"); 1148 // Get registers to move 1149 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1150 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1151 OptoReg::Name dst_second = ra_->get_reg_second(this); 1152 OptoReg::Name dst_first = ra_->get_reg_first(this); 1153 1154 enum RC src_second_rc = rc_class(src_second); 1155 enum RC src_first_rc = rc_class(src_first); 1156 enum RC dst_second_rc = rc_class(dst_second); 1157 enum RC dst_first_rc = rc_class(dst_first); 1158 1159 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), 1160 "must move at least 1 register" ); 1161 1162 if (src_first == dst_first && src_second == dst_second) { 1163 // Self copy, no move 1164 return 0; 1165 } 1166 if (bottom_type()->isa_vect() != NULL) { 1167 uint ireg = ideal_reg(); 1168 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); 1169 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity"); 1170 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1171 // mem -> mem 1172 int src_offset = ra_->reg2offset(src_first); 1173 int dst_offset = ra_->reg2offset(dst_first); 1174 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st); 1175 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) { 1176 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st); 1177 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1178 int stack_offset = ra_->reg2offset(dst_first); 1179 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st); 1180 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) { 1181 int stack_offset = ra_->reg2offset(src_first); 1182 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st); 1183 } else { 1184 ShouldNotReachHere(); 1185 } 1186 return 0; 1187 } 1188 if (src_first_rc == rc_stack) { 1189 // mem -> 1190 if (dst_first_rc == rc_stack) { 1191 // mem -> mem 1192 assert(src_second != dst_first, "overlap"); 1193 if ((src_first & 1) == 0 && src_first + 1 == src_second && 1194 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1195 // 64-bit 1196 int src_offset = ra_->reg2offset(src_first); 1197 int dst_offset = ra_->reg2offset(dst_first); 1198 if (cbuf) { 1199 MacroAssembler _masm(cbuf); 1200 __ pushq(Address(rsp, src_offset)); 1201 __ popq (Address(rsp, dst_offset)); 1202#ifndef PRODUCT 1203 } else { 1204 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" 1205 "popq [rsp + #%d]", 1206 src_offset, dst_offset); 1207#endif 1208 } 1209 } else { 1210 // 32-bit 1211 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); 1212 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); 1213 // No pushl/popl, so: 1214 int src_offset = ra_->reg2offset(src_first); 1215 int dst_offset = ra_->reg2offset(dst_first); 1216 if (cbuf) { 1217 MacroAssembler _masm(cbuf); 1218 __ movq(Address(rsp, -8), rax); 1219 __ movl(rax, Address(rsp, src_offset)); 1220 __ movl(Address(rsp, dst_offset), rax); 1221 __ movq(rax, Address(rsp, -8)); 1222#ifndef PRODUCT 1223 } else { 1224 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" 1225 "movl rax, [rsp + #%d]\n\t" 1226 "movl [rsp + #%d], rax\n\t" 1227 "movq rax, [rsp - #8]", 1228 src_offset, dst_offset); 1229#endif 1230 } 1231 } 1232 return 0; 1233 } else if (dst_first_rc == rc_int) { 1234 // mem -> gpr 1235 if ((src_first & 1) == 0 && src_first + 1 == src_second && 1236 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1237 // 64-bit 1238 int offset = ra_->reg2offset(src_first); 1239 if (cbuf) { 1240 MacroAssembler _masm(cbuf); 1241 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); 1242#ifndef PRODUCT 1243 } else { 1244 st->print("movq %s, [rsp + #%d]\t# spill", 1245 Matcher::regName[dst_first], 1246 offset); 1247#endif 1248 } 1249 } else { 1250 // 32-bit 1251 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); 1252 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); 1253 int offset = ra_->reg2offset(src_first); 1254 if (cbuf) { 1255 MacroAssembler _masm(cbuf); 1256 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); 1257#ifndef PRODUCT 1258 } else { 1259 st->print("movl %s, [rsp + #%d]\t# spill", 1260 Matcher::regName[dst_first], 1261 offset); 1262#endif 1263 } 1264 } 1265 return 0; 1266 } else if (dst_first_rc == rc_float) { 1267 // mem-> xmm 1268 if ((src_first & 1) == 0 && src_first + 1 == src_second && 1269 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1270 // 64-bit 1271 int offset = ra_->reg2offset(src_first); 1272 if (cbuf) { 1273 MacroAssembler _masm(cbuf); 1274 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); 1275#ifndef PRODUCT 1276 } else { 1277 st->print("%s %s, [rsp + #%d]\t# spill", 1278 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", 1279 Matcher::regName[dst_first], 1280 offset); 1281#endif 1282 } 1283 } else { 1284 // 32-bit 1285 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); 1286 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); 1287 int offset = ra_->reg2offset(src_first); 1288 if (cbuf) { 1289 MacroAssembler _masm(cbuf); 1290 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); 1291#ifndef PRODUCT 1292 } else { 1293 st->print("movss %s, [rsp + #%d]\t# spill", 1294 Matcher::regName[dst_first], 1295 offset); 1296#endif 1297 } 1298 } 1299 return 0; 1300 } 1301 } else if (src_first_rc == rc_int) { 1302 // gpr -> 1303 if (dst_first_rc == rc_stack) { 1304 // gpr -> mem 1305 if ((src_first & 1) == 0 && src_first + 1 == src_second && 1306 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1307 // 64-bit 1308 int offset = ra_->reg2offset(dst_first); 1309 if (cbuf) { 1310 MacroAssembler _masm(cbuf); 1311 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); 1312#ifndef PRODUCT 1313 } else { 1314 st->print("movq [rsp + #%d], %s\t# spill", 1315 offset, 1316 Matcher::regName[src_first]); 1317#endif 1318 } 1319 } else { 1320 // 32-bit 1321 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); 1322 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); 1323 int offset = ra_->reg2offset(dst_first); 1324 if (cbuf) { 1325 MacroAssembler _masm(cbuf); 1326 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); 1327#ifndef PRODUCT 1328 } else { 1329 st->print("movl [rsp + #%d], %s\t# spill", 1330 offset, 1331 Matcher::regName[src_first]); 1332#endif 1333 } 1334 } 1335 return 0; 1336 } else if (dst_first_rc == rc_int) { 1337 // gpr -> gpr 1338 if ((src_first & 1) == 0 && src_first + 1 == src_second && 1339 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1340 // 64-bit 1341 if (cbuf) { 1342 MacroAssembler _masm(cbuf); 1343 __ movq(as_Register(Matcher::_regEncode[dst_first]), 1344 as_Register(Matcher::_regEncode[src_first])); 1345#ifndef PRODUCT 1346 } else { 1347 st->print("movq %s, %s\t# spill", 1348 Matcher::regName[dst_first], 1349 Matcher::regName[src_first]); 1350#endif 1351 } 1352 return 0; 1353 } else { 1354 // 32-bit 1355 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); 1356 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); 1357 if (cbuf) { 1358 MacroAssembler _masm(cbuf); 1359 __ movl(as_Register(Matcher::_regEncode[dst_first]), 1360 as_Register(Matcher::_regEncode[src_first])); 1361#ifndef PRODUCT 1362 } else { 1363 st->print("movl %s, %s\t# spill", 1364 Matcher::regName[dst_first], 1365 Matcher::regName[src_first]); 1366#endif 1367 } 1368 return 0; 1369 } 1370 } else if (dst_first_rc == rc_float) { 1371 // gpr -> xmm 1372 if ((src_first & 1) == 0 && src_first + 1 == src_second && 1373 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1374 // 64-bit 1375 if (cbuf) { 1376 MacroAssembler _masm(cbuf); 1377 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); 1378#ifndef PRODUCT 1379 } else { 1380 st->print("movdq %s, %s\t# spill", 1381 Matcher::regName[dst_first], 1382 Matcher::regName[src_first]); 1383#endif 1384 } 1385 } else { 1386 // 32-bit 1387 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); 1388 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); 1389 if (cbuf) { 1390 MacroAssembler _masm(cbuf); 1391 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); 1392#ifndef PRODUCT 1393 } else { 1394 st->print("movdl %s, %s\t# spill", 1395 Matcher::regName[dst_first], 1396 Matcher::regName[src_first]); 1397#endif 1398 } 1399 } 1400 return 0; 1401 } 1402 } else if (src_first_rc == rc_float) { 1403 // xmm -> 1404 if (dst_first_rc == rc_stack) { 1405 // xmm -> mem 1406 if ((src_first & 1) == 0 && src_first + 1 == src_second && 1407 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1408 // 64-bit 1409 int offset = ra_->reg2offset(dst_first); 1410 if (cbuf) { 1411 MacroAssembler _masm(cbuf); 1412 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); 1413#ifndef PRODUCT 1414 } else { 1415 st->print("movsd [rsp + #%d], %s\t# spill", 1416 offset, 1417 Matcher::regName[src_first]); 1418#endif 1419 } 1420 } else { 1421 // 32-bit 1422 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); 1423 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); 1424 int offset = ra_->reg2offset(dst_first); 1425 if (cbuf) { 1426 MacroAssembler _masm(cbuf); 1427 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); 1428#ifndef PRODUCT 1429 } else { 1430 st->print("movss [rsp + #%d], %s\t# spill", 1431 offset, 1432 Matcher::regName[src_first]); 1433#endif 1434 } 1435 } 1436 return 0; 1437 } else if (dst_first_rc == rc_int) { 1438 // xmm -> gpr 1439 if ((src_first & 1) == 0 && src_first + 1 == src_second && 1440 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1441 // 64-bit 1442 if (cbuf) { 1443 MacroAssembler _masm(cbuf); 1444 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); 1445#ifndef PRODUCT 1446 } else { 1447 st->print("movdq %s, %s\t# spill", 1448 Matcher::regName[dst_first], 1449 Matcher::regName[src_first]); 1450#endif 1451 } 1452 } else { 1453 // 32-bit 1454 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); 1455 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); 1456 if (cbuf) { 1457 MacroAssembler _masm(cbuf); 1458 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); 1459#ifndef PRODUCT 1460 } else { 1461 st->print("movdl %s, %s\t# spill", 1462 Matcher::regName[dst_first], 1463 Matcher::regName[src_first]); 1464#endif 1465 } 1466 } 1467 return 0; 1468 } else if (dst_first_rc == rc_float) { 1469 // xmm -> xmm 1470 if ((src_first & 1) == 0 && src_first + 1 == src_second && 1471 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1472 // 64-bit 1473 if (cbuf) { 1474 MacroAssembler _masm(cbuf); 1475 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); 1476#ifndef PRODUCT 1477 } else { 1478 st->print("%s %s, %s\t# spill", 1479 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", 1480 Matcher::regName[dst_first], 1481 Matcher::regName[src_first]); 1482#endif 1483 } 1484 } else { 1485 // 32-bit 1486 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); 1487 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); 1488 if (cbuf) { 1489 MacroAssembler _masm(cbuf); 1490 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); 1491#ifndef PRODUCT 1492 } else { 1493 st->print("%s %s, %s\t# spill", 1494 UseXmmRegToRegMoveAll ? "movaps" : "movss ", 1495 Matcher::regName[dst_first], 1496 Matcher::regName[src_first]); 1497#endif 1498 } 1499 } 1500 return 0; 1501 } 1502 } 1503 1504 assert(0," foo "); 1505 Unimplemented(); 1506 return 0; 1507} 1508 1509#ifndef PRODUCT 1510void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { 1511 implementation(NULL, ra_, false, st); 1512} 1513#endif 1514 1515void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1516 implementation(&cbuf, ra_, false, NULL); 1517} 1518 1519uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1520 return MachNode::size(ra_); 1521} 1522 1523//============================================================================= 1524#ifndef PRODUCT 1525void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const 1526{ 1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1528 int reg = ra_->get_reg_first(this); 1529 st->print("leaq %s, [rsp + #%d]\t# box lock", 1530 Matcher::regName[reg], offset); 1531} 1532#endif 1533 1534void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const 1535{ 1536 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1537 int reg = ra_->get_encode(this); 1538 if (offset >= 0x80) { 1539 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); 1540 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1541 emit_rm(cbuf, 0x2, reg & 7, 0x04); 1542 emit_rm(cbuf, 0x0, 0x04, RSP_enc); 1543 emit_d32(cbuf, offset); 1544 } else { 1545 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); 1546 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1547 emit_rm(cbuf, 0x1, reg & 7, 0x04); 1548 emit_rm(cbuf, 0x0, 0x04, RSP_enc); 1549 emit_d8(cbuf, offset); 1550 } 1551} 1552 1553uint BoxLockNode::size(PhaseRegAlloc *ra_) const 1554{ 1555 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1556 return (offset < 0x80) ? 5 : 8; // REX 1557} 1558 1559//============================================================================= 1560#ifndef PRODUCT 1561void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const 1562{ 1563 if (UseCompressedClassPointers) { 1564 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); 1565 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); 1566 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); 1567 } else { 1568 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" 1569 "# Inline cache check"); 1570 } 1571 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); 1572 st->print_cr("\tnop\t# nops to align entry point"); 1573} 1574#endif 1575 1576void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const 1577{ 1578 MacroAssembler masm(&cbuf); 1579 uint insts_size = cbuf.insts_size(); 1580 if (UseCompressedClassPointers) { 1581 masm.load_klass(rscratch1, j_rarg0); 1582 masm.cmpptr(rax, rscratch1); 1583 } else { 1584 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); 1585 } 1586 1587 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 1588 1589 /* WARNING these NOPs are critical so that verified entry point is properly 1590 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ 1591 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); 1592 if (OptoBreakpoint) { 1593 // Leave space for int3 1594 nops_cnt -= 1; 1595 } 1596 nops_cnt &= 0x3; // Do not add nops if code is aligned. 1597 if (nops_cnt > 0) 1598 masm.nop(nops_cnt); 1599} 1600 1601uint MachUEPNode::size(PhaseRegAlloc* ra_) const 1602{ 1603 return MachNode::size(ra_); // too many variables; just compute it 1604 // the hard way 1605} 1606 1607 1608//============================================================================= 1609 1610int Matcher::regnum_to_fpu_offset(int regnum) 1611{ 1612 return regnum - 32; // The FP registers are in the second chunk 1613} 1614 1615// This is UltraSparc specific, true just means we have fast l2f conversion 1616const bool Matcher::convL2FSupported(void) { 1617 return true; 1618} 1619 1620// Is this branch offset short enough that a short branch can be used? 1621// 1622// NOTE: If the platform does not provide any short branch variants, then 1623// this method should return false for offset 0. 1624bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1625 // The passed offset is relative to address of the branch. 1626 // On 86 a branch displacement is calculated relative to address 1627 // of a next instruction. 1628 offset -= br_size; 1629 1630 // the short version of jmpConUCF2 contains multiple branches, 1631 // making the reach slightly less 1632 if (rule == jmpConUCF2_rule) 1633 return (-126 <= offset && offset <= 125); 1634 return (-128 <= offset && offset <= 127); 1635} 1636 1637const bool Matcher::isSimpleConstant64(jlong value) { 1638 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1639 //return value == (int) value; // Cf. storeImmL and immL32. 1640 1641 // Probably always true, even if a temp register is required. 1642 return true; 1643} 1644 1645// The ecx parameter to rep stosq for the ClearArray node is in words. 1646const bool Matcher::init_array_count_is_in_bytes = false; 1647 1648// No additional cost for CMOVL. 1649const int Matcher::long_cmove_cost() { return 0; } 1650 1651// No CMOVF/CMOVD with SSE2 1652const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 1653 1654// Does the CPU require late expand (see block.cpp for description of late expand)? 1655const bool Matcher::require_postalloc_expand = false; 1656 1657// Do we need to mask the count passed to shift instructions or does 1658// the cpu only look at the lower 5/6 bits anyway? 1659const bool Matcher::need_masked_shift_count = false; 1660 1661bool Matcher::narrow_oop_use_complex_address() { 1662 assert(UseCompressedOops, "only for compressed oops code"); 1663 return (LogMinObjAlignmentInBytes <= 3); 1664} 1665 1666bool Matcher::narrow_klass_use_complex_address() { 1667 assert(UseCompressedClassPointers, "only for compressed klass code"); 1668 return (LogKlassAlignmentInBytes <= 3); 1669} 1670 1671bool Matcher::const_oop_prefer_decode() { 1672 // Prefer ConN+DecodeN over ConP. 1673 return true; 1674} 1675 1676bool Matcher::const_klass_prefer_decode() { 1677 // TODO: Either support matching DecodeNKlass (heap-based) in operand 1678 // or condisider the following: 1679 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. 1680 //return CompressedKlassPointers::base() == NULL; 1681 return true; 1682} 1683 1684// Is it better to copy float constants, or load them directly from 1685// memory? Intel can load a float constant from a direct address, 1686// requiring no extra registers. Most RISCs will have to materialize 1687// an address into a register first, so they would do better to copy 1688// the constant from stack. 1689const bool Matcher::rematerialize_float_constants = true; // XXX 1690 1691// If CPU can load and store mis-aligned doubles directly then no 1692// fixup is needed. Else we split the double into 2 integer pieces 1693// and move it piece-by-piece. Only happens when passing doubles into 1694// C code as the Java calling convention forces doubles to be aligned. 1695const bool Matcher::misaligned_doubles_ok = true; 1696 1697// No-op on amd64 1698void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} 1699 1700// Advertise here if the CPU requires explicit rounding operations to 1701// implement the UseStrictFP mode. 1702const bool Matcher::strict_fp_requires_explicit_rounding = true; 1703 1704// Are floats conerted to double when stored to stack during deoptimization? 1705// On x64 it is stored without convertion so we can use normal access. 1706bool Matcher::float_in_double() { return false; } 1707 1708// Do ints take an entire long register or just half? 1709const bool Matcher::int_in_long = true; 1710 1711// Return whether or not this register is ever used as an argument. 1712// This function is used on startup to build the trampoline stubs in 1713// generateOptoStub. Registers not mentioned will be killed by the VM 1714// call in the trampoline, and arguments in those registers not be 1715// available to the callee. 1716bool Matcher::can_be_java_arg(int reg) 1717{ 1718 return 1719 reg == RDI_num || reg == RDI_H_num || 1720 reg == RSI_num || reg == RSI_H_num || 1721 reg == RDX_num || reg == RDX_H_num || 1722 reg == RCX_num || reg == RCX_H_num || 1723 reg == R8_num || reg == R8_H_num || 1724 reg == R9_num || reg == R9_H_num || 1725 reg == R12_num || reg == R12_H_num || 1726 reg == XMM0_num || reg == XMM0b_num || 1727 reg == XMM1_num || reg == XMM1b_num || 1728 reg == XMM2_num || reg == XMM2b_num || 1729 reg == XMM3_num || reg == XMM3b_num || 1730 reg == XMM4_num || reg == XMM4b_num || 1731 reg == XMM5_num || reg == XMM5b_num || 1732 reg == XMM6_num || reg == XMM6b_num || 1733 reg == XMM7_num || reg == XMM7b_num; 1734} 1735 1736bool Matcher::is_spillable_arg(int reg) 1737{ 1738 return can_be_java_arg(reg); 1739} 1740 1741bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 1742 // In 64 bit mode a code which use multiply when 1743 // devisor is constant is faster than hardware 1744 // DIV instruction (it uses MulHiL). 1745 return false; 1746} 1747 1748// Register for DIVI projection of divmodI 1749RegMask Matcher::divI_proj_mask() { 1750 return INT_RAX_REG_mask(); 1751} 1752 1753// Register for MODI projection of divmodI 1754RegMask Matcher::modI_proj_mask() { 1755 return INT_RDX_REG_mask(); 1756} 1757 1758// Register for DIVL projection of divmodL 1759RegMask Matcher::divL_proj_mask() { 1760 return LONG_RAX_REG_mask(); 1761} 1762 1763// Register for MODL projection of divmodL 1764RegMask Matcher::modL_proj_mask() { 1765 return LONG_RDX_REG_mask(); 1766} 1767 1768// Register for saving SP into on method handle invokes. Not used on x86_64. 1769const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1770 return NO_REG_mask(); 1771} 1772 1773%} 1774 1775//----------ENCODING BLOCK----------------------------------------------------- 1776// This block specifies the encoding classes used by the compiler to 1777// output byte streams. Encoding classes are parameterized macros 1778// used by Machine Instruction Nodes in order to generate the bit 1779// encoding of the instruction. Operands specify their base encoding 1780// interface with the interface keyword. There are currently 1781// supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & 1782// COND_INTER. REG_INTER causes an operand to generate a function 1783// which returns its register number when queried. CONST_INTER causes 1784// an operand to generate a function which returns the value of the 1785// constant when queried. MEMORY_INTER causes an operand to generate 1786// four functions which return the Base Register, the Index Register, 1787// the Scale Value, and the Offset Value of the operand when queried. 1788// COND_INTER causes an operand to generate six functions which return 1789// the encoding code (ie - encoding bits for the instruction) 1790// associated with each basic boolean condition for a conditional 1791// instruction. 1792// 1793// Instructions specify two basic values for encoding. Again, a 1794// function is available to check if the constant displacement is an 1795// oop. They use the ins_encode keyword to specify their encoding 1796// classes (which must be a sequence of enc_class names, and their 1797// parameters, specified in the encoding block), and they use the 1798// opcode keyword to specify, in order, their primary, secondary, and 1799// tertiary opcode. Only the opcode sections which a particular 1800// instruction needs for encoding need to be specified. 1801encode %{ 1802 // Build emit functions for each basic byte or larger field in the 1803 // intel encoding scheme (opcode, rm, sib, immediate), and call them 1804 // from C++ code in the enc_class source block. Emit functions will 1805 // live in the main source block for now. In future, we can 1806 // generalize this by adding a syntax that specifies the sizes of 1807 // fields in an order, so that the adlc can build the emit functions 1808 // automagically 1809 1810 // Emit primary opcode 1811 enc_class OpcP 1812 %{ 1813 emit_opcode(cbuf, $primary); 1814 %} 1815 1816 // Emit secondary opcode 1817 enc_class OpcS 1818 %{ 1819 emit_opcode(cbuf, $secondary); 1820 %} 1821 1822 // Emit tertiary opcode 1823 enc_class OpcT 1824 %{ 1825 emit_opcode(cbuf, $tertiary); 1826 %} 1827 1828 // Emit opcode directly 1829 enc_class Opcode(immI d8) 1830 %{ 1831 emit_opcode(cbuf, $d8$$constant); 1832 %} 1833 1834 // Emit size prefix 1835 enc_class SizePrefix 1836 %{ 1837 emit_opcode(cbuf, 0x66); 1838 %} 1839 1840 enc_class reg(rRegI reg) 1841 %{ 1842 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); 1843 %} 1844 1845 enc_class reg_reg(rRegI dst, rRegI src) 1846 %{ 1847 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); 1848 %} 1849 1850 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) 1851 %{ 1852 emit_opcode(cbuf, $opcode$$constant); 1853 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); 1854 %} 1855 1856 enc_class cdql_enc(no_rax_rdx_RegI div) 1857 %{ 1858 // Full implementation of Java idiv and irem; checks for 1859 // special case as described in JVM spec., p.243 & p.271. 1860 // 1861 // normal case special case 1862 // 1863 // input : rax: dividend min_int 1864 // reg: divisor -1 1865 // 1866 // output: rax: quotient (= rax idiv reg) min_int 1867 // rdx: remainder (= rax irem reg) 0 1868 // 1869 // Code sequnce: 1870 // 1871 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax 1872 // 5: 75 07/08 jne e <normal> 1873 // 7: 33 d2 xor %edx,%edx 1874 // [div >= 8 -> offset + 1] 1875 // [REX_B] 1876 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div 1877 // c: 74 03/04 je 11 <done> 1878 // 000000000000000e <normal>: 1879 // e: 99 cltd 1880 // [div >= 8 -> offset + 1] 1881 // [REX_B] 1882 // f: f7 f9 idiv $div 1883 // 0000000000000011 <done>: 1884 1885 // cmp $0x80000000,%eax 1886 emit_opcode(cbuf, 0x3d); 1887 emit_d8(cbuf, 0x00); 1888 emit_d8(cbuf, 0x00); 1889 emit_d8(cbuf, 0x00); 1890 emit_d8(cbuf, 0x80); 1891 1892 // jne e <normal> 1893 emit_opcode(cbuf, 0x75); 1894 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); 1895 1896 // xor %edx,%edx 1897 emit_opcode(cbuf, 0x33); 1898 emit_d8(cbuf, 0xD2); 1899 1900 // cmp $0xffffffffffffffff,%ecx 1901 if ($div$$reg >= 8) { 1902 emit_opcode(cbuf, Assembler::REX_B); 1903 } 1904 emit_opcode(cbuf, 0x83); 1905 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); 1906 emit_d8(cbuf, 0xFF); 1907 1908 // je 11 <done> 1909 emit_opcode(cbuf, 0x74); 1910 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); 1911 1912 // <normal> 1913 // cltd 1914 emit_opcode(cbuf, 0x99); 1915 1916 // idivl (note: must be emitted by the user of this rule) 1917 // <done> 1918 %} 1919 1920 enc_class cdqq_enc(no_rax_rdx_RegL div) 1921 %{ 1922 // Full implementation of Java ldiv and lrem; checks for 1923 // special case as described in JVM spec., p.243 & p.271. 1924 // 1925 // normal case special case 1926 // 1927 // input : rax: dividend min_long 1928 // reg: divisor -1 1929 // 1930 // output: rax: quotient (= rax idiv reg) min_long 1931 // rdx: remainder (= rax irem reg) 0 1932 // 1933 // Code sequnce: 1934 // 1935 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx 1936 // 7: 00 00 80 1937 // a: 48 39 d0 cmp %rdx,%rax 1938 // d: 75 08 jne 17 <normal> 1939 // f: 33 d2 xor %edx,%edx 1940 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div 1941 // 15: 74 05 je 1c <done> 1942 // 0000000000000017 <normal>: 1943 // 17: 48 99 cqto 1944 // 19: 48 f7 f9 idiv $div 1945 // 000000000000001c <done>: 1946 1947 // mov $0x8000000000000000,%rdx 1948 emit_opcode(cbuf, Assembler::REX_W); 1949 emit_opcode(cbuf, 0xBA); 1950 emit_d8(cbuf, 0x00); 1951 emit_d8(cbuf, 0x00); 1952 emit_d8(cbuf, 0x00); 1953 emit_d8(cbuf, 0x00); 1954 emit_d8(cbuf, 0x00); 1955 emit_d8(cbuf, 0x00); 1956 emit_d8(cbuf, 0x00); 1957 emit_d8(cbuf, 0x80); 1958 1959 // cmp %rdx,%rax 1960 emit_opcode(cbuf, Assembler::REX_W); 1961 emit_opcode(cbuf, 0x39); 1962 emit_d8(cbuf, 0xD0); 1963 1964 // jne 17 <normal> 1965 emit_opcode(cbuf, 0x75); 1966 emit_d8(cbuf, 0x08); 1967 1968 // xor %edx,%edx 1969 emit_opcode(cbuf, 0x33); 1970 emit_d8(cbuf, 0xD2); 1971 1972 // cmp $0xffffffffffffffff,$div 1973 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); 1974 emit_opcode(cbuf, 0x83); 1975 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); 1976 emit_d8(cbuf, 0xFF); 1977 1978 // je 1e <done> 1979 emit_opcode(cbuf, 0x74); 1980 emit_d8(cbuf, 0x05); 1981 1982 // <normal> 1983 // cqto 1984 emit_opcode(cbuf, Assembler::REX_W); 1985 emit_opcode(cbuf, 0x99); 1986 1987 // idivq (note: must be emitted by the user of this rule) 1988 // <done> 1989 %} 1990 1991 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension 1992 enc_class OpcSE(immI imm) 1993 %{ 1994 // Emit primary opcode and set sign-extend bit 1995 // Check for 8-bit immediate, and set sign extend bit in opcode 1996 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { 1997 emit_opcode(cbuf, $primary | 0x02); 1998 } else { 1999 // 32-bit immediate 2000 emit_opcode(cbuf, $primary); 2001 } 2002 %} 2003 2004 enc_class OpcSErm(rRegI dst, immI imm) 2005 %{ 2006 // OpcSEr/m 2007 int dstenc = $dst$$reg; 2008 if (dstenc >= 8) { 2009 emit_opcode(cbuf, Assembler::REX_B); 2010 dstenc -= 8; 2011 } 2012 // Emit primary opcode and set sign-extend bit 2013 // Check for 8-bit immediate, and set sign extend bit in opcode 2014 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { 2015 emit_opcode(cbuf, $primary | 0x02); 2016 } else { 2017 // 32-bit immediate 2018 emit_opcode(cbuf, $primary); 2019 } 2020 // Emit r/m byte with secondary opcode, after primary opcode. 2021 emit_rm(cbuf, 0x3, $secondary, dstenc); 2022 %} 2023 2024 enc_class OpcSErm_wide(rRegL dst, immI imm) 2025 %{ 2026 // OpcSEr/m 2027 int dstenc = $dst$$reg; 2028 if (dstenc < 8) { 2029 emit_opcode(cbuf, Assembler::REX_W); 2030 } else { 2031 emit_opcode(cbuf, Assembler::REX_WB); 2032 dstenc -= 8; 2033 } 2034 // Emit primary opcode and set sign-extend bit 2035 // Check for 8-bit immediate, and set sign extend bit in opcode 2036 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { 2037 emit_opcode(cbuf, $primary | 0x02); 2038 } else { 2039 // 32-bit immediate 2040 emit_opcode(cbuf, $primary); 2041 } 2042 // Emit r/m byte with secondary opcode, after primary opcode. 2043 emit_rm(cbuf, 0x3, $secondary, dstenc); 2044 %} 2045 2046 enc_class Con8or32(immI imm) 2047 %{ 2048 // Check for 8-bit immediate, and set sign extend bit in opcode 2049 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { 2050 $$$emit8$imm$$constant; 2051 } else { 2052 // 32-bit immediate 2053 $$$emit32$imm$$constant; 2054 } 2055 %} 2056 2057 enc_class opc2_reg(rRegI dst) 2058 %{ 2059 // BSWAP 2060 emit_cc(cbuf, $secondary, $dst$$reg); 2061 %} 2062 2063 enc_class opc3_reg(rRegI dst) 2064 %{ 2065 // BSWAP 2066 emit_cc(cbuf, $tertiary, $dst$$reg); 2067 %} 2068 2069 enc_class reg_opc(rRegI div) 2070 %{ 2071 // INC, DEC, IDIV, IMOD, JMP indirect, ... 2072 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); 2073 %} 2074 2075 enc_class enc_cmov(cmpOp cop) 2076 %{ 2077 // CMOV 2078 $$$emit8$primary; 2079 emit_cc(cbuf, $secondary, $cop$$cmpcode); 2080 %} 2081 2082 enc_class enc_PartialSubtypeCheck() 2083 %{ 2084 Register Rrdi = as_Register(RDI_enc); // result register 2085 Register Rrax = as_Register(RAX_enc); // super class 2086 Register Rrcx = as_Register(RCX_enc); // killed 2087 Register Rrsi = as_Register(RSI_enc); // sub class 2088 Label miss; 2089 const bool set_cond_codes = true; 2090 2091 MacroAssembler _masm(&cbuf); 2092 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, 2093 NULL, &miss, 2094 /*set_cond_codes:*/ true); 2095 if ($primary) { 2096 __ xorptr(Rrdi, Rrdi); 2097 } 2098 __ bind(miss); 2099 %} 2100 2101 enc_class clear_avx %{ 2102 debug_only(int off0 = cbuf.insts_size()); 2103 if (generate_vzeroupper(Compile::current())) { 2104 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty 2105 // Clear upper bits of YMM registers when current compiled code uses 2106 // wide vectors to avoid AVX <-> SSE transition penalty during call. 2107 MacroAssembler _masm(&cbuf); 2108 __ vzeroupper(); 2109 } 2110 debug_only(int off1 = cbuf.insts_size()); 2111 assert(off1 - off0 == clear_avx_size(), "correct size prediction"); 2112 %} 2113 2114 enc_class Java_To_Runtime(method meth) %{ 2115 // No relocation needed 2116 MacroAssembler _masm(&cbuf); 2117 __ mov64(r10, (int64_t) $meth$$method); 2118 __ call(r10); 2119 %} 2120 2121 enc_class Java_To_Interpreter(method meth) 2122 %{ 2123 // CALL Java_To_Interpreter 2124 // This is the instruction starting address for relocation info. 2125 cbuf.set_insts_mark(); 2126 $$$emit8$primary; 2127 // CALL directly to the runtime 2128 emit_d32_reloc(cbuf, 2129 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), 2130 runtime_call_Relocation::spec(), 2131 RELOC_DISP32); 2132 %} 2133 2134 enc_class Java_Static_Call(method meth) 2135 %{ 2136 // JAVA STATIC CALL 2137 // CALL to fixup routine. Fixup routine uses ScopeDesc info to 2138 // determine who we intended to call. 2139 cbuf.set_insts_mark(); 2140 $$$emit8$primary; 2141 2142 if (!_method) { 2143 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), 2144 runtime_call_Relocation::spec(), 2145 RELOC_DISP32); 2146 } else { 2147 int method_index = resolved_method_index(cbuf); 2148 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) 2149 : static_call_Relocation::spec(method_index); 2150 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), 2151 rspec, RELOC_DISP32); 2152 // Emit stubs for static call. 2153 address mark = cbuf.insts_mark(); 2154 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark); 2155 if (stub == NULL) { 2156 ciEnv::current()->record_failure("CodeCache is full"); 2157 return; 2158 } 2159#if INCLUDE_AOT 2160 CompiledStaticCall::emit_to_aot_stub(cbuf, mark); 2161#endif 2162 } 2163 %} 2164 2165 enc_class Java_Dynamic_Call(method meth) %{ 2166 MacroAssembler _masm(&cbuf); 2167 __ ic_call((address)$meth$$method, resolved_method_index(cbuf)); 2168 %} 2169 2170 enc_class Java_Compiled_Call(method meth) 2171 %{ 2172 // JAVA COMPILED CALL 2173 int disp = in_bytes(Method:: from_compiled_offset()); 2174 2175 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! 2176 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); 2177 2178 // callq *disp(%rax) 2179 cbuf.set_insts_mark(); 2180 $$$emit8$primary; 2181 if (disp < 0x80) { 2182 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte 2183 emit_d8(cbuf, disp); // Displacement 2184 } else { 2185 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte 2186 emit_d32(cbuf, disp); // Displacement 2187 } 2188 %} 2189 2190 enc_class reg_opc_imm(rRegI dst, immI8 shift) 2191 %{ 2192 // SAL, SAR, SHR 2193 int dstenc = $dst$$reg; 2194 if (dstenc >= 8) { 2195 emit_opcode(cbuf, Assembler::REX_B); 2196 dstenc -= 8; 2197 } 2198 $$$emit8$primary; 2199 emit_rm(cbuf, 0x3, $secondary, dstenc); 2200 $$$emit8$shift$$constant; 2201 %} 2202 2203 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) 2204 %{ 2205 // SAL, SAR, SHR 2206 int dstenc = $dst$$reg; 2207 if (dstenc < 8) { 2208 emit_opcode(cbuf, Assembler::REX_W); 2209 } else { 2210 emit_opcode(cbuf, Assembler::REX_WB); 2211 dstenc -= 8; 2212 } 2213 $$$emit8$primary; 2214 emit_rm(cbuf, 0x3, $secondary, dstenc); 2215 $$$emit8$shift$$constant; 2216 %} 2217 2218 enc_class load_immI(rRegI dst, immI src) 2219 %{ 2220 int dstenc = $dst$$reg; 2221 if (dstenc >= 8) { 2222 emit_opcode(cbuf, Assembler::REX_B); 2223 dstenc -= 8; 2224 } 2225 emit_opcode(cbuf, 0xB8 | dstenc); 2226 $$$emit32$src$$constant; 2227 %} 2228 2229 enc_class load_immL(rRegL dst, immL src) 2230 %{ 2231 int dstenc = $dst$$reg; 2232 if (dstenc < 8) { 2233 emit_opcode(cbuf, Assembler::REX_W); 2234 } else { 2235 emit_opcode(cbuf, Assembler::REX_WB); 2236 dstenc -= 8; 2237 } 2238 emit_opcode(cbuf, 0xB8 | dstenc); 2239 emit_d64(cbuf, $src$$constant); 2240 %} 2241 2242 enc_class load_immUL32(rRegL dst, immUL32 src) 2243 %{ 2244 // same as load_immI, but this time we care about zeroes in the high word 2245 int dstenc = $dst$$reg; 2246 if (dstenc >= 8) { 2247 emit_opcode(cbuf, Assembler::REX_B); 2248 dstenc -= 8; 2249 } 2250 emit_opcode(cbuf, 0xB8 | dstenc); 2251 $$$emit32$src$$constant; 2252 %} 2253 2254 enc_class load_immL32(rRegL dst, immL32 src) 2255 %{ 2256 int dstenc = $dst$$reg; 2257 if (dstenc < 8) { 2258 emit_opcode(cbuf, Assembler::REX_W); 2259 } else { 2260 emit_opcode(cbuf, Assembler::REX_WB); 2261 dstenc -= 8; 2262 } 2263 emit_opcode(cbuf, 0xC7); 2264 emit_rm(cbuf, 0x03, 0x00, dstenc); 2265 $$$emit32$src$$constant; 2266 %} 2267 2268 enc_class load_immP31(rRegP dst, immP32 src) 2269 %{ 2270 // same as load_immI, but this time we care about zeroes in the high word 2271 int dstenc = $dst$$reg; 2272 if (dstenc >= 8) { 2273 emit_opcode(cbuf, Assembler::REX_B); 2274 dstenc -= 8; 2275 } 2276 emit_opcode(cbuf, 0xB8 | dstenc); 2277 $$$emit32$src$$constant; 2278 %} 2279 2280 enc_class load_immP(rRegP dst, immP src) 2281 %{ 2282 int dstenc = $dst$$reg; 2283 if (dstenc < 8) { 2284 emit_opcode(cbuf, Assembler::REX_W); 2285 } else { 2286 emit_opcode(cbuf, Assembler::REX_WB); 2287 dstenc -= 8; 2288 } 2289 emit_opcode(cbuf, 0xB8 | dstenc); 2290 // This next line should be generated from ADLC 2291 if ($src->constant_reloc() != relocInfo::none) { 2292 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64); 2293 } else { 2294 emit_d64(cbuf, $src$$constant); 2295 } 2296 %} 2297 2298 enc_class Con32(immI src) 2299 %{ 2300 // Output immediate 2301 $$$emit32$src$$constant; 2302 %} 2303 2304 enc_class Con32F_as_bits(immF src) 2305 %{ 2306 // Output Float immediate bits 2307 jfloat jf = $src$$constant; 2308 jint jf_as_bits = jint_cast(jf); 2309 emit_d32(cbuf, jf_as_bits); 2310 %} 2311 2312 enc_class Con16(immI src) 2313 %{ 2314 // Output immediate 2315 $$$emit16$src$$constant; 2316 %} 2317 2318 // How is this different from Con32??? XXX 2319 enc_class Con_d32(immI src) 2320 %{ 2321 emit_d32(cbuf,$src$$constant); 2322 %} 2323 2324 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) 2325 // Output immediate memory reference 2326 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); 2327 emit_d32(cbuf, 0x00); 2328 %} 2329 2330 enc_class lock_prefix() 2331 %{ 2332 emit_opcode(cbuf, 0xF0); // lock 2333 %} 2334 2335 enc_class REX_mem(memory mem) 2336 %{ 2337 if ($mem$$base >= 8) { 2338 if ($mem$$index < 8) { 2339 emit_opcode(cbuf, Assembler::REX_B); 2340 } else { 2341 emit_opcode(cbuf, Assembler::REX_XB); 2342 } 2343 } else { 2344 if ($mem$$index >= 8) { 2345 emit_opcode(cbuf, Assembler::REX_X); 2346 } 2347 } 2348 %} 2349 2350 enc_class REX_mem_wide(memory mem) 2351 %{ 2352 if ($mem$$base >= 8) { 2353 if ($mem$$index < 8) { 2354 emit_opcode(cbuf, Assembler::REX_WB); 2355 } else { 2356 emit_opcode(cbuf, Assembler::REX_WXB); 2357 } 2358 } else { 2359 if ($mem$$index < 8) { 2360 emit_opcode(cbuf, Assembler::REX_W); 2361 } else { 2362 emit_opcode(cbuf, Assembler::REX_WX); 2363 } 2364 } 2365 %} 2366 2367 // for byte regs 2368 enc_class REX_breg(rRegI reg) 2369 %{ 2370 if ($reg$$reg >= 4) { 2371 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); 2372 } 2373 %} 2374 2375 // for byte regs 2376 enc_class REX_reg_breg(rRegI dst, rRegI src) 2377 %{ 2378 if ($dst$$reg < 8) { 2379 if ($src$$reg >= 4) { 2380 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); 2381 } 2382 } else { 2383 if ($src$$reg < 8) { 2384 emit_opcode(cbuf, Assembler::REX_R); 2385 } else { 2386 emit_opcode(cbuf, Assembler::REX_RB); 2387 } 2388 } 2389 %} 2390 2391 // for byte regs 2392 enc_class REX_breg_mem(rRegI reg, memory mem) 2393 %{ 2394 if ($reg$$reg < 8) { 2395 if ($mem$$base < 8) { 2396 if ($mem$$index >= 8) { 2397 emit_opcode(cbuf, Assembler::REX_X); 2398 } else if ($reg$$reg >= 4) { 2399 emit_opcode(cbuf, Assembler::REX); 2400 } 2401 } else { 2402 if ($mem$$index < 8) { 2403 emit_opcode(cbuf, Assembler::REX_B); 2404 } else { 2405 emit_opcode(cbuf, Assembler::REX_XB); 2406 } 2407 } 2408 } else { 2409 if ($mem$$base < 8) { 2410 if ($mem$$index < 8) { 2411 emit_opcode(cbuf, Assembler::REX_R); 2412 } else { 2413 emit_opcode(cbuf, Assembler::REX_RX); 2414 } 2415 } else { 2416 if ($mem$$index < 8) { 2417 emit_opcode(cbuf, Assembler::REX_RB); 2418 } else { 2419 emit_opcode(cbuf, Assembler::REX_RXB); 2420 } 2421 } 2422 } 2423 %} 2424 2425 enc_class REX_reg(rRegI reg) 2426 %{ 2427 if ($reg$$reg >= 8) { 2428 emit_opcode(cbuf, Assembler::REX_B); 2429 } 2430 %} 2431 2432 enc_class REX_reg_wide(rRegI reg) 2433 %{ 2434 if ($reg$$reg < 8) { 2435 emit_opcode(cbuf, Assembler::REX_W); 2436 } else { 2437 emit_opcode(cbuf, Assembler::REX_WB); 2438 } 2439 %} 2440 2441 enc_class REX_reg_reg(rRegI dst, rRegI src) 2442 %{ 2443 if ($dst$$reg < 8) { 2444 if ($src$$reg >= 8) { 2445 emit_opcode(cbuf, Assembler::REX_B); 2446 } 2447 } else { 2448 if ($src$$reg < 8) { 2449 emit_opcode(cbuf, Assembler::REX_R); 2450 } else { 2451 emit_opcode(cbuf, Assembler::REX_RB); 2452 } 2453 } 2454 %} 2455 2456 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) 2457 %{ 2458 if ($dst$$reg < 8) { 2459 if ($src$$reg < 8) { 2460 emit_opcode(cbuf, Assembler::REX_W); 2461 } else { 2462 emit_opcode(cbuf, Assembler::REX_WB); 2463 } 2464 } else { 2465 if ($src$$reg < 8) { 2466 emit_opcode(cbuf, Assembler::REX_WR); 2467 } else { 2468 emit_opcode(cbuf, Assembler::REX_WRB); 2469 } 2470 } 2471 %} 2472 2473 enc_class REX_reg_mem(rRegI reg, memory mem) 2474 %{ 2475 if ($reg$$reg < 8) { 2476 if ($mem$$base < 8) { 2477 if ($mem$$index >= 8) { 2478 emit_opcode(cbuf, Assembler::REX_X); 2479 } 2480 } else { 2481 if ($mem$$index < 8) { 2482 emit_opcode(cbuf, Assembler::REX_B); 2483 } else { 2484 emit_opcode(cbuf, Assembler::REX_XB); 2485 } 2486 } 2487 } else { 2488 if ($mem$$base < 8) { 2489 if ($mem$$index < 8) { 2490 emit_opcode(cbuf, Assembler::REX_R); 2491 } else { 2492 emit_opcode(cbuf, Assembler::REX_RX); 2493 } 2494 } else { 2495 if ($mem$$index < 8) { 2496 emit_opcode(cbuf, Assembler::REX_RB); 2497 } else { 2498 emit_opcode(cbuf, Assembler::REX_RXB); 2499 } 2500 } 2501 } 2502 %} 2503 2504 enc_class REX_reg_mem_wide(rRegL reg, memory mem) 2505 %{ 2506 if ($reg$$reg < 8) { 2507 if ($mem$$base < 8) { 2508 if ($mem$$index < 8) { 2509 emit_opcode(cbuf, Assembler::REX_W); 2510 } else { 2511 emit_opcode(cbuf, Assembler::REX_WX); 2512 } 2513 } else { 2514 if ($mem$$index < 8) { 2515 emit_opcode(cbuf, Assembler::REX_WB); 2516 } else { 2517 emit_opcode(cbuf, Assembler::REX_WXB); 2518 } 2519 } 2520 } else { 2521 if ($mem$$base < 8) { 2522 if ($mem$$index < 8) { 2523 emit_opcode(cbuf, Assembler::REX_WR); 2524 } else { 2525 emit_opcode(cbuf, Assembler::REX_WRX); 2526 } 2527 } else { 2528 if ($mem$$index < 8) { 2529 emit_opcode(cbuf, Assembler::REX_WRB); 2530 } else { 2531 emit_opcode(cbuf, Assembler::REX_WRXB); 2532 } 2533 } 2534 } 2535 %} 2536 2537 enc_class reg_mem(rRegI ereg, memory mem) 2538 %{ 2539 // High registers handle in encode_RegMem 2540 int reg = $ereg$$reg; 2541 int base = $mem$$base; 2542 int index = $mem$$index; 2543 int scale = $mem$$scale; 2544 int disp = $mem$$disp; 2545 relocInfo::relocType disp_reloc = $mem->disp_reloc(); 2546 2547 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc); 2548 %} 2549 2550 enc_class RM_opc_mem(immI rm_opcode, memory mem) 2551 %{ 2552 int rm_byte_opcode = $rm_opcode$$constant; 2553 2554 // High registers handle in encode_RegMem 2555 int base = $mem$$base; 2556 int index = $mem$$index; 2557 int scale = $mem$$scale; 2558 int displace = $mem$$disp; 2559 2560 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when 2561 // working with static 2562 // globals 2563 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, 2564 disp_reloc); 2565 %} 2566 2567 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) 2568 %{ 2569 int reg_encoding = $dst$$reg; 2570 int base = $src0$$reg; // 0xFFFFFFFF indicates no base 2571 int index = 0x04; // 0x04 indicates no index 2572 int scale = 0x00; // 0x00 indicates no scale 2573 int displace = $src1$$constant; // 0x00 indicates no displacement 2574 relocInfo::relocType disp_reloc = relocInfo::none; 2575 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, 2576 disp_reloc); 2577 %} 2578 2579 enc_class neg_reg(rRegI dst) 2580 %{ 2581 int dstenc = $dst$$reg; 2582 if (dstenc >= 8) { 2583 emit_opcode(cbuf, Assembler::REX_B); 2584 dstenc -= 8; 2585 } 2586 // NEG $dst 2587 emit_opcode(cbuf, 0xF7); 2588 emit_rm(cbuf, 0x3, 0x03, dstenc); 2589 %} 2590 2591 enc_class neg_reg_wide(rRegI dst) 2592 %{ 2593 int dstenc = $dst$$reg; 2594 if (dstenc < 8) { 2595 emit_opcode(cbuf, Assembler::REX_W); 2596 } else { 2597 emit_opcode(cbuf, Assembler::REX_WB); 2598 dstenc -= 8; 2599 } 2600 // NEG $dst 2601 emit_opcode(cbuf, 0xF7); 2602 emit_rm(cbuf, 0x3, 0x03, dstenc); 2603 %} 2604 2605 enc_class setLT_reg(rRegI dst) 2606 %{ 2607 int dstenc = $dst$$reg; 2608 if (dstenc >= 8) { 2609 emit_opcode(cbuf, Assembler::REX_B); 2610 dstenc -= 8; 2611 } else if (dstenc >= 4) { 2612 emit_opcode(cbuf, Assembler::REX); 2613 } 2614 // SETLT $dst 2615 emit_opcode(cbuf, 0x0F); 2616 emit_opcode(cbuf, 0x9C); 2617 emit_rm(cbuf, 0x3, 0x0, dstenc); 2618 %} 2619 2620 enc_class setNZ_reg(rRegI dst) 2621 %{ 2622 int dstenc = $dst$$reg; 2623 if (dstenc >= 8) { 2624 emit_opcode(cbuf, Assembler::REX_B); 2625 dstenc -= 8; 2626 } else if (dstenc >= 4) { 2627 emit_opcode(cbuf, Assembler::REX); 2628 } 2629 // SETNZ $dst 2630 emit_opcode(cbuf, 0x0F); 2631 emit_opcode(cbuf, 0x95); 2632 emit_rm(cbuf, 0x3, 0x0, dstenc); 2633 %} 2634 2635 2636 // Compare the lonogs and set -1, 0, or 1 into dst 2637 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) 2638 %{ 2639 int src1enc = $src1$$reg; 2640 int src2enc = $src2$$reg; 2641 int dstenc = $dst$$reg; 2642 2643 // cmpq $src1, $src2 2644 if (src1enc < 8) { 2645 if (src2enc < 8) { 2646 emit_opcode(cbuf, Assembler::REX_W); 2647 } else { 2648 emit_opcode(cbuf, Assembler::REX_WB); 2649 } 2650 } else { 2651 if (src2enc < 8) { 2652 emit_opcode(cbuf, Assembler::REX_WR); 2653 } else { 2654 emit_opcode(cbuf, Assembler::REX_WRB); 2655 } 2656 } 2657 emit_opcode(cbuf, 0x3B); 2658 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); 2659 2660 // movl $dst, -1 2661 if (dstenc >= 8) { 2662 emit_opcode(cbuf, Assembler::REX_B); 2663 } 2664 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); 2665 emit_d32(cbuf, -1); 2666 2667 // jl,s done 2668 emit_opcode(cbuf, 0x7C); 2669 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); 2670 2671 // setne $dst 2672 if (dstenc >= 4) { 2673 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); 2674 } 2675 emit_opcode(cbuf, 0x0F); 2676 emit_opcode(cbuf, 0x95); 2677 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); 2678 2679 // movzbl $dst, $dst 2680 if (dstenc >= 4) { 2681 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); 2682 } 2683 emit_opcode(cbuf, 0x0F); 2684 emit_opcode(cbuf, 0xB6); 2685 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); 2686 %} 2687 2688 enc_class Push_ResultXD(regD dst) %{ 2689 MacroAssembler _masm(&cbuf); 2690 __ fstp_d(Address(rsp, 0)); 2691 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); 2692 __ addptr(rsp, 8); 2693 %} 2694 2695 enc_class Push_SrcXD(regD src) %{ 2696 MacroAssembler _masm(&cbuf); 2697 __ subptr(rsp, 8); 2698 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 2699 __ fld_d(Address(rsp, 0)); 2700 %} 2701 2702 2703 enc_class enc_rethrow() 2704 %{ 2705 cbuf.set_insts_mark(); 2706 emit_opcode(cbuf, 0xE9); // jmp entry 2707 emit_d32_reloc(cbuf, 2708 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), 2709 runtime_call_Relocation::spec(), 2710 RELOC_DISP32); 2711 %} 2712 2713%} 2714 2715 2716 2717//----------FRAME-------------------------------------------------------------- 2718// Definition of frame structure and management information. 2719// 2720// S T A C K L A Y O U T Allocators stack-slot number 2721// | (to get allocators register number 2722// G Owned by | | v add OptoReg::stack0()) 2723// r CALLER | | 2724// o | +--------+ pad to even-align allocators stack-slot 2725// w V | pad0 | numbers; owned by CALLER 2726// t -----------+--------+----> Matcher::_in_arg_limit, unaligned 2727// h ^ | in | 5 2728// | | args | 4 Holes in incoming args owned by SELF 2729// | | | | 3 2730// | | +--------+ 2731// V | | old out| Empty on Intel, window on Sparc 2732// | old |preserve| Must be even aligned. 2733// | SP-+--------+----> Matcher::_old_SP, even aligned 2734// | | in | 3 area for Intel ret address 2735// Owned by |preserve| Empty on Sparc. 2736// SELF +--------+ 2737// | | pad2 | 2 pad to align old SP 2738// | +--------+ 1 2739// | | locks | 0 2740// | +--------+----> OptoReg::stack0(), even aligned 2741// | | pad1 | 11 pad to align new SP 2742// | +--------+ 2743// | | | 10 2744// | | spills | 9 spills 2745// V | | 8 (pad0 slot for callee) 2746// -----------+--------+----> Matcher::_out_arg_limit, unaligned 2747// ^ | out | 7 2748// | | args | 6 Holes in outgoing args owned by CALLEE 2749// Owned by +--------+ 2750// CALLEE | new out| 6 Empty on Intel, window on Sparc 2751// | new |preserve| Must be even-aligned. 2752// | SP-+--------+----> Matcher::_new_SP, even aligned 2753// | | | 2754// 2755// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 2756// known from SELF's arguments and the Java calling convention. 2757// Region 6-7 is determined per call site. 2758// Note 2: If the calling convention leaves holes in the incoming argument 2759// area, those holes are owned by SELF. Holes in the outgoing area 2760// are owned by the CALLEE. Holes should not be nessecary in the 2761// incoming area, as the Java calling convention is completely under 2762// the control of the AD file. Doubles can be sorted and packed to 2763// avoid holes. Holes in the outgoing arguments may be nessecary for 2764// varargs C calling conventions. 2765// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 2766// even aligned with pad0 as needed. 2767// Region 6 is even aligned. Region 6-7 is NOT even aligned; 2768// region 6-11 is even aligned; it may be padded out more so that 2769// the region from SP to FP meets the minimum stack alignment. 2770// Note 4: For I2C adapters, the incoming FP may not meet the minimum stack 2771// alignment. Region 11, pad1, may be dynamically extended so that 2772// SP meets the minimum alignment. 2773 2774frame 2775%{ 2776 // What direction does stack grow in (assumed to be same for C & Java) 2777 stack_direction(TOWARDS_LOW); 2778 2779 // These three registers define part of the calling convention 2780 // between compiled code and the interpreter. 2781 inline_cache_reg(RAX); // Inline Cache Register 2782 interpreter_method_oop_reg(RBX); // Method Oop Register when 2783 // calling interpreter 2784 2785 // Optional: name the operand used by cisc-spilling to access 2786 // [stack_pointer + offset] 2787 cisc_spilling_operand_name(indOffset32); 2788 2789 // Number of stack slots consumed by locking an object 2790 sync_stack_slots(2); 2791 2792 // Compiled code's Frame Pointer 2793 frame_pointer(RSP); 2794 2795 // Interpreter stores its frame pointer in a register which is 2796 // stored to the stack by I2CAdaptors. 2797 // I2CAdaptors convert from interpreted java to compiled java. 2798 interpreter_frame_pointer(RBP); 2799 2800 // Stack alignment requirement 2801 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) 2802 2803 // Number of stack slots between incoming argument block and the start of 2804 // a new frame. The PROLOG must add this many slots to the stack. The 2805 // EPILOG must remove this many slots. amd64 needs two slots for 2806 // return address. 2807 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); 2808 2809 // Number of outgoing stack slots killed above the out_preserve_stack_slots 2810 // for calls to C. Supports the var-args backing area for register parms. 2811 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); 2812 2813 // The after-PROLOG location of the return address. Location of 2814 // return address specifies a type (REG or STACK) and a number 2815 // representing the register number (i.e. - use a register name) or 2816 // stack slot. 2817 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. 2818 // Otherwise, it is above the locks and verification slot and alignment word 2819 return_addr(STACK - 2 + 2820 align_up((Compile::current()->in_preserve_stack_slots() + 2821 Compile::current()->fixed_slots()), 2822 stack_alignment_in_slots())); 2823 2824 // Body of function which returns an integer array locating 2825 // arguments either in registers or in stack slots. Passed an array 2826 // of ideal registers called "sig" and a "length" count. Stack-slot 2827 // offsets are based on outgoing arguments, i.e. a CALLER setting up 2828 // arguments for a CALLEE. Incoming stack arguments are 2829 // automatically biased by the preserve_stack_slots field above. 2830 2831 calling_convention 2832 %{ 2833 // No difference between ingoing/outgoing just pass false 2834 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 2835 %} 2836 2837 c_calling_convention 2838 %{ 2839 // This is obviously always outgoing 2840 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 2841 %} 2842 2843 // Location of compiled Java return values. Same as C for now. 2844 return_value 2845 %{ 2846 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, 2847 "only return normal values"); 2848 2849 static const int lo[Op_RegL + 1] = { 2850 0, 2851 0, 2852 RAX_num, // Op_RegN 2853 RAX_num, // Op_RegI 2854 RAX_num, // Op_RegP 2855 XMM0_num, // Op_RegF 2856 XMM0_num, // Op_RegD 2857 RAX_num // Op_RegL 2858 }; 2859 static const int hi[Op_RegL + 1] = { 2860 0, 2861 0, 2862 OptoReg::Bad, // Op_RegN 2863 OptoReg::Bad, // Op_RegI 2864 RAX_H_num, // Op_RegP 2865 OptoReg::Bad, // Op_RegF 2866 XMM0b_num, // Op_RegD 2867 RAX_H_num // Op_RegL 2868 }; 2869 // Excluded flags and vector registers. 2870 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type"); 2871 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); 2872 %} 2873%} 2874 2875//----------ATTRIBUTES--------------------------------------------------------- 2876//----------Operand Attributes------------------------------------------------- 2877op_attrib op_cost(0); // Required cost attribute 2878 2879//----------Instruction Attributes--------------------------------------------- 2880ins_attrib ins_cost(100); // Required cost attribute 2881ins_attrib ins_size(8); // Required size attribute (in bits) 2882ins_attrib ins_short_branch(0); // Required flag: is this instruction 2883 // a non-matching short branch variant 2884 // of some long branch? 2885ins_attrib ins_alignment(1); // Required alignment attribute (must 2886 // be a power of 2) specifies the 2887 // alignment that some part of the 2888 // instruction (not necessarily the 2889 // start) requires. If > 1, a 2890 // compute_padding() function must be 2891 // provided for the instruction 2892 2893//----------OPERANDS----------------------------------------------------------- 2894// Operand definitions must precede instruction definitions for correct parsing 2895// in the ADLC because operands constitute user defined types which are used in 2896// instruction definitions. 2897 2898//----------Simple Operands---------------------------------------------------- 2899// Immediate Operands 2900// Integer Immediate 2901operand immI() 2902%{ 2903 match(ConI); 2904 2905 op_cost(10); 2906 format %{ %} 2907 interface(CONST_INTER); 2908%} 2909 2910// Constant for test vs zero 2911operand immI0() 2912%{ 2913 predicate(n->get_int() == 0); 2914 match(ConI); 2915 2916 op_cost(0); 2917 format %{ %} 2918 interface(CONST_INTER); 2919%} 2920 2921// Constant for increment 2922operand immI1() 2923%{ 2924 predicate(n->get_int() == 1); 2925 match(ConI); 2926 2927 op_cost(0); 2928 format %{ %} 2929 interface(CONST_INTER); 2930%} 2931 2932// Constant for decrement 2933operand immI_M1() 2934%{ 2935 predicate(n->get_int() == -1); 2936 match(ConI); 2937 2938 op_cost(0); 2939 format %{ %} 2940 interface(CONST_INTER); 2941%} 2942 2943// Valid scale values for addressing modes 2944operand immI2() 2945%{ 2946 predicate(0 <= n->get_int() && (n->get_int() <= 3)); 2947 match(ConI); 2948 2949 format %{ %} 2950 interface(CONST_INTER); 2951%} 2952 2953operand immI8() 2954%{ 2955 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); 2956 match(ConI); 2957 2958 op_cost(5); 2959 format %{ %} 2960 interface(CONST_INTER); 2961%} 2962 2963operand immU8() 2964%{ 2965 predicate((0 <= n->get_int()) && (n->get_int() <= 255)); 2966 match(ConI); 2967 2968 op_cost(5); 2969 format %{ %} 2970 interface(CONST_INTER); 2971%} 2972 2973operand immI16() 2974%{ 2975 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); 2976 match(ConI); 2977 2978 op_cost(10); 2979 format %{ %} 2980 interface(CONST_INTER); 2981%} 2982 2983// Int Immediate non-negative 2984operand immU31() 2985%{ 2986 predicate(n->get_int() >= 0); 2987 match(ConI); 2988 2989 op_cost(0); 2990 format %{ %} 2991 interface(CONST_INTER); 2992%} 2993 2994// Constant for long shifts 2995operand immI_32() 2996%{ 2997 predicate( n->get_int() == 32 ); 2998 match(ConI); 2999 3000 op_cost(0); 3001 format %{ %} 3002 interface(CONST_INTER); 3003%} 3004 3005// Constant for long shifts 3006operand immI_64() 3007%{ 3008 predicate( n->get_int() == 64 ); 3009 match(ConI); 3010 3011 op_cost(0); 3012 format %{ %} 3013 interface(CONST_INTER); 3014%} 3015 3016// Pointer Immediate 3017operand immP() 3018%{ 3019 match(ConP); 3020 3021 op_cost(10); 3022 format %{ %} 3023 interface(CONST_INTER); 3024%} 3025 3026// NULL Pointer Immediate 3027operand immP0() 3028%{ 3029 predicate(n->get_ptr() == 0); 3030 match(ConP); 3031 3032 op_cost(5); 3033 format %{ %} 3034 interface(CONST_INTER); 3035%} 3036 3037// Pointer Immediate 3038operand immN() %{ 3039 match(ConN); 3040 3041 op_cost(10); 3042 format %{ %} 3043 interface(CONST_INTER); 3044%} 3045 3046operand immNKlass() %{ 3047 match(ConNKlass); 3048 3049 op_cost(10); 3050 format %{ %} 3051 interface(CONST_INTER); 3052%} 3053 3054// NULL Pointer Immediate 3055operand immN0() %{ 3056 predicate(n->get_narrowcon() == 0); 3057 match(ConN); 3058 3059 op_cost(5); 3060 format %{ %} 3061 interface(CONST_INTER); 3062%} 3063 3064operand immP31() 3065%{ 3066 predicate(n->as_Type()->type()->reloc() == relocInfo::none 3067 && (n->get_ptr() >> 31) == 0); 3068 match(ConP); 3069 3070 op_cost(5); 3071 format %{ %} 3072 interface(CONST_INTER); 3073%} 3074 3075 3076// Long Immediate 3077operand immL() 3078%{ 3079 match(ConL); 3080 3081 op_cost(20); 3082 format %{ %} 3083 interface(CONST_INTER); 3084%} 3085 3086// Long Immediate 8-bit 3087operand immL8() 3088%{ 3089 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); 3090 match(ConL); 3091 3092 op_cost(5); 3093 format %{ %} 3094 interface(CONST_INTER); 3095%} 3096 3097// Long Immediate 32-bit unsigned 3098operand immUL32() 3099%{ 3100 predicate(n->get_long() == (unsigned int) (n->get_long())); 3101 match(ConL); 3102 3103 op_cost(10); 3104 format %{ %} 3105 interface(CONST_INTER); 3106%} 3107 3108// Long Immediate 32-bit signed 3109operand immL32() 3110%{ 3111 predicate(n->get_long() == (int) (n->get_long())); 3112 match(ConL); 3113 3114 op_cost(15); 3115 format %{ %} 3116 interface(CONST_INTER); 3117%} 3118 3119// Long Immediate zero 3120operand immL0() 3121%{ 3122 predicate(n->get_long() == 0L); 3123 match(ConL); 3124 3125 op_cost(10); 3126 format %{ %} 3127 interface(CONST_INTER); 3128%} 3129 3130// Constant for increment 3131operand immL1() 3132%{ 3133 predicate(n->get_long() == 1); 3134 match(ConL); 3135 3136 format %{ %} 3137 interface(CONST_INTER); 3138%} 3139 3140// Constant for decrement 3141operand immL_M1() 3142%{ 3143 predicate(n->get_long() == -1); 3144 match(ConL); 3145 3146 format %{ %} 3147 interface(CONST_INTER); 3148%} 3149 3150// Long Immediate: the value 10 3151operand immL10() 3152%{ 3153 predicate(n->get_long() == 10); 3154 match(ConL); 3155 3156 format %{ %} 3157 interface(CONST_INTER); 3158%} 3159 3160// Long immediate from 0 to 127. 3161// Used for a shorter form of long mul by 10. 3162operand immL_127() 3163%{ 3164 predicate(0 <= n->get_long() && n->get_long() < 0x80); 3165 match(ConL); 3166 3167 op_cost(10); 3168 format %{ %} 3169 interface(CONST_INTER); 3170%} 3171 3172// Long Immediate: low 32-bit mask 3173operand immL_32bits() 3174%{ 3175 predicate(n->get_long() == 0xFFFFFFFFL); 3176 match(ConL); 3177 op_cost(20); 3178 3179 format %{ %} 3180 interface(CONST_INTER); 3181%} 3182 3183// Float Immediate zero 3184operand immF0() 3185%{ 3186 predicate(jint_cast(n->getf()) == 0); 3187 match(ConF); 3188 3189 op_cost(5); 3190 format %{ %} 3191 interface(CONST_INTER); 3192%} 3193 3194// Float Immediate 3195operand immF() 3196%{ 3197 match(ConF); 3198 3199 op_cost(15); 3200 format %{ %} 3201 interface(CONST_INTER); 3202%} 3203 3204// Double Immediate zero 3205operand immD0() 3206%{ 3207 predicate(jlong_cast(n->getd()) == 0); 3208 match(ConD); 3209 3210 op_cost(5); 3211 format %{ %} 3212 interface(CONST_INTER); 3213%} 3214 3215// Double Immediate 3216operand immD() 3217%{ 3218 match(ConD); 3219 3220 op_cost(15); 3221 format %{ %} 3222 interface(CONST_INTER); 3223%} 3224 3225// Immediates for special shifts (sign extend) 3226 3227// Constants for increment 3228operand immI_16() 3229%{ 3230 predicate(n->get_int() == 16); 3231 match(ConI); 3232 3233 format %{ %} 3234 interface(CONST_INTER); 3235%} 3236 3237operand immI_24() 3238%{ 3239 predicate(n->get_int() == 24); 3240 match(ConI); 3241 3242 format %{ %} 3243 interface(CONST_INTER); 3244%} 3245 3246// Constant for byte-wide masking 3247operand immI_255() 3248%{ 3249 predicate(n->get_int() == 255); 3250 match(ConI); 3251 3252 format %{ %} 3253 interface(CONST_INTER); 3254%} 3255 3256// Constant for short-wide masking 3257operand immI_65535() 3258%{ 3259 predicate(n->get_int() == 65535); 3260 match(ConI); 3261 3262 format %{ %} 3263 interface(CONST_INTER); 3264%} 3265 3266// Constant for byte-wide masking 3267operand immL_255() 3268%{ 3269 predicate(n->get_long() == 255); 3270 match(ConL); 3271 3272 format %{ %} 3273 interface(CONST_INTER); 3274%} 3275 3276// Constant for short-wide masking 3277operand immL_65535() 3278%{ 3279 predicate(n->get_long() == 65535); 3280 match(ConL); 3281 3282 format %{ %} 3283 interface(CONST_INTER); 3284%} 3285 3286// Register Operands 3287// Integer Register 3288operand rRegI() 3289%{ 3290 constraint(ALLOC_IN_RC(int_reg)); 3291 match(RegI); 3292 3293 match(rax_RegI); 3294 match(rbx_RegI); 3295 match(rcx_RegI); 3296 match(rdx_RegI); 3297 match(rdi_RegI); 3298 3299 format %{ %} 3300 interface(REG_INTER); 3301%} 3302 3303// Special Registers 3304operand rax_RegI() 3305%{ 3306 constraint(ALLOC_IN_RC(int_rax_reg)); 3307 match(RegI); 3308 match(rRegI); 3309 3310 format %{ "RAX" %} 3311 interface(REG_INTER); 3312%} 3313 3314// Special Registers 3315operand rbx_RegI() 3316%{ 3317 constraint(ALLOC_IN_RC(int_rbx_reg)); 3318 match(RegI); 3319 match(rRegI); 3320 3321 format %{ "RBX" %} 3322 interface(REG_INTER); 3323%} 3324 3325operand rcx_RegI() 3326%{ 3327 constraint(ALLOC_IN_RC(int_rcx_reg)); 3328 match(RegI); 3329 match(rRegI); 3330 3331 format %{ "RCX" %} 3332 interface(REG_INTER); 3333%} 3334 3335operand rdx_RegI() 3336%{ 3337 constraint(ALLOC_IN_RC(int_rdx_reg)); 3338 match(RegI); 3339 match(rRegI); 3340 3341 format %{ "RDX" %} 3342 interface(REG_INTER); 3343%} 3344 3345operand rdi_RegI() 3346%{ 3347 constraint(ALLOC_IN_RC(int_rdi_reg)); 3348 match(RegI); 3349 match(rRegI); 3350 3351 format %{ "RDI" %} 3352 interface(REG_INTER); 3353%} 3354 3355operand no_rcx_RegI() 3356%{ 3357 constraint(ALLOC_IN_RC(int_no_rcx_reg)); 3358 match(RegI); 3359 match(rax_RegI); 3360 match(rbx_RegI); 3361 match(rdx_RegI); 3362 match(rdi_RegI); 3363 3364 format %{ %} 3365 interface(REG_INTER); 3366%} 3367 3368operand no_rax_rdx_RegI() 3369%{ 3370 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); 3371 match(RegI); 3372 match(rbx_RegI); 3373 match(rcx_RegI); 3374 match(rdi_RegI); 3375 3376 format %{ %} 3377 interface(REG_INTER); 3378%} 3379 3380// Pointer Register 3381operand any_RegP() 3382%{ 3383 constraint(ALLOC_IN_RC(any_reg)); 3384 match(RegP); 3385 match(rax_RegP); 3386 match(rbx_RegP); 3387 match(rdi_RegP); 3388 match(rsi_RegP); 3389 match(rbp_RegP); 3390 match(r15_RegP); 3391 match(rRegP); 3392 3393 format %{ %} 3394 interface(REG_INTER); 3395%} 3396 3397operand rRegP() 3398%{ 3399 constraint(ALLOC_IN_RC(ptr_reg)); 3400 match(RegP); 3401 match(rax_RegP); 3402 match(rbx_RegP); 3403 match(rdi_RegP); 3404 match(rsi_RegP); 3405 match(rbp_RegP); // See Q&A below about 3406 match(r15_RegP); // r15_RegP and rbp_RegP. 3407 3408 format %{ %} 3409 interface(REG_INTER); 3410%} 3411 3412operand rRegN() %{ 3413 constraint(ALLOC_IN_RC(int_reg)); 3414 match(RegN); 3415 3416 format %{ %} 3417 interface(REG_INTER); 3418%} 3419 3420// Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? 3421// Answer: Operand match rules govern the DFA as it processes instruction inputs. 3422// It's fine for an instruction input that expects rRegP to match a r15_RegP. 3423// The output of an instruction is controlled by the allocator, which respects 3424// register class masks, not match rules. Unless an instruction mentions 3425// r15_RegP or any_RegP explicitly as its output, r15 will not be considered 3426// by the allocator as an input. 3427// The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true, 3428// the RBP is used as a proper frame pointer and is not included in ptr_reg. As a 3429// result, RBP is not included in the output of the instruction either. 3430 3431operand no_rax_RegP() 3432%{ 3433 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); 3434 match(RegP); 3435 match(rbx_RegP); 3436 match(rsi_RegP); 3437 match(rdi_RegP); 3438 3439 format %{ %} 3440 interface(REG_INTER); 3441%} 3442 3443// This operand is not allowed to use RBP even if 3444// RBP is not used to hold the frame pointer. 3445operand no_rbp_RegP() 3446%{ 3447 constraint(ALLOC_IN_RC(ptr_reg_no_rbp)); 3448 match(RegP); 3449 match(rbx_RegP); 3450 match(rsi_RegP); 3451 match(rdi_RegP); 3452 3453 format %{ %} 3454 interface(REG_INTER); 3455%} 3456 3457operand no_rax_rbx_RegP() 3458%{ 3459 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); 3460 match(RegP); 3461 match(rsi_RegP); 3462 match(rdi_RegP); 3463 3464 format %{ %} 3465 interface(REG_INTER); 3466%} 3467 3468// Special Registers 3469// Return a pointer value 3470operand rax_RegP() 3471%{ 3472 constraint(ALLOC_IN_RC(ptr_rax_reg)); 3473 match(RegP); 3474 match(rRegP); 3475 3476 format %{ %} 3477 interface(REG_INTER); 3478%} 3479 3480// Special Registers 3481// Return a compressed pointer value 3482operand rax_RegN() 3483%{ 3484 constraint(ALLOC_IN_RC(int_rax_reg)); 3485 match(RegN); 3486 match(rRegN); 3487 3488 format %{ %} 3489 interface(REG_INTER); 3490%} 3491 3492// Used in AtomicAdd 3493operand rbx_RegP() 3494%{ 3495 constraint(ALLOC_IN_RC(ptr_rbx_reg)); 3496 match(RegP); 3497 match(rRegP); 3498 3499 format %{ %} 3500 interface(REG_INTER); 3501%} 3502 3503operand rsi_RegP() 3504%{ 3505 constraint(ALLOC_IN_RC(ptr_rsi_reg)); 3506 match(RegP); 3507 match(rRegP); 3508 3509 format %{ %} 3510 interface(REG_INTER); 3511%} 3512 3513// Used in rep stosq 3514operand rdi_RegP() 3515%{ 3516 constraint(ALLOC_IN_RC(ptr_rdi_reg)); 3517 match(RegP); 3518 match(rRegP); 3519 3520 format %{ %} 3521 interface(REG_INTER); 3522%} 3523 3524operand r15_RegP() 3525%{ 3526 constraint(ALLOC_IN_RC(ptr_r15_reg)); 3527 match(RegP); 3528 match(rRegP); 3529 3530 format %{ %} 3531 interface(REG_INTER); 3532%} 3533 3534operand rRegL() 3535%{ 3536 constraint(ALLOC_IN_RC(long_reg)); 3537 match(RegL); 3538 match(rax_RegL); 3539 match(rdx_RegL); 3540 3541 format %{ %} 3542 interface(REG_INTER); 3543%} 3544 3545// Special Registers 3546operand no_rax_rdx_RegL() 3547%{ 3548 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); 3549 match(RegL); 3550 match(rRegL); 3551 3552 format %{ %} 3553 interface(REG_INTER); 3554%} 3555 3556operand no_rax_RegL() 3557%{ 3558 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); 3559 match(RegL); 3560 match(rRegL); 3561 match(rdx_RegL); 3562 3563 format %{ %} 3564 interface(REG_INTER); 3565%} 3566 3567operand no_rcx_RegL() 3568%{ 3569 constraint(ALLOC_IN_RC(long_no_rcx_reg)); 3570 match(RegL); 3571 match(rRegL); 3572 3573 format %{ %} 3574 interface(REG_INTER); 3575%} 3576 3577operand rax_RegL() 3578%{ 3579 constraint(ALLOC_IN_RC(long_rax_reg)); 3580 match(RegL); 3581 match(rRegL); 3582 3583 format %{ "RAX" %} 3584 interface(REG_INTER); 3585%} 3586 3587operand rcx_RegL() 3588%{ 3589 constraint(ALLOC_IN_RC(long_rcx_reg)); 3590 match(RegL); 3591 match(rRegL); 3592 3593 format %{ %} 3594 interface(REG_INTER); 3595%} 3596 3597operand rdx_RegL() 3598%{ 3599 constraint(ALLOC_IN_RC(long_rdx_reg)); 3600 match(RegL); 3601 match(rRegL); 3602 3603 format %{ %} 3604 interface(REG_INTER); 3605%} 3606 3607// Flags register, used as output of compare instructions 3608operand rFlagsReg() 3609%{ 3610 constraint(ALLOC_IN_RC(int_flags)); 3611 match(RegFlags); 3612 3613 format %{ "RFLAGS" %} 3614 interface(REG_INTER); 3615%} 3616 3617// Flags register, used as output of FLOATING POINT compare instructions 3618operand rFlagsRegU() 3619%{ 3620 constraint(ALLOC_IN_RC(int_flags)); 3621 match(RegFlags); 3622 3623 format %{ "RFLAGS_U" %} 3624 interface(REG_INTER); 3625%} 3626 3627operand rFlagsRegUCF() %{ 3628 constraint(ALLOC_IN_RC(int_flags)); 3629 match(RegFlags); 3630 predicate(false); 3631 3632 format %{ "RFLAGS_U_CF" %} 3633 interface(REG_INTER); 3634%} 3635 3636// Float register operands 3637operand regF() %{ 3638 constraint(ALLOC_IN_RC(float_reg)); 3639 match(RegF); 3640 3641 format %{ %} 3642 interface(REG_INTER); 3643%} 3644 3645// Float register operands 3646operand legRegF() %{ 3647 constraint(ALLOC_IN_RC(float_reg_legacy)); 3648 match(RegF); 3649 3650 format %{ %} 3651 interface(REG_INTER); 3652%} 3653 3654// Float register operands 3655operand vlRegF() %{ 3656 constraint(ALLOC_IN_RC(float_reg_vl)); 3657 match(RegF); 3658 3659 format %{ %} 3660 interface(REG_INTER); 3661%} 3662 3663// Double register operands 3664operand regD() %{ 3665 constraint(ALLOC_IN_RC(double_reg)); 3666 match(RegD); 3667 3668 format %{ %} 3669 interface(REG_INTER); 3670%} 3671 3672// Double register operands 3673operand legRegD() %{ 3674 constraint(ALLOC_IN_RC(double_reg_legacy)); 3675 match(RegD); 3676 3677 format %{ %} 3678 interface(REG_INTER); 3679%} 3680 3681// Double register operands 3682operand vlRegD() %{ 3683 constraint(ALLOC_IN_RC(double_reg_vl)); 3684 match(RegD); 3685 3686 format %{ %} 3687 interface(REG_INTER); 3688%} 3689 3690// Vectors 3691operand vecS() %{ 3692 constraint(ALLOC_IN_RC(vectors_reg_vlbwdq)); 3693 match(VecS); 3694 3695 format %{ %} 3696 interface(REG_INTER); 3697%} 3698 3699// Vectors 3700operand legVecS() %{ 3701 constraint(ALLOC_IN_RC(vectors_reg_legacy)); 3702 match(VecS); 3703 3704 format %{ %} 3705 interface(REG_INTER); 3706%} 3707 3708operand vecD() %{ 3709 constraint(ALLOC_IN_RC(vectord_reg_vlbwdq)); 3710 match(VecD); 3711 3712 format %{ %} 3713 interface(REG_INTER); 3714%} 3715 3716operand legVecD() %{ 3717 constraint(ALLOC_IN_RC(vectord_reg_legacy)); 3718 match(VecD); 3719 3720 format %{ %} 3721 interface(REG_INTER); 3722%} 3723 3724operand vecX() %{ 3725 constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq)); 3726 match(VecX); 3727 3728 format %{ %} 3729 interface(REG_INTER); 3730%} 3731 3732operand legVecX() %{ 3733 constraint(ALLOC_IN_RC(vectorx_reg_legacy)); 3734 match(VecX); 3735 3736 format %{ %} 3737 interface(REG_INTER); 3738%} 3739 3740operand vecY() %{ 3741 constraint(ALLOC_IN_RC(vectory_reg_vlbwdq)); 3742 match(VecY); 3743 3744 format %{ %} 3745 interface(REG_INTER); 3746%} 3747 3748operand legVecY() %{ 3749 constraint(ALLOC_IN_RC(vectory_reg_legacy)); 3750 match(VecY); 3751 3752 format %{ %} 3753 interface(REG_INTER); 3754%} 3755 3756//----------Memory Operands---------------------------------------------------- 3757// Direct Memory Operand 3758// operand direct(immP addr) 3759// %{ 3760// match(addr); 3761 3762// format %{ "[$addr]" %} 3763// interface(MEMORY_INTER) %{ 3764// base(0xFFFFFFFF); 3765// index(0x4); 3766// scale(0x0); 3767// disp($addr); 3768// %} 3769// %} 3770 3771// Indirect Memory Operand 3772operand indirect(any_RegP reg) 3773%{ 3774 constraint(ALLOC_IN_RC(ptr_reg)); 3775 match(reg); 3776 3777 format %{ "[$reg]" %} 3778 interface(MEMORY_INTER) %{ 3779 base($reg); 3780 index(0x4); 3781 scale(0x0); 3782 disp(0x0); 3783 %} 3784%} 3785 3786// Indirect Memory Plus Short Offset Operand 3787operand indOffset8(any_RegP reg, immL8 off) 3788%{ 3789 constraint(ALLOC_IN_RC(ptr_reg)); 3790 match(AddP reg off); 3791 3792 format %{ "[$reg + $off (8-bit)]" %} 3793 interface(MEMORY_INTER) %{ 3794 base($reg); 3795 index(0x4); 3796 scale(0x0); 3797 disp($off); 3798 %} 3799%} 3800 3801// Indirect Memory Plus Long Offset Operand 3802operand indOffset32(any_RegP reg, immL32 off) 3803%{ 3804 constraint(ALLOC_IN_RC(ptr_reg)); 3805 match(AddP reg off); 3806 3807 format %{ "[$reg + $off (32-bit)]" %} 3808 interface(MEMORY_INTER) %{ 3809 base($reg); 3810 index(0x4); 3811 scale(0x0); 3812 disp($off); 3813 %} 3814%} 3815 3816// Indirect Memory Plus Index Register Plus Offset Operand 3817operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) 3818%{ 3819 constraint(ALLOC_IN_RC(ptr_reg)); 3820 match(AddP (AddP reg lreg) off); 3821 3822 op_cost(10); 3823 format %{"[$reg + $off + $lreg]" %} 3824 interface(MEMORY_INTER) %{ 3825 base($reg); 3826 index($lreg); 3827 scale(0x0); 3828 disp($off); 3829 %} 3830%} 3831 3832// Indirect Memory Plus Index Register Plus Offset Operand 3833operand indIndex(any_RegP reg, rRegL lreg) 3834%{ 3835 constraint(ALLOC_IN_RC(ptr_reg)); 3836 match(AddP reg lreg); 3837 3838 op_cost(10); 3839 format %{"[$reg + $lreg]" %} 3840 interface(MEMORY_INTER) %{ 3841 base($reg); 3842 index($lreg); 3843 scale(0x0); 3844 disp(0x0); 3845 %} 3846%} 3847 3848// Indirect Memory Times Scale Plus Index Register 3849operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) 3850%{ 3851 constraint(ALLOC_IN_RC(ptr_reg)); 3852 match(AddP reg (LShiftL lreg scale)); 3853 3854 op_cost(10); 3855 format %{"[$reg + $lreg << $scale]" %} 3856 interface(MEMORY_INTER) %{ 3857 base($reg); 3858 index($lreg); 3859 scale($scale); 3860 disp(0x0); 3861 %} 3862%} 3863 3864operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale) 3865%{ 3866 constraint(ALLOC_IN_RC(ptr_reg)); 3867 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); 3868 match(AddP reg (LShiftL (ConvI2L idx) scale)); 3869 3870 op_cost(10); 3871 format %{"[$reg + pos $idx << $scale]" %} 3872 interface(MEMORY_INTER) %{ 3873 base($reg); 3874 index($idx); 3875 scale($scale); 3876 disp(0x0); 3877 %} 3878%} 3879 3880// Indirect Memory Times Scale Plus Index Register Plus Offset Operand 3881operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) 3882%{ 3883 constraint(ALLOC_IN_RC(ptr_reg)); 3884 match(AddP (AddP reg (LShiftL lreg scale)) off); 3885 3886 op_cost(10); 3887 format %{"[$reg + $off + $lreg << $scale]" %} 3888 interface(MEMORY_INTER) %{ 3889 base($reg); 3890 index($lreg); 3891 scale($scale); 3892 disp($off); 3893 %} 3894%} 3895 3896// Indirect Memory Plus Positive Index Register Plus Offset Operand 3897operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx) 3898%{ 3899 constraint(ALLOC_IN_RC(ptr_reg)); 3900 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0); 3901 match(AddP (AddP reg (ConvI2L idx)) off); 3902 3903 op_cost(10); 3904 format %{"[$reg + $off + $idx]" %} 3905 interface(MEMORY_INTER) %{ 3906 base($reg); 3907 index($idx); 3908 scale(0x0); 3909 disp($off); 3910 %} 3911%} 3912 3913// Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand 3914operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) 3915%{ 3916 constraint(ALLOC_IN_RC(ptr_reg)); 3917 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); 3918 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); 3919 3920 op_cost(10); 3921 format %{"[$reg + $off + $idx << $scale]" %} 3922 interface(MEMORY_INTER) %{ 3923 base($reg); 3924 index($idx); 3925 scale($scale); 3926 disp($off); 3927 %} 3928%} 3929 3930// Indirect Narrow Oop Plus Offset Operand 3931// Note: x86 architecture doesn't support "scale * index + offset" without a base 3932// we can't free r12 even with CompressedOops::base() == NULL. 3933operand indCompressedOopOffset(rRegN reg, immL32 off) %{ 3934 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8)); 3935 constraint(ALLOC_IN_RC(ptr_reg)); 3936 match(AddP (DecodeN reg) off); 3937 3938 op_cost(10); 3939 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} 3940 interface(MEMORY_INTER) %{ 3941 base(0xc); // R12 3942 index($reg); 3943 scale(0x3); 3944 disp($off); 3945 %} 3946%} 3947 3948// Indirect Memory Operand 3949operand indirectNarrow(rRegN reg) 3950%{ 3951 predicate(CompressedOops::shift() == 0); 3952 constraint(ALLOC_IN_RC(ptr_reg)); 3953 match(DecodeN reg); 3954 3955 format %{ "[$reg]" %} 3956 interface(MEMORY_INTER) %{ 3957 base($reg); 3958 index(0x4); 3959 scale(0x0); 3960 disp(0x0); 3961 %} 3962%} 3963 3964// Indirect Memory Plus Short Offset Operand 3965operand indOffset8Narrow(rRegN reg, immL8 off) 3966%{ 3967 predicate(CompressedOops::shift() == 0); 3968 constraint(ALLOC_IN_RC(ptr_reg)); 3969 match(AddP (DecodeN reg) off); 3970 3971 format %{ "[$reg + $off (8-bit)]" %} 3972 interface(MEMORY_INTER) %{ 3973 base($reg); 3974 index(0x4); 3975 scale(0x0); 3976 disp($off); 3977 %} 3978%} 3979 3980// Indirect Memory Plus Long Offset Operand 3981operand indOffset32Narrow(rRegN reg, immL32 off) 3982%{ 3983 predicate(CompressedOops::shift() == 0); 3984 constraint(ALLOC_IN_RC(ptr_reg)); 3985 match(AddP (DecodeN reg) off); 3986 3987 format %{ "[$reg + $off (32-bit)]" %} 3988 interface(MEMORY_INTER) %{ 3989 base($reg); 3990 index(0x4); 3991 scale(0x0); 3992 disp($off); 3993 %} 3994%} 3995 3996// Indirect Memory Plus Index Register Plus Offset Operand 3997operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) 3998%{ 3999 predicate(CompressedOops::shift() == 0); 4000 constraint(ALLOC_IN_RC(ptr_reg)); 4001 match(AddP (AddP (DecodeN reg) lreg) off); 4002 4003 op_cost(10); 4004 format %{"[$reg + $off + $lreg]" %} 4005 interface(MEMORY_INTER) %{ 4006 base($reg); 4007 index($lreg); 4008 scale(0x0); 4009 disp($off); 4010 %} 4011%} 4012 4013// Indirect Memory Plus Index Register Plus Offset Operand 4014operand indIndexNarrow(rRegN reg, rRegL lreg) 4015%{ 4016 predicate(CompressedOops::shift() == 0); 4017 constraint(ALLOC_IN_RC(ptr_reg)); 4018 match(AddP (DecodeN reg) lreg); 4019 4020 op_cost(10); 4021 format %{"[$reg + $lreg]" %} 4022 interface(MEMORY_INTER) %{ 4023 base($reg); 4024 index($lreg); 4025 scale(0x0); 4026 disp(0x0); 4027 %} 4028%} 4029 4030// Indirect Memory Times Scale Plus Index Register 4031operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) 4032%{ 4033 predicate(CompressedOops::shift() == 0); 4034 constraint(ALLOC_IN_RC(ptr_reg)); 4035 match(AddP (DecodeN reg) (LShiftL lreg scale)); 4036 4037 op_cost(10); 4038 format %{"[$reg + $lreg << $scale]" %} 4039 interface(MEMORY_INTER) %{ 4040 base($reg); 4041 index($lreg); 4042 scale($scale); 4043 disp(0x0); 4044 %} 4045%} 4046 4047// Indirect Memory Times Scale Plus Index Register Plus Offset Operand 4048operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) 4049%{ 4050 predicate(CompressedOops::shift() == 0); 4051 constraint(ALLOC_IN_RC(ptr_reg)); 4052 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); 4053 4054 op_cost(10); 4055 format %{"[$reg + $off + $lreg << $scale]" %} 4056 interface(MEMORY_INTER) %{ 4057 base($reg); 4058 index($lreg); 4059 scale($scale); 4060 disp($off); 4061 %} 4062%} 4063 4064// Indirect Memory Times Plus Positive Index Register Plus Offset Operand 4065operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx) 4066%{ 4067 constraint(ALLOC_IN_RC(ptr_reg)); 4068 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0); 4069 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off); 4070 4071 op_cost(10); 4072 format %{"[$reg + $off + $idx]" %} 4073 interface(MEMORY_INTER) %{ 4074 base($reg); 4075 index($idx); 4076 scale(0x0); 4077 disp($off); 4078 %} 4079%} 4080 4081// Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand 4082operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) 4083%{ 4084 constraint(ALLOC_IN_RC(ptr_reg)); 4085 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); 4086 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); 4087 4088 op_cost(10); 4089 format %{"[$reg + $off + $idx << $scale]" %} 4090 interface(MEMORY_INTER) %{ 4091 base($reg); 4092 index($idx); 4093 scale($scale); 4094 disp($off); 4095 %} 4096%} 4097 4098//----------Special Memory Operands-------------------------------------------- 4099// Stack Slot Operand - This operand is used for loading and storing temporary 4100// values on the stack where a match requires a value to 4101// flow through memory. 4102operand stackSlotP(sRegP reg) 4103%{ 4104 constraint(ALLOC_IN_RC(stack_slots)); 4105 // No match rule because this operand is only generated in matching 4106 4107 format %{ "[$reg]" %} 4108 interface(MEMORY_INTER) %{ 4109 base(0x4); // RSP 4110 index(0x4); // No Index 4111 scale(0x0); // No Scale 4112 disp($reg); // Stack Offset 4113 %} 4114%} 4115 4116operand stackSlotI(sRegI reg) 4117%{ 4118 constraint(ALLOC_IN_RC(stack_slots)); 4119 // No match rule because this operand is only generated in matching 4120 4121 format %{ "[$reg]" %} 4122 interface(MEMORY_INTER) %{ 4123 base(0x4); // RSP 4124 index(0x4); // No Index 4125 scale(0x0); // No Scale 4126 disp($reg); // Stack Offset 4127 %} 4128%} 4129 4130operand stackSlotF(sRegF reg) 4131%{ 4132 constraint(ALLOC_IN_RC(stack_slots)); 4133 // No match rule because this operand is only generated in matching 4134 4135 format %{ "[$reg]" %} 4136 interface(MEMORY_INTER) %{ 4137 base(0x4); // RSP 4138 index(0x4); // No Index 4139 scale(0x0); // No Scale 4140 disp($reg); // Stack Offset 4141 %} 4142%} 4143 4144operand stackSlotD(sRegD reg) 4145%{ 4146 constraint(ALLOC_IN_RC(stack_slots)); 4147 // No match rule because this operand is only generated in matching 4148 4149 format %{ "[$reg]" %} 4150 interface(MEMORY_INTER) %{ 4151 base(0x4); // RSP 4152 index(0x4); // No Index 4153 scale(0x0); // No Scale 4154 disp($reg); // Stack Offset 4155 %} 4156%} 4157operand stackSlotL(sRegL reg) 4158%{ 4159 constraint(ALLOC_IN_RC(stack_slots)); 4160 // No match rule because this operand is only generated in matching 4161 4162 format %{ "[$reg]" %} 4163 interface(MEMORY_INTER) %{ 4164 base(0x4); // RSP 4165 index(0x4); // No Index 4166 scale(0x0); // No Scale 4167 disp($reg); // Stack Offset 4168 %} 4169%} 4170 4171//----------Conditional Branch Operands---------------------------------------- 4172// Comparison Op - This is the operation of the comparison, and is limited to 4173// the following set of codes: 4174// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4175// 4176// Other attributes of the comparison, such as unsignedness, are specified 4177// by the comparison instruction that sets a condition code flags register. 4178// That result is represented by a flags operand whose subtype is appropriate 4179// to the unsignedness (etc.) of the comparison. 4180// 4181// Later, the instruction which matches both the Comparison Op (a Bool) and 4182// the flags (produced by the Cmp) specifies the coding of the comparison op 4183// by matching a specific subtype of Bool operand below, such as cmpOpU. 4184 4185// Comparision Code 4186operand cmpOp() 4187%{ 4188 match(Bool); 4189 4190 format %{ "" %} 4191 interface(COND_INTER) %{ 4192 equal(0x4, "e"); 4193 not_equal(0x5, "ne"); 4194 less(0xC, "l"); 4195 greater_equal(0xD, "ge"); 4196 less_equal(0xE, "le"); 4197 greater(0xF, "g"); 4198 overflow(0x0, "o"); 4199 no_overflow(0x1, "no"); 4200 %} 4201%} 4202 4203// Comparison Code, unsigned compare. Used by FP also, with 4204// C2 (unordered) turned into GT or LT already. The other bits 4205// C0 and C3 are turned into Carry & Zero flags. 4206operand cmpOpU() 4207%{ 4208 match(Bool); 4209 4210 format %{ "" %} 4211 interface(COND_INTER) %{ 4212 equal(0x4, "e"); 4213 not_equal(0x5, "ne"); 4214 less(0x2, "b"); 4215 greater_equal(0x3, "nb"); 4216 less_equal(0x6, "be"); 4217 greater(0x7, "nbe"); 4218 overflow(0x0, "o"); 4219 no_overflow(0x1, "no"); 4220 %} 4221%} 4222 4223 4224// Floating comparisons that don't require any fixup for the unordered case 4225operand cmpOpUCF() %{ 4226 match(Bool); 4227 predicate(n->as_Bool()->_test._test == BoolTest::lt || 4228 n->as_Bool()->_test._test == BoolTest::ge || 4229 n->as_Bool()->_test._test == BoolTest::le || 4230 n->as_Bool()->_test._test == BoolTest::gt); 4231 format %{ "" %} 4232 interface(COND_INTER) %{ 4233 equal(0x4, "e"); 4234 not_equal(0x5, "ne"); 4235 less(0x2, "b"); 4236 greater_equal(0x3, "nb"); 4237 less_equal(0x6, "be"); 4238 greater(0x7, "nbe"); 4239 overflow(0x0, "o"); 4240 no_overflow(0x1, "no"); 4241 %} 4242%} 4243 4244 4245// Floating comparisons that can be fixed up with extra conditional jumps 4246operand cmpOpUCF2() %{ 4247 match(Bool); 4248 predicate(n->as_Bool()->_test._test == BoolTest::ne || 4249 n->as_Bool()->_test._test == BoolTest::eq); 4250 format %{ "" %} 4251 interface(COND_INTER) %{ 4252 equal(0x4, "e"); 4253 not_equal(0x5, "ne"); 4254 less(0x2, "b"); 4255 greater_equal(0x3, "nb"); 4256 less_equal(0x6, "be"); 4257 greater(0x7, "nbe"); 4258 overflow(0x0, "o"); 4259 no_overflow(0x1, "no"); 4260 %} 4261%} 4262 4263//----------OPERAND CLASSES---------------------------------------------------- 4264// Operand Classes are groups of operands that are used as to simplify 4265// instruction definitions by not requiring the AD writer to specify separate 4266// instructions for every form of operand when the instruction accepts 4267// multiple operand types with the same basic encoding and format. The classic 4268// case of this is memory operands. 4269 4270opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, 4271 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset, 4272 indCompressedOopOffset, 4273 indirectNarrow, indOffset8Narrow, indOffset32Narrow, 4274 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, 4275 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow); 4276 4277//----------PIPELINE----------------------------------------------------------- 4278// Rules which define the behavior of the target architectures pipeline. 4279pipeline %{ 4280 4281//----------ATTRIBUTES--------------------------------------------------------- 4282attributes %{ 4283 variable_size_instructions; // Fixed size instructions 4284 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle 4285 instruction_unit_size = 1; // An instruction is 1 bytes long 4286 instruction_fetch_unit_size = 16; // The processor fetches one line 4287 instruction_fetch_units = 1; // of 16 bytes 4288 4289 // List of nop instructions 4290 nops( MachNop ); 4291%} 4292 4293//----------RESOURCES---------------------------------------------------------- 4294// Resources are the functional units available to the machine 4295 4296// Generic P2/P3 pipeline 4297// 3 decoders, only D0 handles big operands; a "bundle" is the limit of 4298// 3 instructions decoded per cycle. 4299// 2 load/store ops per cycle, 1 branch, 1 FPU, 4300// 3 ALU op, only ALU0 handles mul instructions. 4301resources( D0, D1, D2, DECODE = D0 | D1 | D2, 4302 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, 4303 BR, FPU, 4304 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); 4305 4306//----------PIPELINE DESCRIPTION----------------------------------------------- 4307// Pipeline Description specifies the stages in the machine's pipeline 4308 4309// Generic P2/P3 pipeline 4310pipe_desc(S0, S1, S2, S3, S4, S5); 4311 4312//----------PIPELINE CLASSES--------------------------------------------------- 4313// Pipeline Classes describe the stages in which input and output are 4314// referenced by the hardware pipeline. 4315 4316// Naming convention: ialu or fpu 4317// Then: _reg 4318// Then: _reg if there is a 2nd register 4319// Then: _long if it's a pair of instructions implementing a long 4320// Then: _fat if it requires the big decoder 4321// Or: _mem if it requires the big decoder and a memory unit. 4322 4323// Integer ALU reg operation 4324pipe_class ialu_reg(rRegI dst) 4325%{ 4326 single_instruction; 4327 dst : S4(write); 4328 dst : S3(read); 4329 DECODE : S0; // any decoder 4330 ALU : S3; // any alu 4331%} 4332 4333// Long ALU reg operation 4334pipe_class ialu_reg_long(rRegL dst) 4335%{ 4336 instruction_count(2); 4337 dst : S4(write); 4338 dst : S3(read); 4339 DECODE : S0(2); // any 2 decoders 4340 ALU : S3(2); // both alus 4341%} 4342 4343// Integer ALU reg operation using big decoder 4344pipe_class ialu_reg_fat(rRegI dst) 4345%{ 4346 single_instruction; 4347 dst : S4(write); 4348 dst : S3(read); 4349 D0 : S0; // big decoder only 4350 ALU : S3; // any alu 4351%} 4352 4353// Long ALU reg operation using big decoder 4354pipe_class ialu_reg_long_fat(rRegL dst) 4355%{ 4356 instruction_count(2); 4357 dst : S4(write); 4358 dst : S3(read); 4359 D0 : S0(2); // big decoder only; twice 4360 ALU : S3(2); // any 2 alus 4361%} 4362 4363// Integer ALU reg-reg operation 4364pipe_class ialu_reg_reg(rRegI dst, rRegI src) 4365%{ 4366 single_instruction; 4367 dst : S4(write); 4368 src : S3(read); 4369 DECODE : S0; // any decoder 4370 ALU : S3; // any alu 4371%} 4372 4373// Long ALU reg-reg operation 4374pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) 4375%{ 4376 instruction_count(2); 4377 dst : S4(write); 4378 src : S3(read); 4379 DECODE : S0(2); // any 2 decoders 4380 ALU : S3(2); // both alus 4381%} 4382 4383// Integer ALU reg-reg operation 4384pipe_class ialu_reg_reg_fat(rRegI dst, memory src) 4385%{ 4386 single_instruction; 4387 dst : S4(write); 4388 src : S3(read); 4389 D0 : S0; // big decoder only 4390 ALU : S3; // any alu 4391%} 4392 4393// Long ALU reg-reg operation 4394pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) 4395%{ 4396 instruction_count(2); 4397 dst : S4(write); 4398 src : S3(read); 4399 D0 : S0(2); // big decoder only; twice 4400 ALU : S3(2); // both alus 4401%} 4402 4403// Integer ALU reg-mem operation 4404pipe_class ialu_reg_mem(rRegI dst, memory mem) 4405%{ 4406 single_instruction; 4407 dst : S5(write); 4408 mem : S3(read); 4409 D0 : S0; // big decoder only 4410 ALU : S4; // any alu 4411 MEM : S3; // any mem 4412%} 4413 4414// Integer mem operation (prefetch) 4415pipe_class ialu_mem(memory mem) 4416%{ 4417 single_instruction; 4418 mem : S3(read); 4419 D0 : S0; // big decoder only 4420 MEM : S3; // any mem 4421%} 4422 4423// Integer Store to Memory 4424pipe_class ialu_mem_reg(memory mem, rRegI src) 4425%{ 4426 single_instruction; 4427 mem : S3(read); 4428 src : S5(read); 4429 D0 : S0; // big decoder only 4430 ALU : S4; // any alu 4431 MEM : S3; 4432%} 4433 4434// // Long Store to Memory 4435// pipe_class ialu_mem_long_reg(memory mem, rRegL src) 4436// %{ 4437// instruction_count(2); 4438// mem : S3(read); 4439// src : S5(read); 4440// D0 : S0(2); // big decoder only; twice 4441// ALU : S4(2); // any 2 alus 4442// MEM : S3(2); // Both mems 4443// %} 4444 4445// Integer Store to Memory 4446pipe_class ialu_mem_imm(memory mem) 4447%{ 4448 single_instruction; 4449 mem : S3(read); 4450 D0 : S0; // big decoder only 4451 ALU : S4; // any alu 4452 MEM : S3; 4453%} 4454 4455// Integer ALU0 reg-reg operation 4456pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) 4457%{ 4458 single_instruction; 4459 dst : S4(write); 4460 src : S3(read); 4461 D0 : S0; // Big decoder only 4462 ALU0 : S3; // only alu0 4463%} 4464 4465// Integer ALU0 reg-mem operation 4466pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) 4467%{ 4468 single_instruction; 4469 dst : S5(write); 4470 mem : S3(read); 4471 D0 : S0; // big decoder only 4472 ALU0 : S4; // ALU0 only 4473 MEM : S3; // any mem 4474%} 4475 4476// Integer ALU reg-reg operation 4477pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) 4478%{ 4479 single_instruction; 4480 cr : S4(write); 4481 src1 : S3(read); 4482 src2 : S3(read); 4483 DECODE : S0; // any decoder 4484 ALU : S3; // any alu 4485%} 4486 4487// Integer ALU reg-imm operation 4488pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) 4489%{ 4490 single_instruction; 4491 cr : S4(write); 4492 src1 : S3(read); 4493 DECODE : S0; // any decoder 4494 ALU : S3; // any alu 4495%} 4496 4497// Integer ALU reg-mem operation 4498pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) 4499%{ 4500 single_instruction; 4501 cr : S4(write); 4502 src1 : S3(read); 4503 src2 : S3(read); 4504 D0 : S0; // big decoder only 4505 ALU : S4; // any alu 4506 MEM : S3; 4507%} 4508 4509// Conditional move reg-reg 4510pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) 4511%{ 4512 instruction_count(4); 4513 y : S4(read); 4514 q : S3(read); 4515 p : S3(read); 4516 DECODE : S0(4); // any decoder 4517%} 4518 4519// Conditional move reg-reg 4520pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) 4521%{ 4522 single_instruction; 4523 dst : S4(write); 4524 src : S3(read); 4525 cr : S3(read); 4526 DECODE : S0; // any decoder 4527%} 4528 4529// Conditional move reg-mem 4530pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) 4531%{ 4532 single_instruction; 4533 dst : S4(write); 4534 src : S3(read); 4535 cr : S3(read); 4536 DECODE : S0; // any decoder 4537 MEM : S3; 4538%} 4539 4540// Conditional move reg-reg long 4541pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) 4542%{ 4543 single_instruction; 4544 dst : S4(write); 4545 src : S3(read); 4546 cr : S3(read); 4547 DECODE : S0(2); // any 2 decoders 4548%} 4549 4550// XXX 4551// // Conditional move double reg-reg 4552// pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) 4553// %{ 4554// single_instruction; 4555// dst : S4(write); 4556// src : S3(read); 4557// cr : S3(read); 4558// DECODE : S0; // any decoder 4559// %} 4560 4561// Float reg-reg operation 4562pipe_class fpu_reg(regD dst) 4563%{ 4564 instruction_count(2); 4565 dst : S3(read); 4566 DECODE : S0(2); // any 2 decoders 4567 FPU : S3; 4568%} 4569 4570// Float reg-reg operation 4571pipe_class fpu_reg_reg(regD dst, regD src) 4572%{ 4573 instruction_count(2); 4574 dst : S4(write); 4575 src : S3(read); 4576 DECODE : S0(2); // any 2 decoders 4577 FPU : S3; 4578%} 4579 4580// Float reg-reg operation 4581pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) 4582%{ 4583 instruction_count(3); 4584 dst : S4(write); 4585 src1 : S3(read); 4586 src2 : S3(read); 4587 DECODE : S0(3); // any 3 decoders 4588 FPU : S3(2); 4589%} 4590 4591// Float reg-reg operation 4592pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) 4593%{ 4594 instruction_count(4); 4595 dst : S4(write); 4596 src1 : S3(read); 4597 src2 : S3(read); 4598 src3 : S3(read); 4599 DECODE : S0(4); // any 3 decoders 4600 FPU : S3(2); 4601%} 4602 4603// Float reg-reg operation 4604pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) 4605%{ 4606 instruction_count(4); 4607 dst : S4(write); 4608 src1 : S3(read); 4609 src2 : S3(read); 4610 src3 : S3(read); 4611 DECODE : S1(3); // any 3 decoders 4612 D0 : S0; // Big decoder only 4613 FPU : S3(2); 4614 MEM : S3; 4615%} 4616 4617// Float reg-mem operation 4618pipe_class fpu_reg_mem(regD dst, memory mem) 4619%{ 4620 instruction_count(2); 4621 dst : S5(write); 4622 mem : S3(read); 4623 D0 : S0; // big decoder only 4624 DECODE : S1; // any decoder for FPU POP 4625 FPU : S4; 4626 MEM : S3; // any mem 4627%} 4628 4629// Float reg-mem operation 4630pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) 4631%{ 4632 instruction_count(3); 4633 dst : S5(write); 4634 src1 : S3(read); 4635 mem : S3(read); 4636 D0 : S0; // big decoder only 4637 DECODE : S1(2); // any decoder for FPU POP 4638 FPU : S4; 4639 MEM : S3; // any mem 4640%} 4641 4642// Float mem-reg operation 4643pipe_class fpu_mem_reg(memory mem, regD src) 4644%{ 4645 instruction_count(2); 4646 src : S5(read); 4647 mem : S3(read); 4648 DECODE : S0; // any decoder for FPU PUSH 4649 D0 : S1; // big decoder only 4650 FPU : S4; 4651 MEM : S3; // any mem 4652%} 4653 4654pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) 4655%{ 4656 instruction_count(3); 4657 src1 : S3(read); 4658 src2 : S3(read); 4659 mem : S3(read); 4660 DECODE : S0(2); // any decoder for FPU PUSH 4661 D0 : S1; // big decoder only 4662 FPU : S4; 4663 MEM : S3; // any mem 4664%} 4665 4666pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) 4667%{ 4668 instruction_count(3); 4669 src1 : S3(read); 4670 src2 : S3(read); 4671 mem : S4(read); 4672 DECODE : S0; // any decoder for FPU PUSH 4673 D0 : S0(2); // big decoder only 4674 FPU : S4; 4675 MEM : S3(2); // any mem 4676%} 4677 4678pipe_class fpu_mem_mem(memory dst, memory src1) 4679%{ 4680 instruction_count(2); 4681 src1 : S3(read); 4682 dst : S4(read); 4683 D0 : S0(2); // big decoder only 4684 MEM : S3(2); // any mem 4685%} 4686 4687pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) 4688%{ 4689 instruction_count(3); 4690 src1 : S3(read); 4691 src2 : S3(read); 4692 dst : S4(read); 4693 D0 : S0(3); // big decoder only 4694 FPU : S4; 4695 MEM : S3(3); // any mem 4696%} 4697 4698pipe_class fpu_mem_reg_con(memory mem, regD src1) 4699%{ 4700 instruction_count(3); 4701 src1 : S4(read); 4702 mem : S4(read); 4703 DECODE : S0; // any decoder for FPU PUSH 4704 D0 : S0(2); // big decoder only 4705 FPU : S4; 4706 MEM : S3(2); // any mem 4707%} 4708 4709// Float load constant 4710pipe_class fpu_reg_con(regD dst) 4711%{ 4712 instruction_count(2); 4713 dst : S5(write); 4714 D0 : S0; // big decoder only for the load 4715 DECODE : S1; // any decoder for FPU POP 4716 FPU : S4; 4717 MEM : S3; // any mem 4718%} 4719 4720// Float load constant 4721pipe_class fpu_reg_reg_con(regD dst, regD src) 4722%{ 4723 instruction_count(3); 4724 dst : S5(write); 4725 src : S3(read); 4726 D0 : S0; // big decoder only for the load 4727 DECODE : S1(2); // any decoder for FPU POP 4728 FPU : S4; 4729 MEM : S3; // any mem 4730%} 4731 4732// UnConditional branch 4733pipe_class pipe_jmp(label labl) 4734%{ 4735 single_instruction; 4736 BR : S3; 4737%} 4738 4739// Conditional branch 4740pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) 4741%{ 4742 single_instruction; 4743 cr : S1(read); 4744 BR : S3; 4745%} 4746 4747// Allocation idiom 4748pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) 4749%{ 4750 instruction_count(1); force_serialization; 4751 fixed_latency(6); 4752 heap_ptr : S3(read); 4753 DECODE : S0(3); 4754 D0 : S2; 4755 MEM : S3; 4756 ALU : S3(2); 4757 dst : S5(write); 4758 BR : S5; 4759%} 4760 4761// Generic big/slow expanded idiom 4762pipe_class pipe_slow() 4763%{ 4764 instruction_count(10); multiple_bundles; force_serialization; 4765 fixed_latency(100); 4766 D0 : S0(2); 4767 MEM : S3(2); 4768%} 4769 4770// The real do-nothing guy 4771pipe_class empty() 4772%{ 4773 instruction_count(0); 4774%} 4775 4776// Define the class for the Nop node 4777define 4778%{ 4779 MachNop = empty; 4780%} 4781 4782%} 4783 4784//----------INSTRUCTIONS------------------------------------------------------- 4785// 4786// match -- States which machine-independent subtree may be replaced 4787// by this instruction. 4788// ins_cost -- The estimated cost of this instruction is used by instruction 4789// selection to identify a minimum cost tree of machine 4790// instructions that matches a tree of machine-independent 4791// instructions. 4792// format -- A string providing the disassembly for this instruction. 4793// The value of an instruction's operand may be inserted 4794// by referring to it with a '$' prefix. 4795// opcode -- Three instruction opcodes may be provided. These are referred 4796// to within an encode class as $primary, $secondary, and $tertiary 4797// rrspectively. The primary opcode is commonly used to 4798// indicate the type of machine instruction, while secondary 4799// and tertiary are often used for prefix options or addressing 4800// modes. 4801// ins_encode -- A list of encode classes with parameters. The encode class 4802// name must have been defined in an 'enc_class' specification 4803// in the encode section of the architecture description. 4804 4805 4806//----------Load/Store/Move Instructions--------------------------------------- 4807//----------Load Instructions-------------------------------------------------- 4808 4809// Load Byte (8 bit signed) 4810instruct loadB(rRegI dst, memory mem) 4811%{ 4812 match(Set dst (LoadB mem)); 4813 4814 ins_cost(125); 4815 format %{ "movsbl $dst, $mem\t# byte" %} 4816 4817 ins_encode %{ 4818 __ movsbl($dst$$Register, $mem$$Address); 4819 %} 4820 4821 ins_pipe(ialu_reg_mem); 4822%} 4823 4824// Load Byte (8 bit signed) into Long Register 4825instruct loadB2L(rRegL dst, memory mem) 4826%{ 4827 match(Set dst (ConvI2L (LoadB mem))); 4828 4829 ins_cost(125); 4830 format %{ "movsbq $dst, $mem\t# byte -> long" %} 4831 4832 ins_encode %{ 4833 __ movsbq($dst$$Register, $mem$$Address); 4834 %} 4835 4836 ins_pipe(ialu_reg_mem); 4837%} 4838 4839// Load Unsigned Byte (8 bit UNsigned) 4840instruct loadUB(rRegI dst, memory mem) 4841%{ 4842 match(Set dst (LoadUB mem)); 4843 4844 ins_cost(125); 4845 format %{ "movzbl $dst, $mem\t# ubyte" %} 4846 4847 ins_encode %{ 4848 __ movzbl($dst$$Register, $mem$$Address); 4849 %} 4850 4851 ins_pipe(ialu_reg_mem); 4852%} 4853 4854// Load Unsigned Byte (8 bit UNsigned) into Long Register 4855instruct loadUB2L(rRegL dst, memory mem) 4856%{ 4857 match(Set dst (ConvI2L (LoadUB mem))); 4858 4859 ins_cost(125); 4860 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} 4861 4862 ins_encode %{ 4863 __ movzbq($dst$$Register, $mem$$Address); 4864 %} 4865 4866 ins_pipe(ialu_reg_mem); 4867%} 4868 4869// Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register 4870instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{ 4871 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 4872 effect(KILL cr); 4873 4874 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t" 4875 "andl $dst, right_n_bits($mask, 8)" %} 4876 ins_encode %{ 4877 Register Rdst = $dst$$Register; 4878 __ movzbq(Rdst, $mem$$Address); 4879 __ andl(Rdst, $mask$$constant & right_n_bits(8)); 4880 %} 4881 ins_pipe(ialu_reg_mem); 4882%} 4883 4884// Load Short (16 bit signed) 4885instruct loadS(rRegI dst, memory mem) 4886%{ 4887 match(Set dst (LoadS mem)); 4888 4889 ins_cost(125); 4890 format %{ "movswl $dst, $mem\t# short" %} 4891 4892 ins_encode %{ 4893 __ movswl($dst$$Register, $mem$$Address); 4894 %} 4895 4896 ins_pipe(ialu_reg_mem); 4897%} 4898 4899// Load Short (16 bit signed) to Byte (8 bit signed) 4900instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ 4901 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 4902 4903 ins_cost(125); 4904 format %{ "movsbl $dst, $mem\t# short -> byte" %} 4905 ins_encode %{ 4906 __ movsbl($dst$$Register, $mem$$Address); 4907 %} 4908 ins_pipe(ialu_reg_mem); 4909%} 4910 4911// Load Short (16 bit signed) into Long Register 4912instruct loadS2L(rRegL dst, memory mem) 4913%{ 4914 match(Set dst (ConvI2L (LoadS mem))); 4915 4916 ins_cost(125); 4917 format %{ "movswq $dst, $mem\t# short -> long" %} 4918 4919 ins_encode %{ 4920 __ movswq($dst$$Register, $mem$$Address); 4921 %} 4922 4923 ins_pipe(ialu_reg_mem); 4924%} 4925 4926// Load Unsigned Short/Char (16 bit UNsigned) 4927instruct loadUS(rRegI dst, memory mem) 4928%{ 4929 match(Set dst (LoadUS mem)); 4930 4931 ins_cost(125); 4932 format %{ "movzwl $dst, $mem\t# ushort/char" %} 4933 4934 ins_encode %{ 4935 __ movzwl($dst$$Register, $mem$$Address); 4936 %} 4937 4938 ins_pipe(ialu_reg_mem); 4939%} 4940 4941// Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 4942instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ 4943 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 4944 4945 ins_cost(125); 4946 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} 4947 ins_encode %{ 4948 __ movsbl($dst$$Register, $mem$$Address); 4949 %} 4950 ins_pipe(ialu_reg_mem); 4951%} 4952 4953// Load Unsigned Short/Char (16 bit UNsigned) into Long Register 4954instruct loadUS2L(rRegL dst, memory mem) 4955%{ 4956 match(Set dst (ConvI2L (LoadUS mem))); 4957 4958 ins_cost(125); 4959 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} 4960 4961 ins_encode %{ 4962 __ movzwq($dst$$Register, $mem$$Address); 4963 %} 4964 4965 ins_pipe(ialu_reg_mem); 4966%} 4967 4968// Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register 4969instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ 4970 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 4971 4972 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} 4973 ins_encode %{ 4974 __ movzbq($dst$$Register, $mem$$Address); 4975 %} 4976 ins_pipe(ialu_reg_mem); 4977%} 4978 4979// Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register 4980instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{ 4981 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 4982 effect(KILL cr); 4983 4984 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t" 4985 "andl $dst, right_n_bits($mask, 16)" %} 4986 ins_encode %{ 4987 Register Rdst = $dst$$Register; 4988 __ movzwq(Rdst, $mem$$Address); 4989 __ andl(Rdst, $mask$$constant & right_n_bits(16)); 4990 %} 4991 ins_pipe(ialu_reg_mem); 4992%} 4993 4994// Load Integer 4995instruct loadI(rRegI dst, memory mem) 4996%{ 4997 match(Set dst (LoadI mem)); 4998 4999 ins_cost(125); 5000 format %{ "movl $dst, $mem\t# int" %} 5001 5002 ins_encode %{ 5003 __ movl($dst$$Register, $mem$$Address); 5004 %} 5005 5006 ins_pipe(ialu_reg_mem); 5007%} 5008 5009// Load Integer (32 bit signed) to Byte (8 bit signed) 5010instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ 5011 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5012 5013 ins_cost(125); 5014 format %{ "movsbl $dst, $mem\t# int -> byte" %} 5015 ins_encode %{ 5016 __ movsbl($dst$$Register, $mem$$Address); 5017 %} 5018 ins_pipe(ialu_reg_mem); 5019%} 5020 5021// Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) 5022instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ 5023 match(Set dst (AndI (LoadI mem) mask)); 5024 5025 ins_cost(125); 5026 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} 5027 ins_encode %{ 5028 __ movzbl($dst$$Register, $mem$$Address); 5029 %} 5030 ins_pipe(ialu_reg_mem); 5031%} 5032 5033// Load Integer (32 bit signed) to Short (16 bit signed) 5034instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ 5035 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5036 5037 ins_cost(125); 5038 format %{ "movswl $dst, $mem\t# int -> short" %} 5039 ins_encode %{ 5040 __ movswl($dst$$Register, $mem$$Address); 5041 %} 5042 ins_pipe(ialu_reg_mem); 5043%} 5044 5045// Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) 5046instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ 5047 match(Set dst (AndI (LoadI mem) mask)); 5048 5049 ins_cost(125); 5050 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} 5051 ins_encode %{ 5052 __ movzwl($dst$$Register, $mem$$Address); 5053 %} 5054 ins_pipe(ialu_reg_mem); 5055%} 5056 5057// Load Integer into Long Register 5058instruct loadI2L(rRegL dst, memory mem) 5059%{ 5060 match(Set dst (ConvI2L (LoadI mem))); 5061 5062 ins_cost(125); 5063 format %{ "movslq $dst, $mem\t# int -> long" %} 5064 5065 ins_encode %{ 5066 __ movslq($dst$$Register, $mem$$Address); 5067 %} 5068 5069 ins_pipe(ialu_reg_mem); 5070%} 5071 5072// Load Integer with mask 0xFF into Long Register 5073instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ 5074 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5075 5076 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} 5077 ins_encode %{ 5078 __ movzbq($dst$$Register, $mem$$Address); 5079 %} 5080 ins_pipe(ialu_reg_mem); 5081%} 5082 5083// Load Integer with mask 0xFFFF into Long Register 5084instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ 5085 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5086 5087 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} 5088 ins_encode %{ 5089 __ movzwq($dst$$Register, $mem$$Address); 5090 %} 5091 ins_pipe(ialu_reg_mem); 5092%} 5093 5094// Load Integer with a 31-bit mask into Long Register 5095instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{ 5096 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5097 effect(KILL cr); 5098 5099 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t" 5100 "andl $dst, $mask" %} 5101 ins_encode %{ 5102 Register Rdst = $dst$$Register; 5103 __ movl(Rdst, $mem$$Address); 5104 __ andl(Rdst, $mask$$constant); 5105 %} 5106 ins_pipe(ialu_reg_mem); 5107%} 5108 5109// Load Unsigned Integer into Long Register 5110instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask) 5111%{ 5112 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5113 5114 ins_cost(125); 5115 format %{ "movl $dst, $mem\t# uint -> long" %} 5116 5117 ins_encode %{ 5118 __ movl($dst$$Register, $mem$$Address); 5119 %} 5120 5121 ins_pipe(ialu_reg_mem); 5122%} 5123 5124// Load Long 5125instruct loadL(rRegL dst, memory mem) 5126%{ 5127 match(Set dst (LoadL mem)); 5128 5129 ins_cost(125); 5130 format %{ "movq $dst, $mem\t# long" %} 5131 5132 ins_encode %{ 5133 __ movq($dst$$Register, $mem$$Address); 5134 %} 5135 5136 ins_pipe(ialu_reg_mem); // XXX 5137%} 5138 5139// Load Range 5140instruct loadRange(rRegI dst, memory mem) 5141%{ 5142 match(Set dst (LoadRange mem)); 5143 5144 ins_cost(125); // XXX 5145 format %{ "movl $dst, $mem\t# range" %} 5146 opcode(0x8B); 5147 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); 5148 ins_pipe(ialu_reg_mem); 5149%} 5150 5151// Load Pointer 5152instruct loadP(rRegP dst, memory mem) 5153%{ 5154 match(Set dst (LoadP mem)); 5155 predicate(n->as_Load()->barrier_data() == 0); 5156 5157 ins_cost(125); // XXX 5158 format %{ "movq $dst, $mem\t# ptr" %} 5159 opcode(0x8B); 5160 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5161 ins_pipe(ialu_reg_mem); // XXX 5162%} 5163 5164// Load Compressed Pointer 5165instruct loadN(rRegN dst, memory mem) 5166%{ 5167 match(Set dst (LoadN mem)); 5168 5169 ins_cost(125); // XXX 5170 format %{ "movl $dst, $mem\t# compressed ptr" %} 5171 ins_encode %{ 5172 __ movl($dst$$Register, $mem$$Address); 5173 %} 5174 ins_pipe(ialu_reg_mem); // XXX 5175%} 5176 5177 5178// Load Klass Pointer 5179instruct loadKlass(rRegP dst, memory mem) 5180%{ 5181 match(Set dst (LoadKlass mem)); 5182 5183 ins_cost(125); // XXX 5184 format %{ "movq $dst, $mem\t# class" %} 5185 opcode(0x8B); 5186 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5187 ins_pipe(ialu_reg_mem); // XXX 5188%} 5189 5190// Load narrow Klass Pointer 5191instruct loadNKlass(rRegN dst, memory mem) 5192%{ 5193 match(Set dst (LoadNKlass mem)); 5194 5195 ins_cost(125); // XXX 5196 format %{ "movl $dst, $mem\t# compressed klass ptr" %} 5197 ins_encode %{ 5198 __ movl($dst$$Register, $mem$$Address); 5199 %} 5200 ins_pipe(ialu_reg_mem); // XXX 5201%} 5202 5203// Load Float 5204instruct loadF(regF dst, memory mem) 5205%{ 5206 match(Set dst (LoadF mem)); 5207 5208 ins_cost(145); // XXX 5209 format %{ "movss $dst, $mem\t# float" %} 5210 ins_encode %{ 5211 __ movflt($dst$$XMMRegister, $mem$$Address); 5212 %} 5213 ins_pipe(pipe_slow); // XXX 5214%} 5215 5216// Load Float 5217instruct MoveF2VL(vlRegF dst, regF src) %{ 5218 match(Set dst src); 5219 format %{ "movss $dst,$src\t! load float (4 bytes)" %} 5220 ins_encode %{ 5221 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 5222 %} 5223 ins_pipe( fpu_reg_reg ); 5224%} 5225 5226// Load Float 5227instruct MoveF2LEG(legRegF dst, regF src) %{ 5228 match(Set dst src); 5229 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %} 5230 ins_encode %{ 5231 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 5232 %} 5233 ins_pipe( fpu_reg_reg ); 5234%} 5235 5236// Load Float 5237instruct MoveVL2F(regF dst, vlRegF src) %{ 5238 match(Set dst src); 5239 format %{ "movss $dst,$src\t! load float (4 bytes)" %} 5240 ins_encode %{ 5241 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 5242 %} 5243 ins_pipe( fpu_reg_reg ); 5244%} 5245 5246// Load Float 5247instruct MoveLEG2F(regF dst, legRegF src) %{ 5248 match(Set dst src); 5249 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %} 5250 ins_encode %{ 5251 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 5252 %} 5253 ins_pipe( fpu_reg_reg ); 5254%} 5255 5256// Load Double 5257instruct loadD_partial(regD dst, memory mem) 5258%{ 5259 predicate(!UseXmmLoadAndClearUpper); 5260 match(Set dst (LoadD mem)); 5261 5262 ins_cost(145); // XXX 5263 format %{ "movlpd $dst, $mem\t# double" %} 5264 ins_encode %{ 5265 __ movdbl($dst$$XMMRegister, $mem$$Address); 5266 %} 5267 ins_pipe(pipe_slow); // XXX 5268%} 5269 5270instruct loadD(regD dst, memory mem) 5271%{ 5272 predicate(UseXmmLoadAndClearUpper); 5273 match(Set dst (LoadD mem)); 5274 5275 ins_cost(145); // XXX 5276 format %{ "movsd $dst, $mem\t# double" %} 5277 ins_encode %{ 5278 __ movdbl($dst$$XMMRegister, $mem$$Address); 5279 %} 5280 ins_pipe(pipe_slow); // XXX 5281%} 5282 5283// Load Double 5284instruct MoveD2VL(vlRegD dst, regD src) %{ 5285 match(Set dst src); 5286 format %{ "movsd $dst,$src\t! load double (8 bytes)" %} 5287 ins_encode %{ 5288 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 5289 %} 5290 ins_pipe( fpu_reg_reg ); 5291%} 5292 5293// Load Double 5294instruct MoveD2LEG(legRegD dst, regD src) %{ 5295 match(Set dst src); 5296 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %} 5297 ins_encode %{ 5298 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 5299 %} 5300 ins_pipe( fpu_reg_reg ); 5301%} 5302 5303// Load Double 5304instruct MoveVL2D(regD dst, vlRegD src) %{ 5305 match(Set dst src); 5306 format %{ "movsd $dst,$src\t! load double (8 bytes)" %} 5307 ins_encode %{ 5308 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 5309 %} 5310 ins_pipe( fpu_reg_reg ); 5311%} 5312 5313// Load Double 5314instruct MoveLEG2D(regD dst, legRegD src) %{ 5315 match(Set dst src); 5316 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %} 5317 ins_encode %{ 5318 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 5319 %} 5320 ins_pipe( fpu_reg_reg ); 5321%} 5322 5323// Following pseudo code describes the algorithm for max[FD]: 5324// Min algorithm is on similar lines 5325// btmp = (b < +0.0) ? a : b 5326// atmp = (b < +0.0) ? b : a 5327// Tmp = Max_Float(atmp , btmp) 5328// Res = (atmp == NaN) ? atmp : Tmp 5329 5330// max = java.lang.Math.max(float a, float b) 5331instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{ 5332 predicate(UseAVX > 0 && !n->is_reduction()); 5333 match(Set dst (MaxF a b)); 5334 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp); 5335 format %{ 5336 "blendvps $btmp,$b,$a,$b \n\t" 5337 "blendvps $atmp,$a,$b,$b \n\t" 5338 "vmaxss $tmp,$atmp,$btmp \n\t" 5339 "cmpps.unordered $btmp,$atmp,$atmp \n\t" 5340 "blendvps $dst,$tmp,$atmp,$btmp \n\t" 5341 %} 5342 ins_encode %{ 5343 int vector_len = Assembler::AVX_128bit; 5344 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len); 5345 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len); 5346 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister); 5347 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len); 5348 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); 5349 %} 5350 ins_pipe( pipe_slow ); 5351%} 5352 5353instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{ 5354 predicate(UseAVX > 0 && n->is_reduction()); 5355 match(Set dst (MaxF a b)); 5356 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); 5357 5358 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %} 5359 ins_encode %{ 5360 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register, 5361 false /*min*/, true /*single*/); 5362 %} 5363 ins_pipe( pipe_slow ); 5364%} 5365 5366// max = java.lang.Math.max(double a, double b) 5367instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{ 5368 predicate(UseAVX > 0 && !n->is_reduction()); 5369 match(Set dst (MaxD a b)); 5370 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp); 5371 format %{ 5372 "blendvpd $btmp,$b,$a,$b \n\t" 5373 "blendvpd $atmp,$a,$b,$b \n\t" 5374 "vmaxsd $tmp,$atmp,$btmp \n\t" 5375 "cmppd.unordered $btmp,$atmp,$atmp \n\t" 5376 "blendvpd $dst,$tmp,$atmp,$btmp \n\t" 5377 %} 5378 ins_encode %{ 5379 int vector_len = Assembler::AVX_128bit; 5380 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len); 5381 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len); 5382 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister); 5383 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len); 5384 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); 5385 %} 5386 ins_pipe( pipe_slow ); 5387%} 5388 5389instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{ 5390 predicate(UseAVX > 0 && n->is_reduction()); 5391 match(Set dst (MaxD a b)); 5392 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); 5393 5394 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %} 5395 ins_encode %{ 5396 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register, 5397 false /*min*/, false /*single*/); 5398 %} 5399 ins_pipe( pipe_slow ); 5400%} 5401 5402// min = java.lang.Math.min(float a, float b) 5403instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{ 5404 predicate(UseAVX > 0 && !n->is_reduction()); 5405 match(Set dst (MinF a b)); 5406 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp); 5407 format %{ 5408 "blendvps $atmp,$a,$b,$a \n\t" 5409 "blendvps $btmp,$b,$a,$a \n\t" 5410 "vminss $tmp,$atmp,$btmp \n\t" 5411 "cmpps.unordered $btmp,$atmp,$atmp \n\t" 5412 "blendvps $dst,$tmp,$atmp,$btmp \n\t" 5413 %} 5414 ins_encode %{ 5415 int vector_len = Assembler::AVX_128bit; 5416 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len); 5417 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len); 5418 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister); 5419 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len); 5420 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); 5421 %} 5422 ins_pipe( pipe_slow ); 5423%} 5424 5425instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{ 5426 predicate(UseAVX > 0 && n->is_reduction()); 5427 match(Set dst (MinF a b)); 5428 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); 5429 5430 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %} 5431 ins_encode %{ 5432 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register, 5433 true /*min*/, true /*single*/); 5434 %} 5435 ins_pipe( pipe_slow ); 5436%} 5437 5438// min = java.lang.Math.min(double a, double b) 5439instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{ 5440 predicate(UseAVX > 0 && !n->is_reduction()); 5441 match(Set dst (MinD a b)); 5442 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp); 5443 format %{ 5444 "blendvpd $atmp,$a,$b,$a \n\t" 5445 "blendvpd $btmp,$b,$a,$a \n\t" 5446 "vminsd $tmp,$atmp,$btmp \n\t" 5447 "cmppd.unordered $btmp,$atmp,$atmp \n\t" 5448 "blendvpd $dst,$tmp,$atmp,$btmp \n\t" 5449 %} 5450 ins_encode %{ 5451 int vector_len = Assembler::AVX_128bit; 5452 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len); 5453 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len); 5454 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister); 5455 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len); 5456 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); 5457 %} 5458 ins_pipe( pipe_slow ); 5459%} 5460 5461instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{ 5462 predicate(UseAVX > 0 && n->is_reduction()); 5463 match(Set dst (MinD a b)); 5464 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); 5465 5466 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %} 5467 ins_encode %{ 5468 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register, 5469 true /*min*/, false /*single*/); 5470 %} 5471 ins_pipe( pipe_slow ); 5472%} 5473 5474// Load Effective Address 5475instruct leaP8(rRegP dst, indOffset8 mem) 5476%{ 5477 match(Set dst mem); 5478 5479 ins_cost(110); // XXX 5480 format %{ "leaq $dst, $mem\t# ptr 8" %} 5481 opcode(0x8D); 5482 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5483 ins_pipe(ialu_reg_reg_fat); 5484%} 5485 5486instruct leaP32(rRegP dst, indOffset32 mem) 5487%{ 5488 match(Set dst mem); 5489 5490 ins_cost(110); 5491 format %{ "leaq $dst, $mem\t# ptr 32" %} 5492 opcode(0x8D); 5493 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5494 ins_pipe(ialu_reg_reg_fat); 5495%} 5496 5497// instruct leaPIdx(rRegP dst, indIndex mem) 5498// %{ 5499// match(Set dst mem); 5500 5501// ins_cost(110); 5502// format %{ "leaq $dst, $mem\t# ptr idx" %} 5503// opcode(0x8D); 5504// ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5505// ins_pipe(ialu_reg_reg_fat); 5506// %} 5507 5508instruct leaPIdxOff(rRegP dst, indIndexOffset mem) 5509%{ 5510 match(Set dst mem); 5511 5512 ins_cost(110); 5513 format %{ "leaq $dst, $mem\t# ptr idxoff" %} 5514 opcode(0x8D); 5515 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5516 ins_pipe(ialu_reg_reg_fat); 5517%} 5518 5519instruct leaPIdxScale(rRegP dst, indIndexScale mem) 5520%{ 5521 match(Set dst mem); 5522 5523 ins_cost(110); 5524 format %{ "leaq $dst, $mem\t# ptr idxscale" %} 5525 opcode(0x8D); 5526 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5527 ins_pipe(ialu_reg_reg_fat); 5528%} 5529 5530instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem) 5531%{ 5532 match(Set dst mem); 5533 5534 ins_cost(110); 5535 format %{ "leaq $dst, $mem\t# ptr idxscale" %} 5536 opcode(0x8D); 5537 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5538 ins_pipe(ialu_reg_reg_fat); 5539%} 5540 5541instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) 5542%{ 5543 match(Set dst mem); 5544 5545 ins_cost(110); 5546 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} 5547 opcode(0x8D); 5548 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5549 ins_pipe(ialu_reg_reg_fat); 5550%} 5551 5552instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem) 5553%{ 5554 match(Set dst mem); 5555 5556 ins_cost(110); 5557 format %{ "leaq $dst, $mem\t# ptr posidxoff" %} 5558 opcode(0x8D); 5559 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5560 ins_pipe(ialu_reg_reg_fat); 5561%} 5562 5563instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) 5564%{ 5565 match(Set dst mem); 5566 5567 ins_cost(110); 5568 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} 5569 opcode(0x8D); 5570 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5571 ins_pipe(ialu_reg_reg_fat); 5572%} 5573 5574// Load Effective Address which uses Narrow (32-bits) oop 5575instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) 5576%{ 5577 predicate(UseCompressedOops && (CompressedOops::shift() != 0)); 5578 match(Set dst mem); 5579 5580 ins_cost(110); 5581 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} 5582 opcode(0x8D); 5583 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5584 ins_pipe(ialu_reg_reg_fat); 5585%} 5586 5587instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) 5588%{ 5589 predicate(CompressedOops::shift() == 0); 5590 match(Set dst mem); 5591 5592 ins_cost(110); // XXX 5593 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} 5594 opcode(0x8D); 5595 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5596 ins_pipe(ialu_reg_reg_fat); 5597%} 5598 5599instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) 5600%{ 5601 predicate(CompressedOops::shift() == 0); 5602 match(Set dst mem); 5603 5604 ins_cost(110); 5605 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} 5606 opcode(0x8D); 5607 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5608 ins_pipe(ialu_reg_reg_fat); 5609%} 5610 5611instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) 5612%{ 5613 predicate(CompressedOops::shift() == 0); 5614 match(Set dst mem); 5615 5616 ins_cost(110); 5617 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} 5618 opcode(0x8D); 5619 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5620 ins_pipe(ialu_reg_reg_fat); 5621%} 5622 5623instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) 5624%{ 5625 predicate(CompressedOops::shift() == 0); 5626 match(Set dst mem); 5627 5628 ins_cost(110); 5629 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} 5630 opcode(0x8D); 5631 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5632 ins_pipe(ialu_reg_reg_fat); 5633%} 5634 5635instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) 5636%{ 5637 predicate(CompressedOops::shift() == 0); 5638 match(Set dst mem); 5639 5640 ins_cost(110); 5641 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} 5642 opcode(0x8D); 5643 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5644 ins_pipe(ialu_reg_reg_fat); 5645%} 5646 5647instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem) 5648%{ 5649 predicate(CompressedOops::shift() == 0); 5650 match(Set dst mem); 5651 5652 ins_cost(110); 5653 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %} 5654 opcode(0x8D); 5655 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5656 ins_pipe(ialu_reg_reg_fat); 5657%} 5658 5659instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) 5660%{ 5661 predicate(CompressedOops::shift() == 0); 5662 match(Set dst mem); 5663 5664 ins_cost(110); 5665 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} 5666 opcode(0x8D); 5667 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 5668 ins_pipe(ialu_reg_reg_fat); 5669%} 5670 5671instruct loadConI(rRegI dst, immI src) 5672%{ 5673 match(Set dst src); 5674 5675 format %{ "movl $dst, $src\t# int" %} 5676 ins_encode(load_immI(dst, src)); 5677 ins_pipe(ialu_reg_fat); // XXX 5678%} 5679 5680instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) 5681%{ 5682 match(Set dst src); 5683 effect(KILL cr); 5684 5685 ins_cost(50); 5686 format %{ "xorl $dst, $dst\t# int" %} 5687 opcode(0x33); /* + rd */ 5688 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); 5689 ins_pipe(ialu_reg); 5690%} 5691 5692instruct loadConL(rRegL dst, immL src) 5693%{ 5694 match(Set dst src); 5695 5696 ins_cost(150); 5697 format %{ "movq $dst, $src\t# long" %} 5698 ins_encode(load_immL(dst, src)); 5699 ins_pipe(ialu_reg); 5700%} 5701 5702instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) 5703%{ 5704 match(Set dst src); 5705 effect(KILL cr); 5706 5707 ins_cost(50); 5708 format %{ "xorl $dst, $dst\t# long" %} 5709 opcode(0x33); /* + rd */ 5710 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); 5711 ins_pipe(ialu_reg); // XXX 5712%} 5713 5714instruct loadConUL32(rRegL dst, immUL32 src) 5715%{ 5716 match(Set dst src); 5717 5718 ins_cost(60); 5719 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} 5720 ins_encode(load_immUL32(dst, src)); 5721 ins_pipe(ialu_reg); 5722%} 5723 5724instruct loadConL32(rRegL dst, immL32 src) 5725%{ 5726 match(Set dst src); 5727 5728 ins_cost(70); 5729 format %{ "movq $dst, $src\t# long (32-bit)" %} 5730 ins_encode(load_immL32(dst, src)); 5731 ins_pipe(ialu_reg); 5732%} 5733 5734instruct loadConP(rRegP dst, immP con) %{ 5735 match(Set dst con); 5736 5737 format %{ "movq $dst, $con\t# ptr" %} 5738 ins_encode(load_immP(dst, con)); 5739 ins_pipe(ialu_reg_fat); // XXX 5740%} 5741 5742instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) 5743%{ 5744 match(Set dst src); 5745 effect(KILL cr); 5746 5747 ins_cost(50); 5748 format %{ "xorl $dst, $dst\t# ptr" %} 5749 opcode(0x33); /* + rd */ 5750 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); 5751 ins_pipe(ialu_reg); 5752%} 5753 5754instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) 5755%{ 5756 match(Set dst src); 5757 effect(KILL cr); 5758 5759 ins_cost(60); 5760 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} 5761 ins_encode(load_immP31(dst, src)); 5762 ins_pipe(ialu_reg); 5763%} 5764 5765instruct loadConF(regF dst, immF con) %{ 5766 match(Set dst con); 5767 ins_cost(125); 5768 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} 5769 ins_encode %{ 5770 __ movflt($dst$$XMMRegister, $constantaddress($con)); 5771 %} 5772 ins_pipe(pipe_slow); 5773%} 5774 5775instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ 5776 match(Set dst src); 5777 effect(KILL cr); 5778 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} 5779 ins_encode %{ 5780 __ xorq($dst$$Register, $dst$$Register); 5781 %} 5782 ins_pipe(ialu_reg); 5783%} 5784 5785instruct loadConN(rRegN dst, immN src) %{ 5786 match(Set dst src); 5787 5788 ins_cost(125); 5789 format %{ "movl $dst, $src\t# compressed ptr" %} 5790 ins_encode %{ 5791 address con = (address)$src$$constant; 5792 if (con == NULL) { 5793 ShouldNotReachHere(); 5794 } else { 5795 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); 5796 } 5797 %} 5798 ins_pipe(ialu_reg_fat); // XXX 5799%} 5800 5801instruct loadConNKlass(rRegN dst, immNKlass src) %{ 5802 match(Set dst src); 5803 5804 ins_cost(125); 5805 format %{ "movl $dst, $src\t# compressed klass ptr" %} 5806 ins_encode %{ 5807 address con = (address)$src$$constant; 5808 if (con == NULL) { 5809 ShouldNotReachHere(); 5810 } else { 5811 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant); 5812 } 5813 %} 5814 ins_pipe(ialu_reg_fat); // XXX 5815%} 5816 5817instruct loadConF0(regF dst, immF0 src) 5818%{ 5819 match(Set dst src); 5820 ins_cost(100); 5821 5822 format %{ "xorps $dst, $dst\t# float 0.0" %} 5823 ins_encode %{ 5824 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); 5825 %} 5826 ins_pipe(pipe_slow); 5827%} 5828 5829// Use the same format since predicate() can not be used here. 5830instruct loadConD(regD dst, immD con) %{ 5831 match(Set dst con); 5832 ins_cost(125); 5833 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} 5834 ins_encode %{ 5835 __ movdbl($dst$$XMMRegister, $constantaddress($con)); 5836 %} 5837 ins_pipe(pipe_slow); 5838%} 5839 5840instruct loadConD0(regD dst, immD0 src) 5841%{ 5842 match(Set dst src); 5843 ins_cost(100); 5844 5845 format %{ "xorpd $dst, $dst\t# double 0.0" %} 5846 ins_encode %{ 5847 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); 5848 %} 5849 ins_pipe(pipe_slow); 5850%} 5851 5852instruct loadSSI(rRegI dst, stackSlotI src) 5853%{ 5854 match(Set dst src); 5855 5856 ins_cost(125); 5857 format %{ "movl $dst, $src\t# int stk" %} 5858 opcode(0x8B); 5859 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); 5860 ins_pipe(ialu_reg_mem); 5861%} 5862 5863instruct loadSSL(rRegL dst, stackSlotL src) 5864%{ 5865 match(Set dst src); 5866 5867 ins_cost(125); 5868 format %{ "movq $dst, $src\t# long stk" %} 5869 opcode(0x8B); 5870 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); 5871 ins_pipe(ialu_reg_mem); 5872%} 5873 5874instruct loadSSP(rRegP dst, stackSlotP src) 5875%{ 5876 match(Set dst src); 5877 5878 ins_cost(125); 5879 format %{ "movq $dst, $src\t# ptr stk" %} 5880 opcode(0x8B); 5881 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); 5882 ins_pipe(ialu_reg_mem); 5883%} 5884 5885instruct loadSSF(regF dst, stackSlotF src) 5886%{ 5887 match(Set dst src); 5888 5889 ins_cost(125); 5890 format %{ "movss $dst, $src\t# float stk" %} 5891 ins_encode %{ 5892 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); 5893 %} 5894 ins_pipe(pipe_slow); // XXX 5895%} 5896 5897// Use the same format since predicate() can not be used here. 5898instruct loadSSD(regD dst, stackSlotD src) 5899%{ 5900 match(Set dst src); 5901 5902 ins_cost(125); 5903 format %{ "movsd $dst, $src\t# double stk" %} 5904 ins_encode %{ 5905 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); 5906 %} 5907 ins_pipe(pipe_slow); // XXX 5908%} 5909 5910// Prefetch instructions for allocation. 5911// Must be safe to execute with invalid address (cannot fault). 5912 5913instruct prefetchAlloc( memory mem ) %{ 5914 predicate(AllocatePrefetchInstr==3); 5915 match(PrefetchAllocation mem); 5916 ins_cost(125); 5917 5918 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} 5919 ins_encode %{ 5920 __ prefetchw($mem$$Address); 5921 %} 5922 ins_pipe(ialu_mem); 5923%} 5924 5925instruct prefetchAllocNTA( memory mem ) %{ 5926 predicate(AllocatePrefetchInstr==0); 5927 match(PrefetchAllocation mem); 5928 ins_cost(125); 5929 5930 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} 5931 ins_encode %{ 5932 __ prefetchnta($mem$$Address); 5933 %} 5934 ins_pipe(ialu_mem); 5935%} 5936 5937instruct prefetchAllocT0( memory mem ) %{ 5938 predicate(AllocatePrefetchInstr==1); 5939 match(PrefetchAllocation mem); 5940 ins_cost(125); 5941 5942 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} 5943 ins_encode %{ 5944 __ prefetcht0($mem$$Address); 5945 %} 5946 ins_pipe(ialu_mem); 5947%} 5948 5949instruct prefetchAllocT2( memory mem ) %{ 5950 predicate(AllocatePrefetchInstr==2); 5951 match(PrefetchAllocation mem); 5952 ins_cost(125); 5953 5954 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} 5955 ins_encode %{ 5956 __ prefetcht2($mem$$Address); 5957 %} 5958 ins_pipe(ialu_mem); 5959%} 5960 5961//----------Store Instructions------------------------------------------------- 5962 5963// Store Byte 5964instruct storeB(memory mem, rRegI src) 5965%{ 5966 match(Set mem (StoreB mem src)); 5967 5968 ins_cost(125); // XXX 5969 format %{ "movb $mem, $src\t# byte" %} 5970 opcode(0x88); 5971 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); 5972 ins_pipe(ialu_mem_reg); 5973%} 5974 5975// Store Char/Short 5976instruct storeC(memory mem, rRegI src) 5977%{ 5978 match(Set mem (StoreC mem src)); 5979 5980 ins_cost(125); // XXX 5981 format %{ "movw $mem, $src\t# char/short" %} 5982 opcode(0x89); 5983 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); 5984 ins_pipe(ialu_mem_reg); 5985%} 5986 5987// Store Integer 5988instruct storeI(memory mem, rRegI src) 5989%{ 5990 match(Set mem (StoreI mem src)); 5991 5992 ins_cost(125); // XXX 5993 format %{ "movl $mem, $src\t# int" %} 5994 opcode(0x89); 5995 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); 5996 ins_pipe(ialu_mem_reg); 5997%} 5998 5999// Store Long 6000instruct storeL(memory mem, rRegL src) 6001%{ 6002 match(Set mem (StoreL mem src)); 6003 6004 ins_cost(125); // XXX 6005 format %{ "movq $mem, $src\t# long" %} 6006 opcode(0x89); 6007 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); 6008 ins_pipe(ialu_mem_reg); // XXX 6009%} 6010 6011// Store Pointer 6012instruct storeP(memory mem, any_RegP src) 6013%{ 6014 match(Set mem (StoreP mem src)); 6015 6016 ins_cost(125); // XXX 6017 format %{ "movq $mem, $src\t# ptr" %} 6018 opcode(0x89); 6019 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); 6020 ins_pipe(ialu_mem_reg); 6021%} 6022 6023instruct storeImmP0(memory mem, immP0 zero) 6024%{ 6025 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); 6026 match(Set mem (StoreP mem zero)); 6027 6028 ins_cost(125); // XXX 6029 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} 6030 ins_encode %{ 6031 __ movq($mem$$Address, r12); 6032 %} 6033 ins_pipe(ialu_mem_reg); 6034%} 6035 6036// Store NULL Pointer, mark word, or other simple pointer constant. 6037instruct storeImmP(memory mem, immP31 src) 6038%{ 6039 match(Set mem (StoreP mem src)); 6040 6041 ins_cost(150); // XXX 6042 format %{ "movq $mem, $src\t# ptr" %} 6043 opcode(0xC7); /* C7 /0 */ 6044 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); 6045 ins_pipe(ialu_mem_imm); 6046%} 6047 6048// Store Compressed Pointer 6049instruct storeN(memory mem, rRegN src) 6050%{ 6051 match(Set mem (StoreN mem src)); 6052 6053 ins_cost(125); // XXX 6054 format %{ "movl $mem, $src\t# compressed ptr" %} 6055 ins_encode %{ 6056 __ movl($mem$$Address, $src$$Register); 6057 %} 6058 ins_pipe(ialu_mem_reg); 6059%} 6060 6061instruct storeNKlass(memory mem, rRegN src) 6062%{ 6063 match(Set mem (StoreNKlass mem src)); 6064 6065 ins_cost(125); // XXX 6066 format %{ "movl $mem, $src\t# compressed klass ptr" %} 6067 ins_encode %{ 6068 __ movl($mem$$Address, $src$$Register); 6069 %} 6070 ins_pipe(ialu_mem_reg); 6071%} 6072 6073instruct storeImmN0(memory mem, immN0 zero) 6074%{ 6075 predicate(CompressedOops::base() == NULL && CompressedKlassPointers::base() == NULL); 6076 match(Set mem (StoreN mem zero)); 6077 6078 ins_cost(125); // XXX 6079 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} 6080 ins_encode %{ 6081 __ movl($mem$$Address, r12); 6082 %} 6083 ins_pipe(ialu_mem_reg); 6084%} 6085 6086instruct storeImmN(memory mem, immN src) 6087%{ 6088 match(Set mem (StoreN mem src)); 6089 6090 ins_cost(150); // XXX 6091 format %{ "movl $mem, $src\t# compressed ptr" %} 6092 ins_encode %{ 6093 address con = (address)$src$$constant; 6094 if (con == NULL) { 6095 __ movl($mem$$Address, (int32_t)0); 6096 } else { 6097 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); 6098 } 6099 %} 6100 ins_pipe(ialu_mem_imm); 6101%} 6102 6103instruct storeImmNKlass(memory mem, immNKlass src) 6104%{ 6105 match(Set mem (StoreNKlass mem src)); 6106 6107 ins_cost(150); // XXX 6108 format %{ "movl $mem, $src\t# compressed klass ptr" %} 6109 ins_encode %{ 6110 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant); 6111 %} 6112 ins_pipe(ialu_mem_imm); 6113%} 6114 6115// Store Integer Immediate 6116instruct storeImmI0(memory mem, immI0 zero) 6117%{ 6118 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); 6119 match(Set mem (StoreI mem zero)); 6120 6121 ins_cost(125); // XXX 6122 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} 6123 ins_encode %{ 6124 __ movl($mem$$Address, r12); 6125 %} 6126 ins_pipe(ialu_mem_reg); 6127%} 6128 6129instruct storeImmI(memory mem, immI src) 6130%{ 6131 match(Set mem (StoreI mem src)); 6132 6133 ins_cost(150); 6134 format %{ "movl $mem, $src\t# int" %} 6135 opcode(0xC7); /* C7 /0 */ 6136 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); 6137 ins_pipe(ialu_mem_imm); 6138%} 6139 6140// Store Long Immediate 6141instruct storeImmL0(memory mem, immL0 zero) 6142%{ 6143 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); 6144 match(Set mem (StoreL mem zero)); 6145 6146 ins_cost(125); // XXX 6147 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} 6148 ins_encode %{ 6149 __ movq($mem$$Address, r12); 6150 %} 6151 ins_pipe(ialu_mem_reg); 6152%} 6153 6154instruct storeImmL(memory mem, immL32 src) 6155%{ 6156 match(Set mem (StoreL mem src)); 6157 6158 ins_cost(150); 6159 format %{ "movq $mem, $src\t# long" %} 6160 opcode(0xC7); /* C7 /0 */ 6161 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); 6162 ins_pipe(ialu_mem_imm); 6163%} 6164 6165// Store Short/Char Immediate 6166instruct storeImmC0(memory mem, immI0 zero) 6167%{ 6168 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); 6169 match(Set mem (StoreC mem zero)); 6170 6171 ins_cost(125); // XXX 6172 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} 6173 ins_encode %{ 6174 __ movw($mem$$Address, r12); 6175 %} 6176 ins_pipe(ialu_mem_reg); 6177%} 6178 6179instruct storeImmI16(memory mem, immI16 src) 6180%{ 6181 predicate(UseStoreImmI16); 6182 match(Set mem (StoreC mem src)); 6183 6184 ins_cost(150); 6185 format %{ "movw $mem, $src\t# short/char" %} 6186 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ 6187 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); 6188 ins_pipe(ialu_mem_imm); 6189%} 6190 6191// Store Byte Immediate 6192instruct storeImmB0(memory mem, immI0 zero) 6193%{ 6194 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); 6195 match(Set mem (StoreB mem zero)); 6196 6197 ins_cost(125); // XXX 6198 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} 6199 ins_encode %{ 6200 __ movb($mem$$Address, r12); 6201 %} 6202 ins_pipe(ialu_mem_reg); 6203%} 6204 6205instruct storeImmB(memory mem, immI8 src) 6206%{ 6207 match(Set mem (StoreB mem src)); 6208 6209 ins_cost(150); // XXX 6210 format %{ "movb $mem, $src\t# byte" %} 6211 opcode(0xC6); /* C6 /0 */ 6212 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); 6213 ins_pipe(ialu_mem_imm); 6214%} 6215 6216// Store CMS card-mark Immediate 6217instruct storeImmCM0_reg(memory mem, immI0 zero) 6218%{ 6219 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); 6220 match(Set mem (StoreCM mem zero)); 6221 6222 ins_cost(125); // XXX 6223 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} 6224 ins_encode %{ 6225 __ movb($mem$$Address, r12); 6226 %} 6227 ins_pipe(ialu_mem_reg); 6228%} 6229 6230instruct storeImmCM0(memory mem, immI0 src) 6231%{ 6232 match(Set mem (StoreCM mem src)); 6233 6234 ins_cost(150); // XXX 6235 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} 6236 opcode(0xC6); /* C6 /0 */ 6237 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); 6238 ins_pipe(ialu_mem_imm); 6239%} 6240 6241// Store Float 6242instruct storeF(memory mem, regF src) 6243%{ 6244 match(Set mem (StoreF mem src)); 6245 6246 ins_cost(95); // XXX 6247 format %{ "movss $mem, $src\t# float" %} 6248 ins_encode %{ 6249 __ movflt($mem$$Address, $src$$XMMRegister); 6250 %} 6251 ins_pipe(pipe_slow); // XXX 6252%} 6253 6254// Store immediate Float value (it is faster than store from XMM register) 6255instruct storeF0(memory mem, immF0 zero) 6256%{ 6257 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); 6258 match(Set mem (StoreF mem zero)); 6259 6260 ins_cost(25); // XXX 6261 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} 6262 ins_encode %{ 6263 __ movl($mem$$Address, r12); 6264 %} 6265 ins_pipe(ialu_mem_reg); 6266%} 6267 6268instruct storeF_imm(memory mem, immF src) 6269%{ 6270 match(Set mem (StoreF mem src)); 6271 6272 ins_cost(50); 6273 format %{ "movl $mem, $src\t# float" %} 6274 opcode(0xC7); /* C7 /0 */ 6275 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); 6276 ins_pipe(ialu_mem_imm); 6277%} 6278 6279// Store Double 6280instruct storeD(memory mem, regD src) 6281%{ 6282 match(Set mem (StoreD mem src)); 6283 6284 ins_cost(95); // XXX 6285 format %{ "movsd $mem, $src\t# double" %} 6286 ins_encode %{ 6287 __ movdbl($mem$$Address, $src$$XMMRegister); 6288 %} 6289 ins_pipe(pipe_slow); // XXX 6290%} 6291 6292// Store immediate double 0.0 (it is faster than store from XMM register) 6293instruct storeD0_imm(memory mem, immD0 src) 6294%{ 6295 predicate(!UseCompressedOops || (CompressedOops::base() != NULL)); 6296 match(Set mem (StoreD mem src)); 6297 6298 ins_cost(50); 6299 format %{ "movq $mem, $src\t# double 0." %} 6300 opcode(0xC7); /* C7 /0 */ 6301 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); 6302 ins_pipe(ialu_mem_imm); 6303%} 6304 6305instruct storeD0(memory mem, immD0 zero) 6306%{ 6307 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); 6308 match(Set mem (StoreD mem zero)); 6309 6310 ins_cost(25); // XXX 6311 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} 6312 ins_encode %{ 6313 __ movq($mem$$Address, r12); 6314 %} 6315 ins_pipe(ialu_mem_reg); 6316%} 6317 6318instruct storeSSI(stackSlotI dst, rRegI src) 6319%{ 6320 match(Set dst src); 6321 6322 ins_cost(100); 6323 format %{ "movl $dst, $src\t# int stk" %} 6324 opcode(0x89); 6325 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); 6326 ins_pipe( ialu_mem_reg ); 6327%} 6328 6329instruct storeSSL(stackSlotL dst, rRegL src) 6330%{ 6331 match(Set dst src); 6332 6333 ins_cost(100); 6334 format %{ "movq $dst, $src\t# long stk" %} 6335 opcode(0x89); 6336 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); 6337 ins_pipe(ialu_mem_reg); 6338%} 6339 6340instruct storeSSP(stackSlotP dst, rRegP src) 6341%{ 6342 match(Set dst src); 6343 6344 ins_cost(100); 6345 format %{ "movq $dst, $src\t# ptr stk" %} 6346 opcode(0x89); 6347 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); 6348 ins_pipe(ialu_mem_reg); 6349%} 6350 6351instruct storeSSF(stackSlotF dst, regF src) 6352%{ 6353 match(Set dst src); 6354 6355 ins_cost(95); // XXX 6356 format %{ "movss $dst, $src\t# float stk" %} 6357 ins_encode %{ 6358 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); 6359 %} 6360 ins_pipe(pipe_slow); // XXX 6361%} 6362 6363instruct storeSSD(stackSlotD dst, regD src) 6364%{ 6365 match(Set dst src); 6366 6367 ins_cost(95); // XXX 6368 format %{ "movsd $dst, $src\t# double stk" %} 6369 ins_encode %{ 6370 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); 6371 %} 6372 ins_pipe(pipe_slow); // XXX 6373%} 6374 6375//----------BSWAP Instructions------------------------------------------------- 6376instruct bytes_reverse_int(rRegI dst) %{ 6377 match(Set dst (ReverseBytesI dst)); 6378 6379 format %{ "bswapl $dst" %} 6380 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ 6381 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); 6382 ins_pipe( ialu_reg ); 6383%} 6384 6385instruct bytes_reverse_long(rRegL dst) %{ 6386 match(Set dst (ReverseBytesL dst)); 6387 6388 format %{ "bswapq $dst" %} 6389 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ 6390 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); 6391 ins_pipe( ialu_reg); 6392%} 6393 6394instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{ 6395 match(Set dst (ReverseBytesUS dst)); 6396 effect(KILL cr); 6397 6398 format %{ "bswapl $dst\n\t" 6399 "shrl $dst,16\n\t" %} 6400 ins_encode %{ 6401 __ bswapl($dst$$Register); 6402 __ shrl($dst$$Register, 16); 6403 %} 6404 ins_pipe( ialu_reg ); 6405%} 6406 6407instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{ 6408 match(Set dst (ReverseBytesS dst)); 6409 effect(KILL cr); 6410 6411 format %{ "bswapl $dst\n\t" 6412 "sar $dst,16\n\t" %} 6413 ins_encode %{ 6414 __ bswapl($dst$$Register); 6415 __ sarl($dst$$Register, 16); 6416 %} 6417 ins_pipe( ialu_reg ); 6418%} 6419 6420//---------- Zeros Count Instructions ------------------------------------------ 6421 6422instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ 6423 predicate(UseCountLeadingZerosInstruction); 6424 match(Set dst (CountLeadingZerosI src)); 6425 effect(KILL cr); 6426 6427 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} 6428 ins_encode %{ 6429 __ lzcntl($dst$$Register, $src$$Register); 6430 %} 6431 ins_pipe(ialu_reg); 6432%} 6433 6434instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ 6435 predicate(!UseCountLeadingZerosInstruction); 6436 match(Set dst (CountLeadingZerosI src)); 6437 effect(KILL cr); 6438 6439 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" 6440 "jnz skip\n\t" 6441 "movl $dst, -1\n" 6442 "skip:\n\t" 6443 "negl $dst\n\t" 6444 "addl $dst, 31" %} 6445 ins_encode %{ 6446 Register Rdst = $dst$$Register; 6447 Register Rsrc = $src$$Register; 6448 Label skip; 6449 __ bsrl(Rdst, Rsrc); 6450 __ jccb(Assembler::notZero, skip); 6451 __ movl(Rdst, -1); 6452 __ bind(skip); 6453 __ negl(Rdst); 6454 __ addl(Rdst, BitsPerInt - 1); 6455 %} 6456 ins_pipe(ialu_reg); 6457%} 6458 6459instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ 6460 predicate(UseCountLeadingZerosInstruction); 6461 match(Set dst (CountLeadingZerosL src)); 6462 effect(KILL cr); 6463 6464 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} 6465 ins_encode %{ 6466 __ lzcntq($dst$$Register, $src$$Register); 6467 %} 6468 ins_pipe(ialu_reg); 6469%} 6470 6471instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ 6472 predicate(!UseCountLeadingZerosInstruction); 6473 match(Set dst (CountLeadingZerosL src)); 6474 effect(KILL cr); 6475 6476 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" 6477 "jnz skip\n\t" 6478 "movl $dst, -1\n" 6479 "skip:\n\t" 6480 "negl $dst\n\t" 6481 "addl $dst, 63" %} 6482 ins_encode %{ 6483 Register Rdst = $dst$$Register; 6484 Register Rsrc = $src$$Register; 6485 Label skip; 6486 __ bsrq(Rdst, Rsrc); 6487 __ jccb(Assembler::notZero, skip); 6488 __ movl(Rdst, -1); 6489 __ bind(skip); 6490 __ negl(Rdst); 6491 __ addl(Rdst, BitsPerLong - 1); 6492 %} 6493 ins_pipe(ialu_reg); 6494%} 6495 6496instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ 6497 predicate(UseCountTrailingZerosInstruction); 6498 match(Set dst (CountTrailingZerosI src)); 6499 effect(KILL cr); 6500 6501 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %} 6502 ins_encode %{ 6503 __ tzcntl($dst$$Register, $src$$Register); 6504 %} 6505 ins_pipe(ialu_reg); 6506%} 6507 6508instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{ 6509 predicate(!UseCountTrailingZerosInstruction); 6510 match(Set dst (CountTrailingZerosI src)); 6511 effect(KILL cr); 6512 6513 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" 6514 "jnz done\n\t" 6515 "movl $dst, 32\n" 6516 "done:" %} 6517 ins_encode %{ 6518 Register Rdst = $dst$$Register; 6519 Label done; 6520 __ bsfl(Rdst, $src$$Register); 6521 __ jccb(Assembler::notZero, done); 6522 __ movl(Rdst, BitsPerInt); 6523 __ bind(done); 6524 %} 6525 ins_pipe(ialu_reg); 6526%} 6527 6528instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ 6529 predicate(UseCountTrailingZerosInstruction); 6530 match(Set dst (CountTrailingZerosL src)); 6531 effect(KILL cr); 6532 6533 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %} 6534 ins_encode %{ 6535 __ tzcntq($dst$$Register, $src$$Register); 6536 %} 6537 ins_pipe(ialu_reg); 6538%} 6539 6540instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{ 6541 predicate(!UseCountTrailingZerosInstruction); 6542 match(Set dst (CountTrailingZerosL src)); 6543 effect(KILL cr); 6544 6545 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" 6546 "jnz done\n\t" 6547 "movl $dst, 64\n" 6548 "done:" %} 6549 ins_encode %{ 6550 Register Rdst = $dst$$Register; 6551 Label done; 6552 __ bsfq(Rdst, $src$$Register); 6553 __ jccb(Assembler::notZero, done); 6554 __ movl(Rdst, BitsPerLong); 6555 __ bind(done); 6556 %} 6557 ins_pipe(ialu_reg); 6558%} 6559 6560 6561//---------- Population Count Instructions ------------------------------------- 6562 6563instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{ 6564 predicate(UsePopCountInstruction); 6565 match(Set dst (PopCountI src)); 6566 effect(KILL cr); 6567 6568 format %{ "popcnt $dst, $src" %} 6569 ins_encode %{ 6570 __ popcntl($dst$$Register, $src$$Register); 6571 %} 6572 ins_pipe(ialu_reg); 6573%} 6574 6575instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{ 6576 predicate(UsePopCountInstruction); 6577 match(Set dst (PopCountI (LoadI mem))); 6578 effect(KILL cr); 6579 6580 format %{ "popcnt $dst, $mem" %} 6581 ins_encode %{ 6582 __ popcntl($dst$$Register, $mem$$Address); 6583 %} 6584 ins_pipe(ialu_reg); 6585%} 6586 6587// Note: Long.bitCount(long) returns an int. 6588instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{ 6589 predicate(UsePopCountInstruction); 6590 match(Set dst (PopCountL src)); 6591 effect(KILL cr); 6592 6593 format %{ "popcnt $dst, $src" %} 6594 ins_encode %{ 6595 __ popcntq($dst$$Register, $src$$Register); 6596 %} 6597 ins_pipe(ialu_reg); 6598%} 6599 6600// Note: Long.bitCount(long) returns an int. 6601instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{ 6602 predicate(UsePopCountInstruction); 6603 match(Set dst (PopCountL (LoadL mem))); 6604 effect(KILL cr); 6605 6606 format %{ "popcnt $dst, $mem" %} 6607 ins_encode %{ 6608 __ popcntq($dst$$Register, $mem$$Address); 6609 %} 6610 ins_pipe(ialu_reg); 6611%} 6612 6613 6614//----------MemBar Instructions----------------------------------------------- 6615// Memory barrier flavors 6616 6617instruct membar_acquire() 6618%{ 6619 match(MemBarAcquire); 6620 match(LoadFence); 6621 ins_cost(0); 6622 6623 size(0); 6624 format %{ "MEMBAR-acquire ! (empty encoding)" %} 6625 ins_encode(); 6626 ins_pipe(empty); 6627%} 6628 6629instruct membar_acquire_lock() 6630%{ 6631 match(MemBarAcquireLock); 6632 ins_cost(0); 6633 6634 size(0); 6635 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} 6636 ins_encode(); 6637 ins_pipe(empty); 6638%} 6639 6640instruct membar_release() 6641%{ 6642 match(MemBarRelease); 6643 match(StoreFence); 6644 ins_cost(0); 6645 6646 size(0); 6647 format %{ "MEMBAR-release ! (empty encoding)" %} 6648 ins_encode(); 6649 ins_pipe(empty); 6650%} 6651 6652instruct membar_release_lock() 6653%{ 6654 match(MemBarReleaseLock); 6655 ins_cost(0); 6656 6657 size(0); 6658 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} 6659 ins_encode(); 6660 ins_pipe(empty); 6661%} 6662 6663instruct membar_volatile(rFlagsReg cr) %{ 6664 match(MemBarVolatile); 6665 effect(KILL cr); 6666 ins_cost(400); 6667 6668 format %{ 6669 $$template 6670 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" 6671 %} 6672 ins_encode %{ 6673 __ membar(Assembler::StoreLoad); 6674 %} 6675 ins_pipe(pipe_slow); 6676%} 6677 6678instruct unnecessary_membar_volatile() 6679%{ 6680 match(MemBarVolatile); 6681 predicate(Matcher::post_store_load_barrier(n)); 6682 ins_cost(0); 6683 6684 size(0); 6685 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} 6686 ins_encode(); 6687 ins_pipe(empty); 6688%} 6689 6690instruct membar_storestore() %{ 6691 match(MemBarStoreStore); 6692 ins_cost(0); 6693 6694 size(0); 6695 format %{ "MEMBAR-storestore (empty encoding)" %} 6696 ins_encode( ); 6697 ins_pipe(empty); 6698%} 6699 6700//----------Move Instructions-------------------------------------------------- 6701 6702instruct castX2P(rRegP dst, rRegL src) 6703%{ 6704 match(Set dst (CastX2P src)); 6705 6706 format %{ "movq $dst, $src\t# long->ptr" %} 6707 ins_encode %{ 6708 if ($dst$$reg != $src$$reg) { 6709 __ movptr($dst$$Register, $src$$Register); 6710 } 6711 %} 6712 ins_pipe(ialu_reg_reg); // XXX 6713%} 6714 6715instruct castP2X(rRegL dst, rRegP src) 6716%{ 6717 match(Set dst (CastP2X src)); 6718 6719 format %{ "movq $dst, $src\t# ptr -> long" %} 6720 ins_encode %{ 6721 if ($dst$$reg != $src$$reg) { 6722 __ movptr($dst$$Register, $src$$Register); 6723 } 6724 %} 6725 ins_pipe(ialu_reg_reg); // XXX 6726%} 6727 6728// Convert oop into int for vectors alignment masking 6729instruct convP2I(rRegI dst, rRegP src) 6730%{ 6731 match(Set dst (ConvL2I (CastP2X src))); 6732 6733 format %{ "movl $dst, $src\t# ptr -> int" %} 6734 ins_encode %{ 6735 __ movl($dst$$Register, $src$$Register); 6736 %} 6737 ins_pipe(ialu_reg_reg); // XXX 6738%} 6739 6740// Convert compressed oop into int for vectors alignment masking 6741// in case of 32bit oops (heap < 4Gb). 6742instruct convN2I(rRegI dst, rRegN src) 6743%{ 6744 predicate(CompressedOops::shift() == 0); 6745 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); 6746 6747 format %{ "movl $dst, $src\t# compressed ptr -> int" %} 6748 ins_encode %{ 6749 __ movl($dst$$Register, $src$$Register); 6750 %} 6751 ins_pipe(ialu_reg_reg); // XXX 6752%} 6753 6754// Convert oop pointer into compressed form 6755instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ 6756 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6757 match(Set dst (EncodeP src)); 6758 effect(KILL cr); 6759 format %{ "encode_heap_oop $dst,$src" %} 6760 ins_encode %{ 6761 Register s = $src$$Register; 6762 Register d = $dst$$Register; 6763 if (s != d) { 6764 __ movq(d, s); 6765 } 6766 __ encode_heap_oop(d); 6767 %} 6768 ins_pipe(ialu_reg_long); 6769%} 6770 6771instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ 6772 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6773 match(Set dst (EncodeP src)); 6774 effect(KILL cr); 6775 format %{ "encode_heap_oop_not_null $dst,$src" %} 6776 ins_encode %{ 6777 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); 6778 %} 6779 ins_pipe(ialu_reg_long); 6780%} 6781 6782instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ 6783 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull && 6784 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant); 6785 match(Set dst (DecodeN src)); 6786 effect(KILL cr); 6787 format %{ "decode_heap_oop $dst,$src" %} 6788 ins_encode %{ 6789 Register s = $src$$Register; 6790 Register d = $dst$$Register; 6791 if (s != d) { 6792 __ movq(d, s); 6793 } 6794 __ decode_heap_oop(d); 6795 %} 6796 ins_pipe(ialu_reg_long); 6797%} 6798 6799instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ 6800 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull || 6801 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant); 6802 match(Set dst (DecodeN src)); 6803 effect(KILL cr); 6804 format %{ "decode_heap_oop_not_null $dst,$src" %} 6805 ins_encode %{ 6806 Register s = $src$$Register; 6807 Register d = $dst$$Register; 6808 if (s != d) { 6809 __ decode_heap_oop_not_null(d, s); 6810 } else { 6811 __ decode_heap_oop_not_null(d); 6812 } 6813 %} 6814 ins_pipe(ialu_reg_long); 6815%} 6816 6817instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ 6818 match(Set dst (EncodePKlass src)); 6819 effect(KILL cr); 6820 format %{ "encode_klass_not_null $dst,$src" %} 6821 ins_encode %{ 6822 __ encode_klass_not_null($dst$$Register, $src$$Register); 6823 %} 6824 ins_pipe(ialu_reg_long); 6825%} 6826 6827instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ 6828 match(Set dst (DecodeNKlass src)); 6829 effect(KILL cr); 6830 format %{ "decode_klass_not_null $dst,$src" %} 6831 ins_encode %{ 6832 Register s = $src$$Register; 6833 Register d = $dst$$Register; 6834 if (s != d) { 6835 __ decode_klass_not_null(d, s); 6836 } else { 6837 __ decode_klass_not_null(d); 6838 } 6839 %} 6840 ins_pipe(ialu_reg_long); 6841%} 6842 6843 6844//----------Conditional Move--------------------------------------------------- 6845// Jump 6846// dummy instruction for generating temp registers 6847instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ 6848 match(Jump (LShiftL switch_val shift)); 6849 ins_cost(350); 6850 predicate(false); 6851 effect(TEMP dest); 6852 6853 format %{ "leaq $dest, [$constantaddress]\n\t" 6854 "jmp [$dest + $switch_val << $shift]\n\t" %} 6855 ins_encode %{ 6856 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 6857 // to do that and the compiler is using that register as one it can allocate. 6858 // So we build it all by hand. 6859 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); 6860 // ArrayAddress dispatch(table, index); 6861 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); 6862 __ lea($dest$$Register, $constantaddress); 6863 __ jmp(dispatch); 6864 %} 6865 ins_pipe(pipe_jmp); 6866%} 6867 6868instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ 6869 match(Jump (AddL (LShiftL switch_val shift) offset)); 6870 ins_cost(350); 6871 effect(TEMP dest); 6872 6873 format %{ "leaq $dest, [$constantaddress]\n\t" 6874 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} 6875 ins_encode %{ 6876 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 6877 // to do that and the compiler is using that register as one it can allocate. 6878 // So we build it all by hand. 6879 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); 6880 // ArrayAddress dispatch(table, index); 6881 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); 6882 __ lea($dest$$Register, $constantaddress); 6883 __ jmp(dispatch); 6884 %} 6885 ins_pipe(pipe_jmp); 6886%} 6887 6888instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ 6889 match(Jump switch_val); 6890 ins_cost(350); 6891 effect(TEMP dest); 6892 6893 format %{ "leaq $dest, [$constantaddress]\n\t" 6894 "jmp [$dest + $switch_val]\n\t" %} 6895 ins_encode %{ 6896 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 6897 // to do that and the compiler is using that register as one it can allocate. 6898 // So we build it all by hand. 6899 // Address index(noreg, switch_reg, Address::times_1); 6900 // ArrayAddress dispatch(table, index); 6901 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); 6902 __ lea($dest$$Register, $constantaddress); 6903 __ jmp(dispatch); 6904 %} 6905 ins_pipe(pipe_jmp); 6906%} 6907 6908// Conditional move 6909instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) 6910%{ 6911 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 6912 6913 ins_cost(200); // XXX 6914 format %{ "cmovl$cop $dst, $src\t# signed, int" %} 6915 opcode(0x0F, 0x40); 6916 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); 6917 ins_pipe(pipe_cmov_reg); 6918%} 6919 6920instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ 6921 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 6922 6923 ins_cost(200); // XXX 6924 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} 6925 opcode(0x0F, 0x40); 6926 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); 6927 ins_pipe(pipe_cmov_reg); 6928%} 6929 6930instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ 6931 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 6932 ins_cost(200); 6933 expand %{ 6934 cmovI_regU(cop, cr, dst, src); 6935 %} 6936%} 6937 6938// Conditional move 6939instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ 6940 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 6941 6942 ins_cost(250); // XXX 6943 format %{ "cmovl$cop $dst, $src\t# signed, int" %} 6944 opcode(0x0F, 0x40); 6945 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); 6946 ins_pipe(pipe_cmov_mem); 6947%} 6948 6949// Conditional move 6950instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) 6951%{ 6952 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 6953 6954 ins_cost(250); // XXX 6955 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} 6956 opcode(0x0F, 0x40); 6957 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); 6958 ins_pipe(pipe_cmov_mem); 6959%} 6960 6961instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ 6962 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 6963 ins_cost(250); 6964 expand %{ 6965 cmovI_memU(cop, cr, dst, src); 6966 %} 6967%} 6968 6969// Conditional move 6970instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) 6971%{ 6972 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); 6973 6974 ins_cost(200); // XXX 6975 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} 6976 opcode(0x0F, 0x40); 6977 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); 6978 ins_pipe(pipe_cmov_reg); 6979%} 6980 6981// Conditional move 6982instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) 6983%{ 6984 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); 6985 6986 ins_cost(200); // XXX 6987 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} 6988 opcode(0x0F, 0x40); 6989 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); 6990 ins_pipe(pipe_cmov_reg); 6991%} 6992 6993instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ 6994 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); 6995 ins_cost(200); 6996 expand %{ 6997 cmovN_regU(cop, cr, dst, src); 6998 %} 6999%} 7000 7001// Conditional move 7002instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) 7003%{ 7004 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7005 7006 ins_cost(200); // XXX 7007 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} 7008 opcode(0x0F, 0x40); 7009 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); 7010 ins_pipe(pipe_cmov_reg); // XXX 7011%} 7012 7013// Conditional move 7014instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) 7015%{ 7016 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7017 7018 ins_cost(200); // XXX 7019 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} 7020 opcode(0x0F, 0x40); 7021 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); 7022 ins_pipe(pipe_cmov_reg); // XXX 7023%} 7024 7025instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ 7026 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7027 ins_cost(200); 7028 expand %{ 7029 cmovP_regU(cop, cr, dst, src); 7030 %} 7031%} 7032 7033// DISABLED: Requires the ADLC to emit a bottom_type call that 7034// correctly meets the two pointer arguments; one is an incoming 7035// register but the other is a memory operand. ALSO appears to 7036// be buggy with implicit null checks. 7037// 7038//// Conditional move 7039//instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) 7040//%{ 7041// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7042// ins_cost(250); 7043// format %{ "CMOV$cop $dst,$src\t# ptr" %} 7044// opcode(0x0F,0x40); 7045// ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); 7046// ins_pipe( pipe_cmov_mem ); 7047//%} 7048// 7049//// Conditional move 7050//instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) 7051//%{ 7052// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7053// ins_cost(250); 7054// format %{ "CMOV$cop $dst,$src\t# ptr" %} 7055// opcode(0x0F,0x40); 7056// ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); 7057// ins_pipe( pipe_cmov_mem ); 7058//%} 7059 7060instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) 7061%{ 7062 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7063 7064 ins_cost(200); // XXX 7065 format %{ "cmovq$cop $dst, $src\t# signed, long" %} 7066 opcode(0x0F, 0x40); 7067 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); 7068 ins_pipe(pipe_cmov_reg); // XXX 7069%} 7070 7071instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) 7072%{ 7073 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); 7074 7075 ins_cost(200); // XXX 7076 format %{ "cmovq$cop $dst, $src\t# signed, long" %} 7077 opcode(0x0F, 0x40); 7078 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); 7079 ins_pipe(pipe_cmov_mem); // XXX 7080%} 7081 7082instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) 7083%{ 7084 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7085 7086 ins_cost(200); // XXX 7087 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} 7088 opcode(0x0F, 0x40); 7089 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); 7090 ins_pipe(pipe_cmov_reg); // XXX 7091%} 7092 7093instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ 7094 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7095 ins_cost(200); 7096 expand %{ 7097 cmovL_regU(cop, cr, dst, src); 7098 %} 7099%} 7100 7101instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) 7102%{ 7103 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); 7104 7105 ins_cost(200); // XXX 7106 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} 7107 opcode(0x0F, 0x40); 7108 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); 7109 ins_pipe(pipe_cmov_mem); // XXX 7110%} 7111 7112instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ 7113 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); 7114 ins_cost(200); 7115 expand %{ 7116 cmovL_memU(cop, cr, dst, src); 7117 %} 7118%} 7119 7120instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) 7121%{ 7122 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7123 7124 ins_cost(200); // XXX 7125 format %{ "jn$cop skip\t# signed cmove float\n\t" 7126 "movss $dst, $src\n" 7127 "skip:" %} 7128 ins_encode %{ 7129 Label Lskip; 7130 // Invert sense of branch from sense of CMOV 7131 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); 7132 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7133 __ bind(Lskip); 7134 %} 7135 ins_pipe(pipe_slow); 7136%} 7137 7138// instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) 7139// %{ 7140// match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); 7141 7142// ins_cost(200); // XXX 7143// format %{ "jn$cop skip\t# signed cmove float\n\t" 7144// "movss $dst, $src\n" 7145// "skip:" %} 7146// ins_encode(enc_cmovf_mem_branch(cop, dst, src)); 7147// ins_pipe(pipe_slow); 7148// %} 7149 7150instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) 7151%{ 7152 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7153 7154 ins_cost(200); // XXX 7155 format %{ "jn$cop skip\t# unsigned cmove float\n\t" 7156 "movss $dst, $src\n" 7157 "skip:" %} 7158 ins_encode %{ 7159 Label Lskip; 7160 // Invert sense of branch from sense of CMOV 7161 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); 7162 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7163 __ bind(Lskip); 7164 %} 7165 ins_pipe(pipe_slow); 7166%} 7167 7168instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ 7169 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7170 ins_cost(200); 7171 expand %{ 7172 cmovF_regU(cop, cr, dst, src); 7173 %} 7174%} 7175 7176instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) 7177%{ 7178 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7179 7180 ins_cost(200); // XXX 7181 format %{ "jn$cop skip\t# signed cmove double\n\t" 7182 "movsd $dst, $src\n" 7183 "skip:" %} 7184 ins_encode %{ 7185 Label Lskip; 7186 // Invert sense of branch from sense of CMOV 7187 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); 7188 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7189 __ bind(Lskip); 7190 %} 7191 ins_pipe(pipe_slow); 7192%} 7193 7194instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) 7195%{ 7196 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7197 7198 ins_cost(200); // XXX 7199 format %{ "jn$cop skip\t# unsigned cmove double\n\t" 7200 "movsd $dst, $src\n" 7201 "skip:" %} 7202 ins_encode %{ 7203 Label Lskip; 7204 // Invert sense of branch from sense of CMOV 7205 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); 7206 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7207 __ bind(Lskip); 7208 %} 7209 ins_pipe(pipe_slow); 7210%} 7211 7212instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ 7213 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7214 ins_cost(200); 7215 expand %{ 7216 cmovD_regU(cop, cr, dst, src); 7217 %} 7218%} 7219 7220//----------Arithmetic Instructions-------------------------------------------- 7221//----------Addition Instructions---------------------------------------------- 7222 7223instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 7224%{ 7225 match(Set dst (AddI dst src)); 7226 effect(KILL cr); 7227 7228 format %{ "addl $dst, $src\t# int" %} 7229 opcode(0x03); 7230 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); 7231 ins_pipe(ialu_reg_reg); 7232%} 7233 7234instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) 7235%{ 7236 match(Set dst (AddI dst src)); 7237 effect(KILL cr); 7238 7239 format %{ "addl $dst, $src\t# int" %} 7240 opcode(0x81, 0x00); /* /0 id */ 7241 ins_encode(OpcSErm(dst, src), Con8or32(src)); 7242 ins_pipe( ialu_reg ); 7243%} 7244 7245instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) 7246%{ 7247 match(Set dst (AddI dst (LoadI src))); 7248 effect(KILL cr); 7249 7250 ins_cost(125); // XXX 7251 format %{ "addl $dst, $src\t# int" %} 7252 opcode(0x03); 7253 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); 7254 ins_pipe(ialu_reg_mem); 7255%} 7256 7257instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) 7258%{ 7259 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7260 effect(KILL cr); 7261 7262 ins_cost(150); // XXX 7263 format %{ "addl $dst, $src\t# int" %} 7264 opcode(0x01); /* Opcode 01 /r */ 7265 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); 7266 ins_pipe(ialu_mem_reg); 7267%} 7268 7269instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) 7270%{ 7271 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7272 effect(KILL cr); 7273 7274 ins_cost(125); // XXX 7275 format %{ "addl $dst, $src\t# int" %} 7276 opcode(0x81); /* Opcode 81 /0 id */ 7277 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); 7278 ins_pipe(ialu_mem_imm); 7279%} 7280 7281instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) 7282%{ 7283 predicate(UseIncDec); 7284 match(Set dst (AddI dst src)); 7285 effect(KILL cr); 7286 7287 format %{ "incl $dst\t# int" %} 7288 opcode(0xFF, 0x00); // FF /0 7289 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 7290 ins_pipe(ialu_reg); 7291%} 7292 7293instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) 7294%{ 7295 predicate(UseIncDec); 7296 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7297 effect(KILL cr); 7298 7299 ins_cost(125); // XXX 7300 format %{ "incl $dst\t# int" %} 7301 opcode(0xFF); /* Opcode FF /0 */ 7302 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); 7303 ins_pipe(ialu_mem_imm); 7304%} 7305 7306// XXX why does that use AddI 7307instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) 7308%{ 7309 predicate(UseIncDec); 7310 match(Set dst (AddI dst src)); 7311 effect(KILL cr); 7312 7313 format %{ "decl $dst\t# int" %} 7314 opcode(0xFF, 0x01); // FF /1 7315 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 7316 ins_pipe(ialu_reg); 7317%} 7318 7319// XXX why does that use AddI 7320instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) 7321%{ 7322 predicate(UseIncDec); 7323 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7324 effect(KILL cr); 7325 7326 ins_cost(125); // XXX 7327 format %{ "decl $dst\t# int" %} 7328 opcode(0xFF); /* Opcode FF /1 */ 7329 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); 7330 ins_pipe(ialu_mem_imm); 7331%} 7332 7333instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) 7334%{ 7335 match(Set dst (AddI src0 src1)); 7336 7337 ins_cost(110); 7338 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} 7339 opcode(0x8D); /* 0x8D /r */ 7340 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX 7341 ins_pipe(ialu_reg_reg); 7342%} 7343 7344instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) 7345%{ 7346 match(Set dst (AddL dst src)); 7347 effect(KILL cr); 7348 7349 format %{ "addq $dst, $src\t# long" %} 7350 opcode(0x03); 7351 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); 7352 ins_pipe(ialu_reg_reg); 7353%} 7354 7355instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) 7356%{ 7357 match(Set dst (AddL dst src)); 7358 effect(KILL cr); 7359 7360 format %{ "addq $dst, $src\t# long" %} 7361 opcode(0x81, 0x00); /* /0 id */ 7362 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); 7363 ins_pipe( ialu_reg ); 7364%} 7365 7366instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) 7367%{ 7368 match(Set dst (AddL dst (LoadL src))); 7369 effect(KILL cr); 7370 7371 ins_cost(125); // XXX 7372 format %{ "addq $dst, $src\t# long" %} 7373 opcode(0x03); 7374 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); 7375 ins_pipe(ialu_reg_mem); 7376%} 7377 7378instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) 7379%{ 7380 match(Set dst (StoreL dst (AddL (LoadL dst) src))); 7381 effect(KILL cr); 7382 7383 ins_cost(150); // XXX 7384 format %{ "addq $dst, $src\t# long" %} 7385 opcode(0x01); /* Opcode 01 /r */ 7386 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); 7387 ins_pipe(ialu_mem_reg); 7388%} 7389 7390instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) 7391%{ 7392 match(Set dst (StoreL dst (AddL (LoadL dst) src))); 7393 effect(KILL cr); 7394 7395 ins_cost(125); // XXX 7396 format %{ "addq $dst, $src\t# long" %} 7397 opcode(0x81); /* Opcode 81 /0 id */ 7398 ins_encode(REX_mem_wide(dst), 7399 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); 7400 ins_pipe(ialu_mem_imm); 7401%} 7402 7403instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) 7404%{ 7405 predicate(UseIncDec); 7406 match(Set dst (AddL dst src)); 7407 effect(KILL cr); 7408 7409 format %{ "incq $dst\t# long" %} 7410 opcode(0xFF, 0x00); // FF /0 7411 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 7412 ins_pipe(ialu_reg); 7413%} 7414 7415instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) 7416%{ 7417 predicate(UseIncDec); 7418 match(Set dst (StoreL dst (AddL (LoadL dst) src))); 7419 effect(KILL cr); 7420 7421 ins_cost(125); // XXX 7422 format %{ "incq $dst\t# long" %} 7423 opcode(0xFF); /* Opcode FF /0 */ 7424 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); 7425 ins_pipe(ialu_mem_imm); 7426%} 7427 7428// XXX why does that use AddL 7429instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) 7430%{ 7431 predicate(UseIncDec); 7432 match(Set dst (AddL dst src)); 7433 effect(KILL cr); 7434 7435 format %{ "decq $dst\t# long" %} 7436 opcode(0xFF, 0x01); // FF /1 7437 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 7438 ins_pipe(ialu_reg); 7439%} 7440 7441// XXX why does that use AddL 7442instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) 7443%{ 7444 predicate(UseIncDec); 7445 match(Set dst (StoreL dst (AddL (LoadL dst) src))); 7446 effect(KILL cr); 7447 7448 ins_cost(125); // XXX 7449 format %{ "decq $dst\t# long" %} 7450 opcode(0xFF); /* Opcode FF /1 */ 7451 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); 7452 ins_pipe(ialu_mem_imm); 7453%} 7454 7455instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) 7456%{ 7457 match(Set dst (AddL src0 src1)); 7458 7459 ins_cost(110); 7460 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} 7461 opcode(0x8D); /* 0x8D /r */ 7462 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX 7463 ins_pipe(ialu_reg_reg); 7464%} 7465 7466instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) 7467%{ 7468 match(Set dst (AddP dst src)); 7469 effect(KILL cr); 7470 7471 format %{ "addq $dst, $src\t# ptr" %} 7472 opcode(0x03); 7473 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); 7474 ins_pipe(ialu_reg_reg); 7475%} 7476 7477instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) 7478%{ 7479 match(Set dst (AddP dst src)); 7480 effect(KILL cr); 7481 7482 format %{ "addq $dst, $src\t# ptr" %} 7483 opcode(0x81, 0x00); /* /0 id */ 7484 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); 7485 ins_pipe( ialu_reg ); 7486%} 7487 7488// XXX addP mem ops ???? 7489 7490instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) 7491%{ 7492 match(Set dst (AddP src0 src1)); 7493 7494 ins_cost(110); 7495 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} 7496 opcode(0x8D); /* 0x8D /r */ 7497 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX 7498 ins_pipe(ialu_reg_reg); 7499%} 7500 7501instruct checkCastPP(rRegP dst) 7502%{ 7503 match(Set dst (CheckCastPP dst)); 7504 7505 size(0); 7506 format %{ "# checkcastPP of $dst" %} 7507 ins_encode(/* empty encoding */); 7508 ins_pipe(empty); 7509%} 7510 7511instruct castPP(rRegP dst) 7512%{ 7513 match(Set dst (CastPP dst)); 7514 7515 size(0); 7516 format %{ "# castPP of $dst" %} 7517 ins_encode(/* empty encoding */); 7518 ins_pipe(empty); 7519%} 7520 7521instruct castII(rRegI dst) 7522%{ 7523 match(Set dst (CastII dst)); 7524 7525 size(0); 7526 format %{ "# castII of $dst" %} 7527 ins_encode(/* empty encoding */); 7528 ins_cost(0); 7529 ins_pipe(empty); 7530%} 7531 7532// LoadP-locked same as a regular LoadP when used with compare-swap 7533instruct loadPLocked(rRegP dst, memory mem) 7534%{ 7535 match(Set dst (LoadPLocked mem)); 7536 7537 ins_cost(125); // XXX 7538 format %{ "movq $dst, $mem\t# ptr locked" %} 7539 opcode(0x8B); 7540 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 7541 ins_pipe(ialu_reg_mem); // XXX 7542%} 7543 7544// Conditional-store of the updated heap-top. 7545// Used during allocation of the shared heap. 7546// Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. 7547 7548instruct storePConditional(memory heap_top_ptr, 7549 rax_RegP oldval, rRegP newval, 7550 rFlagsReg cr) 7551%{ 7552 predicate(n->as_LoadStore()->barrier_data() == 0); 7553 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); 7554 7555 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " 7556 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} 7557 opcode(0x0F, 0xB1); 7558 ins_encode(lock_prefix, 7559 REX_reg_mem_wide(newval, heap_top_ptr), 7560 OpcP, OpcS, 7561 reg_mem(newval, heap_top_ptr)); 7562 ins_pipe(pipe_cmpxchg); 7563%} 7564 7565// Conditional-store of an int value. 7566// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. 7567instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) 7568%{ 7569 match(Set cr (StoreIConditional mem (Binary oldval newval))); 7570 effect(KILL oldval); 7571 7572 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} 7573 opcode(0x0F, 0xB1); 7574 ins_encode(lock_prefix, 7575 REX_reg_mem(newval, mem), 7576 OpcP, OpcS, 7577 reg_mem(newval, mem)); 7578 ins_pipe(pipe_cmpxchg); 7579%} 7580 7581// Conditional-store of a long value. 7582// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. 7583instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) 7584%{ 7585 match(Set cr (StoreLConditional mem (Binary oldval newval))); 7586 effect(KILL oldval); 7587 7588 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} 7589 opcode(0x0F, 0xB1); 7590 ins_encode(lock_prefix, 7591 REX_reg_mem_wide(newval, mem), 7592 OpcP, OpcS, 7593 reg_mem(newval, mem)); 7594 ins_pipe(pipe_cmpxchg); 7595%} 7596 7597 7598// XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7599instruct compareAndSwapP(rRegI res, 7600 memory mem_ptr, 7601 rax_RegP oldval, rRegP newval, 7602 rFlagsReg cr) 7603%{ 7604 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0); 7605 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7606 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); 7607 effect(KILL cr, KILL oldval); 7608 7609 format %{ "cmpxchgq $mem_ptr,$newval\t# " 7610 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" 7611 "sete $res\n\t" 7612 "movzbl $res, $res" %} 7613 opcode(0x0F, 0xB1); 7614 ins_encode(lock_prefix, 7615 REX_reg_mem_wide(newval, mem_ptr), 7616 OpcP, OpcS, 7617 reg_mem(newval, mem_ptr), 7618 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete 7619 REX_reg_breg(res, res), // movzbl 7620 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); 7621 ins_pipe( pipe_cmpxchg ); 7622%} 7623 7624instruct compareAndSwapL(rRegI res, 7625 memory mem_ptr, 7626 rax_RegL oldval, rRegL newval, 7627 rFlagsReg cr) 7628%{ 7629 predicate(VM_Version::supports_cx8()); 7630 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7631 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval))); 7632 effect(KILL cr, KILL oldval); 7633 7634 format %{ "cmpxchgq $mem_ptr,$newval\t# " 7635 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" 7636 "sete $res\n\t" 7637 "movzbl $res, $res" %} 7638 opcode(0x0F, 0xB1); 7639 ins_encode(lock_prefix, 7640 REX_reg_mem_wide(newval, mem_ptr), 7641 OpcP, OpcS, 7642 reg_mem(newval, mem_ptr), 7643 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete 7644 REX_reg_breg(res, res), // movzbl 7645 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); 7646 ins_pipe( pipe_cmpxchg ); 7647%} 7648 7649instruct compareAndSwapI(rRegI res, 7650 memory mem_ptr, 7651 rax_RegI oldval, rRegI newval, 7652 rFlagsReg cr) 7653%{ 7654 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7655 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval))); 7656 effect(KILL cr, KILL oldval); 7657 7658 format %{ "cmpxchgl $mem_ptr,$newval\t# " 7659 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" 7660 "sete $res\n\t" 7661 "movzbl $res, $res" %} 7662 opcode(0x0F, 0xB1); 7663 ins_encode(lock_prefix, 7664 REX_reg_mem(newval, mem_ptr), 7665 OpcP, OpcS, 7666 reg_mem(newval, mem_ptr), 7667 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete 7668 REX_reg_breg(res, res), // movzbl 7669 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); 7670 ins_pipe( pipe_cmpxchg ); 7671%} 7672 7673instruct compareAndSwapB(rRegI res, 7674 memory mem_ptr, 7675 rax_RegI oldval, rRegI newval, 7676 rFlagsReg cr) 7677%{ 7678 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval))); 7679 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval))); 7680 effect(KILL cr, KILL oldval); 7681 7682 format %{ "cmpxchgb $mem_ptr,$newval\t# " 7683 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" 7684 "sete $res\n\t" 7685 "movzbl $res, $res" %} 7686 opcode(0x0F, 0xB0); 7687 ins_encode(lock_prefix, 7688 REX_breg_mem(newval, mem_ptr), 7689 OpcP, OpcS, 7690 reg_mem(newval, mem_ptr), 7691 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete 7692 REX_reg_breg(res, res), // movzbl 7693 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); 7694 ins_pipe( pipe_cmpxchg ); 7695%} 7696 7697instruct compareAndSwapS(rRegI res, 7698 memory mem_ptr, 7699 rax_RegI oldval, rRegI newval, 7700 rFlagsReg cr) 7701%{ 7702 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval))); 7703 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval))); 7704 effect(KILL cr, KILL oldval); 7705 7706 format %{ "cmpxchgw $mem_ptr,$newval\t# " 7707 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" 7708 "sete $res\n\t" 7709 "movzbl $res, $res" %} 7710 opcode(0x0F, 0xB1); 7711 ins_encode(lock_prefix, 7712 SizePrefix, 7713 REX_reg_mem(newval, mem_ptr), 7714 OpcP, OpcS, 7715 reg_mem(newval, mem_ptr), 7716 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete 7717 REX_reg_breg(res, res), // movzbl 7718 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); 7719 ins_pipe( pipe_cmpxchg ); 7720%} 7721 7722instruct compareAndSwapN(rRegI res, 7723 memory mem_ptr, 7724 rax_RegN oldval, rRegN newval, 7725 rFlagsReg cr) %{ 7726 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7727 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval))); 7728 effect(KILL cr, KILL oldval); 7729 7730 format %{ "cmpxchgl $mem_ptr,$newval\t# " 7731 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" 7732 "sete $res\n\t" 7733 "movzbl $res, $res" %} 7734 opcode(0x0F, 0xB1); 7735 ins_encode(lock_prefix, 7736 REX_reg_mem(newval, mem_ptr), 7737 OpcP, OpcS, 7738 reg_mem(newval, mem_ptr), 7739 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete 7740 REX_reg_breg(res, res), // movzbl 7741 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); 7742 ins_pipe( pipe_cmpxchg ); 7743%} 7744 7745instruct compareAndExchangeB( 7746 memory mem_ptr, 7747 rax_RegI oldval, rRegI newval, 7748 rFlagsReg cr) 7749%{ 7750 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval))); 7751 effect(KILL cr); 7752 7753 format %{ "cmpxchgb $mem_ptr,$newval\t# " 7754 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} 7755 opcode(0x0F, 0xB0); 7756 ins_encode(lock_prefix, 7757 REX_breg_mem(newval, mem_ptr), 7758 OpcP, OpcS, 7759 reg_mem(newval, mem_ptr) // lock cmpxchg 7760 ); 7761 ins_pipe( pipe_cmpxchg ); 7762%} 7763 7764instruct compareAndExchangeS( 7765 memory mem_ptr, 7766 rax_RegI oldval, rRegI newval, 7767 rFlagsReg cr) 7768%{ 7769 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval))); 7770 effect(KILL cr); 7771 7772 format %{ "cmpxchgw $mem_ptr,$newval\t# " 7773 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} 7774 opcode(0x0F, 0xB1); 7775 ins_encode(lock_prefix, 7776 SizePrefix, 7777 REX_reg_mem(newval, mem_ptr), 7778 OpcP, OpcS, 7779 reg_mem(newval, mem_ptr) // lock cmpxchg 7780 ); 7781 ins_pipe( pipe_cmpxchg ); 7782%} 7783 7784instruct compareAndExchangeI( 7785 memory mem_ptr, 7786 rax_RegI oldval, rRegI newval, 7787 rFlagsReg cr) 7788%{ 7789 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval))); 7790 effect(KILL cr); 7791 7792 format %{ "cmpxchgl $mem_ptr,$newval\t# " 7793 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} 7794 opcode(0x0F, 0xB1); 7795 ins_encode(lock_prefix, 7796 REX_reg_mem(newval, mem_ptr), 7797 OpcP, OpcS, 7798 reg_mem(newval, mem_ptr) // lock cmpxchg 7799 ); 7800 ins_pipe( pipe_cmpxchg ); 7801%} 7802 7803instruct compareAndExchangeL( 7804 memory mem_ptr, 7805 rax_RegL oldval, rRegL newval, 7806 rFlagsReg cr) 7807%{ 7808 predicate(VM_Version::supports_cx8()); 7809 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval))); 7810 effect(KILL cr); 7811 7812 format %{ "cmpxchgq $mem_ptr,$newval\t# " 7813 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} 7814 opcode(0x0F, 0xB1); 7815 ins_encode(lock_prefix, 7816 REX_reg_mem_wide(newval, mem_ptr), 7817 OpcP, OpcS, 7818 reg_mem(newval, mem_ptr) // lock cmpxchg 7819 ); 7820 ins_pipe( pipe_cmpxchg ); 7821%} 7822 7823instruct compareAndExchangeN( 7824 memory mem_ptr, 7825 rax_RegN oldval, rRegN newval, 7826 rFlagsReg cr) %{ 7827 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval))); 7828 effect(KILL cr); 7829 7830 format %{ "cmpxchgl $mem_ptr,$newval\t# " 7831 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} 7832 opcode(0x0F, 0xB1); 7833 ins_encode(lock_prefix, 7834 REX_reg_mem(newval, mem_ptr), 7835 OpcP, OpcS, 7836 reg_mem(newval, mem_ptr) // lock cmpxchg 7837 ); 7838 ins_pipe( pipe_cmpxchg ); 7839%} 7840 7841instruct compareAndExchangeP( 7842 memory mem_ptr, 7843 rax_RegP oldval, rRegP newval, 7844 rFlagsReg cr) 7845%{ 7846 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0); 7847 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval))); 7848 effect(KILL cr); 7849 7850 format %{ "cmpxchgq $mem_ptr,$newval\t# " 7851 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} 7852 opcode(0x0F, 0xB1); 7853 ins_encode(lock_prefix, 7854 REX_reg_mem_wide(newval, mem_ptr), 7855 OpcP, OpcS, 7856 reg_mem(newval, mem_ptr) // lock cmpxchg 7857 ); 7858 ins_pipe( pipe_cmpxchg ); 7859%} 7860 7861instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{ 7862 predicate(n->as_LoadStore()->result_not_used()); 7863 match(Set dummy (GetAndAddB mem add)); 7864 effect(KILL cr); 7865 format %{ "ADDB [$mem],$add" %} 7866 ins_encode %{ 7867 __ lock(); 7868 __ addb($mem$$Address, $add$$constant); 7869 %} 7870 ins_pipe( pipe_cmpxchg ); 7871%} 7872 7873instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{ 7874 match(Set newval (GetAndAddB mem newval)); 7875 effect(KILL cr); 7876 format %{ "XADDB [$mem],$newval" %} 7877 ins_encode %{ 7878 __ lock(); 7879 __ xaddb($mem$$Address, $newval$$Register); 7880 %} 7881 ins_pipe( pipe_cmpxchg ); 7882%} 7883 7884instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{ 7885 predicate(n->as_LoadStore()->result_not_used()); 7886 match(Set dummy (GetAndAddS mem add)); 7887 effect(KILL cr); 7888 format %{ "ADDW [$mem],$add" %} 7889 ins_encode %{ 7890 __ lock(); 7891 __ addw($mem$$Address, $add$$constant); 7892 %} 7893 ins_pipe( pipe_cmpxchg ); 7894%} 7895 7896instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{ 7897 match(Set newval (GetAndAddS mem newval)); 7898 effect(KILL cr); 7899 format %{ "XADDW [$mem],$newval" %} 7900 ins_encode %{ 7901 __ lock(); 7902 __ xaddw($mem$$Address, $newval$$Register); 7903 %} 7904 ins_pipe( pipe_cmpxchg ); 7905%} 7906 7907instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{ 7908 predicate(n->as_LoadStore()->result_not_used()); 7909 match(Set dummy (GetAndAddI mem add)); 7910 effect(KILL cr); 7911 format %{ "ADDL [$mem],$add" %} 7912 ins_encode %{ 7913 __ lock(); 7914 __ addl($mem$$Address, $add$$constant); 7915 %} 7916 ins_pipe( pipe_cmpxchg ); 7917%} 7918 7919instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{ 7920 match(Set newval (GetAndAddI mem newval)); 7921 effect(KILL cr); 7922 format %{ "XADDL [$mem],$newval" %} 7923 ins_encode %{ 7924 __ lock(); 7925 __ xaddl($mem$$Address, $newval$$Register); 7926 %} 7927 ins_pipe( pipe_cmpxchg ); 7928%} 7929 7930instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{ 7931 predicate(n->as_LoadStore()->result_not_used()); 7932 match(Set dummy (GetAndAddL mem add)); 7933 effect(KILL cr); 7934 format %{ "ADDQ [$mem],$add" %} 7935 ins_encode %{ 7936 __ lock(); 7937 __ addq($mem$$Address, $add$$constant); 7938 %} 7939 ins_pipe( pipe_cmpxchg ); 7940%} 7941 7942instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{ 7943 match(Set newval (GetAndAddL mem newval)); 7944 effect(KILL cr); 7945 format %{ "XADDQ [$mem],$newval" %} 7946 ins_encode %{ 7947 __ lock(); 7948 __ xaddq($mem$$Address, $newval$$Register); 7949 %} 7950 ins_pipe( pipe_cmpxchg ); 7951%} 7952 7953instruct xchgB( memory mem, rRegI newval) %{ 7954 match(Set newval (GetAndSetB mem newval)); 7955 format %{ "XCHGB $newval,[$mem]" %} 7956 ins_encode %{ 7957 __ xchgb($newval$$Register, $mem$$Address); 7958 %} 7959 ins_pipe( pipe_cmpxchg ); 7960%} 7961 7962instruct xchgS( memory mem, rRegI newval) %{ 7963 match(Set newval (GetAndSetS mem newval)); 7964 format %{ "XCHGW $newval,[$mem]" %} 7965 ins_encode %{ 7966 __ xchgw($newval$$Register, $mem$$Address); 7967 %} 7968 ins_pipe( pipe_cmpxchg ); 7969%} 7970 7971instruct xchgI( memory mem, rRegI newval) %{ 7972 match(Set newval (GetAndSetI mem newval)); 7973 format %{ "XCHGL $newval,[$mem]" %} 7974 ins_encode %{ 7975 __ xchgl($newval$$Register, $mem$$Address); 7976 %} 7977 ins_pipe( pipe_cmpxchg ); 7978%} 7979 7980instruct xchgL( memory mem, rRegL newval) %{ 7981 match(Set newval (GetAndSetL mem newval)); 7982 format %{ "XCHGL $newval,[$mem]" %} 7983 ins_encode %{ 7984 __ xchgq($newval$$Register, $mem$$Address); 7985 %} 7986 ins_pipe( pipe_cmpxchg ); 7987%} 7988 7989instruct xchgP( memory mem, rRegP newval) %{ 7990 match(Set newval (GetAndSetP mem newval)); 7991 predicate(n->as_LoadStore()->barrier_data() == 0); 7992 format %{ "XCHGQ $newval,[$mem]" %} 7993 ins_encode %{ 7994 __ xchgq($newval$$Register, $mem$$Address); 7995 %} 7996 ins_pipe( pipe_cmpxchg ); 7997%} 7998 7999instruct xchgN( memory mem, rRegN newval) %{ 8000 match(Set newval (GetAndSetN mem newval)); 8001 format %{ "XCHGL $newval,$mem]" %} 8002 ins_encode %{ 8003 __ xchgl($newval$$Register, $mem$$Address); 8004 %} 8005 ins_pipe( pipe_cmpxchg ); 8006%} 8007 8008//----------Abs Instructions------------------------------------------- 8009 8010// Integer Absolute Instructions 8011instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr) 8012%{ 8013 match(Set dst (AbsI src)); 8014 effect(TEMP dst, TEMP tmp, KILL cr); 8015 format %{ "movl $tmp, $src\n\t" 8016 "sarl $tmp, 31\n\t" 8017 "movl $dst, $src\n\t" 8018 "xorl $dst, $tmp\n\t" 8019 "subl $dst, $tmp\n" 8020 %} 8021 ins_encode %{ 8022 __ movl($tmp$$Register, $src$$Register); 8023 __ sarl($tmp$$Register, 31); 8024 __ movl($dst$$Register, $src$$Register); 8025 __ xorl($dst$$Register, $tmp$$Register); 8026 __ subl($dst$$Register, $tmp$$Register); 8027 %} 8028 8029 ins_pipe(ialu_reg_reg); 8030%} 8031 8032// Long Absolute Instructions 8033instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr) 8034%{ 8035 match(Set dst (AbsL src)); 8036 effect(TEMP dst, TEMP tmp, KILL cr); 8037 format %{ "movq $tmp, $src\n\t" 8038 "sarq $tmp, 63\n\t" 8039 "movq $dst, $src\n\t" 8040 "xorq $dst, $tmp\n\t" 8041 "subq $dst, $tmp\n" 8042 %} 8043 ins_encode %{ 8044 __ movq($tmp$$Register, $src$$Register); 8045 __ sarq($tmp$$Register, 63); 8046 __ movq($dst$$Register, $src$$Register); 8047 __ xorq($dst$$Register, $tmp$$Register); 8048 __ subq($dst$$Register, $tmp$$Register); 8049 %} 8050 8051 ins_pipe(ialu_reg_reg); 8052%} 8053 8054//----------Subtraction Instructions------------------------------------------- 8055 8056// Integer Subtraction Instructions 8057instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 8058%{ 8059 match(Set dst (SubI dst src)); 8060 effect(KILL cr); 8061 8062 format %{ "subl $dst, $src\t# int" %} 8063 opcode(0x2B); 8064 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); 8065 ins_pipe(ialu_reg_reg); 8066%} 8067 8068instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) 8069%{ 8070 match(Set dst (SubI dst src)); 8071 effect(KILL cr); 8072 8073 format %{ "subl $dst, $src\t# int" %} 8074 opcode(0x81, 0x05); /* Opcode 81 /5 */ 8075 ins_encode(OpcSErm(dst, src), Con8or32(src)); 8076 ins_pipe(ialu_reg); 8077%} 8078 8079instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) 8080%{ 8081 match(Set dst (SubI dst (LoadI src))); 8082 effect(KILL cr); 8083 8084 ins_cost(125); 8085 format %{ "subl $dst, $src\t# int" %} 8086 opcode(0x2B); 8087 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); 8088 ins_pipe(ialu_reg_mem); 8089%} 8090 8091instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) 8092%{ 8093 match(Set dst (StoreI dst (SubI (LoadI dst) src))); 8094 effect(KILL cr); 8095 8096 ins_cost(150); 8097 format %{ "subl $dst, $src\t# int" %} 8098 opcode(0x29); /* Opcode 29 /r */ 8099 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); 8100 ins_pipe(ialu_mem_reg); 8101%} 8102 8103instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) 8104%{ 8105 match(Set dst (StoreI dst (SubI (LoadI dst) src))); 8106 effect(KILL cr); 8107 8108 ins_cost(125); // XXX 8109 format %{ "subl $dst, $src\t# int" %} 8110 opcode(0x81); /* Opcode 81 /5 id */ 8111 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); 8112 ins_pipe(ialu_mem_imm); 8113%} 8114 8115instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) 8116%{ 8117 match(Set dst (SubL dst src)); 8118 effect(KILL cr); 8119 8120 format %{ "subq $dst, $src\t# long" %} 8121 opcode(0x2B); 8122 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); 8123 ins_pipe(ialu_reg_reg); 8124%} 8125 8126instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) 8127%{ 8128 match(Set dst (SubL dst src)); 8129 effect(KILL cr); 8130 8131 format %{ "subq $dst, $src\t# long" %} 8132 opcode(0x81, 0x05); /* Opcode 81 /5 */ 8133 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); 8134 ins_pipe(ialu_reg); 8135%} 8136 8137instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) 8138%{ 8139 match(Set dst (SubL dst (LoadL src))); 8140 effect(KILL cr); 8141 8142 ins_cost(125); 8143 format %{ "subq $dst, $src\t# long" %} 8144 opcode(0x2B); 8145 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); 8146 ins_pipe(ialu_reg_mem); 8147%} 8148 8149instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) 8150%{ 8151 match(Set dst (StoreL dst (SubL (LoadL dst) src))); 8152 effect(KILL cr); 8153 8154 ins_cost(150); 8155 format %{ "subq $dst, $src\t# long" %} 8156 opcode(0x29); /* Opcode 29 /r */ 8157 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); 8158 ins_pipe(ialu_mem_reg); 8159%} 8160 8161instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) 8162%{ 8163 match(Set dst (StoreL dst (SubL (LoadL dst) src))); 8164 effect(KILL cr); 8165 8166 ins_cost(125); // XXX 8167 format %{ "subq $dst, $src\t# long" %} 8168 opcode(0x81); /* Opcode 81 /5 id */ 8169 ins_encode(REX_mem_wide(dst), 8170 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); 8171 ins_pipe(ialu_mem_imm); 8172%} 8173 8174// Subtract from a pointer 8175// XXX hmpf??? 8176instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) 8177%{ 8178 match(Set dst (AddP dst (SubI zero src))); 8179 effect(KILL cr); 8180 8181 format %{ "subq $dst, $src\t# ptr - int" %} 8182 opcode(0x2B); 8183 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); 8184 ins_pipe(ialu_reg_reg); 8185%} 8186 8187instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) 8188%{ 8189 match(Set dst (SubI zero dst)); 8190 effect(KILL cr); 8191 8192 format %{ "negl $dst\t# int" %} 8193 opcode(0xF7, 0x03); // Opcode F7 /3 8194 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 8195 ins_pipe(ialu_reg); 8196%} 8197 8198instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) 8199%{ 8200 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); 8201 effect(KILL cr); 8202 8203 format %{ "negl $dst\t# int" %} 8204 opcode(0xF7, 0x03); // Opcode F7 /3 8205 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); 8206 ins_pipe(ialu_reg); 8207%} 8208 8209instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) 8210%{ 8211 match(Set dst (SubL zero dst)); 8212 effect(KILL cr); 8213 8214 format %{ "negq $dst\t# long" %} 8215 opcode(0xF7, 0x03); // Opcode F7 /3 8216 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 8217 ins_pipe(ialu_reg); 8218%} 8219 8220instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) 8221%{ 8222 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); 8223 effect(KILL cr); 8224 8225 format %{ "negq $dst\t# long" %} 8226 opcode(0xF7, 0x03); // Opcode F7 /3 8227 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); 8228 ins_pipe(ialu_reg); 8229%} 8230 8231//----------Multiplication/Division Instructions------------------------------- 8232// Integer Multiplication Instructions 8233// Multiply Register 8234 8235instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 8236%{ 8237 match(Set dst (MulI dst src)); 8238 effect(KILL cr); 8239 8240 ins_cost(300); 8241 format %{ "imull $dst, $src\t# int" %} 8242 opcode(0x0F, 0xAF); 8243 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); 8244 ins_pipe(ialu_reg_reg_alu0); 8245%} 8246 8247instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) 8248%{ 8249 match(Set dst (MulI src imm)); 8250 effect(KILL cr); 8251 8252 ins_cost(300); 8253 format %{ "imull $dst, $src, $imm\t# int" %} 8254 opcode(0x69); /* 69 /r id */ 8255 ins_encode(REX_reg_reg(dst, src), 8256 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); 8257 ins_pipe(ialu_reg_reg_alu0); 8258%} 8259 8260instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) 8261%{ 8262 match(Set dst (MulI dst (LoadI src))); 8263 effect(KILL cr); 8264 8265 ins_cost(350); 8266 format %{ "imull $dst, $src\t# int" %} 8267 opcode(0x0F, 0xAF); 8268 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); 8269 ins_pipe(ialu_reg_mem_alu0); 8270%} 8271 8272instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) 8273%{ 8274 match(Set dst (MulI (LoadI src) imm)); 8275 effect(KILL cr); 8276 8277 ins_cost(300); 8278 format %{ "imull $dst, $src, $imm\t# int" %} 8279 opcode(0x69); /* 69 /r id */ 8280 ins_encode(REX_reg_mem(dst, src), 8281 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); 8282 ins_pipe(ialu_reg_mem_alu0); 8283%} 8284 8285instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr) 8286%{ 8287 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3))); 8288 effect(KILL cr, KILL src2); 8289 8290 expand %{ mulI_rReg(dst, src1, cr); 8291 mulI_rReg(src2, src3, cr); 8292 addI_rReg(dst, src2, cr); %} 8293%} 8294 8295instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) 8296%{ 8297 match(Set dst (MulL dst src)); 8298 effect(KILL cr); 8299 8300 ins_cost(300); 8301 format %{ "imulq $dst, $src\t# long" %} 8302 opcode(0x0F, 0xAF); 8303 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); 8304 ins_pipe(ialu_reg_reg_alu0); 8305%} 8306 8307instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) 8308%{ 8309 match(Set dst (MulL src imm)); 8310 effect(KILL cr); 8311 8312 ins_cost(300); 8313 format %{ "imulq $dst, $src, $imm\t# long" %} 8314 opcode(0x69); /* 69 /r id */ 8315 ins_encode(REX_reg_reg_wide(dst, src), 8316 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); 8317 ins_pipe(ialu_reg_reg_alu0); 8318%} 8319 8320instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) 8321%{ 8322 match(Set dst (MulL dst (LoadL src))); 8323 effect(KILL cr); 8324 8325 ins_cost(350); 8326 format %{ "imulq $dst, $src\t# long" %} 8327 opcode(0x0F, 0xAF); 8328 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); 8329 ins_pipe(ialu_reg_mem_alu0); 8330%} 8331 8332instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) 8333%{ 8334 match(Set dst (MulL (LoadL src) imm)); 8335 effect(KILL cr); 8336 8337 ins_cost(300); 8338 format %{ "imulq $dst, $src, $imm\t# long" %} 8339 opcode(0x69); /* 69 /r id */ 8340 ins_encode(REX_reg_mem_wide(dst, src), 8341 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); 8342 ins_pipe(ialu_reg_mem_alu0); 8343%} 8344 8345instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) 8346%{ 8347 match(Set dst (MulHiL src rax)); 8348 effect(USE_KILL rax, KILL cr); 8349 8350 ins_cost(300); 8351 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} 8352 opcode(0xF7, 0x5); /* Opcode F7 /5 */ 8353 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); 8354 ins_pipe(ialu_reg_reg_alu0); 8355%} 8356 8357instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, 8358 rFlagsReg cr) 8359%{ 8360 match(Set rax (DivI rax div)); 8361 effect(KILL rdx, KILL cr); 8362 8363 ins_cost(30*100+10*100); // XXX 8364 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" 8365 "jne,s normal\n\t" 8366 "xorl rdx, rdx\n\t" 8367 "cmpl $div, -1\n\t" 8368 "je,s done\n" 8369 "normal: cdql\n\t" 8370 "idivl $div\n" 8371 "done:" %} 8372 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8373 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); 8374 ins_pipe(ialu_reg_reg_alu0); 8375%} 8376 8377instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, 8378 rFlagsReg cr) 8379%{ 8380 match(Set rax (DivL rax div)); 8381 effect(KILL rdx, KILL cr); 8382 8383 ins_cost(30*100+10*100); // XXX 8384 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" 8385 "cmpq rax, rdx\n\t" 8386 "jne,s normal\n\t" 8387 "xorl rdx, rdx\n\t" 8388 "cmpq $div, -1\n\t" 8389 "je,s done\n" 8390 "normal: cdqq\n\t" 8391 "idivq $div\n" 8392 "done:" %} 8393 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8394 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); 8395 ins_pipe(ialu_reg_reg_alu0); 8396%} 8397 8398// Integer DIVMOD with Register, both quotient and mod results 8399instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, 8400 rFlagsReg cr) 8401%{ 8402 match(DivModI rax div); 8403 effect(KILL cr); 8404 8405 ins_cost(30*100+10*100); // XXX 8406 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" 8407 "jne,s normal\n\t" 8408 "xorl rdx, rdx\n\t" 8409 "cmpl $div, -1\n\t" 8410 "je,s done\n" 8411 "normal: cdql\n\t" 8412 "idivl $div\n" 8413 "done:" %} 8414 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8415 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); 8416 ins_pipe(pipe_slow); 8417%} 8418 8419// Long DIVMOD with Register, both quotient and mod results 8420instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, 8421 rFlagsReg cr) 8422%{ 8423 match(DivModL rax div); 8424 effect(KILL cr); 8425 8426 ins_cost(30*100+10*100); // XXX 8427 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" 8428 "cmpq rax, rdx\n\t" 8429 "jne,s normal\n\t" 8430 "xorl rdx, rdx\n\t" 8431 "cmpq $div, -1\n\t" 8432 "je,s done\n" 8433 "normal: cdqq\n\t" 8434 "idivq $div\n" 8435 "done:" %} 8436 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8437 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); 8438 ins_pipe(pipe_slow); 8439%} 8440 8441//----------- DivL-By-Constant-Expansions-------------------------------------- 8442// DivI cases are handled by the compiler 8443 8444// Magic constant, reciprocal of 10 8445instruct loadConL_0x6666666666666667(rRegL dst) 8446%{ 8447 effect(DEF dst); 8448 8449 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} 8450 ins_encode(load_immL(dst, 0x6666666666666667)); 8451 ins_pipe(ialu_reg); 8452%} 8453 8454instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) 8455%{ 8456 effect(DEF dst, USE src, USE_KILL rax, KILL cr); 8457 8458 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} 8459 opcode(0xF7, 0x5); /* Opcode F7 /5 */ 8460 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); 8461 ins_pipe(ialu_reg_reg_alu0); 8462%} 8463 8464instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) 8465%{ 8466 effect(USE_DEF dst, KILL cr); 8467 8468 format %{ "sarq $dst, #63\t# Used in div-by-10" %} 8469 opcode(0xC1, 0x7); /* C1 /7 ib */ 8470 ins_encode(reg_opc_imm_wide(dst, 0x3F)); 8471 ins_pipe(ialu_reg); 8472%} 8473 8474instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) 8475%{ 8476 effect(USE_DEF dst, KILL cr); 8477 8478 format %{ "sarq $dst, #2\t# Used in div-by-10" %} 8479 opcode(0xC1, 0x7); /* C1 /7 ib */ 8480 ins_encode(reg_opc_imm_wide(dst, 0x2)); 8481 ins_pipe(ialu_reg); 8482%} 8483 8484instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) 8485%{ 8486 match(Set dst (DivL src div)); 8487 8488 ins_cost((5+8)*100); 8489 expand %{ 8490 rax_RegL rax; // Killed temp 8491 rFlagsReg cr; // Killed 8492 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 8493 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src 8494 sarL_rReg_63(src, cr); // sarq src, 63 8495 sarL_rReg_2(dst, cr); // sarq rdx, 2 8496 subL_rReg(dst, src, cr); // subl rdx, src 8497 %} 8498%} 8499 8500//----------------------------------------------------------------------------- 8501 8502instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, 8503 rFlagsReg cr) 8504%{ 8505 match(Set rdx (ModI rax div)); 8506 effect(KILL rax, KILL cr); 8507 8508 ins_cost(300); // XXX 8509 format %{ "cmpl rax, 0x80000000\t# irem\n\t" 8510 "jne,s normal\n\t" 8511 "xorl rdx, rdx\n\t" 8512 "cmpl $div, -1\n\t" 8513 "je,s done\n" 8514 "normal: cdql\n\t" 8515 "idivl $div\n" 8516 "done:" %} 8517 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8518 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); 8519 ins_pipe(ialu_reg_reg_alu0); 8520%} 8521 8522instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, 8523 rFlagsReg cr) 8524%{ 8525 match(Set rdx (ModL rax div)); 8526 effect(KILL rax, KILL cr); 8527 8528 ins_cost(300); // XXX 8529 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" 8530 "cmpq rax, rdx\n\t" 8531 "jne,s normal\n\t" 8532 "xorl rdx, rdx\n\t" 8533 "cmpq $div, -1\n\t" 8534 "je,s done\n" 8535 "normal: cdqq\n\t" 8536 "idivq $div\n" 8537 "done:" %} 8538 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8539 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); 8540 ins_pipe(ialu_reg_reg_alu0); 8541%} 8542 8543// Integer Shift Instructions 8544// Shift Left by one 8545instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) 8546%{ 8547 match(Set dst (LShiftI dst shift)); 8548 effect(KILL cr); 8549 8550 format %{ "sall $dst, $shift" %} 8551 opcode(0xD1, 0x4); /* D1 /4 */ 8552 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 8553 ins_pipe(ialu_reg); 8554%} 8555 8556// Shift Left by one 8557instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) 8558%{ 8559 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); 8560 effect(KILL cr); 8561 8562 format %{ "sall $dst, $shift\t" %} 8563 opcode(0xD1, 0x4); /* D1 /4 */ 8564 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); 8565 ins_pipe(ialu_mem_imm); 8566%} 8567 8568// Shift Left by 8-bit immediate 8569instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) 8570%{ 8571 match(Set dst (LShiftI dst shift)); 8572 effect(KILL cr); 8573 8574 format %{ "sall $dst, $shift" %} 8575 opcode(0xC1, 0x4); /* C1 /4 ib */ 8576 ins_encode(reg_opc_imm(dst, shift)); 8577 ins_pipe(ialu_reg); 8578%} 8579 8580// Shift Left by 8-bit immediate 8581instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) 8582%{ 8583 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); 8584 effect(KILL cr); 8585 8586 format %{ "sall $dst, $shift" %} 8587 opcode(0xC1, 0x4); /* C1 /4 ib */ 8588 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); 8589 ins_pipe(ialu_mem_imm); 8590%} 8591 8592// Shift Left by variable 8593instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) 8594%{ 8595 match(Set dst (LShiftI dst shift)); 8596 effect(KILL cr); 8597 8598 format %{ "sall $dst, $shift" %} 8599 opcode(0xD3, 0x4); /* D3 /4 */ 8600 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 8601 ins_pipe(ialu_reg_reg); 8602%} 8603 8604// Shift Left by variable 8605instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) 8606%{ 8607 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); 8608 effect(KILL cr); 8609 8610 format %{ "sall $dst, $shift" %} 8611 opcode(0xD3, 0x4); /* D3 /4 */ 8612 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); 8613 ins_pipe(ialu_mem_reg); 8614%} 8615 8616// Arithmetic shift right by one 8617instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) 8618%{ 8619 match(Set dst (RShiftI dst shift)); 8620 effect(KILL cr); 8621 8622 format %{ "sarl $dst, $shift" %} 8623 opcode(0xD1, 0x7); /* D1 /7 */ 8624 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 8625 ins_pipe(ialu_reg); 8626%} 8627 8628// Arithmetic shift right by one 8629instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) 8630%{ 8631 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8632 effect(KILL cr); 8633 8634 format %{ "sarl $dst, $shift" %} 8635 opcode(0xD1, 0x7); /* D1 /7 */ 8636 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); 8637 ins_pipe(ialu_mem_imm); 8638%} 8639 8640// Arithmetic Shift Right by 8-bit immediate 8641instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) 8642%{ 8643 match(Set dst (RShiftI dst shift)); 8644 effect(KILL cr); 8645 8646 format %{ "sarl $dst, $shift" %} 8647 opcode(0xC1, 0x7); /* C1 /7 ib */ 8648 ins_encode(reg_opc_imm(dst, shift)); 8649 ins_pipe(ialu_mem_imm); 8650%} 8651 8652// Arithmetic Shift Right by 8-bit immediate 8653instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) 8654%{ 8655 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8656 effect(KILL cr); 8657 8658 format %{ "sarl $dst, $shift" %} 8659 opcode(0xC1, 0x7); /* C1 /7 ib */ 8660 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); 8661 ins_pipe(ialu_mem_imm); 8662%} 8663 8664// Arithmetic Shift Right by variable 8665instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) 8666%{ 8667 match(Set dst (RShiftI dst shift)); 8668 effect(KILL cr); 8669 8670 format %{ "sarl $dst, $shift" %} 8671 opcode(0xD3, 0x7); /* D3 /7 */ 8672 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 8673 ins_pipe(ialu_reg_reg); 8674%} 8675 8676// Arithmetic Shift Right by variable 8677instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) 8678%{ 8679 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8680 effect(KILL cr); 8681 8682 format %{ "sarl $dst, $shift" %} 8683 opcode(0xD3, 0x7); /* D3 /7 */ 8684 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); 8685 ins_pipe(ialu_mem_reg); 8686%} 8687 8688// Logical shift right by one 8689instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) 8690%{ 8691 match(Set dst (URShiftI dst shift)); 8692 effect(KILL cr); 8693 8694 format %{ "shrl $dst, $shift" %} 8695 opcode(0xD1, 0x5); /* D1 /5 */ 8696 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 8697 ins_pipe(ialu_reg); 8698%} 8699 8700// Logical shift right by one 8701instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) 8702%{ 8703 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); 8704 effect(KILL cr); 8705 8706 format %{ "shrl $dst, $shift" %} 8707 opcode(0xD1, 0x5); /* D1 /5 */ 8708 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); 8709 ins_pipe(ialu_mem_imm); 8710%} 8711 8712// Logical Shift Right by 8-bit immediate 8713instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) 8714%{ 8715 match(Set dst (URShiftI dst shift)); 8716 effect(KILL cr); 8717 8718 format %{ "shrl $dst, $shift" %} 8719 opcode(0xC1, 0x5); /* C1 /5 ib */ 8720 ins_encode(reg_opc_imm(dst, shift)); 8721 ins_pipe(ialu_reg); 8722%} 8723 8724// Logical Shift Right by 8-bit immediate 8725instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) 8726%{ 8727 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); 8728 effect(KILL cr); 8729 8730 format %{ "shrl $dst, $shift" %} 8731 opcode(0xC1, 0x5); /* C1 /5 ib */ 8732 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); 8733 ins_pipe(ialu_mem_imm); 8734%} 8735 8736// Logical Shift Right by variable 8737instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) 8738%{ 8739 match(Set dst (URShiftI dst shift)); 8740 effect(KILL cr); 8741 8742 format %{ "shrl $dst, $shift" %} 8743 opcode(0xD3, 0x5); /* D3 /5 */ 8744 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 8745 ins_pipe(ialu_reg_reg); 8746%} 8747 8748// Logical Shift Right by variable 8749instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) 8750%{ 8751 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); 8752 effect(KILL cr); 8753 8754 format %{ "shrl $dst, $shift" %} 8755 opcode(0xD3, 0x5); /* D3 /5 */ 8756 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); 8757 ins_pipe(ialu_mem_reg); 8758%} 8759 8760// Long Shift Instructions 8761// Shift Left by one 8762instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) 8763%{ 8764 match(Set dst (LShiftL dst shift)); 8765 effect(KILL cr); 8766 8767 format %{ "salq $dst, $shift" %} 8768 opcode(0xD1, 0x4); /* D1 /4 */ 8769 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 8770 ins_pipe(ialu_reg); 8771%} 8772 8773// Shift Left by one 8774instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) 8775%{ 8776 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); 8777 effect(KILL cr); 8778 8779 format %{ "salq $dst, $shift" %} 8780 opcode(0xD1, 0x4); /* D1 /4 */ 8781 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); 8782 ins_pipe(ialu_mem_imm); 8783%} 8784 8785// Shift Left by 8-bit immediate 8786instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) 8787%{ 8788 match(Set dst (LShiftL dst shift)); 8789 effect(KILL cr); 8790 8791 format %{ "salq $dst, $shift" %} 8792 opcode(0xC1, 0x4); /* C1 /4 ib */ 8793 ins_encode(reg_opc_imm_wide(dst, shift)); 8794 ins_pipe(ialu_reg); 8795%} 8796 8797// Shift Left by 8-bit immediate 8798instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) 8799%{ 8800 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); 8801 effect(KILL cr); 8802 8803 format %{ "salq $dst, $shift" %} 8804 opcode(0xC1, 0x4); /* C1 /4 ib */ 8805 ins_encode(REX_mem_wide(dst), OpcP, 8806 RM_opc_mem(secondary, dst), Con8or32(shift)); 8807 ins_pipe(ialu_mem_imm); 8808%} 8809 8810// Shift Left by variable 8811instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) 8812%{ 8813 match(Set dst (LShiftL dst shift)); 8814 effect(KILL cr); 8815 8816 format %{ "salq $dst, $shift" %} 8817 opcode(0xD3, 0x4); /* D3 /4 */ 8818 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 8819 ins_pipe(ialu_reg_reg); 8820%} 8821 8822// Shift Left by variable 8823instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) 8824%{ 8825 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); 8826 effect(KILL cr); 8827 8828 format %{ "salq $dst, $shift" %} 8829 opcode(0xD3, 0x4); /* D3 /4 */ 8830 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); 8831 ins_pipe(ialu_mem_reg); 8832%} 8833 8834// Arithmetic shift right by one 8835instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) 8836%{ 8837 match(Set dst (RShiftL dst shift)); 8838 effect(KILL cr); 8839 8840 format %{ "sarq $dst, $shift" %} 8841 opcode(0xD1, 0x7); /* D1 /7 */ 8842 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 8843 ins_pipe(ialu_reg); 8844%} 8845 8846// Arithmetic shift right by one 8847instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) 8848%{ 8849 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); 8850 effect(KILL cr); 8851 8852 format %{ "sarq $dst, $shift" %} 8853 opcode(0xD1, 0x7); /* D1 /7 */ 8854 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); 8855 ins_pipe(ialu_mem_imm); 8856%} 8857 8858// Arithmetic Shift Right by 8-bit immediate 8859instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) 8860%{ 8861 match(Set dst (RShiftL dst shift)); 8862 effect(KILL cr); 8863 8864 format %{ "sarq $dst, $shift" %} 8865 opcode(0xC1, 0x7); /* C1 /7 ib */ 8866 ins_encode(reg_opc_imm_wide(dst, shift)); 8867 ins_pipe(ialu_mem_imm); 8868%} 8869 8870// Arithmetic Shift Right by 8-bit immediate 8871instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) 8872%{ 8873 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); 8874 effect(KILL cr); 8875 8876 format %{ "sarq $dst, $shift" %} 8877 opcode(0xC1, 0x7); /* C1 /7 ib */ 8878 ins_encode(REX_mem_wide(dst), OpcP, 8879 RM_opc_mem(secondary, dst), Con8or32(shift)); 8880 ins_pipe(ialu_mem_imm); 8881%} 8882 8883// Arithmetic Shift Right by variable 8884instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) 8885%{ 8886 match(Set dst (RShiftL dst shift)); 8887 effect(KILL cr); 8888 8889 format %{ "sarq $dst, $shift" %} 8890 opcode(0xD3, 0x7); /* D3 /7 */ 8891 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 8892 ins_pipe(ialu_reg_reg); 8893%} 8894 8895// Arithmetic Shift Right by variable 8896instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) 8897%{ 8898 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); 8899 effect(KILL cr); 8900 8901 format %{ "sarq $dst, $shift" %} 8902 opcode(0xD3, 0x7); /* D3 /7 */ 8903 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); 8904 ins_pipe(ialu_mem_reg); 8905%} 8906 8907// Logical shift right by one 8908instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) 8909%{ 8910 match(Set dst (URShiftL dst shift)); 8911 effect(KILL cr); 8912 8913 format %{ "shrq $dst, $shift" %} 8914 opcode(0xD1, 0x5); /* D1 /5 */ 8915 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); 8916 ins_pipe(ialu_reg); 8917%} 8918 8919// Logical shift right by one 8920instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) 8921%{ 8922 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); 8923 effect(KILL cr); 8924 8925 format %{ "shrq $dst, $shift" %} 8926 opcode(0xD1, 0x5); /* D1 /5 */ 8927 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); 8928 ins_pipe(ialu_mem_imm); 8929%} 8930 8931// Logical Shift Right by 8-bit immediate 8932instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) 8933%{ 8934 match(Set dst (URShiftL dst shift)); 8935 effect(KILL cr); 8936 8937 format %{ "shrq $dst, $shift" %} 8938 opcode(0xC1, 0x5); /* C1 /5 ib */ 8939 ins_encode(reg_opc_imm_wide(dst, shift)); 8940 ins_pipe(ialu_reg); 8941%} 8942 8943 8944// Logical Shift Right by 8-bit immediate 8945instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) 8946%{ 8947 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); 8948 effect(KILL cr); 8949 8950 format %{ "shrq $dst, $shift" %} 8951 opcode(0xC1, 0x5); /* C1 /5 ib */ 8952 ins_encode(REX_mem_wide(dst), OpcP, 8953 RM_opc_mem(secondary, dst), Con8or32(shift)); 8954 ins_pipe(ialu_mem_imm); 8955%} 8956 8957// Logical Shift Right by variable 8958instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) 8959%{ 8960 match(Set dst (URShiftL dst shift)); 8961 effect(KILL cr); 8962 8963 format %{ "shrq $dst, $shift" %} 8964 opcode(0xD3, 0x5); /* D3 /5 */ 8965 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 8966 ins_pipe(ialu_reg_reg); 8967%} 8968 8969// Logical Shift Right by variable 8970instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) 8971%{ 8972 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); 8973 effect(KILL cr); 8974 8975 format %{ "shrq $dst, $shift" %} 8976 opcode(0xD3, 0x5); /* D3 /5 */ 8977 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); 8978 ins_pipe(ialu_mem_reg); 8979%} 8980 8981// Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. 8982// This idiom is used by the compiler for the i2b bytecode. 8983instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) 8984%{ 8985 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); 8986 8987 format %{ "movsbl $dst, $src\t# i2b" %} 8988 opcode(0x0F, 0xBE); 8989 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); 8990 ins_pipe(ialu_reg_reg); 8991%} 8992 8993// Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. 8994// This idiom is used by the compiler the i2s bytecode. 8995instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) 8996%{ 8997 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); 8998 8999 format %{ "movswl $dst, $src\t# i2s" %} 9000 opcode(0x0F, 0xBF); 9001 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); 9002 ins_pipe(ialu_reg_reg); 9003%} 9004 9005// ROL/ROR instructions 9006 9007// ROL expand 9008instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ 9009 effect(KILL cr, USE_DEF dst); 9010 9011 format %{ "roll $dst" %} 9012 opcode(0xD1, 0x0); /* Opcode D1 /0 */ 9013 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 9014 ins_pipe(ialu_reg); 9015%} 9016 9017instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ 9018 effect(USE_DEF dst, USE shift, KILL cr); 9019 9020 format %{ "roll $dst, $shift" %} 9021 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ 9022 ins_encode( reg_opc_imm(dst, shift) ); 9023 ins_pipe(ialu_reg); 9024%} 9025 9026instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) 9027%{ 9028 effect(USE_DEF dst, USE shift, KILL cr); 9029 9030 format %{ "roll $dst, $shift" %} 9031 opcode(0xD3, 0x0); /* Opcode D3 /0 */ 9032 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 9033 ins_pipe(ialu_reg_reg); 9034%} 9035// end of ROL expand 9036 9037// Rotate Left by one 9038instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) 9039%{ 9040 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); 9041 9042 expand %{ 9043 rolI_rReg_imm1(dst, cr); 9044 %} 9045%} 9046 9047// Rotate Left by 8-bit immediate 9048instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) 9049%{ 9050 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 9051 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); 9052 9053 expand %{ 9054 rolI_rReg_imm8(dst, lshift, cr); 9055 %} 9056%} 9057 9058// Rotate Left by variable 9059instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) 9060%{ 9061 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); 9062 9063 expand %{ 9064 rolI_rReg_CL(dst, shift, cr); 9065 %} 9066%} 9067 9068// Rotate Left by variable 9069instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) 9070%{ 9071 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); 9072 9073 expand %{ 9074 rolI_rReg_CL(dst, shift, cr); 9075 %} 9076%} 9077 9078// ROR expand 9079instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) 9080%{ 9081 effect(USE_DEF dst, KILL cr); 9082 9083 format %{ "rorl $dst" %} 9084 opcode(0xD1, 0x1); /* D1 /1 */ 9085 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 9086 ins_pipe(ialu_reg); 9087%} 9088 9089instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) 9090%{ 9091 effect(USE_DEF dst, USE shift, KILL cr); 9092 9093 format %{ "rorl $dst, $shift" %} 9094 opcode(0xC1, 0x1); /* C1 /1 ib */ 9095 ins_encode(reg_opc_imm(dst, shift)); 9096 ins_pipe(ialu_reg); 9097%} 9098 9099instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) 9100%{ 9101 effect(USE_DEF dst, USE shift, KILL cr); 9102 9103 format %{ "rorl $dst, $shift" %} 9104 opcode(0xD3, 0x1); /* D3 /1 */ 9105 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); 9106 ins_pipe(ialu_reg_reg); 9107%} 9108// end of ROR expand 9109 9110// Rotate Right by one 9111instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) 9112%{ 9113 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); 9114 9115 expand %{ 9116 rorI_rReg_imm1(dst, cr); 9117 %} 9118%} 9119 9120// Rotate Right by 8-bit immediate 9121instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) 9122%{ 9123 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 9124 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); 9125 9126 expand %{ 9127 rorI_rReg_imm8(dst, rshift, cr); 9128 %} 9129%} 9130 9131// Rotate Right by variable 9132instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) 9133%{ 9134 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); 9135 9136 expand %{ 9137 rorI_rReg_CL(dst, shift, cr); 9138 %} 9139%} 9140 9141// Rotate Right by variable 9142instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) 9143%{ 9144 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); 9145 9146 expand %{ 9147 rorI_rReg_CL(dst, shift, cr); 9148 %} 9149%} 9150 9151// for long rotate 9152// ROL expand 9153instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ 9154 effect(USE_DEF dst, KILL cr); 9155 9156 format %{ "rolq $dst" %} 9157 opcode(0xD1, 0x0); /* Opcode D1 /0 */ 9158 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 9159 ins_pipe(ialu_reg); 9160%} 9161 9162instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ 9163 effect(USE_DEF dst, USE shift, KILL cr); 9164 9165 format %{ "rolq $dst, $shift" %} 9166 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ 9167 ins_encode( reg_opc_imm_wide(dst, shift) ); 9168 ins_pipe(ialu_reg); 9169%} 9170 9171instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) 9172%{ 9173 effect(USE_DEF dst, USE shift, KILL cr); 9174 9175 format %{ "rolq $dst, $shift" %} 9176 opcode(0xD3, 0x0); /* Opcode D3 /0 */ 9177 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 9178 ins_pipe(ialu_reg_reg); 9179%} 9180// end of ROL expand 9181 9182// Rotate Left by one 9183instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) 9184%{ 9185 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); 9186 9187 expand %{ 9188 rolL_rReg_imm1(dst, cr); 9189 %} 9190%} 9191 9192// Rotate Left by 8-bit immediate 9193instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) 9194%{ 9195 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 9196 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); 9197 9198 expand %{ 9199 rolL_rReg_imm8(dst, lshift, cr); 9200 %} 9201%} 9202 9203// Rotate Left by variable 9204instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) 9205%{ 9206 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); 9207 9208 expand %{ 9209 rolL_rReg_CL(dst, shift, cr); 9210 %} 9211%} 9212 9213// Rotate Left by variable 9214instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) 9215%{ 9216 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); 9217 9218 expand %{ 9219 rolL_rReg_CL(dst, shift, cr); 9220 %} 9221%} 9222 9223// ROR expand 9224instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) 9225%{ 9226 effect(USE_DEF dst, KILL cr); 9227 9228 format %{ "rorq $dst" %} 9229 opcode(0xD1, 0x1); /* D1 /1 */ 9230 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 9231 ins_pipe(ialu_reg); 9232%} 9233 9234instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) 9235%{ 9236 effect(USE_DEF dst, USE shift, KILL cr); 9237 9238 format %{ "rorq $dst, $shift" %} 9239 opcode(0xC1, 0x1); /* C1 /1 ib */ 9240 ins_encode(reg_opc_imm_wide(dst, shift)); 9241 ins_pipe(ialu_reg); 9242%} 9243 9244instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) 9245%{ 9246 effect(USE_DEF dst, USE shift, KILL cr); 9247 9248 format %{ "rorq $dst, $shift" %} 9249 opcode(0xD3, 0x1); /* D3 /1 */ 9250 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); 9251 ins_pipe(ialu_reg_reg); 9252%} 9253// end of ROR expand 9254 9255// Rotate Right by one 9256instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) 9257%{ 9258 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); 9259 9260 expand %{ 9261 rorL_rReg_imm1(dst, cr); 9262 %} 9263%} 9264 9265// Rotate Right by 8-bit immediate 9266instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) 9267%{ 9268 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 9269 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); 9270 9271 expand %{ 9272 rorL_rReg_imm8(dst, rshift, cr); 9273 %} 9274%} 9275 9276// Rotate Right by variable 9277instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) 9278%{ 9279 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); 9280 9281 expand %{ 9282 rorL_rReg_CL(dst, shift, cr); 9283 %} 9284%} 9285 9286// Rotate Right by variable 9287instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) 9288%{ 9289 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); 9290 9291 expand %{ 9292 rorL_rReg_CL(dst, shift, cr); 9293 %} 9294%} 9295 9296// Logical Instructions 9297 9298// Integer Logical Instructions 9299 9300// And Instructions 9301// And Register with Register 9302instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 9303%{ 9304 match(Set dst (AndI dst src)); 9305 effect(KILL cr); 9306 9307 format %{ "andl $dst, $src\t# int" %} 9308 opcode(0x23); 9309 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); 9310 ins_pipe(ialu_reg_reg); 9311%} 9312 9313// And Register with Immediate 255 9314instruct andI_rReg_imm255(rRegI dst, immI_255 src) 9315%{ 9316 match(Set dst (AndI dst src)); 9317 9318 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} 9319 opcode(0x0F, 0xB6); 9320 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); 9321 ins_pipe(ialu_reg); 9322%} 9323 9324// And Register with Immediate 255 and promote to long 9325instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) 9326%{ 9327 match(Set dst (ConvI2L (AndI src mask))); 9328 9329 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} 9330 opcode(0x0F, 0xB6); 9331 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); 9332 ins_pipe(ialu_reg); 9333%} 9334 9335// And Register with Immediate 65535 9336instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) 9337%{ 9338 match(Set dst (AndI dst src)); 9339 9340 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} 9341 opcode(0x0F, 0xB7); 9342 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); 9343 ins_pipe(ialu_reg); 9344%} 9345 9346// And Register with Immediate 65535 and promote to long 9347instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) 9348%{ 9349 match(Set dst (ConvI2L (AndI src mask))); 9350 9351 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} 9352 opcode(0x0F, 0xB7); 9353 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); 9354 ins_pipe(ialu_reg); 9355%} 9356 9357// And Register with Immediate 9358instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) 9359%{ 9360 match(Set dst (AndI dst src)); 9361 effect(KILL cr); 9362 9363 format %{ "andl $dst, $src\t# int" %} 9364 opcode(0x81, 0x04); /* Opcode 81 /4 */ 9365 ins_encode(OpcSErm(dst, src), Con8or32(src)); 9366 ins_pipe(ialu_reg); 9367%} 9368 9369// And Register with Memory 9370instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) 9371%{ 9372 match(Set dst (AndI dst (LoadI src))); 9373 effect(KILL cr); 9374 9375 ins_cost(125); 9376 format %{ "andl $dst, $src\t# int" %} 9377 opcode(0x23); 9378 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); 9379 ins_pipe(ialu_reg_mem); 9380%} 9381 9382// And Memory with Register 9383instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr) 9384%{ 9385 match(Set dst (StoreB dst (AndI (LoadB dst) src))); 9386 effect(KILL cr); 9387 9388 ins_cost(150); 9389 format %{ "andb $dst, $src\t# byte" %} 9390 opcode(0x20); 9391 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst)); 9392 ins_pipe(ialu_mem_reg); 9393%} 9394 9395instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) 9396%{ 9397 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 9398 effect(KILL cr); 9399 9400 ins_cost(150); 9401 format %{ "andl $dst, $src\t# int" %} 9402 opcode(0x21); /* Opcode 21 /r */ 9403 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); 9404 ins_pipe(ialu_mem_reg); 9405%} 9406 9407// And Memory with Immediate 9408instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) 9409%{ 9410 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 9411 effect(KILL cr); 9412 9413 ins_cost(125); 9414 format %{ "andl $dst, $src\t# int" %} 9415 opcode(0x81, 0x4); /* Opcode 81 /4 id */ 9416 ins_encode(REX_mem(dst), OpcSE(src), 9417 RM_opc_mem(secondary, dst), Con8or32(src)); 9418 ins_pipe(ialu_mem_imm); 9419%} 9420 9421// BMI1 instructions 9422instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{ 9423 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2))); 9424 predicate(UseBMI1Instructions); 9425 effect(KILL cr); 9426 9427 ins_cost(125); 9428 format %{ "andnl $dst, $src1, $src2" %} 9429 9430 ins_encode %{ 9431 __ andnl($dst$$Register, $src1$$Register, $src2$$Address); 9432 %} 9433 ins_pipe(ialu_reg_mem); 9434%} 9435 9436instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{ 9437 match(Set dst (AndI (XorI src1 minus_1) src2)); 9438 predicate(UseBMI1Instructions); 9439 effect(KILL cr); 9440 9441 format %{ "andnl $dst, $src1, $src2" %} 9442 9443 ins_encode %{ 9444 __ andnl($dst$$Register, $src1$$Register, $src2$$Register); 9445 %} 9446 ins_pipe(ialu_reg); 9447%} 9448 9449instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{ 9450 match(Set dst (AndI (SubI imm_zero src) src)); 9451 predicate(UseBMI1Instructions); 9452 effect(KILL cr); 9453 9454 format %{ "blsil $dst, $src" %} 9455 9456 ins_encode %{ 9457 __ blsil($dst$$Register, $src$$Register); 9458 %} 9459 ins_pipe(ialu_reg); 9460%} 9461 9462instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{ 9463 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) )); 9464 predicate(UseBMI1Instructions); 9465 effect(KILL cr); 9466 9467 ins_cost(125); 9468 format %{ "blsil $dst, $src" %} 9469 9470 ins_encode %{ 9471 __ blsil($dst$$Register, $src$$Address); 9472 %} 9473 ins_pipe(ialu_reg_mem); 9474%} 9475 9476instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr) 9477%{ 9478 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) ); 9479 predicate(UseBMI1Instructions); 9480 effect(KILL cr); 9481 9482 ins_cost(125); 9483 format %{ "blsmskl $dst, $src" %} 9484 9485 ins_encode %{ 9486 __ blsmskl($dst$$Register, $src$$Address); 9487 %} 9488 ins_pipe(ialu_reg_mem); 9489%} 9490 9491instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr) 9492%{ 9493 match(Set dst (XorI (AddI src minus_1) src)); 9494 predicate(UseBMI1Instructions); 9495 effect(KILL cr); 9496 9497 format %{ "blsmskl $dst, $src" %} 9498 9499 ins_encode %{ 9500 __ blsmskl($dst$$Register, $src$$Register); 9501 %} 9502 9503 ins_pipe(ialu_reg); 9504%} 9505 9506instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr) 9507%{ 9508 match(Set dst (AndI (AddI src minus_1) src) ); 9509 predicate(UseBMI1Instructions); 9510 effect(KILL cr); 9511 9512 format %{ "blsrl $dst, $src" %} 9513 9514 ins_encode %{ 9515 __ blsrl($dst$$Register, $src$$Register); 9516 %} 9517 9518 ins_pipe(ialu_reg_mem); 9519%} 9520 9521instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr) 9522%{ 9523 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) ); 9524 predicate(UseBMI1Instructions); 9525 effect(KILL cr); 9526 9527 ins_cost(125); 9528 format %{ "blsrl $dst, $src" %} 9529 9530 ins_encode %{ 9531 __ blsrl($dst$$Register, $src$$Address); 9532 %} 9533 9534 ins_pipe(ialu_reg); 9535%} 9536 9537// Or Instructions 9538// Or Register with Register 9539instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 9540%{ 9541 match(Set dst (OrI dst src)); 9542 effect(KILL cr); 9543 9544 format %{ "orl $dst, $src\t# int" %} 9545 opcode(0x0B); 9546 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); 9547 ins_pipe(ialu_reg_reg); 9548%} 9549 9550// Or Register with Immediate 9551instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) 9552%{ 9553 match(Set dst (OrI dst src)); 9554 effect(KILL cr); 9555 9556 format %{ "orl $dst, $src\t# int" %} 9557 opcode(0x81, 0x01); /* Opcode 81 /1 id */ 9558 ins_encode(OpcSErm(dst, src), Con8or32(src)); 9559 ins_pipe(ialu_reg); 9560%} 9561 9562// Or Register with Memory 9563instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) 9564%{ 9565 match(Set dst (OrI dst (LoadI src))); 9566 effect(KILL cr); 9567 9568 ins_cost(125); 9569 format %{ "orl $dst, $src\t# int" %} 9570 opcode(0x0B); 9571 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); 9572 ins_pipe(ialu_reg_mem); 9573%} 9574 9575// Or Memory with Register 9576instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr) 9577%{ 9578 match(Set dst (StoreB dst (OrI (LoadB dst) src))); 9579 effect(KILL cr); 9580 9581 ins_cost(150); 9582 format %{ "orb $dst, $src\t# byte" %} 9583 opcode(0x08); 9584 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst)); 9585 ins_pipe(ialu_mem_reg); 9586%} 9587 9588instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) 9589%{ 9590 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 9591 effect(KILL cr); 9592 9593 ins_cost(150); 9594 format %{ "orl $dst, $src\t# int" %} 9595 opcode(0x09); /* Opcode 09 /r */ 9596 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); 9597 ins_pipe(ialu_mem_reg); 9598%} 9599 9600// Or Memory with Immediate 9601instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) 9602%{ 9603 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 9604 effect(KILL cr); 9605 9606 ins_cost(125); 9607 format %{ "orl $dst, $src\t# int" %} 9608 opcode(0x81, 0x1); /* Opcode 81 /1 id */ 9609 ins_encode(REX_mem(dst), OpcSE(src), 9610 RM_opc_mem(secondary, dst), Con8or32(src)); 9611 ins_pipe(ialu_mem_imm); 9612%} 9613 9614// Xor Instructions 9615// Xor Register with Register 9616instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 9617%{ 9618 match(Set dst (XorI dst src)); 9619 effect(KILL cr); 9620 9621 format %{ "xorl $dst, $src\t# int" %} 9622 opcode(0x33); 9623 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); 9624 ins_pipe(ialu_reg_reg); 9625%} 9626 9627// Xor Register with Immediate -1 9628instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ 9629 match(Set dst (XorI dst imm)); 9630 9631 format %{ "not $dst" %} 9632 ins_encode %{ 9633 __ notl($dst$$Register); 9634 %} 9635 ins_pipe(ialu_reg); 9636%} 9637 9638// Xor Register with Immediate 9639instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) 9640%{ 9641 match(Set dst (XorI dst src)); 9642 effect(KILL cr); 9643 9644 format %{ "xorl $dst, $src\t# int" %} 9645 opcode(0x81, 0x06); /* Opcode 81 /6 id */ 9646 ins_encode(OpcSErm(dst, src), Con8or32(src)); 9647 ins_pipe(ialu_reg); 9648%} 9649 9650// Xor Register with Memory 9651instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) 9652%{ 9653 match(Set dst (XorI dst (LoadI src))); 9654 effect(KILL cr); 9655 9656 ins_cost(125); 9657 format %{ "xorl $dst, $src\t# int" %} 9658 opcode(0x33); 9659 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); 9660 ins_pipe(ialu_reg_mem); 9661%} 9662 9663// Xor Memory with Register 9664instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr) 9665%{ 9666 match(Set dst (StoreB dst (XorI (LoadB dst) src))); 9667 effect(KILL cr); 9668 9669 ins_cost(150); 9670 format %{ "xorb $dst, $src\t# byte" %} 9671 opcode(0x30); 9672 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst)); 9673 ins_pipe(ialu_mem_reg); 9674%} 9675 9676instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) 9677%{ 9678 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 9679 effect(KILL cr); 9680 9681 ins_cost(150); 9682 format %{ "xorl $dst, $src\t# int" %} 9683 opcode(0x31); /* Opcode 31 /r */ 9684 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); 9685 ins_pipe(ialu_mem_reg); 9686%} 9687 9688// Xor Memory with Immediate 9689instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) 9690%{ 9691 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 9692 effect(KILL cr); 9693 9694 ins_cost(125); 9695 format %{ "xorl $dst, $src\t# int" %} 9696 opcode(0x81, 0x6); /* Opcode 81 /6 id */ 9697 ins_encode(REX_mem(dst), OpcSE(src), 9698 RM_opc_mem(secondary, dst), Con8or32(src)); 9699 ins_pipe(ialu_mem_imm); 9700%} 9701 9702 9703// Long Logical Instructions 9704 9705// And Instructions 9706// And Register with Register 9707instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) 9708%{ 9709 match(Set dst (AndL dst src)); 9710 effect(KILL cr); 9711 9712 format %{ "andq $dst, $src\t# long" %} 9713 opcode(0x23); 9714 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); 9715 ins_pipe(ialu_reg_reg); 9716%} 9717 9718// And Register with Immediate 255 9719instruct andL_rReg_imm255(rRegL dst, immL_255 src) 9720%{ 9721 match(Set dst (AndL dst src)); 9722 9723 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} 9724 opcode(0x0F, 0xB6); 9725 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); 9726 ins_pipe(ialu_reg); 9727%} 9728 9729// And Register with Immediate 65535 9730instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) 9731%{ 9732 match(Set dst (AndL dst src)); 9733 9734 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} 9735 opcode(0x0F, 0xB7); 9736 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); 9737 ins_pipe(ialu_reg); 9738%} 9739 9740// And Register with Immediate 9741instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) 9742%{ 9743 match(Set dst (AndL dst src)); 9744 effect(KILL cr); 9745 9746 format %{ "andq $dst, $src\t# long" %} 9747 opcode(0x81, 0x04); /* Opcode 81 /4 */ 9748 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); 9749 ins_pipe(ialu_reg); 9750%} 9751 9752// And Register with Memory 9753instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) 9754%{ 9755 match(Set dst (AndL dst (LoadL src))); 9756 effect(KILL cr); 9757 9758 ins_cost(125); 9759 format %{ "andq $dst, $src\t# long" %} 9760 opcode(0x23); 9761 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); 9762 ins_pipe(ialu_reg_mem); 9763%} 9764 9765// And Memory with Register 9766instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) 9767%{ 9768 match(Set dst (StoreL dst (AndL (LoadL dst) src))); 9769 effect(KILL cr); 9770 9771 ins_cost(150); 9772 format %{ "andq $dst, $src\t# long" %} 9773 opcode(0x21); /* Opcode 21 /r */ 9774 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); 9775 ins_pipe(ialu_mem_reg); 9776%} 9777 9778// And Memory with Immediate 9779instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) 9780%{ 9781 match(Set dst (StoreL dst (AndL (LoadL dst) src))); 9782 effect(KILL cr); 9783 9784 ins_cost(125); 9785 format %{ "andq $dst, $src\t# long" %} 9786 opcode(0x81, 0x4); /* Opcode 81 /4 id */ 9787 ins_encode(REX_mem_wide(dst), OpcSE(src), 9788 RM_opc_mem(secondary, dst), Con8or32(src)); 9789 ins_pipe(ialu_mem_imm); 9790%} 9791 9792// BMI1 instructions 9793instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{ 9794 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2))); 9795 predicate(UseBMI1Instructions); 9796 effect(KILL cr); 9797 9798 ins_cost(125); 9799 format %{ "andnq $dst, $src1, $src2" %} 9800 9801 ins_encode %{ 9802 __ andnq($dst$$Register, $src1$$Register, $src2$$Address); 9803 %} 9804 ins_pipe(ialu_reg_mem); 9805%} 9806 9807instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{ 9808 match(Set dst (AndL (XorL src1 minus_1) src2)); 9809 predicate(UseBMI1Instructions); 9810 effect(KILL cr); 9811 9812 format %{ "andnq $dst, $src1, $src2" %} 9813 9814 ins_encode %{ 9815 __ andnq($dst$$Register, $src1$$Register, $src2$$Register); 9816 %} 9817 ins_pipe(ialu_reg_mem); 9818%} 9819 9820instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{ 9821 match(Set dst (AndL (SubL imm_zero src) src)); 9822 predicate(UseBMI1Instructions); 9823 effect(KILL cr); 9824 9825 format %{ "blsiq $dst, $src" %} 9826 9827 ins_encode %{ 9828 __ blsiq($dst$$Register, $src$$Register); 9829 %} 9830 ins_pipe(ialu_reg); 9831%} 9832 9833instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{ 9834 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) )); 9835 predicate(UseBMI1Instructions); 9836 effect(KILL cr); 9837 9838 ins_cost(125); 9839 format %{ "blsiq $dst, $src" %} 9840 9841 ins_encode %{ 9842 __ blsiq($dst$$Register, $src$$Address); 9843 %} 9844 ins_pipe(ialu_reg_mem); 9845%} 9846 9847instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr) 9848%{ 9849 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) ); 9850 predicate(UseBMI1Instructions); 9851 effect(KILL cr); 9852 9853 ins_cost(125); 9854 format %{ "blsmskq $dst, $src" %} 9855 9856 ins_encode %{ 9857 __ blsmskq($dst$$Register, $src$$Address); 9858 %} 9859 ins_pipe(ialu_reg_mem); 9860%} 9861 9862instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr) 9863%{ 9864 match(Set dst (XorL (AddL src minus_1) src)); 9865 predicate(UseBMI1Instructions); 9866 effect(KILL cr); 9867 9868 format %{ "blsmskq $dst, $src" %} 9869 9870 ins_encode %{ 9871 __ blsmskq($dst$$Register, $src$$Register); 9872 %} 9873 9874 ins_pipe(ialu_reg); 9875%} 9876 9877instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr) 9878%{ 9879 match(Set dst (AndL (AddL src minus_1) src) ); 9880 predicate(UseBMI1Instructions); 9881 effect(KILL cr); 9882 9883 format %{ "blsrq $dst, $src" %} 9884 9885 ins_encode %{ 9886 __ blsrq($dst$$Register, $src$$Register); 9887 %} 9888 9889 ins_pipe(ialu_reg); 9890%} 9891 9892instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr) 9893%{ 9894 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) ); 9895 predicate(UseBMI1Instructions); 9896 effect(KILL cr); 9897 9898 ins_cost(125); 9899 format %{ "blsrq $dst, $src" %} 9900 9901 ins_encode %{ 9902 __ blsrq($dst$$Register, $src$$Address); 9903 %} 9904 9905 ins_pipe(ialu_reg); 9906%} 9907 9908// Or Instructions 9909// Or Register with Register 9910instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) 9911%{ 9912 match(Set dst (OrL dst src)); 9913 effect(KILL cr); 9914 9915 format %{ "orq $dst, $src\t# long" %} 9916 opcode(0x0B); 9917 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); 9918 ins_pipe(ialu_reg_reg); 9919%} 9920 9921// Use any_RegP to match R15 (TLS register) without spilling. 9922instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ 9923 match(Set dst (OrL dst (CastP2X src))); 9924 effect(KILL cr); 9925 9926 format %{ "orq $dst, $src\t# long" %} 9927 opcode(0x0B); 9928 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); 9929 ins_pipe(ialu_reg_reg); 9930%} 9931 9932 9933// Or Register with Immediate 9934instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) 9935%{ 9936 match(Set dst (OrL dst src)); 9937 effect(KILL cr); 9938 9939 format %{ "orq $dst, $src\t# long" %} 9940 opcode(0x81, 0x01); /* Opcode 81 /1 id */ 9941 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); 9942 ins_pipe(ialu_reg); 9943%} 9944 9945// Or Register with Memory 9946instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) 9947%{ 9948 match(Set dst (OrL dst (LoadL src))); 9949 effect(KILL cr); 9950 9951 ins_cost(125); 9952 format %{ "orq $dst, $src\t# long" %} 9953 opcode(0x0B); 9954 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); 9955 ins_pipe(ialu_reg_mem); 9956%} 9957 9958// Or Memory with Register 9959instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) 9960%{ 9961 match(Set dst (StoreL dst (OrL (LoadL dst) src))); 9962 effect(KILL cr); 9963 9964 ins_cost(150); 9965 format %{ "orq $dst, $src\t# long" %} 9966 opcode(0x09); /* Opcode 09 /r */ 9967 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); 9968 ins_pipe(ialu_mem_reg); 9969%} 9970 9971// Or Memory with Immediate 9972instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) 9973%{ 9974 match(Set dst (StoreL dst (OrL (LoadL dst) src))); 9975 effect(KILL cr); 9976 9977 ins_cost(125); 9978 format %{ "orq $dst, $src\t# long" %} 9979 opcode(0x81, 0x1); /* Opcode 81 /1 id */ 9980 ins_encode(REX_mem_wide(dst), OpcSE(src), 9981 RM_opc_mem(secondary, dst), Con8or32(src)); 9982 ins_pipe(ialu_mem_imm); 9983%} 9984 9985// Xor Instructions 9986// Xor Register with Register 9987instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) 9988%{ 9989 match(Set dst (XorL dst src)); 9990 effect(KILL cr); 9991 9992 format %{ "xorq $dst, $src\t# long" %} 9993 opcode(0x33); 9994 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); 9995 ins_pipe(ialu_reg_reg); 9996%} 9997 9998// Xor Register with Immediate -1 9999instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ 10000 match(Set dst (XorL dst imm)); 10001 10002 format %{ "notq $dst" %} 10003 ins_encode %{ 10004 __ notq($dst$$Register); 10005 %} 10006 ins_pipe(ialu_reg); 10007%} 10008 10009// Xor Register with Immediate 10010instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) 10011%{ 10012 match(Set dst (XorL dst src)); 10013 effect(KILL cr); 10014 10015 format %{ "xorq $dst, $src\t# long" %} 10016 opcode(0x81, 0x06); /* Opcode 81 /6 id */ 10017 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); 10018 ins_pipe(ialu_reg); 10019%} 10020 10021// Xor Register with Memory 10022instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) 10023%{ 10024 match(Set dst (XorL dst (LoadL src))); 10025 effect(KILL cr); 10026 10027 ins_cost(125); 10028 format %{ "xorq $dst, $src\t# long" %} 10029 opcode(0x33); 10030 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); 10031 ins_pipe(ialu_reg_mem); 10032%} 10033 10034// Xor Memory with Register 10035instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) 10036%{ 10037 match(Set dst (StoreL dst (XorL (LoadL dst) src))); 10038 effect(KILL cr); 10039 10040 ins_cost(150); 10041 format %{ "xorq $dst, $src\t# long" %} 10042 opcode(0x31); /* Opcode 31 /r */ 10043 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); 10044 ins_pipe(ialu_mem_reg); 10045%} 10046 10047// Xor Memory with Immediate 10048instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) 10049%{ 10050 match(Set dst (StoreL dst (XorL (LoadL dst) src))); 10051 effect(KILL cr); 10052 10053 ins_cost(125); 10054 format %{ "xorq $dst, $src\t# long" %} 10055 opcode(0x81, 0x6); /* Opcode 81 /6 id */ 10056 ins_encode(REX_mem_wide(dst), OpcSE(src), 10057 RM_opc_mem(secondary, dst), Con8or32(src)); 10058 ins_pipe(ialu_mem_imm); 10059%} 10060 10061// Convert Int to Boolean 10062instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) 10063%{ 10064 match(Set dst (Conv2B src)); 10065 effect(KILL cr); 10066 10067 format %{ "testl $src, $src\t# ci2b\n\t" 10068 "setnz $dst\n\t" 10069 "movzbl $dst, $dst" %} 10070 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl 10071 setNZ_reg(dst), 10072 REX_reg_breg(dst, dst), // movzbl 10073 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); 10074 ins_pipe(pipe_slow); // XXX 10075%} 10076 10077// Convert Pointer to Boolean 10078instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) 10079%{ 10080 match(Set dst (Conv2B src)); 10081 effect(KILL cr); 10082 10083 format %{ "testq $src, $src\t# cp2b\n\t" 10084 "setnz $dst\n\t" 10085 "movzbl $dst, $dst" %} 10086 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq 10087 setNZ_reg(dst), 10088 REX_reg_breg(dst, dst), // movzbl 10089 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); 10090 ins_pipe(pipe_slow); // XXX 10091%} 10092 10093instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) 10094%{ 10095 match(Set dst (CmpLTMask p q)); 10096 effect(KILL cr); 10097 10098 ins_cost(400); 10099 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" 10100 "setlt $dst\n\t" 10101 "movzbl $dst, $dst\n\t" 10102 "negl $dst" %} 10103 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl 10104 setLT_reg(dst), 10105 REX_reg_breg(dst, dst), // movzbl 10106 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), 10107 neg_reg(dst)); 10108 ins_pipe(pipe_slow); 10109%} 10110 10111instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) 10112%{ 10113 match(Set dst (CmpLTMask dst zero)); 10114 effect(KILL cr); 10115 10116 ins_cost(100); 10117 format %{ "sarl $dst, #31\t# cmpLTMask0" %} 10118 ins_encode %{ 10119 __ sarl($dst$$Register, 31); 10120 %} 10121 ins_pipe(ialu_reg); 10122%} 10123 10124/* Better to save a register than avoid a branch */ 10125instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) 10126%{ 10127 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 10128 effect(KILL cr); 10129 ins_cost(300); 10130 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t" 10131 "jge done\n\t" 10132 "addl $p,$y\n" 10133 "done: " %} 10134 ins_encode %{ 10135 Register Rp = $p$$Register; 10136 Register Rq = $q$$Register; 10137 Register Ry = $y$$Register; 10138 Label done; 10139 __ subl(Rp, Rq); 10140 __ jccb(Assembler::greaterEqual, done); 10141 __ addl(Rp, Ry); 10142 __ bind(done); 10143 %} 10144 ins_pipe(pipe_cmplt); 10145%} 10146 10147/* Better to save a register than avoid a branch */ 10148instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) 10149%{ 10150 match(Set y (AndI (CmpLTMask p q) y)); 10151 effect(KILL cr); 10152 10153 ins_cost(300); 10154 10155 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t" 10156 "jlt done\n\t" 10157 "xorl $y, $y\n" 10158 "done: " %} 10159 ins_encode %{ 10160 Register Rp = $p$$Register; 10161 Register Rq = $q$$Register; 10162 Register Ry = $y$$Register; 10163 Label done; 10164 __ cmpl(Rp, Rq); 10165 __ jccb(Assembler::less, done); 10166 __ xorl(Ry, Ry); 10167 __ bind(done); 10168 %} 10169 ins_pipe(pipe_cmplt); 10170%} 10171 10172 10173//---------- FP Instructions------------------------------------------------ 10174 10175instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) 10176%{ 10177 match(Set cr (CmpF src1 src2)); 10178 10179 ins_cost(145); 10180 format %{ "ucomiss $src1, $src2\n\t" 10181 "jnp,s exit\n\t" 10182 "pushfq\t# saw NaN, set CF\n\t" 10183 "andq [rsp], #0xffffff2b\n\t" 10184 "popfq\n" 10185 "exit:" %} 10186 ins_encode %{ 10187 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); 10188 emit_cmpfp_fixup(_masm); 10189 %} 10190 ins_pipe(pipe_slow); 10191%} 10192 10193instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ 10194 match(Set cr (CmpF src1 src2)); 10195 10196 ins_cost(100); 10197 format %{ "ucomiss $src1, $src2" %} 10198 ins_encode %{ 10199 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); 10200 %} 10201 ins_pipe(pipe_slow); 10202%} 10203 10204instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) 10205%{ 10206 match(Set cr (CmpF src1 (LoadF src2))); 10207 10208 ins_cost(145); 10209 format %{ "ucomiss $src1, $src2\n\t" 10210 "jnp,s exit\n\t" 10211 "pushfq\t# saw NaN, set CF\n\t" 10212 "andq [rsp], #0xffffff2b\n\t" 10213 "popfq\n" 10214 "exit:" %} 10215 ins_encode %{ 10216 __ ucomiss($src1$$XMMRegister, $src2$$Address); 10217 emit_cmpfp_fixup(_masm); 10218 %} 10219 ins_pipe(pipe_slow); 10220%} 10221 10222instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ 10223 match(Set cr (CmpF src1 (LoadF src2))); 10224 10225 ins_cost(100); 10226 format %{ "ucomiss $src1, $src2" %} 10227 ins_encode %{ 10228 __ ucomiss($src1$$XMMRegister, $src2$$Address); 10229 %} 10230 ins_pipe(pipe_slow); 10231%} 10232 10233instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ 10234 match(Set cr (CmpF src con)); 10235 10236 ins_cost(145); 10237 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" 10238 "jnp,s exit\n\t" 10239 "pushfq\t# saw NaN, set CF\n\t" 10240 "andq [rsp], #0xffffff2b\n\t" 10241 "popfq\n" 10242 "exit:" %} 10243 ins_encode %{ 10244 __ ucomiss($src$$XMMRegister, $constantaddress($con)); 10245 emit_cmpfp_fixup(_masm); 10246 %} 10247 ins_pipe(pipe_slow); 10248%} 10249 10250instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ 10251 match(Set cr (CmpF src con)); 10252 ins_cost(100); 10253 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} 10254 ins_encode %{ 10255 __ ucomiss($src$$XMMRegister, $constantaddress($con)); 10256 %} 10257 ins_pipe(pipe_slow); 10258%} 10259 10260instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) 10261%{ 10262 match(Set cr (CmpD src1 src2)); 10263 10264 ins_cost(145); 10265 format %{ "ucomisd $src1, $src2\n\t" 10266 "jnp,s exit\n\t" 10267 "pushfq\t# saw NaN, set CF\n\t" 10268 "andq [rsp], #0xffffff2b\n\t" 10269 "popfq\n" 10270 "exit:" %} 10271 ins_encode %{ 10272 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); 10273 emit_cmpfp_fixup(_masm); 10274 %} 10275 ins_pipe(pipe_slow); 10276%} 10277 10278instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ 10279 match(Set cr (CmpD src1 src2)); 10280 10281 ins_cost(100); 10282 format %{ "ucomisd $src1, $src2 test" %} 10283 ins_encode %{ 10284 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); 10285 %} 10286 ins_pipe(pipe_slow); 10287%} 10288 10289instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) 10290%{ 10291 match(Set cr (CmpD src1 (LoadD src2))); 10292 10293 ins_cost(145); 10294 format %{ "ucomisd $src1, $src2\n\t" 10295 "jnp,s exit\n\t" 10296 "pushfq\t# saw NaN, set CF\n\t" 10297 "andq [rsp], #0xffffff2b\n\t" 10298 "popfq\n" 10299 "exit:" %} 10300 ins_encode %{ 10301 __ ucomisd($src1$$XMMRegister, $src2$$Address); 10302 emit_cmpfp_fixup(_masm); 10303 %} 10304 ins_pipe(pipe_slow); 10305%} 10306 10307instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ 10308 match(Set cr (CmpD src1 (LoadD src2))); 10309 10310 ins_cost(100); 10311 format %{ "ucomisd $src1, $src2" %} 10312 ins_encode %{ 10313 __ ucomisd($src1$$XMMRegister, $src2$$Address); 10314 %} 10315 ins_pipe(pipe_slow); 10316%} 10317 10318instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ 10319 match(Set cr (CmpD src con)); 10320 10321 ins_cost(145); 10322 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" 10323 "jnp,s exit\n\t" 10324 "pushfq\t# saw NaN, set CF\n\t" 10325 "andq [rsp], #0xffffff2b\n\t" 10326 "popfq\n" 10327 "exit:" %} 10328 ins_encode %{ 10329 __ ucomisd($src$$XMMRegister, $constantaddress($con)); 10330 emit_cmpfp_fixup(_masm); 10331 %} 10332 ins_pipe(pipe_slow); 10333%} 10334 10335instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ 10336 match(Set cr (CmpD src con)); 10337 ins_cost(100); 10338 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} 10339 ins_encode %{ 10340 __ ucomisd($src$$XMMRegister, $constantaddress($con)); 10341 %} 10342 ins_pipe(pipe_slow); 10343%} 10344 10345// Compare into -1,0,1 10346instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) 10347%{ 10348 match(Set dst (CmpF3 src1 src2)); 10349 effect(KILL cr); 10350 10351 ins_cost(275); 10352 format %{ "ucomiss $src1, $src2\n\t" 10353 "movl $dst, #-1\n\t" 10354 "jp,s done\n\t" 10355 "jb,s done\n\t" 10356 "setne $dst\n\t" 10357 "movzbl $dst, $dst\n" 10358 "done:" %} 10359 ins_encode %{ 10360 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); 10361 emit_cmpfp3(_masm, $dst$$Register); 10362 %} 10363 ins_pipe(pipe_slow); 10364%} 10365 10366// Compare into -1,0,1 10367instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) 10368%{ 10369 match(Set dst (CmpF3 src1 (LoadF src2))); 10370 effect(KILL cr); 10371 10372 ins_cost(275); 10373 format %{ "ucomiss $src1, $src2\n\t" 10374 "movl $dst, #-1\n\t" 10375 "jp,s done\n\t" 10376 "jb,s done\n\t" 10377 "setne $dst\n\t" 10378 "movzbl $dst, $dst\n" 10379 "done:" %} 10380 ins_encode %{ 10381 __ ucomiss($src1$$XMMRegister, $src2$$Address); 10382 emit_cmpfp3(_masm, $dst$$Register); 10383 %} 10384 ins_pipe(pipe_slow); 10385%} 10386 10387// Compare into -1,0,1 10388instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ 10389 match(Set dst (CmpF3 src con)); 10390 effect(KILL cr); 10391 10392 ins_cost(275); 10393 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" 10394 "movl $dst, #-1\n\t" 10395 "jp,s done\n\t" 10396 "jb,s done\n\t" 10397 "setne $dst\n\t" 10398 "movzbl $dst, $dst\n" 10399 "done:" %} 10400 ins_encode %{ 10401 __ ucomiss($src$$XMMRegister, $constantaddress($con)); 10402 emit_cmpfp3(_masm, $dst$$Register); 10403 %} 10404 ins_pipe(pipe_slow); 10405%} 10406 10407// Compare into -1,0,1 10408instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) 10409%{ 10410 match(Set dst (CmpD3 src1 src2)); 10411 effect(KILL cr); 10412 10413 ins_cost(275); 10414 format %{ "ucomisd $src1, $src2\n\t" 10415 "movl $dst, #-1\n\t" 10416 "jp,s done\n\t" 10417 "jb,s done\n\t" 10418 "setne $dst\n\t" 10419 "movzbl $dst, $dst\n" 10420 "done:" %} 10421 ins_encode %{ 10422 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); 10423 emit_cmpfp3(_masm, $dst$$Register); 10424 %} 10425 ins_pipe(pipe_slow); 10426%} 10427 10428// Compare into -1,0,1 10429instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) 10430%{ 10431 match(Set dst (CmpD3 src1 (LoadD src2))); 10432 effect(KILL cr); 10433 10434 ins_cost(275); 10435 format %{ "ucomisd $src1, $src2\n\t" 10436 "movl $dst, #-1\n\t" 10437 "jp,s done\n\t" 10438 "jb,s done\n\t" 10439 "setne $dst\n\t" 10440 "movzbl $dst, $dst\n" 10441 "done:" %} 10442 ins_encode %{ 10443 __ ucomisd($src1$$XMMRegister, $src2$$Address); 10444 emit_cmpfp3(_masm, $dst$$Register); 10445 %} 10446 ins_pipe(pipe_slow); 10447%} 10448 10449// Compare into -1,0,1 10450instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ 10451 match(Set dst (CmpD3 src con)); 10452 effect(KILL cr); 10453 10454 ins_cost(275); 10455 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" 10456 "movl $dst, #-1\n\t" 10457 "jp,s done\n\t" 10458 "jb,s done\n\t" 10459 "setne $dst\n\t" 10460 "movzbl $dst, $dst\n" 10461 "done:" %} 10462 ins_encode %{ 10463 __ ucomisd($src$$XMMRegister, $constantaddress($con)); 10464 emit_cmpfp3(_masm, $dst$$Register); 10465 %} 10466 ins_pipe(pipe_slow); 10467%} 10468 10469//----------Arithmetic Conversion Instructions--------------------------------- 10470 10471instruct roundFloat_nop(regF dst) 10472%{ 10473 match(Set dst (RoundFloat dst)); 10474 10475 ins_cost(0); 10476 ins_encode(); 10477 ins_pipe(empty); 10478%} 10479 10480instruct roundDouble_nop(regD dst) 10481%{ 10482 match(Set dst (RoundDouble dst)); 10483 10484 ins_cost(0); 10485 ins_encode(); 10486 ins_pipe(empty); 10487%} 10488 10489instruct convF2D_reg_reg(regD dst, regF src) 10490%{ 10491 match(Set dst (ConvF2D src)); 10492 10493 format %{ "cvtss2sd $dst, $src" %} 10494 ins_encode %{ 10495 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); 10496 %} 10497 ins_pipe(pipe_slow); // XXX 10498%} 10499 10500instruct convF2D_reg_mem(regD dst, memory src) 10501%{ 10502 match(Set dst (ConvF2D (LoadF src))); 10503 10504 format %{ "cvtss2sd $dst, $src" %} 10505 ins_encode %{ 10506 __ cvtss2sd ($dst$$XMMRegister, $src$$Address); 10507 %} 10508 ins_pipe(pipe_slow); // XXX 10509%} 10510 10511instruct convD2F_reg_reg(regF dst, regD src) 10512%{ 10513 match(Set dst (ConvD2F src)); 10514 10515 format %{ "cvtsd2ss $dst, $src" %} 10516 ins_encode %{ 10517 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); 10518 %} 10519 ins_pipe(pipe_slow); // XXX 10520%} 10521 10522instruct convD2F_reg_mem(regF dst, memory src) 10523%{ 10524 match(Set dst (ConvD2F (LoadD src))); 10525 10526 format %{ "cvtsd2ss $dst, $src" %} 10527 ins_encode %{ 10528 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address); 10529 %} 10530 ins_pipe(pipe_slow); // XXX 10531%} 10532 10533// XXX do mem variants 10534instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) 10535%{ 10536 match(Set dst (ConvF2I src)); 10537 effect(KILL cr); 10538 10539 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" 10540 "cmpl $dst, #0x80000000\n\t" 10541 "jne,s done\n\t" 10542 "subq rsp, #8\n\t" 10543 "movss [rsp], $src\n\t" 10544 "call f2i_fixup\n\t" 10545 "popq $dst\n" 10546 "done: "%} 10547 ins_encode %{ 10548 Label done; 10549 __ cvttss2sil($dst$$Register, $src$$XMMRegister); 10550 __ cmpl($dst$$Register, 0x80000000); 10551 __ jccb(Assembler::notEqual, done); 10552 __ subptr(rsp, 8); 10553 __ movflt(Address(rsp, 0), $src$$XMMRegister); 10554 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); 10555 __ pop($dst$$Register); 10556 __ bind(done); 10557 %} 10558 ins_pipe(pipe_slow); 10559%} 10560 10561instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) 10562%{ 10563 match(Set dst (ConvF2L src)); 10564 effect(KILL cr); 10565 10566 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" 10567 "cmpq $dst, [0x8000000000000000]\n\t" 10568 "jne,s done\n\t" 10569 "subq rsp, #8\n\t" 10570 "movss [rsp], $src\n\t" 10571 "call f2l_fixup\n\t" 10572 "popq $dst\n" 10573 "done: "%} 10574 ins_encode %{ 10575 Label done; 10576 __ cvttss2siq($dst$$Register, $src$$XMMRegister); 10577 __ cmp64($dst$$Register, 10578 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); 10579 __ jccb(Assembler::notEqual, done); 10580 __ subptr(rsp, 8); 10581 __ movflt(Address(rsp, 0), $src$$XMMRegister); 10582 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); 10583 __ pop($dst$$Register); 10584 __ bind(done); 10585 %} 10586 ins_pipe(pipe_slow); 10587%} 10588 10589instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) 10590%{ 10591 match(Set dst (ConvD2I src)); 10592 effect(KILL cr); 10593 10594 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" 10595 "cmpl $dst, #0x80000000\n\t" 10596 "jne,s done\n\t" 10597 "subq rsp, #8\n\t" 10598 "movsd [rsp], $src\n\t" 10599 "call d2i_fixup\n\t" 10600 "popq $dst\n" 10601 "done: "%} 10602 ins_encode %{ 10603 Label done; 10604 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); 10605 __ cmpl($dst$$Register, 0x80000000); 10606 __ jccb(Assembler::notEqual, done); 10607 __ subptr(rsp, 8); 10608 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 10609 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); 10610 __ pop($dst$$Register); 10611 __ bind(done); 10612 %} 10613 ins_pipe(pipe_slow); 10614%} 10615 10616instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) 10617%{ 10618 match(Set dst (ConvD2L src)); 10619 effect(KILL cr); 10620 10621 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" 10622 "cmpq $dst, [0x8000000000000000]\n\t" 10623 "jne,s done\n\t" 10624 "subq rsp, #8\n\t" 10625 "movsd [rsp], $src\n\t" 10626 "call d2l_fixup\n\t" 10627 "popq $dst\n" 10628 "done: "%} 10629 ins_encode %{ 10630 Label done; 10631 __ cvttsd2siq($dst$$Register, $src$$XMMRegister); 10632 __ cmp64($dst$$Register, 10633 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); 10634 __ jccb(Assembler::notEqual, done); 10635 __ subptr(rsp, 8); 10636 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 10637 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); 10638 __ pop($dst$$Register); 10639 __ bind(done); 10640 %} 10641 ins_pipe(pipe_slow); 10642%} 10643 10644instruct convI2F_reg_reg(regF dst, rRegI src) 10645%{ 10646 predicate(!UseXmmI2F); 10647 match(Set dst (ConvI2F src)); 10648 10649 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} 10650 ins_encode %{ 10651 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); 10652 %} 10653 ins_pipe(pipe_slow); // XXX 10654%} 10655 10656instruct convI2F_reg_mem(regF dst, memory src) 10657%{ 10658 match(Set dst (ConvI2F (LoadI src))); 10659 10660 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} 10661 ins_encode %{ 10662 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); 10663 %} 10664 ins_pipe(pipe_slow); // XXX 10665%} 10666 10667instruct convI2D_reg_reg(regD dst, rRegI src) 10668%{ 10669 predicate(!UseXmmI2D); 10670 match(Set dst (ConvI2D src)); 10671 10672 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} 10673 ins_encode %{ 10674 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); 10675 %} 10676 ins_pipe(pipe_slow); // XXX 10677%} 10678 10679instruct convI2D_reg_mem(regD dst, memory src) 10680%{ 10681 match(Set dst (ConvI2D (LoadI src))); 10682 10683 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} 10684 ins_encode %{ 10685 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); 10686 %} 10687 ins_pipe(pipe_slow); // XXX 10688%} 10689 10690instruct convXI2F_reg(regF dst, rRegI src) 10691%{ 10692 predicate(UseXmmI2F); 10693 match(Set dst (ConvI2F src)); 10694 10695 format %{ "movdl $dst, $src\n\t" 10696 "cvtdq2psl $dst, $dst\t# i2f" %} 10697 ins_encode %{ 10698 __ movdl($dst$$XMMRegister, $src$$Register); 10699 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); 10700 %} 10701 ins_pipe(pipe_slow); // XXX 10702%} 10703 10704instruct convXI2D_reg(regD dst, rRegI src) 10705%{ 10706 predicate(UseXmmI2D); 10707 match(Set dst (ConvI2D src)); 10708 10709 format %{ "movdl $dst, $src\n\t" 10710 "cvtdq2pdl $dst, $dst\t# i2d" %} 10711 ins_encode %{ 10712 __ movdl($dst$$XMMRegister, $src$$Register); 10713 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); 10714 %} 10715 ins_pipe(pipe_slow); // XXX 10716%} 10717 10718instruct convL2F_reg_reg(regF dst, rRegL src) 10719%{ 10720 match(Set dst (ConvL2F src)); 10721 10722 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} 10723 ins_encode %{ 10724 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); 10725 %} 10726 ins_pipe(pipe_slow); // XXX 10727%} 10728 10729instruct convL2F_reg_mem(regF dst, memory src) 10730%{ 10731 match(Set dst (ConvL2F (LoadL src))); 10732 10733 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} 10734 ins_encode %{ 10735 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); 10736 %} 10737 ins_pipe(pipe_slow); // XXX 10738%} 10739 10740instruct convL2D_reg_reg(regD dst, rRegL src) 10741%{ 10742 match(Set dst (ConvL2D src)); 10743 10744 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} 10745 ins_encode %{ 10746 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); 10747 %} 10748 ins_pipe(pipe_slow); // XXX 10749%} 10750 10751instruct convL2D_reg_mem(regD dst, memory src) 10752%{ 10753 match(Set dst (ConvL2D (LoadL src))); 10754 10755 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} 10756 ins_encode %{ 10757 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); 10758 %} 10759 ins_pipe(pipe_slow); // XXX 10760%} 10761 10762instruct convI2L_reg_reg(rRegL dst, rRegI src) 10763%{ 10764 match(Set dst (ConvI2L src)); 10765 10766 ins_cost(125); 10767 format %{ "movslq $dst, $src\t# i2l" %} 10768 ins_encode %{ 10769 __ movslq($dst$$Register, $src$$Register); 10770 %} 10771 ins_pipe(ialu_reg_reg); 10772%} 10773 10774// instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) 10775// %{ 10776// match(Set dst (ConvI2L src)); 10777// // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && 10778// // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); 10779// predicate(((const TypeNode*) n)->type()->is_long()->_hi == 10780// (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && 10781// ((const TypeNode*) n)->type()->is_long()->_lo == 10782// (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); 10783 10784// format %{ "movl $dst, $src\t# unsigned i2l" %} 10785// ins_encode(enc_copy(dst, src)); 10786// // opcode(0x63); // needs REX.W 10787// // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); 10788// ins_pipe(ialu_reg_reg); 10789// %} 10790 10791// Zero-extend convert int to long 10792instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) 10793%{ 10794 match(Set dst (AndL (ConvI2L src) mask)); 10795 10796 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} 10797 ins_encode %{ 10798 if ($dst$$reg != $src$$reg) { 10799 __ movl($dst$$Register, $src$$Register); 10800 } 10801 %} 10802 ins_pipe(ialu_reg_reg); 10803%} 10804 10805// Zero-extend convert int to long 10806instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) 10807%{ 10808 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); 10809 10810 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} 10811 ins_encode %{ 10812 __ movl($dst$$Register, $src$$Address); 10813 %} 10814 ins_pipe(ialu_reg_mem); 10815%} 10816 10817instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) 10818%{ 10819 match(Set dst (AndL src mask)); 10820 10821 format %{ "movl $dst, $src\t# zero-extend long" %} 10822 ins_encode %{ 10823 __ movl($dst$$Register, $src$$Register); 10824 %} 10825 ins_pipe(ialu_reg_reg); 10826%} 10827 10828instruct convL2I_reg_reg(rRegI dst, rRegL src) 10829%{ 10830 match(Set dst (ConvL2I src)); 10831 10832 format %{ "movl $dst, $src\t# l2i" %} 10833 ins_encode %{ 10834 __ movl($dst$$Register, $src$$Register); 10835 %} 10836 ins_pipe(ialu_reg_reg); 10837%} 10838 10839 10840instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ 10841 match(Set dst (MoveF2I src)); 10842 effect(DEF dst, USE src); 10843 10844 ins_cost(125); 10845 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} 10846 ins_encode %{ 10847 __ movl($dst$$Register, Address(rsp, $src$$disp)); 10848 %} 10849 ins_pipe(ialu_reg_mem); 10850%} 10851 10852instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 10853 match(Set dst (MoveI2F src)); 10854 effect(DEF dst, USE src); 10855 10856 ins_cost(125); 10857 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} 10858 ins_encode %{ 10859 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); 10860 %} 10861 ins_pipe(pipe_slow); 10862%} 10863 10864instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ 10865 match(Set dst (MoveD2L src)); 10866 effect(DEF dst, USE src); 10867 10868 ins_cost(125); 10869 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} 10870 ins_encode %{ 10871 __ movq($dst$$Register, Address(rsp, $src$$disp)); 10872 %} 10873 ins_pipe(ialu_reg_mem); 10874%} 10875 10876instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ 10877 predicate(!UseXmmLoadAndClearUpper); 10878 match(Set dst (MoveL2D src)); 10879 effect(DEF dst, USE src); 10880 10881 ins_cost(125); 10882 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} 10883 ins_encode %{ 10884 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); 10885 %} 10886 ins_pipe(pipe_slow); 10887%} 10888 10889instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 10890 predicate(UseXmmLoadAndClearUpper); 10891 match(Set dst (MoveL2D src)); 10892 effect(DEF dst, USE src); 10893 10894 ins_cost(125); 10895 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} 10896 ins_encode %{ 10897 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); 10898 %} 10899 ins_pipe(pipe_slow); 10900%} 10901 10902 10903instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 10904 match(Set dst (MoveF2I src)); 10905 effect(DEF dst, USE src); 10906 10907 ins_cost(95); // XXX 10908 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} 10909 ins_encode %{ 10910 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); 10911 %} 10912 ins_pipe(pipe_slow); 10913%} 10914 10915instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ 10916 match(Set dst (MoveI2F src)); 10917 effect(DEF dst, USE src); 10918 10919 ins_cost(100); 10920 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} 10921 ins_encode %{ 10922 __ movl(Address(rsp, $dst$$disp), $src$$Register); 10923 %} 10924 ins_pipe( ialu_mem_reg ); 10925%} 10926 10927instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 10928 match(Set dst (MoveD2L src)); 10929 effect(DEF dst, USE src); 10930 10931 ins_cost(95); // XXX 10932 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} 10933 ins_encode %{ 10934 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); 10935 %} 10936 ins_pipe(pipe_slow); 10937%} 10938 10939instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ 10940 match(Set dst (MoveL2D src)); 10941 effect(DEF dst, USE src); 10942 10943 ins_cost(100); 10944 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} 10945 ins_encode %{ 10946 __ movq(Address(rsp, $dst$$disp), $src$$Register); 10947 %} 10948 ins_pipe(ialu_mem_reg); 10949%} 10950 10951instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ 10952 match(Set dst (MoveF2I src)); 10953 effect(DEF dst, USE src); 10954 ins_cost(85); 10955 format %{ "movd $dst,$src\t# MoveF2I" %} 10956 ins_encode %{ 10957 __ movdl($dst$$Register, $src$$XMMRegister); 10958 %} 10959 ins_pipe( pipe_slow ); 10960%} 10961 10962instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ 10963 match(Set dst (MoveD2L src)); 10964 effect(DEF dst, USE src); 10965 ins_cost(85); 10966 format %{ "movd $dst,$src\t# MoveD2L" %} 10967 ins_encode %{ 10968 __ movdq($dst$$Register, $src$$XMMRegister); 10969 %} 10970 ins_pipe( pipe_slow ); 10971%} 10972 10973instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ 10974 match(Set dst (MoveI2F src)); 10975 effect(DEF dst, USE src); 10976 ins_cost(100); 10977 format %{ "movd $dst,$src\t# MoveI2F" %} 10978 ins_encode %{ 10979 __ movdl($dst$$XMMRegister, $src$$Register); 10980 %} 10981 ins_pipe( pipe_slow ); 10982%} 10983 10984instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ 10985 match(Set dst (MoveL2D src)); 10986 effect(DEF dst, USE src); 10987 ins_cost(100); 10988 format %{ "movd $dst,$src\t# MoveL2D" %} 10989 ins_encode %{ 10990 __ movdq($dst$$XMMRegister, $src$$Register); 10991 %} 10992 ins_pipe( pipe_slow ); 10993%} 10994 10995 10996// ======================================================================= 10997// fast clearing of an array 10998instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero, 10999 Universe dummy, rFlagsReg cr) 11000%{ 11001 predicate(!((ClearArrayNode*)n)->is_large()); 11002 match(Set dummy (ClearArray cnt base)); 11003 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr); 11004 11005 format %{ $$template 11006 $$emit$$"xorq rax, rax\t# ClearArray:\n\t" 11007 $$emit$$"cmp InitArrayShortSize,rcx\n\t" 11008 $$emit$$"jg LARGE\n\t" 11009 $$emit$$"dec rcx\n\t" 11010 $$emit$$"js DONE\t# Zero length\n\t" 11011 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t" 11012 $$emit$$"dec rcx\n\t" 11013 $$emit$$"jge LOOP\n\t" 11014 $$emit$$"jmp DONE\n\t" 11015 $$emit$$"# LARGE:\n\t" 11016 if (UseFastStosb) { 11017 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t" 11018 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t" 11019 } else if (UseXMMForObjInit) { 11020 $$emit$$"mov rdi,rax\n\t" 11021 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t" 11022 $$emit$$"jmpq L_zero_64_bytes\n\t" 11023 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t" 11024 $$emit$$"vmovdqu ymm0,(rax)\n\t" 11025 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t" 11026 $$emit$$"add 0x40,rax\n\t" 11027 $$emit$$"# L_zero_64_bytes:\n\t" 11028 $$emit$$"sub 0x8,rcx\n\t" 11029 $$emit$$"jge L_loop\n\t" 11030 $$emit$$"add 0x4,rcx\n\t" 11031 $$emit$$"jl L_tail\n\t" 11032 $$emit$$"vmovdqu ymm0,(rax)\n\t" 11033 $$emit$$"add 0x20,rax\n\t" 11034 $$emit$$"sub 0x4,rcx\n\t" 11035 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t" 11036 $$emit$$"add 0x4,rcx\n\t" 11037 $$emit$$"jle L_end\n\t" 11038 $$emit$$"dec rcx\n\t" 11039 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t" 11040 $$emit$$"vmovq xmm0,(rax)\n\t" 11041 $$emit$$"add 0x8,rax\n\t" 11042 $$emit$$"dec rcx\n\t" 11043 $$emit$$"jge L_sloop\n\t" 11044 $$emit$$"# L_end:\n\t" 11045 } else { 11046 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t" 11047 } 11048 $$emit$$"# DONE" 11049 %} 11050 ins_encode %{ 11051 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, 11052 $tmp$$XMMRegister, false); 11053 %} 11054 ins_pipe(pipe_slow); 11055%} 11056 11057instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero, 11058 Universe dummy, rFlagsReg cr) 11059%{ 11060 predicate(((ClearArrayNode*)n)->is_large()); 11061 match(Set dummy (ClearArray cnt base)); 11062 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr); 11063 11064 format %{ $$template 11065 if (UseFastStosb) { 11066 $$emit$$"xorq rax, rax\t# ClearArray:\n\t" 11067 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t" 11068 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--" 11069 } else if (UseXMMForObjInit) { 11070 $$emit$$"mov rdi,rax\t# ClearArray:\n\t" 11071 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t" 11072 $$emit$$"jmpq L_zero_64_bytes\n\t" 11073 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t" 11074 $$emit$$"vmovdqu ymm0,(rax)\n\t" 11075 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t" 11076 $$emit$$"add 0x40,rax\n\t" 11077 $$emit$$"# L_zero_64_bytes:\n\t" 11078 $$emit$$"sub 0x8,rcx\n\t" 11079 $$emit$$"jge L_loop\n\t" 11080 $$emit$$"add 0x4,rcx\n\t" 11081 $$emit$$"jl L_tail\n\t" 11082 $$emit$$"vmovdqu ymm0,(rax)\n\t" 11083 $$emit$$"add 0x20,rax\n\t" 11084 $$emit$$"sub 0x4,rcx\n\t" 11085 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t" 11086 $$emit$$"add 0x4,rcx\n\t" 11087 $$emit$$"jle L_end\n\t" 11088 $$emit$$"dec rcx\n\t" 11089 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t" 11090 $$emit$$"vmovq xmm0,(rax)\n\t" 11091 $$emit$$"add 0x8,rax\n\t" 11092 $$emit$$"dec rcx\n\t" 11093 $$emit$$"jge L_sloop\n\t" 11094 $$emit$$"# L_end:\n\t" 11095 } else { 11096 $$emit$$"xorq rax, rax\t# ClearArray:\n\t" 11097 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--" 11098 } 11099 %} 11100 ins_encode %{ 11101 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, 11102 $tmp$$XMMRegister, true); 11103 %} 11104 ins_pipe(pipe_slow); 11105%} 11106 11107instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, 11108 rax_RegI result, legVecS tmp1, rFlagsReg cr) 11109%{ 11110 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 11111 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11112 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); 11113 11114 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} 11115 ins_encode %{ 11116 __ string_compare($str1$$Register, $str2$$Register, 11117 $cnt1$$Register, $cnt2$$Register, $result$$Register, 11118 $tmp1$$XMMRegister, StrIntrinsicNode::LL); 11119 %} 11120 ins_pipe( pipe_slow ); 11121%} 11122 11123instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, 11124 rax_RegI result, legVecS tmp1, rFlagsReg cr) 11125%{ 11126 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU); 11127 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11128 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); 11129 11130 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} 11131 ins_encode %{ 11132 __ string_compare($str1$$Register, $str2$$Register, 11133 $cnt1$$Register, $cnt2$$Register, $result$$Register, 11134 $tmp1$$XMMRegister, StrIntrinsicNode::UU); 11135 %} 11136 ins_pipe( pipe_slow ); 11137%} 11138 11139instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, 11140 rax_RegI result, legVecS tmp1, rFlagsReg cr) 11141%{ 11142 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 11143 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11144 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); 11145 11146 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} 11147 ins_encode %{ 11148 __ string_compare($str1$$Register, $str2$$Register, 11149 $cnt1$$Register, $cnt2$$Register, $result$$Register, 11150 $tmp1$$XMMRegister, StrIntrinsicNode::LU); 11151 %} 11152 ins_pipe( pipe_slow ); 11153%} 11154 11155instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2, 11156 rax_RegI result, legVecS tmp1, rFlagsReg cr) 11157%{ 11158 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 11159 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11160 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); 11161 11162 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} 11163 ins_encode %{ 11164 __ string_compare($str2$$Register, $str1$$Register, 11165 $cnt2$$Register, $cnt1$$Register, $result$$Register, 11166 $tmp1$$XMMRegister, StrIntrinsicNode::UL); 11167 %} 11168 ins_pipe( pipe_slow ); 11169%} 11170 11171// fast search of substring with known size. 11172instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, 11173 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) 11174%{ 11175 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL)); 11176 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); 11177 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); 11178 11179 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} 11180 ins_encode %{ 11181 int icnt2 = (int)$int_cnt2$$constant; 11182 if (icnt2 >= 16) { 11183 // IndexOf for constant substrings with size >= 16 elements 11184 // which don't need to be loaded through stack. 11185 __ string_indexofC8($str1$$Register, $str2$$Register, 11186 $cnt1$$Register, $cnt2$$Register, 11187 icnt2, $result$$Register, 11188 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL); 11189 } else { 11190 // Small strings are loaded through stack if they cross page boundary. 11191 __ string_indexof($str1$$Register, $str2$$Register, 11192 $cnt1$$Register, $cnt2$$Register, 11193 icnt2, $result$$Register, 11194 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL); 11195 } 11196 %} 11197 ins_pipe( pipe_slow ); 11198%} 11199 11200// fast search of substring with known size. 11201instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, 11202 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) 11203%{ 11204 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU)); 11205 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); 11206 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); 11207 11208 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} 11209 ins_encode %{ 11210 int icnt2 = (int)$int_cnt2$$constant; 11211 if (icnt2 >= 8) { 11212 // IndexOf for constant substrings with size >= 8 elements 11213 // which don't need to be loaded through stack. 11214 __ string_indexofC8($str1$$Register, $str2$$Register, 11215 $cnt1$$Register, $cnt2$$Register, 11216 icnt2, $result$$Register, 11217 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU); 11218 } else { 11219 // Small strings are loaded through stack if they cross page boundary. 11220 __ string_indexof($str1$$Register, $str2$$Register, 11221 $cnt1$$Register, $cnt2$$Register, 11222 icnt2, $result$$Register, 11223 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU); 11224 } 11225 %} 11226 ins_pipe( pipe_slow ); 11227%} 11228 11229// fast search of substring with known size. 11230instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, 11231 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) 11232%{ 11233 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL)); 11234 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); 11235 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); 11236 11237 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} 11238 ins_encode %{ 11239 int icnt2 = (int)$int_cnt2$$constant; 11240 if (icnt2 >= 8) { 11241 // IndexOf for constant substrings with size >= 8 elements 11242 // which don't need to be loaded through stack. 11243 __ string_indexofC8($str1$$Register, $str2$$Register, 11244 $cnt1$$Register, $cnt2$$Register, 11245 icnt2, $result$$Register, 11246 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL); 11247 } else { 11248 // Small strings are loaded through stack if they cross page boundary. 11249 __ string_indexof($str1$$Register, $str2$$Register, 11250 $cnt1$$Register, $cnt2$$Register, 11251 icnt2, $result$$Register, 11252 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL); 11253 } 11254 %} 11255 ins_pipe( pipe_slow ); 11256%} 11257 11258instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, 11259 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr) 11260%{ 11261 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL)); 11262 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); 11263 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); 11264 11265 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} 11266 ins_encode %{ 11267 __ string_indexof($str1$$Register, $str2$$Register, 11268 $cnt1$$Register, $cnt2$$Register, 11269 (-1), $result$$Register, 11270 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL); 11271 %} 11272 ins_pipe( pipe_slow ); 11273%} 11274 11275instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, 11276 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr) 11277%{ 11278 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU)); 11279 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); 11280 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); 11281 11282 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} 11283 ins_encode %{ 11284 __ string_indexof($str1$$Register, $str2$$Register, 11285 $cnt1$$Register, $cnt2$$Register, 11286 (-1), $result$$Register, 11287 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU); 11288 %} 11289 ins_pipe( pipe_slow ); 11290%} 11291 11292instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, 11293 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr) 11294%{ 11295 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL)); 11296 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); 11297 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); 11298 11299 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} 11300 ins_encode %{ 11301 __ string_indexof($str1$$Register, $str2$$Register, 11302 $cnt1$$Register, $cnt2$$Register, 11303 (-1), $result$$Register, 11304 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL); 11305 %} 11306 ins_pipe( pipe_slow ); 11307%} 11308 11309instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch, 11310 rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr) 11311%{ 11312 predicate(UseSSE42Intrinsics); 11313 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch)); 11314 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr); 11315 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %} 11316 ins_encode %{ 11317 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register, 11318 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register); 11319 %} 11320 ins_pipe( pipe_slow ); 11321%} 11322 11323// fast string equals 11324instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, 11325 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr) 11326%{ 11327 match(Set result (StrEquals (Binary str1 str2) cnt)); 11328 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); 11329 11330 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} 11331 ins_encode %{ 11332 __ arrays_equals(false, $str1$$Register, $str2$$Register, 11333 $cnt$$Register, $result$$Register, $tmp3$$Register, 11334 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */); 11335 %} 11336 ins_pipe( pipe_slow ); 11337%} 11338 11339// fast array equals 11340instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, 11341 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) 11342%{ 11343 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 11344 match(Set result (AryEq ary1 ary2)); 11345 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); 11346 11347 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} 11348 ins_encode %{ 11349 __ arrays_equals(true, $ary1$$Register, $ary2$$Register, 11350 $tmp3$$Register, $result$$Register, $tmp4$$Register, 11351 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */); 11352 %} 11353 ins_pipe( pipe_slow ); 11354%} 11355 11356instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, 11357 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) 11358%{ 11359 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 11360 match(Set result (AryEq ary1 ary2)); 11361 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); 11362 11363 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} 11364 ins_encode %{ 11365 __ arrays_equals(true, $ary1$$Register, $ary2$$Register, 11366 $tmp3$$Register, $result$$Register, $tmp4$$Register, 11367 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */); 11368 %} 11369 ins_pipe( pipe_slow ); 11370%} 11371 11372instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result, 11373 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr) 11374%{ 11375 match(Set result (HasNegatives ary1 len)); 11376 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr); 11377 11378 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %} 11379 ins_encode %{ 11380 __ has_negatives($ary1$$Register, $len$$Register, 11381 $result$$Register, $tmp3$$Register, 11382 $tmp1$$XMMRegister, $tmp2$$XMMRegister); 11383 %} 11384 ins_pipe( pipe_slow ); 11385%} 11386 11387// fast char[] to byte[] compression 11388instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4, 11389 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{ 11390 match(Set result (StrCompressedCopy src (Binary dst len))); 11391 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); 11392 11393 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %} 11394 ins_encode %{ 11395 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register, 11396 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, 11397 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); 11398 %} 11399 ins_pipe( pipe_slow ); 11400%} 11401 11402// fast byte[] to char[] inflation 11403instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len, 11404 legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{ 11405 match(Set dummy (StrInflatedCopy src (Binary dst len))); 11406 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr); 11407 11408 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %} 11409 ins_encode %{ 11410 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register, 11411 $tmp1$$XMMRegister, $tmp2$$Register); 11412 %} 11413 ins_pipe( pipe_slow ); 11414%} 11415 11416// encode char[] to byte[] in ISO_8859_1 11417instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len, 11418 legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4, 11419 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{ 11420 match(Set result (EncodeISOArray src (Binary dst len))); 11421 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); 11422 11423 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %} 11424 ins_encode %{ 11425 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, 11426 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, 11427 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); 11428 %} 11429 ins_pipe( pipe_slow ); 11430%} 11431 11432//----------Overflow Math Instructions----------------------------------------- 11433 11434instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2) 11435%{ 11436 match(Set cr (OverflowAddI op1 op2)); 11437 effect(DEF cr, USE_KILL op1, USE op2); 11438 11439 format %{ "addl $op1, $op2\t# overflow check int" %} 11440 11441 ins_encode %{ 11442 __ addl($op1$$Register, $op2$$Register); 11443 %} 11444 ins_pipe(ialu_reg_reg); 11445%} 11446 11447instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2) 11448%{ 11449 match(Set cr (OverflowAddI op1 op2)); 11450 effect(DEF cr, USE_KILL op1, USE op2); 11451 11452 format %{ "addl $op1, $op2\t# overflow check int" %} 11453 11454 ins_encode %{ 11455 __ addl($op1$$Register, $op2$$constant); 11456 %} 11457 ins_pipe(ialu_reg_reg); 11458%} 11459 11460instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2) 11461%{ 11462 match(Set cr (OverflowAddL op1 op2)); 11463 effect(DEF cr, USE_KILL op1, USE op2); 11464 11465 format %{ "addq $op1, $op2\t# overflow check long" %} 11466 ins_encode %{ 11467 __ addq($op1$$Register, $op2$$Register); 11468 %} 11469 ins_pipe(ialu_reg_reg); 11470%} 11471 11472instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2) 11473%{ 11474 match(Set cr (OverflowAddL op1 op2)); 11475 effect(DEF cr, USE_KILL op1, USE op2); 11476 11477 format %{ "addq $op1, $op2\t# overflow check long" %} 11478 ins_encode %{ 11479 __ addq($op1$$Register, $op2$$constant); 11480 %} 11481 ins_pipe(ialu_reg_reg); 11482%} 11483 11484instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) 11485%{ 11486 match(Set cr (OverflowSubI op1 op2)); 11487 11488 format %{ "cmpl $op1, $op2\t# overflow check int" %} 11489 ins_encode %{ 11490 __ cmpl($op1$$Register, $op2$$Register); 11491 %} 11492 ins_pipe(ialu_reg_reg); 11493%} 11494 11495instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) 11496%{ 11497 match(Set cr (OverflowSubI op1 op2)); 11498 11499 format %{ "cmpl $op1, $op2\t# overflow check int" %} 11500 ins_encode %{ 11501 __ cmpl($op1$$Register, $op2$$constant); 11502 %} 11503 ins_pipe(ialu_reg_reg); 11504%} 11505 11506instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) 11507%{ 11508 match(Set cr (OverflowSubL op1 op2)); 11509 11510 format %{ "cmpq $op1, $op2\t# overflow check long" %} 11511 ins_encode %{ 11512 __ cmpq($op1$$Register, $op2$$Register); 11513 %} 11514 ins_pipe(ialu_reg_reg); 11515%} 11516 11517instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) 11518%{ 11519 match(Set cr (OverflowSubL op1 op2)); 11520 11521 format %{ "cmpq $op1, $op2\t# overflow check long" %} 11522 ins_encode %{ 11523 __ cmpq($op1$$Register, $op2$$constant); 11524 %} 11525 ins_pipe(ialu_reg_reg); 11526%} 11527 11528instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2) 11529%{ 11530 match(Set cr (OverflowSubI zero op2)); 11531 effect(DEF cr, USE_KILL op2); 11532 11533 format %{ "negl $op2\t# overflow check int" %} 11534 ins_encode %{ 11535 __ negl($op2$$Register); 11536 %} 11537 ins_pipe(ialu_reg_reg); 11538%} 11539 11540instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2) 11541%{ 11542 match(Set cr (OverflowSubL zero op2)); 11543 effect(DEF cr, USE_KILL op2); 11544 11545 format %{ "negq $op2\t# overflow check long" %} 11546 ins_encode %{ 11547 __ negq($op2$$Register); 11548 %} 11549 ins_pipe(ialu_reg_reg); 11550%} 11551 11552instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2) 11553%{ 11554 match(Set cr (OverflowMulI op1 op2)); 11555 effect(DEF cr, USE_KILL op1, USE op2); 11556 11557 format %{ "imull $op1, $op2\t# overflow check int" %} 11558 ins_encode %{ 11559 __ imull($op1$$Register, $op2$$Register); 11560 %} 11561 ins_pipe(ialu_reg_reg_alu0); 11562%} 11563 11564instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp) 11565%{ 11566 match(Set cr (OverflowMulI op1 op2)); 11567 effect(DEF cr, TEMP tmp, USE op1, USE op2); 11568 11569 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %} 11570 ins_encode %{ 11571 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); 11572 %} 11573 ins_pipe(ialu_reg_reg_alu0); 11574%} 11575 11576instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2) 11577%{ 11578 match(Set cr (OverflowMulL op1 op2)); 11579 effect(DEF cr, USE_KILL op1, USE op2); 11580 11581 format %{ "imulq $op1, $op2\t# overflow check long" %} 11582 ins_encode %{ 11583 __ imulq($op1$$Register, $op2$$Register); 11584 %} 11585 ins_pipe(ialu_reg_reg_alu0); 11586%} 11587 11588instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp) 11589%{ 11590 match(Set cr (OverflowMulL op1 op2)); 11591 effect(DEF cr, TEMP tmp, USE op1, USE op2); 11592 11593 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %} 11594 ins_encode %{ 11595 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant); 11596 %} 11597 ins_pipe(ialu_reg_reg_alu0); 11598%} 11599 11600 11601//----------Control Flow Instructions------------------------------------------ 11602// Signed compare Instructions 11603 11604// XXX more variants!! 11605instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) 11606%{ 11607 match(Set cr (CmpI op1 op2)); 11608 effect(DEF cr, USE op1, USE op2); 11609 11610 format %{ "cmpl $op1, $op2" %} 11611 opcode(0x3B); /* Opcode 3B /r */ 11612 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); 11613 ins_pipe(ialu_cr_reg_reg); 11614%} 11615 11616instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) 11617%{ 11618 match(Set cr (CmpI op1 op2)); 11619 11620 format %{ "cmpl $op1, $op2" %} 11621 opcode(0x81, 0x07); /* Opcode 81 /7 */ 11622 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); 11623 ins_pipe(ialu_cr_reg_imm); 11624%} 11625 11626instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) 11627%{ 11628 match(Set cr (CmpI op1 (LoadI op2))); 11629 11630 ins_cost(500); // XXX 11631 format %{ "cmpl $op1, $op2" %} 11632 opcode(0x3B); /* Opcode 3B /r */ 11633 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); 11634 ins_pipe(ialu_cr_reg_mem); 11635%} 11636 11637instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) 11638%{ 11639 match(Set cr (CmpI src zero)); 11640 11641 format %{ "testl $src, $src" %} 11642 opcode(0x85); 11643 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); 11644 ins_pipe(ialu_cr_reg_imm); 11645%} 11646 11647instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) 11648%{ 11649 match(Set cr (CmpI (AndI src con) zero)); 11650 11651 format %{ "testl $src, $con" %} 11652 opcode(0xF7, 0x00); 11653 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); 11654 ins_pipe(ialu_cr_reg_imm); 11655%} 11656 11657instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) 11658%{ 11659 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); 11660 11661 format %{ "testl $src, $mem" %} 11662 opcode(0x85); 11663 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); 11664 ins_pipe(ialu_cr_reg_mem); 11665%} 11666 11667// Unsigned compare Instructions; really, same as signed except they 11668// produce an rFlagsRegU instead of rFlagsReg. 11669instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) 11670%{ 11671 match(Set cr (CmpU op1 op2)); 11672 11673 format %{ "cmpl $op1, $op2\t# unsigned" %} 11674 opcode(0x3B); /* Opcode 3B /r */ 11675 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); 11676 ins_pipe(ialu_cr_reg_reg); 11677%} 11678 11679instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) 11680%{ 11681 match(Set cr (CmpU op1 op2)); 11682 11683 format %{ "cmpl $op1, $op2\t# unsigned" %} 11684 opcode(0x81,0x07); /* Opcode 81 /7 */ 11685 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); 11686 ins_pipe(ialu_cr_reg_imm); 11687%} 11688 11689instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) 11690%{ 11691 match(Set cr (CmpU op1 (LoadI op2))); 11692 11693 ins_cost(500); // XXX 11694 format %{ "cmpl $op1, $op2\t# unsigned" %} 11695 opcode(0x3B); /* Opcode 3B /r */ 11696 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); 11697 ins_pipe(ialu_cr_reg_mem); 11698%} 11699 11700// // // Cisc-spilled version of cmpU_rReg 11701// //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) 11702// //%{ 11703// // match(Set cr (CmpU (LoadI op1) op2)); 11704// // 11705// // format %{ "CMPu $op1,$op2" %} 11706// // ins_cost(500); 11707// // opcode(0x39); /* Opcode 39 /r */ 11708// // ins_encode( OpcP, reg_mem( op1, op2) ); 11709// //%} 11710 11711instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) 11712%{ 11713 match(Set cr (CmpU src zero)); 11714 11715 format %{ "testl $src, $src\t# unsigned" %} 11716 opcode(0x85); 11717 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); 11718 ins_pipe(ialu_cr_reg_imm); 11719%} 11720 11721instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) 11722%{ 11723 match(Set cr (CmpP op1 op2)); 11724 11725 format %{ "cmpq $op1, $op2\t# ptr" %} 11726 opcode(0x3B); /* Opcode 3B /r */ 11727 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); 11728 ins_pipe(ialu_cr_reg_reg); 11729%} 11730 11731instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) 11732%{ 11733 match(Set cr (CmpP op1 (LoadP op2))); 11734 predicate(n->in(2)->as_Load()->barrier_data() == 0); 11735 11736 ins_cost(500); // XXX 11737 format %{ "cmpq $op1, $op2\t# ptr" %} 11738 opcode(0x3B); /* Opcode 3B /r */ 11739 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); 11740 ins_pipe(ialu_cr_reg_mem); 11741%} 11742 11743// // // Cisc-spilled version of cmpP_rReg 11744// //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) 11745// //%{ 11746// // match(Set cr (CmpP (LoadP op1) op2)); 11747// // 11748// // format %{ "CMPu $op1,$op2" %} 11749// // ins_cost(500); 11750// // opcode(0x39); /* Opcode 39 /r */ 11751// // ins_encode( OpcP, reg_mem( op1, op2) ); 11752// //%} 11753 11754// XXX this is generalized by compP_rReg_mem??? 11755// Compare raw pointer (used in out-of-heap check). 11756// Only works because non-oop pointers must be raw pointers 11757// and raw pointers have no anti-dependencies. 11758instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) 11759%{ 11760 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none && 11761 n->in(2)->as_Load()->barrier_data() == 0); 11762 match(Set cr (CmpP op1 (LoadP op2))); 11763 11764 format %{ "cmpq $op1, $op2\t# raw ptr" %} 11765 opcode(0x3B); /* Opcode 3B /r */ 11766 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); 11767 ins_pipe(ialu_cr_reg_mem); 11768%} 11769 11770// This will generate a signed flags result. This should be OK since 11771// any compare to a zero should be eq/neq. 11772instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) 11773%{ 11774 match(Set cr (CmpP src zero)); 11775 11776 format %{ "testq $src, $src\t# ptr" %} 11777 opcode(0x85); 11778 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); 11779 ins_pipe(ialu_cr_reg_imm); 11780%} 11781 11782// This will generate a signed flags result. This should be OK since 11783// any compare to a zero should be eq/neq. 11784instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) 11785%{ 11786 predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) && 11787 n->in(1)->as_Load()->barrier_data() == 0); 11788 match(Set cr (CmpP (LoadP op) zero)); 11789 11790 ins_cost(500); // XXX 11791 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} 11792 opcode(0xF7); /* Opcode F7 /0 */ 11793 ins_encode(REX_mem_wide(op), 11794 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); 11795 ins_pipe(ialu_cr_reg_imm); 11796%} 11797 11798instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) 11799%{ 11800 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && 11801 (CompressedKlassPointers::base() == NULL) && 11802 n->in(1)->as_Load()->barrier_data() == 0); 11803 match(Set cr (CmpP (LoadP mem) zero)); 11804 11805 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} 11806 ins_encode %{ 11807 __ cmpq(r12, $mem$$Address); 11808 %} 11809 ins_pipe(ialu_cr_reg_mem); 11810%} 11811 11812instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) 11813%{ 11814 match(Set cr (CmpN op1 op2)); 11815 11816 format %{ "cmpl $op1, $op2\t# compressed ptr" %} 11817 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} 11818 ins_pipe(ialu_cr_reg_reg); 11819%} 11820 11821instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) 11822%{ 11823 match(Set cr (CmpN src (LoadN mem))); 11824 11825 format %{ "cmpl $src, $mem\t# compressed ptr" %} 11826 ins_encode %{ 11827 __ cmpl($src$$Register, $mem$$Address); 11828 %} 11829 ins_pipe(ialu_cr_reg_mem); 11830%} 11831 11832instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ 11833 match(Set cr (CmpN op1 op2)); 11834 11835 format %{ "cmpl $op1, $op2\t# compressed ptr" %} 11836 ins_encode %{ 11837 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); 11838 %} 11839 ins_pipe(ialu_cr_reg_imm); 11840%} 11841 11842instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) 11843%{ 11844 match(Set cr (CmpN src (LoadN mem))); 11845 11846 format %{ "cmpl $mem, $src\t# compressed ptr" %} 11847 ins_encode %{ 11848 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); 11849 %} 11850 ins_pipe(ialu_cr_reg_mem); 11851%} 11852 11853instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{ 11854 match(Set cr (CmpN op1 op2)); 11855 11856 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %} 11857 ins_encode %{ 11858 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant); 11859 %} 11860 ins_pipe(ialu_cr_reg_imm); 11861%} 11862 11863instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src) 11864%{ 11865 match(Set cr (CmpN src (LoadNKlass mem))); 11866 11867 format %{ "cmpl $mem, $src\t# compressed klass ptr" %} 11868 ins_encode %{ 11869 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant); 11870 %} 11871 ins_pipe(ialu_cr_reg_mem); 11872%} 11873 11874instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ 11875 match(Set cr (CmpN src zero)); 11876 11877 format %{ "testl $src, $src\t# compressed ptr" %} 11878 ins_encode %{ __ testl($src$$Register, $src$$Register); %} 11879 ins_pipe(ialu_cr_reg_imm); 11880%} 11881 11882instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) 11883%{ 11884 predicate(CompressedOops::base() != NULL); 11885 match(Set cr (CmpN (LoadN mem) zero)); 11886 11887 ins_cost(500); // XXX 11888 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} 11889 ins_encode %{ 11890 __ cmpl($mem$$Address, (int)0xFFFFFFFF); 11891 %} 11892 ins_pipe(ialu_cr_reg_mem); 11893%} 11894 11895instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) 11896%{ 11897 predicate(CompressedOops::base() == NULL && (CompressedKlassPointers::base() == NULL)); 11898 match(Set cr (CmpN (LoadN mem) zero)); 11899 11900 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} 11901 ins_encode %{ 11902 __ cmpl(r12, $mem$$Address); 11903 %} 11904 ins_pipe(ialu_cr_reg_mem); 11905%} 11906 11907// Yanked all unsigned pointer compare operations. 11908// Pointer compares are done with CmpP which is already unsigned. 11909 11910instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) 11911%{ 11912 match(Set cr (CmpL op1 op2)); 11913 11914 format %{ "cmpq $op1, $op2" %} 11915 opcode(0x3B); /* Opcode 3B /r */ 11916 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); 11917 ins_pipe(ialu_cr_reg_reg); 11918%} 11919 11920instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) 11921%{ 11922 match(Set cr (CmpL op1 op2)); 11923 11924 format %{ "cmpq $op1, $op2" %} 11925 opcode(0x81, 0x07); /* Opcode 81 /7 */ 11926 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); 11927 ins_pipe(ialu_cr_reg_imm); 11928%} 11929 11930instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) 11931%{ 11932 match(Set cr (CmpL op1 (LoadL op2))); 11933 11934 format %{ "cmpq $op1, $op2" %} 11935 opcode(0x3B); /* Opcode 3B /r */ 11936 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); 11937 ins_pipe(ialu_cr_reg_mem); 11938%} 11939 11940instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) 11941%{ 11942 match(Set cr (CmpL src zero)); 11943 11944 format %{ "testq $src, $src" %} 11945 opcode(0x85); 11946 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); 11947 ins_pipe(ialu_cr_reg_imm); 11948%} 11949 11950instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) 11951%{ 11952 match(Set cr (CmpL (AndL src con) zero)); 11953 11954 format %{ "testq $src, $con\t# long" %} 11955 opcode(0xF7, 0x00); 11956 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); 11957 ins_pipe(ialu_cr_reg_imm); 11958%} 11959 11960instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) 11961%{ 11962 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); 11963 11964 format %{ "testq $src, $mem" %} 11965 opcode(0x85); 11966 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); 11967 ins_pipe(ialu_cr_reg_mem); 11968%} 11969 11970instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero) 11971%{ 11972 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero)); 11973 11974 format %{ "testq $src, $mem" %} 11975 opcode(0x85); 11976 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); 11977 ins_pipe(ialu_cr_reg_mem); 11978%} 11979 11980// Manifest a CmpL result in an integer register. Very painful. 11981// This is the test to avoid. 11982instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) 11983%{ 11984 match(Set dst (CmpL3 src1 src2)); 11985 effect(KILL flags); 11986 11987 ins_cost(275); // XXX 11988 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" 11989 "movl $dst, -1\n\t" 11990 "jl,s done\n\t" 11991 "setne $dst\n\t" 11992 "movzbl $dst, $dst\n\t" 11993 "done:" %} 11994 ins_encode(cmpl3_flag(src1, src2, dst)); 11995 ins_pipe(pipe_slow); 11996%} 11997 11998// Unsigned long compare Instructions; really, same as signed long except they 11999// produce an rFlagsRegU instead of rFlagsReg. 12000instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2) 12001%{ 12002 match(Set cr (CmpUL op1 op2)); 12003 12004 format %{ "cmpq $op1, $op2\t# unsigned" %} 12005 opcode(0x3B); /* Opcode 3B /r */ 12006 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); 12007 ins_pipe(ialu_cr_reg_reg); 12008%} 12009 12010instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2) 12011%{ 12012 match(Set cr (CmpUL op1 op2)); 12013 12014 format %{ "cmpq $op1, $op2\t# unsigned" %} 12015 opcode(0x81, 0x07); /* Opcode 81 /7 */ 12016 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); 12017 ins_pipe(ialu_cr_reg_imm); 12018%} 12019 12020instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2) 12021%{ 12022 match(Set cr (CmpUL op1 (LoadL op2))); 12023 12024 format %{ "cmpq $op1, $op2\t# unsigned" %} 12025 opcode(0x3B); /* Opcode 3B /r */ 12026 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); 12027 ins_pipe(ialu_cr_reg_mem); 12028%} 12029 12030instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero) 12031%{ 12032 match(Set cr (CmpUL src zero)); 12033 12034 format %{ "testq $src, $src\t# unsigned" %} 12035 opcode(0x85); 12036 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); 12037 ins_pipe(ialu_cr_reg_imm); 12038%} 12039 12040instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm) 12041%{ 12042 match(Set cr (CmpI (LoadB mem) imm)); 12043 12044 ins_cost(125); 12045 format %{ "cmpb $mem, $imm" %} 12046 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %} 12047 ins_pipe(ialu_cr_reg_mem); 12048%} 12049 12050instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero) 12051%{ 12052 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero)); 12053 12054 ins_cost(125); 12055 format %{ "testb $mem, $imm\t# ubyte" %} 12056 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %} 12057 ins_pipe(ialu_cr_reg_mem); 12058%} 12059 12060instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero) 12061%{ 12062 match(Set cr (CmpI (AndI (LoadB mem) imm) zero)); 12063 12064 ins_cost(125); 12065 format %{ "testb $mem, $imm\t# byte" %} 12066 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %} 12067 ins_pipe(ialu_cr_reg_mem); 12068%} 12069 12070//----------Max and Min-------------------------------------------------------- 12071// Min Instructions 12072 12073instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) 12074%{ 12075 effect(USE_DEF dst, USE src, USE cr); 12076 12077 format %{ "cmovlgt $dst, $src\t# min" %} 12078 opcode(0x0F, 0x4F); 12079 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); 12080 ins_pipe(pipe_cmov_reg); 12081%} 12082 12083 12084instruct minI_rReg(rRegI dst, rRegI src) 12085%{ 12086 match(Set dst (MinI dst src)); 12087 12088 ins_cost(200); 12089 expand %{ 12090 rFlagsReg cr; 12091 compI_rReg(cr, dst, src); 12092 cmovI_reg_g(dst, src, cr); 12093 %} 12094%} 12095 12096instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) 12097%{ 12098 effect(USE_DEF dst, USE src, USE cr); 12099 12100 format %{ "cmovllt $dst, $src\t# max" %} 12101 opcode(0x0F, 0x4C); 12102 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); 12103 ins_pipe(pipe_cmov_reg); 12104%} 12105 12106 12107instruct maxI_rReg(rRegI dst, rRegI src) 12108%{ 12109 match(Set dst (MaxI dst src)); 12110 12111 ins_cost(200); 12112 expand %{ 12113 rFlagsReg cr; 12114 compI_rReg(cr, dst, src); 12115 cmovI_reg_l(dst, src, cr); 12116 %} 12117%} 12118 12119// ============================================================================ 12120// Branch Instructions 12121 12122// Jump Direct - Label defines a relative address from JMP+1 12123instruct jmpDir(label labl) 12124%{ 12125 match(Goto); 12126 effect(USE labl); 12127 12128 ins_cost(300); 12129 format %{ "jmp $labl" %} 12130 size(5); 12131 ins_encode %{ 12132 Label* L = $labl$$label; 12133 __ jmp(*L, false); // Always long jump 12134 %} 12135 ins_pipe(pipe_jmp); 12136%} 12137 12138// Jump Direct Conditional - Label defines a relative address from Jcc+1 12139instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) 12140%{ 12141 match(If cop cr); 12142 effect(USE labl); 12143 12144 ins_cost(300); 12145 format %{ "j$cop $labl" %} 12146 size(6); 12147 ins_encode %{ 12148 Label* L = $labl$$label; 12149 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12150 %} 12151 ins_pipe(pipe_jcc); 12152%} 12153 12154// Jump Direct Conditional - Label defines a relative address from Jcc+1 12155instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) 12156%{ 12157 predicate(!n->has_vector_mask_set()); 12158 match(CountedLoopEnd cop cr); 12159 effect(USE labl); 12160 12161 ins_cost(300); 12162 format %{ "j$cop $labl\t# loop end" %} 12163 size(6); 12164 ins_encode %{ 12165 Label* L = $labl$$label; 12166 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12167 %} 12168 ins_pipe(pipe_jcc); 12169%} 12170 12171// Jump Direct Conditional - Label defines a relative address from Jcc+1 12172instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ 12173 predicate(!n->has_vector_mask_set()); 12174 match(CountedLoopEnd cop cmp); 12175 effect(USE labl); 12176 12177 ins_cost(300); 12178 format %{ "j$cop,u $labl\t# loop end" %} 12179 size(6); 12180 ins_encode %{ 12181 Label* L = $labl$$label; 12182 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12183 %} 12184 ins_pipe(pipe_jcc); 12185%} 12186 12187instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ 12188 predicate(!n->has_vector_mask_set()); 12189 match(CountedLoopEnd cop cmp); 12190 effect(USE labl); 12191 12192 ins_cost(200); 12193 format %{ "j$cop,u $labl\t# loop end" %} 12194 size(6); 12195 ins_encode %{ 12196 Label* L = $labl$$label; 12197 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12198 %} 12199 ins_pipe(pipe_jcc); 12200%} 12201 12202// mask version 12203// Jump Direct Conditional - Label defines a relative address from Jcc+1 12204instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl) 12205%{ 12206 predicate(n->has_vector_mask_set()); 12207 match(CountedLoopEnd cop cr); 12208 effect(USE labl); 12209 12210 ins_cost(400); 12211 format %{ "j$cop $labl\t# loop end\n\t" 12212 "restorevectmask \t# vector mask restore for loops" %} 12213 size(10); 12214 ins_encode %{ 12215 Label* L = $labl$$label; 12216 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12217 __ restorevectmask(); 12218 %} 12219 ins_pipe(pipe_jcc); 12220%} 12221 12222// Jump Direct Conditional - Label defines a relative address from Jcc+1 12223instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{ 12224 predicate(n->has_vector_mask_set()); 12225 match(CountedLoopEnd cop cmp); 12226 effect(USE labl); 12227 12228 ins_cost(400); 12229 format %{ "j$cop,u $labl\t# loop end\n\t" 12230 "restorevectmask \t# vector mask restore for loops" %} 12231 size(10); 12232 ins_encode %{ 12233 Label* L = $labl$$label; 12234 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12235 __ restorevectmask(); 12236 %} 12237 ins_pipe(pipe_jcc); 12238%} 12239 12240instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ 12241 predicate(n->has_vector_mask_set()); 12242 match(CountedLoopEnd cop cmp); 12243 effect(USE labl); 12244 12245 ins_cost(300); 12246 format %{ "j$cop,u $labl\t# loop end\n\t" 12247 "restorevectmask \t# vector mask restore for loops" %} 12248 size(10); 12249 ins_encode %{ 12250 Label* L = $labl$$label; 12251 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12252 __ restorevectmask(); 12253 %} 12254 ins_pipe(pipe_jcc); 12255%} 12256 12257// Jump Direct Conditional - using unsigned comparison 12258instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ 12259 match(If cop cmp); 12260 effect(USE labl); 12261 12262 ins_cost(300); 12263 format %{ "j$cop,u $labl" %} 12264 size(6); 12265 ins_encode %{ 12266 Label* L = $labl$$label; 12267 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12268 %} 12269 ins_pipe(pipe_jcc); 12270%} 12271 12272instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ 12273 match(If cop cmp); 12274 effect(USE labl); 12275 12276 ins_cost(200); 12277 format %{ "j$cop,u $labl" %} 12278 size(6); 12279 ins_encode %{ 12280 Label* L = $labl$$label; 12281 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12282 %} 12283 ins_pipe(pipe_jcc); 12284%} 12285 12286instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ 12287 match(If cop cmp); 12288 effect(USE labl); 12289 12290 ins_cost(200); 12291 format %{ $$template 12292 if ($cop$$cmpcode == Assembler::notEqual) { 12293 $$emit$$"jp,u $labl\n\t" 12294 $$emit$$"j$cop,u $labl" 12295 } else { 12296 $$emit$$"jp,u done\n\t" 12297 $$emit$$"j$cop,u $labl\n\t" 12298 $$emit$$"done:" 12299 } 12300 %} 12301 ins_encode %{ 12302 Label* l = $labl$$label; 12303 if ($cop$$cmpcode == Assembler::notEqual) { 12304 __ jcc(Assembler::parity, *l, false); 12305 __ jcc(Assembler::notEqual, *l, false); 12306 } else if ($cop$$cmpcode == Assembler::equal) { 12307 Label done; 12308 __ jccb(Assembler::parity, done); 12309 __ jcc(Assembler::equal, *l, false); 12310 __ bind(done); 12311 } else { 12312 ShouldNotReachHere(); 12313 } 12314 %} 12315 ins_pipe(pipe_jcc); 12316%} 12317 12318// ============================================================================ 12319// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary 12320// superklass array for an instance of the superklass. Set a hidden 12321// internal cache on a hit (cache is checked with exposed code in 12322// gen_subtype_check()). Return NZ for a miss or zero for a hit. The 12323// encoding ALSO sets flags. 12324 12325instruct partialSubtypeCheck(rdi_RegP result, 12326 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, 12327 rFlagsReg cr) 12328%{ 12329 match(Set result (PartialSubtypeCheck sub super)); 12330 effect(KILL rcx, KILL cr); 12331 12332 ins_cost(1100); // slightly larger than the next version 12333 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" 12334 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" 12335 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" 12336 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" 12337 "jne,s miss\t\t# Missed: rdi not-zero\n\t" 12338 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" 12339 "xorq $result, $result\t\t Hit: rdi zero\n\t" 12340 "miss:\t" %} 12341 12342 opcode(0x1); // Force a XOR of RDI 12343 ins_encode(enc_PartialSubtypeCheck()); 12344 ins_pipe(pipe_slow); 12345%} 12346 12347instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, 12348 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, 12349 immP0 zero, 12350 rdi_RegP result) 12351%{ 12352 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); 12353 effect(KILL rcx, KILL result); 12354 12355 ins_cost(1000); 12356 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" 12357 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" 12358 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" 12359 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" 12360 "jne,s miss\t\t# Missed: flags nz\n\t" 12361 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" 12362 "miss:\t" %} 12363 12364 opcode(0x0); // No need to XOR RDI 12365 ins_encode(enc_PartialSubtypeCheck()); 12366 ins_pipe(pipe_slow); 12367%} 12368 12369// ============================================================================ 12370// Branch Instructions -- short offset versions 12371// 12372// These instructions are used to replace jumps of a long offset (the default 12373// match) with jumps of a shorter offset. These instructions are all tagged 12374// with the ins_short_branch attribute, which causes the ADLC to suppress the 12375// match rules in general matching. Instead, the ADLC generates a conversion 12376// method in the MachNode which can be used to do in-place replacement of the 12377// long variant with the shorter variant. The compiler will determine if a 12378// branch can be taken by the is_short_branch_offset() predicate in the machine 12379// specific code section of the file. 12380 12381// Jump Direct - Label defines a relative address from JMP+1 12382instruct jmpDir_short(label labl) %{ 12383 match(Goto); 12384 effect(USE labl); 12385 12386 ins_cost(300); 12387 format %{ "jmp,s $labl" %} 12388 size(2); 12389 ins_encode %{ 12390 Label* L = $labl$$label; 12391 __ jmpb(*L); 12392 %} 12393 ins_pipe(pipe_jmp); 12394 ins_short_branch(1); 12395%} 12396 12397// Jump Direct Conditional - Label defines a relative address from Jcc+1 12398instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ 12399 match(If cop cr); 12400 effect(USE labl); 12401 12402 ins_cost(300); 12403 format %{ "j$cop,s $labl" %} 12404 size(2); 12405 ins_encode %{ 12406 Label* L = $labl$$label; 12407 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12408 %} 12409 ins_pipe(pipe_jcc); 12410 ins_short_branch(1); 12411%} 12412 12413// Jump Direct Conditional - Label defines a relative address from Jcc+1 12414instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ 12415 match(CountedLoopEnd cop cr); 12416 effect(USE labl); 12417 12418 ins_cost(300); 12419 format %{ "j$cop,s $labl\t# loop end" %} 12420 size(2); 12421 ins_encode %{ 12422 Label* L = $labl$$label; 12423 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12424 %} 12425 ins_pipe(pipe_jcc); 12426 ins_short_branch(1); 12427%} 12428 12429// Jump Direct Conditional - Label defines a relative address from Jcc+1 12430instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ 12431 match(CountedLoopEnd cop cmp); 12432 effect(USE labl); 12433 12434 ins_cost(300); 12435 format %{ "j$cop,us $labl\t# loop end" %} 12436 size(2); 12437 ins_encode %{ 12438 Label* L = $labl$$label; 12439 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12440 %} 12441 ins_pipe(pipe_jcc); 12442 ins_short_branch(1); 12443%} 12444 12445instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ 12446 match(CountedLoopEnd cop cmp); 12447 effect(USE labl); 12448 12449 ins_cost(300); 12450 format %{ "j$cop,us $labl\t# loop end" %} 12451 size(2); 12452 ins_encode %{ 12453 Label* L = $labl$$label; 12454 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12455 %} 12456 ins_pipe(pipe_jcc); 12457 ins_short_branch(1); 12458%} 12459 12460// Jump Direct Conditional - using unsigned comparison 12461instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ 12462 match(If cop cmp); 12463 effect(USE labl); 12464 12465 ins_cost(300); 12466 format %{ "j$cop,us $labl" %} 12467 size(2); 12468 ins_encode %{ 12469 Label* L = $labl$$label; 12470 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12471 %} 12472 ins_pipe(pipe_jcc); 12473 ins_short_branch(1); 12474%} 12475 12476instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ 12477 match(If cop cmp); 12478 effect(USE labl); 12479 12480 ins_cost(300); 12481 format %{ "j$cop,us $labl" %} 12482 size(2); 12483 ins_encode %{ 12484 Label* L = $labl$$label; 12485 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12486 %} 12487 ins_pipe(pipe_jcc); 12488 ins_short_branch(1); 12489%} 12490 12491instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ 12492 match(If cop cmp); 12493 effect(USE labl); 12494 12495 ins_cost(300); 12496 format %{ $$template 12497 if ($cop$$cmpcode == Assembler::notEqual) { 12498 $$emit$$"jp,u,s $labl\n\t" 12499 $$emit$$"j$cop,u,s $labl" 12500 } else { 12501 $$emit$$"jp,u,s done\n\t" 12502 $$emit$$"j$cop,u,s $labl\n\t" 12503 $$emit$$"done:" 12504 } 12505 %} 12506 size(4); 12507 ins_encode %{ 12508 Label* l = $labl$$label; 12509 if ($cop$$cmpcode == Assembler::notEqual) { 12510 __ jccb(Assembler::parity, *l); 12511 __ jccb(Assembler::notEqual, *l); 12512 } else if ($cop$$cmpcode == Assembler::equal) { 12513 Label done; 12514 __ jccb(Assembler::parity, done); 12515 __ jccb(Assembler::equal, *l); 12516 __ bind(done); 12517 } else { 12518 ShouldNotReachHere(); 12519 } 12520 %} 12521 ins_pipe(pipe_jcc); 12522 ins_short_branch(1); 12523%} 12524 12525// ============================================================================ 12526// inlined locking and unlocking 12527 12528instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{ 12529 predicate(Compile::current()->use_rtm()); 12530 match(Set cr (FastLock object box)); 12531 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box); 12532 ins_cost(300); 12533 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %} 12534 ins_encode %{ 12535 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, 12536 $scr$$Register, $cx1$$Register, $cx2$$Register, 12537 _counters, _rtm_counters, _stack_rtm_counters, 12538 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), 12539 true, ra_->C->profile_rtm()); 12540 %} 12541 ins_pipe(pipe_slow); 12542%} 12543 12544instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{ 12545 predicate(!Compile::current()->use_rtm()); 12546 match(Set cr (FastLock object box)); 12547 effect(TEMP tmp, TEMP scr, USE_KILL box); 12548 ins_cost(300); 12549 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} 12550 ins_encode %{ 12551 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, 12552 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false); 12553 %} 12554 ins_pipe(pipe_slow); 12555%} 12556 12557instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{ 12558 match(Set cr (FastUnlock object box)); 12559 effect(TEMP tmp, USE_KILL box); 12560 ins_cost(300); 12561 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} 12562 ins_encode %{ 12563 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm()); 12564 %} 12565 ins_pipe(pipe_slow); 12566%} 12567 12568 12569// ============================================================================ 12570// Safepoint Instructions 12571instruct safePoint_poll(rFlagsReg cr) 12572%{ 12573 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll()); 12574 match(SafePoint); 12575 effect(KILL cr); 12576 12577 format %{ "testl rax, [rip + #offset_to_poll_page]\t" 12578 "# Safepoint: poll for GC" %} 12579 ins_cost(125); 12580 ins_encode %{ 12581 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type); 12582 __ testl(rax, addr); 12583 %} 12584 ins_pipe(ialu_reg_mem); 12585%} 12586 12587instruct safePoint_poll_far(rFlagsReg cr, rRegP poll) 12588%{ 12589 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll()); 12590 match(SafePoint poll); 12591 effect(KILL cr, USE poll); 12592 12593 format %{ "testl rax, [$poll]\t" 12594 "# Safepoint: poll for GC" %} 12595 ins_cost(125); 12596 ins_encode %{ 12597 __ relocate(relocInfo::poll_type); 12598 __ testl(rax, Address($poll$$Register, 0)); 12599 %} 12600 ins_pipe(ialu_reg_mem); 12601%} 12602 12603instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll) 12604%{ 12605 predicate(SafepointMechanism::uses_thread_local_poll()); 12606 match(SafePoint poll); 12607 effect(KILL cr, USE poll); 12608 12609 format %{ "testl rax, [$poll]\t" 12610 "# Safepoint: poll for GC" %} 12611 ins_cost(125); 12612 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */ 12613 ins_encode %{ 12614 __ relocate(relocInfo::poll_type); 12615 address pre_pc = __ pc(); 12616 __ testl(rax, Address($poll$$Register, 0)); 12617 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]"); 12618 %} 12619 ins_pipe(ialu_reg_mem); 12620%} 12621 12622// ============================================================================ 12623// Procedure Call/Return Instructions 12624// Call Java Static Instruction 12625// Note: If this code changes, the corresponding ret_addr_offset() and 12626// compute_padding() functions will have to be adjusted. 12627instruct CallStaticJavaDirect(method meth) %{ 12628 match(CallStaticJava); 12629 effect(USE meth); 12630 12631 ins_cost(300); 12632 format %{ "call,static " %} 12633 opcode(0xE8); /* E8 cd */ 12634 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog); 12635 ins_pipe(pipe_slow); 12636 ins_alignment(4); 12637%} 12638 12639// Call Java Dynamic Instruction 12640// Note: If this code changes, the corresponding ret_addr_offset() and 12641// compute_padding() functions will have to be adjusted. 12642instruct CallDynamicJavaDirect(method meth) 12643%{ 12644 match(CallDynamicJava); 12645 effect(USE meth); 12646 12647 ins_cost(300); 12648 format %{ "movq rax, #Universe::non_oop_word()\n\t" 12649 "call,dynamic " %} 12650 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog); 12651 ins_pipe(pipe_slow); 12652 ins_alignment(4); 12653%} 12654 12655// Call Runtime Instruction 12656instruct CallRuntimeDirect(method meth) 12657%{ 12658 match(CallRuntime); 12659 effect(USE meth); 12660 12661 ins_cost(300); 12662 format %{ "call,runtime " %} 12663 ins_encode(clear_avx, Java_To_Runtime(meth)); 12664 ins_pipe(pipe_slow); 12665%} 12666 12667// Call runtime without safepoint 12668instruct CallLeafDirect(method meth) 12669%{ 12670 match(CallLeaf); 12671 effect(USE meth); 12672 12673 ins_cost(300); 12674 format %{ "call_leaf,runtime " %} 12675 ins_encode(clear_avx, Java_To_Runtime(meth)); 12676 ins_pipe(pipe_slow); 12677%} 12678 12679// Call runtime without safepoint 12680instruct CallLeafNoFPDirect(method meth) 12681%{ 12682 match(CallLeafNoFP); 12683 effect(USE meth); 12684 12685 ins_cost(300); 12686 format %{ "call_leaf_nofp,runtime " %} 12687 ins_encode(clear_avx, Java_To_Runtime(meth)); 12688 ins_pipe(pipe_slow); 12689%} 12690 12691// Return Instruction 12692// Remove the return address & jump to it. 12693// Notice: We always emit a nop after a ret to make sure there is room 12694// for safepoint patching 12695instruct Ret() 12696%{ 12697 match(Return); 12698 12699 format %{ "ret" %} 12700 opcode(0xC3); 12701 ins_encode(OpcP); 12702 ins_pipe(pipe_jmp); 12703%} 12704 12705// Tail Call; Jump from runtime stub to Java code. 12706// Also known as an 'interprocedural jump'. 12707// Target of jump will eventually return to caller. 12708// TailJump below removes the return address. 12709instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) 12710%{ 12711 match(TailCall jump_target method_oop); 12712 12713 ins_cost(300); 12714 format %{ "jmp $jump_target\t# rbx holds method oop" %} 12715 opcode(0xFF, 0x4); /* Opcode FF /4 */ 12716 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); 12717 ins_pipe(pipe_jmp); 12718%} 12719 12720// Tail Jump; remove the return address; jump to target. 12721// TailCall above leaves the return address around. 12722instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) 12723%{ 12724 match(TailJump jump_target ex_oop); 12725 12726 ins_cost(300); 12727 format %{ "popq rdx\t# pop return address\n\t" 12728 "jmp $jump_target" %} 12729 opcode(0xFF, 0x4); /* Opcode FF /4 */ 12730 ins_encode(Opcode(0x5a), // popq rdx 12731 REX_reg(jump_target), OpcP, reg_opc(jump_target)); 12732 ins_pipe(pipe_jmp); 12733%} 12734 12735// Create exception oop: created by stack-crawling runtime code. 12736// Created exception is now available to this handler, and is setup 12737// just prior to jumping to this handler. No code emitted. 12738instruct CreateException(rax_RegP ex_oop) 12739%{ 12740 match(Set ex_oop (CreateEx)); 12741 12742 size(0); 12743 // use the following format syntax 12744 format %{ "# exception oop is in rax; no code emitted" %} 12745 ins_encode(); 12746 ins_pipe(empty); 12747%} 12748 12749// Rethrow exception: 12750// The exception oop will come in the first argument position. 12751// Then JUMP (not call) to the rethrow stub code. 12752instruct RethrowException() 12753%{ 12754 match(Rethrow); 12755 12756 // use the following format syntax 12757 format %{ "jmp rethrow_stub" %} 12758 ins_encode(enc_rethrow); 12759 ins_pipe(pipe_jmp); 12760%} 12761 12762// ============================================================================ 12763// This name is KNOWN by the ADLC and cannot be changed. 12764// The ADLC forces a 'TypeRawPtr::BOTTOM' output type 12765// for this guy. 12766instruct tlsLoadP(r15_RegP dst) %{ 12767 match(Set dst (ThreadLocal)); 12768 effect(DEF dst); 12769 12770 size(0); 12771 format %{ "# TLS is in R15" %} 12772 ins_encode( /*empty encoding*/ ); 12773 ins_pipe(ialu_reg_reg); 12774%} 12775 12776 12777//----------PEEPHOLE RULES----------------------------------------------------- 12778// These must follow all instruction definitions as they use the names 12779// defined in the instructions definitions. 12780// 12781// peepmatch ( root_instr_name [preceding_instruction]* ); 12782// 12783// peepconstraint %{ 12784// (instruction_number.operand_name relational_op instruction_number.operand_name 12785// [, ...] ); 12786// // instruction numbers are zero-based using left to right order in peepmatch 12787// 12788// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12789// // provide an instruction_number.operand_name for each operand that appears 12790// // in the replacement instruction's match rule 12791// 12792// ---------VM FLAGS--------------------------------------------------------- 12793// 12794// All peephole optimizations can be turned off using -XX:-OptoPeephole 12795// 12796// Each peephole rule is given an identifying number starting with zero and 12797// increasing by one in the order seen by the parser. An individual peephole 12798// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12799// on the command-line. 12800// 12801// ---------CURRENT LIMITATIONS---------------------------------------------- 12802// 12803// Only match adjacent instructions in same basic block 12804// Only equality constraints 12805// Only constraints between operands, not (0.dest_reg == RAX_enc) 12806// Only one replacement instruction 12807// 12808// ---------EXAMPLE---------------------------------------------------------- 12809// 12810// // pertinent parts of existing instructions in architecture description 12811// instruct movI(rRegI dst, rRegI src) 12812// %{ 12813// match(Set dst (CopyI src)); 12814// %} 12815// 12816// instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) 12817// %{ 12818// match(Set dst (AddI dst src)); 12819// effect(KILL cr); 12820// %} 12821// 12822// // Change (inc mov) to lea 12823// peephole %{ 12824// // increment preceeded by register-register move 12825// peepmatch ( incI_rReg movI ); 12826// // require that the destination register of the increment 12827// // match the destination register of the move 12828// peepconstraint ( 0.dst == 1.dst ); 12829// // construct a replacement instruction that sets 12830// // the destination to ( move's source register + one ) 12831// peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); 12832// %} 12833// 12834 12835// Implementation no longer uses movX instructions since 12836// machine-independent system no longer uses CopyX nodes. 12837// 12838// peephole 12839// %{ 12840// peepmatch (incI_rReg movI); 12841// peepconstraint (0.dst == 1.dst); 12842// peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); 12843// %} 12844 12845// peephole 12846// %{ 12847// peepmatch (decI_rReg movI); 12848// peepconstraint (0.dst == 1.dst); 12849// peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); 12850// %} 12851 12852// peephole 12853// %{ 12854// peepmatch (addI_rReg_imm movI); 12855// peepconstraint (0.dst == 1.dst); 12856// peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); 12857// %} 12858 12859// peephole 12860// %{ 12861// peepmatch (incL_rReg movL); 12862// peepconstraint (0.dst == 1.dst); 12863// peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); 12864// %} 12865 12866// peephole 12867// %{ 12868// peepmatch (decL_rReg movL); 12869// peepconstraint (0.dst == 1.dst); 12870// peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); 12871// %} 12872 12873// peephole 12874// %{ 12875// peepmatch (addL_rReg_imm movL); 12876// peepconstraint (0.dst == 1.dst); 12877// peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); 12878// %} 12879 12880// peephole 12881// %{ 12882// peepmatch (addP_rReg_imm movP); 12883// peepconstraint (0.dst == 1.dst); 12884// peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); 12885// %} 12886 12887// // Change load of spilled value to only a spill 12888// instruct storeI(memory mem, rRegI src) 12889// %{ 12890// match(Set mem (StoreI mem src)); 12891// %} 12892// 12893// instruct loadI(rRegI dst, memory mem) 12894// %{ 12895// match(Set dst (LoadI mem)); 12896// %} 12897// 12898 12899peephole 12900%{ 12901 peepmatch (loadI storeI); 12902 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 12903 peepreplace (storeI(1.mem 1.mem 1.src)); 12904%} 12905 12906peephole 12907%{ 12908 peepmatch (loadL storeL); 12909 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 12910 peepreplace (storeL(1.mem 1.mem 1.src)); 12911%} 12912 12913//----------SMARTSPILL RULES--------------------------------------------------- 12914// These must follow all instruction definitions as they use the names 12915// defined in the instructions definitions. 12916