1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020 Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 */
24
25 #include <stdio.h>
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32
33 #ifndef PRODUCT
34 const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;
35 #endif
36
37 #include "compiler/disassembler.hpp"
38 #include "memory/resourceArea.hpp"
39 #include "runtime/interfaceSupport.inline.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "immediate_aarch64.hpp"
42
43 extern "C" void entry(CodeBuffer *cb);
44
45 #define __ _masm.
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #else
49 #define BLOCK_COMMENT(str) block_comment(str)
50 #endif
51
52 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
53
54 static float unpack(unsigned value);
55
56 short Assembler::SIMD_Size_in_bytes[] = {
57 // T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
58 8, 16, 8, 16, 8, 16, 8, 16, 16
59 };
60
61 #ifdef ASSERT
asm_check(const unsigned int * insns,const unsigned int * insns1,size_t len)62 static void asm_check(const unsigned int *insns, const unsigned int *insns1, size_t len) {
63 bool ok = true;
64 for (unsigned int i = 0; i < len; i++) {
65 if (insns[i] != insns1[i]) {
66 ok = false;
67 printf("Ours:\n");
68 Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
69 printf("Theirs:\n");
70 Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
71 printf("\n");
72 }
73 }
74 assert(ok, "Assembler smoke test failed");
75 }
76
entry(CodeBuffer * cb)77 void entry(CodeBuffer *cb) {
78
79 // {
80 // for (int i = 0; i < 256; i+=16)
81 // {
82 // printf("\"%20.20g\", ", unpack(i));
83 // printf("\"%20.20g\", ", unpack(i+1));
84 // }
85 // printf("\n");
86 // }
87
88 Assembler _masm(cb);
89 address entry = __ pc();
90
91 // Smoke test for assembler
92
93 // BEGIN Generated code -- do not edit
94 // Generated by aarch64-asmtest.py
95 Label back, forth;
96 __ bind(back);
97
98 // ArithOp
99 __ add(r15, r12, r16, Assembler::LSR, 30); // add x15, x12, x16, LSR #30
100 __ sub(r1, r15, r3, Assembler::LSR, 32); // sub x1, x15, x3, LSR #32
101 __ adds(r13, r25, r5, Assembler::LSL, 13); // adds x13, x25, x5, LSL #13
102 __ subs(r22, r28, r6, Assembler::ASR, 17); // subs x22, x28, x6, ASR #17
103 __ addw(r0, r9, r22, Assembler::ASR, 6); // add w0, w9, w22, ASR #6
104 __ subw(r19, r3, r25, Assembler::LSL, 21); // sub w19, w3, w25, LSL #21
105 __ addsw(r4, r19, r11, Assembler::LSL, 20); // adds w4, w19, w11, LSL #20
106 __ subsw(r24, r7, r19, Assembler::ASR, 0); // subs w24, w7, w19, ASR #0
107 __ andr(r30, r7, r11, Assembler::LSL, 48); // and x30, x7, x11, LSL #48
108 __ orr(r24, r8, r15, Assembler::LSL, 12); // orr x24, x8, x15, LSL #12
109 __ eor(r17, r9, r23, Assembler::LSL, 1); // eor x17, x9, x23, LSL #1
110 __ ands(r14, r11, r4, Assembler::LSR, 55); // ands x14, x11, x4, LSR #55
111 __ andw(r19, r7, r12, Assembler::LSR, 17); // and w19, w7, w12, LSR #17
112 __ orrw(r19, r27, r11, Assembler::ASR, 28); // orr w19, w27, w11, ASR #28
113 __ eorw(r30, r3, r22, Assembler::LSR, 31); // eor w30, w3, w22, LSR #31
114 __ andsw(r19, r26, r28, Assembler::ASR, 0); // ands w19, w26, w28, ASR #0
115 __ bic(r29, r6, r26, Assembler::LSL, 51); // bic x29, x6, x26, LSL #51
116 __ orn(r26, r27, r17, Assembler::LSL, 35); // orn x26, x27, x17, LSL #35
117 __ eon(r21, r4, r14, Assembler::LSL, 5); // eon x21, x4, x14, LSL #5
118 __ bics(r2, r15, r0, Assembler::ASR, 5); // bics x2, x15, x0, ASR #5
119 __ bicw(r2, r7, r2, Assembler::LSL, 29); // bic w2, w7, w2, LSL #29
120 __ ornw(r24, r12, r21, Assembler::LSR, 5); // orn w24, w12, w21, LSR #5
121 __ eonw(r30, r15, r19, Assembler::LSL, 2); // eon w30, w15, w19, LSL #2
122 __ bicsw(r30, r23, r17, Assembler::ASR, 28); // bics w30, w23, w17, ASR #28
123
124 // AddSubImmOp
125 __ addw(r4, r20, 660u); // add w4, w20, #660
126 __ addsw(r2, r10, 710u); // adds w2, w10, #710
127 __ subw(r19, r26, 244u); // sub w19, w26, #244
128 __ subsw(r28, r13, 73u); // subs w28, w13, #73
129 __ add(r2, r30, 862u); // add x2, x30, #862
130 __ adds(r27, r16, 574u); // adds x27, x16, #574
131 __ sub(r22, r9, 589u); // sub x22, x9, #589
132 __ subs(r4, r1, 698u); // subs x4, x1, #698
133
134 // LogicalImmOp
135 __ andw(r28, r19, 4294709247ul); // and w28, w19, #0xfffc0fff
136 __ orrw(r27, r5, 536870910ul); // orr w27, w5, #0x1ffffffe
137 __ eorw(r30, r20, 4294840319ul); // eor w30, w20, #0xfffe0fff
138 __ andsw(r22, r26, 4294959615ul); // ands w22, w26, #0xffffe1ff
139 __ andr(r5, r7, 4194300ul); // and x5, x7, #0x3ffffc
140 __ orr(r13, r7, 18014398509481728ul); // orr x13, x7, #0x3fffffffffff00
141 __ eor(r7, r9, 18442240474082197503ul); // eor x7, x9, #0xfff0000000003fff
142 __ ands(r3, r0, 18374686479671656447ul); // ands x3, x0, #0xff00000000007fff
143
144 // AbsOp
145 __ b(__ pc()); // b .
146 __ b(back); // b back
147 __ b(forth); // b forth
148 __ bl(__ pc()); // bl .
149 __ bl(back); // bl back
150 __ bl(forth); // bl forth
151
152 // RegAndAbsOp
153 __ cbzw(r16, __ pc()); // cbz w16, .
154 __ cbzw(r16, back); // cbz w16, back
155 __ cbzw(r16, forth); // cbz w16, forth
156 __ cbnzw(r19, __ pc()); // cbnz w19, .
157 __ cbnzw(r19, back); // cbnz w19, back
158 __ cbnzw(r19, forth); // cbnz w19, forth
159 __ cbz(r5, __ pc()); // cbz x5, .
160 __ cbz(r5, back); // cbz x5, back
161 __ cbz(r5, forth); // cbz x5, forth
162 __ cbnz(r4, __ pc()); // cbnz x4, .
163 __ cbnz(r4, back); // cbnz x4, back
164 __ cbnz(r4, forth); // cbnz x4, forth
165 __ adr(r27, __ pc()); // adr x27, .
166 __ adr(r27, back); // adr x27, back
167 __ adr(r27, forth); // adr x27, forth
168 __ _adrp(r16, __ pc()); // adrp x16, .
169
170 // RegImmAbsOp
171 __ tbz(r28, 8, __ pc()); // tbz x28, #8, .
172 __ tbz(r28, 8, back); // tbz x28, #8, back
173 __ tbz(r28, 8, forth); // tbz x28, #8, forth
174 __ tbnz(r1, 1, __ pc()); // tbnz x1, #1, .
175 __ tbnz(r1, 1, back); // tbnz x1, #1, back
176 __ tbnz(r1, 1, forth); // tbnz x1, #1, forth
177
178 // MoveWideImmOp
179 __ movnw(r20, 8639, 16); // movn w20, #8639, lsl 16
180 __ movzw(r7, 25835, 0); // movz w7, #25835, lsl 0
181 __ movkw(r17, 7261, 0); // movk w17, #7261, lsl 0
182 __ movn(r14, 2097, 32); // movn x14, #2097, lsl 32
183 __ movz(r9, 16082, 0); // movz x9, #16082, lsl 0
184 __ movk(r19, 13962, 16); // movk x19, #13962, lsl 16
185
186 // BitfieldOp
187 __ sbfm(r9, r22, 6, 22); // sbfm x9, x22, #6, #22
188 __ bfmw(r19, r0, 11, 0); // bfm w19, w0, #11, #0
189 __ ubfmw(r10, r19, 11, 19); // ubfm w10, w19, #11, #19
190 __ sbfm(r4, r15, 5, 17); // sbfm x4, x15, #5, #17
191 __ bfm(r3, r5, 19, 28); // bfm x3, x5, #19, #28
192 __ ubfm(r12, r28, 17, 2); // ubfm x12, x28, #17, #2
193
194 // ExtractOp
195 __ extrw(r15, r0, r22, 3); // extr w15, w0, w22, #3
196 __ extr(r6, r14, r14, 55); // extr x6, x14, x14, #55
197
198 // CondBranchOp
199 __ br(Assembler::EQ, __ pc()); // b.EQ .
200 __ br(Assembler::EQ, back); // b.EQ back
201 __ br(Assembler::EQ, forth); // b.EQ forth
202 __ br(Assembler::NE, __ pc()); // b.NE .
203 __ br(Assembler::NE, back); // b.NE back
204 __ br(Assembler::NE, forth); // b.NE forth
205 __ br(Assembler::HS, __ pc()); // b.HS .
206 __ br(Assembler::HS, back); // b.HS back
207 __ br(Assembler::HS, forth); // b.HS forth
208 __ br(Assembler::CS, __ pc()); // b.CS .
209 __ br(Assembler::CS, back); // b.CS back
210 __ br(Assembler::CS, forth); // b.CS forth
211 __ br(Assembler::LO, __ pc()); // b.LO .
212 __ br(Assembler::LO, back); // b.LO back
213 __ br(Assembler::LO, forth); // b.LO forth
214 __ br(Assembler::CC, __ pc()); // b.CC .
215 __ br(Assembler::CC, back); // b.CC back
216 __ br(Assembler::CC, forth); // b.CC forth
217 __ br(Assembler::MI, __ pc()); // b.MI .
218 __ br(Assembler::MI, back); // b.MI back
219 __ br(Assembler::MI, forth); // b.MI forth
220 __ br(Assembler::PL, __ pc()); // b.PL .
221 __ br(Assembler::PL, back); // b.PL back
222 __ br(Assembler::PL, forth); // b.PL forth
223 __ br(Assembler::VS, __ pc()); // b.VS .
224 __ br(Assembler::VS, back); // b.VS back
225 __ br(Assembler::VS, forth); // b.VS forth
226 __ br(Assembler::VC, __ pc()); // b.VC .
227 __ br(Assembler::VC, back); // b.VC back
228 __ br(Assembler::VC, forth); // b.VC forth
229 __ br(Assembler::HI, __ pc()); // b.HI .
230 __ br(Assembler::HI, back); // b.HI back
231 __ br(Assembler::HI, forth); // b.HI forth
232 __ br(Assembler::LS, __ pc()); // b.LS .
233 __ br(Assembler::LS, back); // b.LS back
234 __ br(Assembler::LS, forth); // b.LS forth
235 __ br(Assembler::GE, __ pc()); // b.GE .
236 __ br(Assembler::GE, back); // b.GE back
237 __ br(Assembler::GE, forth); // b.GE forth
238 __ br(Assembler::LT, __ pc()); // b.LT .
239 __ br(Assembler::LT, back); // b.LT back
240 __ br(Assembler::LT, forth); // b.LT forth
241 __ br(Assembler::GT, __ pc()); // b.GT .
242 __ br(Assembler::GT, back); // b.GT back
243 __ br(Assembler::GT, forth); // b.GT forth
244 __ br(Assembler::LE, __ pc()); // b.LE .
245 __ br(Assembler::LE, back); // b.LE back
246 __ br(Assembler::LE, forth); // b.LE forth
247 __ br(Assembler::AL, __ pc()); // b.AL .
248 __ br(Assembler::AL, back); // b.AL back
249 __ br(Assembler::AL, forth); // b.AL forth
250 __ br(Assembler::NV, __ pc()); // b.NV .
251 __ br(Assembler::NV, back); // b.NV back
252 __ br(Assembler::NV, forth); // b.NV forth
253
254 // ImmOp
255 __ svc(22064); // svc #22064
256 __ hvc(533); // hvc #533
257 __ smc(9942); // smc #9942
258 __ brk(4714); // brk #4714
259 __ hlt(4302); // hlt #4302
260
261 // Op
262 __ nop(); // nop
263 __ eret(); // eret
264 __ drps(); // drps
265 __ isb(); // isb
266
267 // SystemOp
268 __ dsb(Assembler::OSH); // dsb OSH
269 __ dmb(Assembler::NSHLD); // dmb NSHLD
270
271 // OneRegOp
272 __ br(r20); // br x20
273 __ blr(r2); // blr x2
274
275 // LoadStoreExclusiveOp
276 __ stxr(r18, r23, r0); // stxr w18, x23, [x0]
277 __ stlxr(r30, r5, r22); // stlxr w30, x5, [x22]
278 __ ldxr(r5, r8); // ldxr x5, [x8]
279 __ ldaxr(r20, r16); // ldaxr x20, [x16]
280 __ stlr(r6, r11); // stlr x6, [x11]
281 __ ldar(r6, r27); // ldar x6, [x27]
282
283 // LoadStoreExclusiveOp
284 __ stxrw(r10, r17, r5); // stxr w10, w17, [x5]
285 __ stlxrw(r22, r9, r12); // stlxr w22, w9, [x12]
286 __ ldxrw(r27, r8); // ldxr w27, [x8]
287 __ ldaxrw(r23, r2); // ldaxr w23, [x2]
288 __ stlrw(r26, r29); // stlr w26, [x29]
289 __ ldarw(r13, r10); // ldar w13, [x10]
290
291 // LoadStoreExclusiveOp
292 __ stxrh(r25, r28, r27); // stxrh w25, w28, [x27]
293 __ stlxrh(r29, r22, r12); // stlxrh w29, w22, [x12]
294 __ ldxrh(r22, r28); // ldxrh w22, [x28]
295 __ ldaxrh(r3, r30); // ldaxrh w3, [x30]
296 __ stlrh(r24, r15); // stlrh w24, [x15]
297 __ ldarh(r27, r26); // ldarh w27, [x26]
298
299 // LoadStoreExclusiveOp
300 __ stxrb(r11, r10, r19); // stxrb w11, w10, [x19]
301 __ stlxrb(r23, r27, r22); // stlxrb w23, w27, [x22]
302 __ ldxrb(r24, r16); // ldxrb w24, [x16]
303 __ ldaxrb(r24, r1); // ldaxrb w24, [x1]
304 __ stlrb(r5, r29); // stlrb w5, [x29]
305 __ ldarb(r24, r16); // ldarb w24, [x16]
306
307 // LoadStoreExclusiveOp
308 __ ldxp(r25, r24, r17); // ldxp x25, x24, [x17]
309 __ ldaxp(r22, r12, r19); // ldaxp x22, x12, [x19]
310 __ stxp(r0, r26, r21, r25); // stxp w0, x26, x21, [x25]
311 __ stlxp(r1, r6, r11, r5); // stlxp w1, x6, x11, [x5]
312
313 // LoadStoreExclusiveOp
314 __ ldxpw(r13, r14, r4); // ldxp w13, w14, [x4]
315 __ ldaxpw(r17, r2, r6); // ldaxp w17, w2, [x6]
316 __ stxpw(r15, r3, r9, r18); // stxp w15, w3, w9, [x18]
317 __ stlxpw(r18, r17, r4, r9); // stlxp w18, w17, w4, [x9]
318
319 // base_plus_unscaled_offset
320 // LoadStoreOp
321 __ str(r23, Address(r21, -49)); // str x23, [x21, -49]
322 __ strw(r21, Address(r2, 63)); // str w21, [x2, 63]
323 __ strb(r27, Address(r28, 11)); // strb w27, [x28, 11]
324 __ strh(r29, Address(r15, -13)); // strh w29, [x15, -13]
325 __ ldr(r14, Address(r30, -45)); // ldr x14, [x30, -45]
326 __ ldrw(r29, Address(r28, 53)); // ldr w29, [x28, 53]
327 __ ldrb(r20, Address(r26, 7)); // ldrb w20, [x26, 7]
328 __ ldrh(r25, Address(r2, -50)); // ldrh w25, [x2, -50]
329 __ ldrsb(r3, Address(r10, -15)); // ldrsb x3, [x10, -15]
330 __ ldrsh(r14, Address(r15, 19)); // ldrsh x14, [x15, 19]
331 __ ldrshw(r29, Address(r11, -5)); // ldrsh w29, [x11, -5]
332 __ ldrsw(r15, Address(r5, -71)); // ldrsw x15, [x5, -71]
333 __ ldrd(v19, Address(r12, 3)); // ldr d19, [x12, 3]
334 __ ldrs(v12, Address(r27, 42)); // ldr s12, [x27, 42]
335 __ strd(v22, Address(r28, 125)); // str d22, [x28, 125]
336 __ strs(v24, Address(r15, -20)); // str s24, [x15, -20]
337
338 // pre
339 // LoadStoreOp
340 __ str(r8, Address(__ pre(r28, -24))); // str x8, [x28, -24]!
341 __ strw(r6, Address(__ pre(r15, 37))); // str w6, [x15, 37]!
342 __ strb(r7, Address(__ pre(r1, 7))); // strb w7, [x1, 7]!
343 __ strh(r0, Address(__ pre(r17, 30))); // strh w0, [x17, 30]!
344 __ ldr(r25, Address(__ pre(r29, 84))); // ldr x25, [x29, 84]!
345 __ ldrw(r26, Address(__ pre(r20, -52))); // ldr w26, [x20, -52]!
346 __ ldrb(r26, Address(__ pre(r29, -25))); // ldrb w26, [x29, -25]!
347 __ ldrh(r4, Address(__ pre(r25, 26))); // ldrh w4, [x25, 26]!
348 __ ldrsb(r28, Address(__ pre(r8, -21))); // ldrsb x28, [x8, -21]!
349 __ ldrsh(r17, Address(__ pre(r14, -6))); // ldrsh x17, [x14, -6]!
350 __ ldrshw(r28, Address(__ pre(r23, 10))); // ldrsh w28, [x23, 10]!
351 __ ldrsw(r30, Address(__ pre(r27, -64))); // ldrsw x30, [x27, -64]!
352 __ ldrd(v20, Address(__ pre(r30, -242))); // ldr d20, [x30, -242]!
353 __ ldrs(v17, Address(__ pre(r27, 20))); // ldr s17, [x27, 20]!
354 __ strd(v7, Address(__ pre(r3, 17))); // str d7, [x3, 17]!
355 __ strs(v13, Address(__ pre(r11, -16))); // str s13, [x11, -16]!
356
357 // post
358 // LoadStoreOp
359 __ str(r6, Address(__ post(r9, -61))); // str x6, [x9], -61
360 __ strw(r16, Address(__ post(r5, -29))); // str w16, [x5], -29
361 __ strb(r29, Address(__ post(r29, 15))); // strb w29, [x29], 15
362 __ strh(r4, Address(__ post(r20, 18))); // strh w4, [x20], 18
363 __ ldr(r19, Address(__ post(r18, 46))); // ldr x19, [x18], 46
364 __ ldrw(r22, Address(__ post(r2, 23))); // ldr w22, [x2], 23
365 __ ldrb(r7, Address(__ post(r3, -30))); // ldrb w7, [x3], -30
366 __ ldrh(r11, Address(__ post(r12, -29))); // ldrh w11, [x12], -29
367 __ ldrsb(r8, Address(__ post(r6, -29))); // ldrsb x8, [x6], -29
368 __ ldrsh(r24, Address(__ post(r23, 4))); // ldrsh x24, [x23], 4
369 __ ldrshw(r17, Address(__ post(r16, 0))); // ldrsh w17, [x16], 0
370 __ ldrsw(r0, Address(__ post(r20, -8))); // ldrsw x0, [x20], -8
371 __ ldrd(v20, Address(__ post(r2, -126))); // ldr d20, [x2], -126
372 __ ldrs(v19, Address(__ post(r30, -104))); // ldr s19, [x30], -104
373 __ strd(v4, Address(__ post(r17, 118))); // str d4, [x17], 118
374 __ strs(v21, Address(__ post(r19, -112))); // str s21, [x19], -112
375
376 // base_plus_reg
377 // LoadStoreOp
378 __ str(r26, Address(r2, r19, Address::lsl(3))); // str x26, [x2, x19, lsl #3]
379 __ strw(r9, Address(r0, r15, Address::sxtw(2))); // str w9, [x0, w15, sxtw #2]
380 __ strb(r26, Address(r12, r1, Address::lsl(0))); // strb w26, [x12, x1, lsl #0]
381 __ strh(r21, Address(r11, r10, Address::lsl(1))); // strh w21, [x11, x10, lsl #1]
382 __ ldr(r16, Address(r23, r16, Address::sxtx(0))); // ldr x16, [x23, x16, sxtx #0]
383 __ ldrw(r10, Address(r11, r17, Address::sxtw(2))); // ldr w10, [x11, w17, sxtw #2]
384 __ ldrb(r13, Address(r23, r11, Address::lsl(0))); // ldrb w13, [x23, x11, lsl #0]
385 __ ldrh(r27, Address(r4, r21, Address::lsl(0))); // ldrh w27, [x4, x21, lsl #0]
386 __ ldrsb(r26, Address(r8, r15, Address::sxtw(0))); // ldrsb x26, [x8, w15, sxtw #0]
387 __ ldrsh(r21, Address(r10, r2, Address::sxtw(0))); // ldrsh x21, [x10, w2, sxtw #0]
388 __ ldrshw(r8, Address(r30, r14, Address::lsl(0))); // ldrsh w8, [x30, x14, lsl #0]
389 __ ldrsw(r29, Address(r14, r20, Address::sxtx(2))); // ldrsw x29, [x14, x20, sxtx #2]
390 __ ldrd(v30, Address(r27, r22, Address::sxtx(0))); // ldr d30, [x27, x22, sxtx #0]
391 __ ldrs(v13, Address(r9, r22, Address::lsl(0))); // ldr s13, [x9, x22, lsl #0]
392 __ strd(v8, Address(r25, r17, Address::sxtw(3))); // str d8, [x25, w17, sxtw #3]
393 __ strs(v1, Address(r24, r5, Address::uxtw(2))); // str s1, [x24, w5, uxtw #2]
394
395 // base_plus_scaled_offset
396 // LoadStoreOp
397 __ str(r10, Address(r21, 14496)); // str x10, [x21, 14496]
398 __ strw(r18, Address(r29, 7228)); // str w18, [x29, 7228]
399 __ strb(r23, Address(r3, 2018)); // strb w23, [x3, 2018]
400 __ strh(r28, Address(r11, 3428)); // strh w28, [x11, 3428]
401 __ ldr(r24, Address(r26, 14376)); // ldr x24, [x26, 14376]
402 __ ldrw(r21, Address(r2, 6972)); // ldr w21, [x2, 6972]
403 __ ldrb(r4, Address(r5, 1848)); // ldrb w4, [x5, 1848]
404 __ ldrh(r14, Address(r14, 3112)); // ldrh w14, [x14, 3112]
405 __ ldrsb(r4, Address(r27, 1959)); // ldrsb x4, [x27, 1959]
406 __ ldrsh(r4, Address(r27, 3226)); // ldrsh x4, [x27, 3226]
407 __ ldrshw(r10, Address(r28, 3286)); // ldrsh w10, [x28, 3286]
408 __ ldrsw(r10, Address(r17, 7912)); // ldrsw x10, [x17, 7912]
409 __ ldrd(v13, Address(r28, 13400)); // ldr d13, [x28, 13400]
410 __ ldrs(v24, Address(r3, 7596)); // ldr s24, [x3, 7596]
411 __ strd(v2, Address(r12, 15360)); // str d2, [x12, 15360]
412 __ strs(v17, Address(r1, 6492)); // str s17, [x1, 6492]
413
414 // pcrel
415 // LoadStoreOp
416 __ ldr(r16, __ pc()); // ldr x16, .
417 __ ldrw(r13, __ pc()); // ldr w13, .
418
419 // LoadStoreOp
420 __ prfm(Address(r18, -127)); // prfm PLDL1KEEP, [x18, -127]
421
422 // LoadStoreOp
423 __ prfm(back); // prfm PLDL1KEEP, back
424
425 // LoadStoreOp
426 __ prfm(Address(r20, r2, Address::lsl(3))); // prfm PLDL1KEEP, [x20, x2, lsl #3]
427
428 // LoadStoreOp
429 __ prfm(Address(r9, 13808)); // prfm PLDL1KEEP, [x9, 13808]
430
431 // AddSubCarryOp
432 __ adcw(r8, r23, r2); // adc w8, w23, w2
433 __ adcsw(r24, r3, r19); // adcs w24, w3, w19
434 __ sbcw(r22, r24, r29); // sbc w22, w24, w29
435 __ sbcsw(r12, r27, r3); // sbcs w12, w27, w3
436 __ adc(r11, r23, r1); // adc x11, x23, x1
437 __ adcs(r29, r5, r23); // adcs x29, x5, x23
438 __ sbc(r9, r25, r12); // sbc x9, x25, x12
439 __ sbcs(r12, r0, r22); // sbcs x12, x0, x22
440
441 // AddSubExtendedOp
442 __ addw(r26, r12, r3, ext::uxtw, 1); // add w26, w12, w3, uxtw #1
443 __ addsw(r20, r16, r18, ext::sxtb, 2); // adds w20, w16, w18, sxtb #2
444 __ sub(r30, r30, r7, ext::uxtw, 2); // sub x30, x30, x7, uxtw #2
445 __ subsw(r11, r21, r2, ext::uxth, 3); // subs w11, w21, w2, uxth #3
446 __ add(r2, r26, r1, ext::uxtw, 2); // add x2, x26, x1, uxtw #2
447 __ adds(r18, r29, r20, ext::sxth, 1); // adds x18, x29, x20, sxth #1
448 __ sub(r14, r16, r4, ext::uxtw, 4); // sub x14, x16, x4, uxtw #4
449 __ subs(r0, r17, r23, ext::sxtb, 3); // subs x0, x17, x23, sxtb #3
450
451 // ConditionalCompareOp
452 __ ccmnw(r20, r22, 3u, Assembler::PL); // ccmn w20, w22, #3, PL
453 __ ccmpw(r25, r2, 1u, Assembler::EQ); // ccmp w25, w2, #1, EQ
454 __ ccmn(r18, r24, 7u, Assembler::GT); // ccmn x18, x24, #7, GT
455 __ ccmp(r8, r13, 6u, Assembler::PL); // ccmp x8, x13, #6, PL
456
457 // ConditionalCompareImmedOp
458 __ ccmnw(r9, 2, 4, Assembler::VS); // ccmn w9, #2, #4, VS
459 __ ccmpw(r2, 27, 7, Assembler::EQ); // ccmp w2, #27, #7, EQ
460 __ ccmn(r16, 1, 2, Assembler::CC); // ccmn x16, #1, #2, CC
461 __ ccmp(r17, 31, 3, Assembler::LT); // ccmp x17, #31, #3, LT
462
463 // ConditionalSelectOp
464 __ cselw(r23, r27, r23, Assembler::LS); // csel w23, w27, w23, LS
465 __ csincw(r10, r0, r6, Assembler::VS); // csinc w10, w0, w6, VS
466 __ csinvw(r11, r0, r9, Assembler::CC); // csinv w11, w0, w9, CC
467 __ csnegw(r17, r27, r18, Assembler::LO); // csneg w17, w27, w18, LO
468 __ csel(r12, r16, r11, Assembler::VC); // csel x12, x16, x11, VC
469 __ csinc(r6, r28, r6, Assembler::HI); // csinc x6, x28, x6, HI
470 __ csinv(r13, r27, r26, Assembler::VC); // csinv x13, x27, x26, VC
471 __ csneg(r29, r22, r18, Assembler::PL); // csneg x29, x22, x18, PL
472
473 // TwoRegOp
474 __ rbitw(r12, r19); // rbit w12, w19
475 __ rev16w(r23, r18); // rev16 w23, w18
476 __ revw(r9, r28); // rev w9, w28
477 __ clzw(r2, r19); // clz w2, w19
478 __ clsw(r25, r29); // cls w25, w29
479 __ rbit(r4, r23); // rbit x4, x23
480 __ rev16(r29, r18); // rev16 x29, x18
481 __ rev32(r7, r8); // rev32 x7, x8
482 __ rev(r13, r17); // rev x13, x17
483 __ clz(r17, r0); // clz x17, x0
484 __ cls(r18, r26); // cls x18, x26
485
486 // ThreeRegOp
487 __ udivw(r11, r12, r16); // udiv w11, w12, w16
488 __ sdivw(r4, r9, r7); // sdiv w4, w9, w7
489 __ lslvw(r12, r7, r16); // lslv w12, w7, w16
490 __ lsrvw(r19, r16, r23); // lsrv w19, w16, w23
491 __ asrvw(r7, r4, r6); // asrv w7, w4, w6
492 __ rorvw(r21, r20, r23); // rorv w21, w20, w23
493 __ udiv(r16, r12, r28); // udiv x16, x12, x28
494 __ sdiv(r4, r12, r13); // sdiv x4, x12, x13
495 __ lslv(r9, r13, r7); // lslv x9, x13, x7
496 __ lsrv(r28, r27, r15); // lsrv x28, x27, x15
497 __ asrv(r20, r30, r14); // asrv x20, x30, x14
498 __ rorv(r14, r18, r30); // rorv x14, x18, x30
499 __ umulh(r3, r11, r7); // umulh x3, x11, x7
500 __ smulh(r23, r20, r24); // smulh x23, x20, x24
501
502 // FourRegMulOp
503 __ maddw(r2, r5, r21, r9); // madd w2, w5, w21, w9
504 __ msubw(r24, r24, r4, r8); // msub w24, w24, w4, w8
505 __ madd(r11, r12, r15, r19); // madd x11, x12, x15, x19
506 __ msub(r29, r25, r12, r25); // msub x29, x25, x12, x25
507 __ smaddl(r17, r11, r12, r22); // smaddl x17, w11, w12, x22
508 __ smsubl(r28, r3, r20, r18); // smsubl x28, w3, w20, x18
509 __ umaddl(r7, r4, r28, r26); // umaddl x7, w4, w28, x26
510 __ umsubl(r22, r10, r17, r5); // umsubl x22, w10, w17, x5
511
512 // ThreeRegFloatOp
513 __ fmuls(v17, v3, v17); // fmul s17, s3, s17
514 __ fdivs(v11, v17, v6); // fdiv s11, s17, s6
515 __ fadds(v29, v7, v9); // fadd s29, s7, s9
516 __ fsubs(v7, v12, v19); // fsub s7, s12, s19
517 __ fmuls(v0, v23, v3); // fmul s0, s23, s3
518 __ fmuld(v26, v3, v21); // fmul d26, d3, d21
519 __ fdivd(v0, v19, v5); // fdiv d0, d19, d5
520 __ faddd(v0, v26, v9); // fadd d0, d26, d9
521 __ fsubd(v25, v21, v21); // fsub d25, d21, d21
522 __ fmuld(v16, v13, v19); // fmul d16, d13, d19
523
524 // FourRegFloatOp
525 __ fmadds(v29, v18, v0, v16); // fmadd s29, s18, s0, s16
526 __ fmsubs(v23, v13, v29, v5); // fmsub s23, s13, s29, s5
527 __ fnmadds(v9, v7, v10, v14); // fnmadd s9, s7, s10, s14
528 __ fnmadds(v25, v28, v15, v23); // fnmadd s25, s28, s15, s23
529 __ fmaddd(v6, v13, v21, v17); // fmadd d6, d13, d21, d17
530 __ fmsubd(v3, v21, v2, v7); // fmsub d3, d21, d2, d7
531 __ fnmaddd(v10, v25, v5, v17); // fnmadd d10, d25, d5, d17
532 __ fnmaddd(v14, v14, v20, v18); // fnmadd d14, d14, d20, d18
533
534 // TwoRegFloatOp
535 __ fmovs(v15, v2); // fmov s15, s2
536 __ fabss(v18, v7); // fabs s18, s7
537 __ fnegs(v3, v6); // fneg s3, s6
538 __ fsqrts(v12, v1); // fsqrt s12, s1
539 __ fcvts(v9, v0); // fcvt d9, s0
540 __ fmovd(v4, v5); // fmov d4, d5
541 __ fabsd(v3, v15); // fabs d3, d15
542 __ fnegd(v17, v25); // fneg d17, d25
543 __ fsqrtd(v12, v24); // fsqrt d12, d24
544 __ fcvtd(v21, v5); // fcvt s21, d5
545
546 // FloatConvertOp
547 __ fcvtzsw(r4, v21); // fcvtzs w4, s21
548 __ fcvtzs(r27, v3); // fcvtzs x27, s3
549 __ fcvtzdw(r29, v8); // fcvtzs w29, d8
550 __ fcvtzd(r9, v21); // fcvtzs x9, d21
551 __ scvtfws(v20, r29); // scvtf s20, w29
552 __ scvtfs(v7, r8); // scvtf s7, x8
553 __ scvtfwd(v12, r21); // scvtf d12, w21
554 __ scvtfd(v16, r21); // scvtf d16, x21
555 __ fmovs(r18, v5); // fmov w18, s5
556 __ fmovd(r25, v8); // fmov x25, d8
557 __ fmovs(v18, r26); // fmov s18, w26
558 __ fmovd(v0, r11); // fmov d0, x11
559
560 // TwoRegFloatOp
561 __ fcmps(v16, v6); // fcmp s16, s6
562 __ fcmpd(v16, v29); // fcmp d16, d29
563 __ fcmps(v30, 0.0); // fcmp s30, #0.0
564 __ fcmpd(v9, 0.0); // fcmp d9, #0.0
565
566 // LoadStorePairOp
567 __ stpw(r27, r4, Address(r12, -16)); // stp w27, w4, [x12, #-16]
568 __ ldpw(r3, r9, Address(r10, 80)); // ldp w3, w9, [x10, #80]
569 __ ldpsw(r16, r3, Address(r3, 64)); // ldpsw x16, x3, [x3, #64]
570 __ stp(r10, r28, Address(r19, -192)); // stp x10, x28, [x19, #-192]
571 __ ldp(r19, r18, Address(r7, -192)); // ldp x19, x18, [x7, #-192]
572
573 // LoadStorePairOp
574 __ stpw(r10, r16, Address(__ pre(r30, 16))); // stp w10, w16, [x30, #16]!
575 __ ldpw(r2, r4, Address(__ pre(r18, -240))); // ldp w2, w4, [x18, #-240]!
576 __ ldpsw(r24, r19, Address(__ pre(r13, 48))); // ldpsw x24, x19, [x13, #48]!
577 __ stp(r17, r0, Address(__ pre(r24, 0))); // stp x17, x0, [x24, #0]!
578 __ ldp(r14, r26, Address(__ pre(r3, -192))); // ldp x14, x26, [x3, #-192]!
579
580 // LoadStorePairOp
581 __ stpw(r22, r1, Address(__ post(r0, 80))); // stp w22, w1, [x0], #80
582 __ ldpw(r18, r10, Address(__ post(r0, -16))); // ldp w18, w10, [x0], #-16
583 __ ldpsw(r24, r24, Address(__ post(r22, -16))); // ldpsw x24, x24, [x22], #-16
584 __ stp(r12, r12, Address(__ post(r4, 80))); // stp x12, x12, [x4], #80
585 __ ldp(r4, r9, Address(__ post(r19, -240))); // ldp x4, x9, [x19], #-240
586
587 // LoadStorePairOp
588 __ stnpw(r18, r26, Address(r6, -224)); // stnp w18, w26, [x6, #-224]
589 __ ldnpw(r21, r20, Address(r1, 112)); // ldnp w21, w20, [x1, #112]
590 __ stnp(r25, r29, Address(r20, -224)); // stnp x25, x29, [x20, #-224]
591 __ ldnp(r1, r5, Address(r23, 112)); // ldnp x1, x5, [x23, #112]
592
593 // LdStSIMDOp
594 __ ld1(v4, __ T8B, Address(r20)); // ld1 {v4.8B}, [x20]
595 __ ld1(v24, v25, __ T16B, Address(__ post(r10, 32))); // ld1 {v24.16B, v25.16B}, [x10], 32
596 __ ld1(v24, v25, v26, __ T1D, Address(__ post(r6, r15))); // ld1 {v24.1D, v25.1D, v26.1D}, [x6], x15
597 __ ld1(v3, v4, v5, v6, __ T8H, Address(__ post(r4, 64))); // ld1 {v3.8H, v4.8H, v5.8H, v6.8H}, [x4], 64
598 __ ld1r(v2, __ T8B, Address(r6)); // ld1r {v2.8B}, [x6]
599 __ ld1r(v13, __ T4S, Address(__ post(r14, 4))); // ld1r {v13.4S}, [x14], 4
600 __ ld1r(v15, __ T1D, Address(__ post(r21, r24))); // ld1r {v15.1D}, [x21], x24
601 __ ld2(v9, v10, __ T2D, Address(r21)); // ld2 {v9.2D, v10.2D}, [x21]
602 __ ld2(v29, v30, __ T4H, Address(__ post(r21, 16))); // ld2 {v29.4H, v30.4H}, [x21], 16
603 __ ld2r(v8, v9, __ T16B, Address(r14)); // ld2r {v8.16B, v9.16B}, [x14]
604 __ ld2r(v7, v8, __ T2S, Address(__ post(r20, 8))); // ld2r {v7.2S, v8.2S}, [x20], 8
605 __ ld2r(v28, v29, __ T2D, Address(__ post(r3, r3))); // ld2r {v28.2D, v29.2D}, [x3], x3
606 __ ld3(v27, v28, v29, __ T4S, Address(__ post(r11, r29))); // ld3 {v27.4S, v28.4S, v29.4S}, [x11], x29
607 __ ld3(v16, v17, v18, __ T2S, Address(r10)); // ld3 {v16.2S, v17.2S, v18.2S}, [x10]
608 __ ld3r(v21, v22, v23, __ T8H, Address(r12)); // ld3r {v21.8H, v22.8H, v23.8H}, [x12]
609 __ ld3r(v4, v5, v6, __ T4S, Address(__ post(r29, 12))); // ld3r {v4.4S, v5.4S, v6.4S}, [x29], 12
610 __ ld3r(v24, v25, v26, __ T1D, Address(__ post(r9, r19))); // ld3r {v24.1D, v25.1D, v26.1D}, [x9], x19
611 __ ld4(v10, v11, v12, v13, __ T8H, Address(__ post(r3, 64))); // ld4 {v10.8H, v11.8H, v12.8H, v13.8H}, [x3], 64
612 __ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r28, r9))); // ld4 {v27.8B, v28.8B, v29.8B, v30.8B}, [x28], x9
613 __ ld4r(v21, v22, v23, v24, __ T8B, Address(r30)); // ld4r {v21.8B, v22.8B, v23.8B, v24.8B}, [x30]
614 __ ld4r(v23, v24, v25, v26, __ T4H, Address(__ post(r14, 8))); // ld4r {v23.4H, v24.4H, v25.4H, v26.4H}, [x14], 8
615 __ ld4r(v4, v5, v6, v7, __ T2S, Address(__ post(r13, r20))); // ld4r {v4.2S, v5.2S, v6.2S, v7.2S}, [x13], x20
616
617 // SpecialCases
618 __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE
619 __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ
620 __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE
621 __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT
622 __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0
623 __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp]
624 __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3]
625 __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5]
626 __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]
627 __ dup(v0, __ T16B, zr); // dup v0.16b, wzr
628 __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr
629 __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr
630 __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr
631 __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr
632 __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0
633
634 // FloatImmediateOp
635 __ fmovd(v0, 2.0); // fmov d0, #2.0
636 __ fmovd(v0, 2.125); // fmov d0, #2.125
637 __ fmovd(v0, 4.0); // fmov d0, #4.0
638 __ fmovd(v0, 4.25); // fmov d0, #4.25
639 __ fmovd(v0, 8.0); // fmov d0, #8.0
640 __ fmovd(v0, 8.5); // fmov d0, #8.5
641 __ fmovd(v0, 16.0); // fmov d0, #16.0
642 __ fmovd(v0, 17.0); // fmov d0, #17.0
643 __ fmovd(v0, 0.125); // fmov d0, #0.125
644 __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
645 __ fmovd(v0, 0.25); // fmov d0, #0.25
646 __ fmovd(v0, 0.265625); // fmov d0, #0.265625
647 __ fmovd(v0, 0.5); // fmov d0, #0.5
648 __ fmovd(v0, 0.53125); // fmov d0, #0.53125
649 __ fmovd(v0, 1.0); // fmov d0, #1.0
650 __ fmovd(v0, 1.0625); // fmov d0, #1.0625
651 __ fmovd(v0, -2.0); // fmov d0, #-2.0
652 __ fmovd(v0, -2.125); // fmov d0, #-2.125
653 __ fmovd(v0, -4.0); // fmov d0, #-4.0
654 __ fmovd(v0, -4.25); // fmov d0, #-4.25
655 __ fmovd(v0, -8.0); // fmov d0, #-8.0
656 __ fmovd(v0, -8.5); // fmov d0, #-8.5
657 __ fmovd(v0, -16.0); // fmov d0, #-16.0
658 __ fmovd(v0, -17.0); // fmov d0, #-17.0
659 __ fmovd(v0, -0.125); // fmov d0, #-0.125
660 __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
661 __ fmovd(v0, -0.25); // fmov d0, #-0.25
662 __ fmovd(v0, -0.265625); // fmov d0, #-0.265625
663 __ fmovd(v0, -0.5); // fmov d0, #-0.5
664 __ fmovd(v0, -0.53125); // fmov d0, #-0.53125
665 __ fmovd(v0, -1.0); // fmov d0, #-1.0
666 __ fmovd(v0, -1.0625); // fmov d0, #-1.0625
667
668 // LSEOp
669 __ swp(Assembler::xword, r21, r5, r24); // swp x21, x5, [x24]
670 __ ldadd(Assembler::xword, r13, r13, r15); // ldadd x13, x13, [x15]
671 __ ldbic(Assembler::xword, r22, r19, r26); // ldclr x22, x19, [x26]
672 __ ldeor(Assembler::xword, r25, r10, r26); // ldeor x25, x10, [x26]
673 __ ldorr(Assembler::xword, r5, r27, r15); // ldset x5, x27, [x15]
674 __ ldsmin(Assembler::xword, r19, r5, r11); // ldsmin x19, x5, [x11]
675 __ ldsmax(Assembler::xword, r26, r0, r4); // ldsmax x26, x0, [x4]
676 __ ldumin(Assembler::xword, r22, r23, r30); // ldumin x22, x23, [x30]
677 __ ldumax(Assembler::xword, r18, r28, r8); // ldumax x18, x28, [x8]
678
679 // LSEOp
680 __ swpa(Assembler::xword, r13, r29, r27); // swpa x13, x29, [x27]
681 __ ldadda(Assembler::xword, r11, r5, r13); // ldadda x11, x5, [x13]
682 __ ldbica(Assembler::xword, r1, r24, r21); // ldclra x1, x24, [x21]
683 __ ldeora(Assembler::xword, r27, r17, r24); // ldeora x27, x17, [x24]
684 __ ldorra(Assembler::xword, r18, r30, r5); // ldseta x18, x30, [x5]
685 __ ldsmina(Assembler::xword, r7, r22, r25); // ldsmina x7, x22, [x25]
686 __ ldsmaxa(Assembler::xword, r4, r26, r19); // ldsmaxa x4, x26, [x19]
687 __ ldumina(Assembler::xword, r6, r30, r3); // ldumina x6, x30, [x3]
688 __ ldumaxa(Assembler::xword, r24, r23, r5); // ldumaxa x24, x23, [x5]
689
690 // LSEOp
691 __ swpal(Assembler::xword, r24, r18, r28); // swpal x24, x18, [x28]
692 __ ldaddal(Assembler::xword, r19, zr, r7); // ldaddal x19, xzr, [x7]
693 __ ldbical(Assembler::xword, r13, r6, r28); // ldclral x13, x6, [x28]
694 __ ldeoral(Assembler::xword, r8, r15, r21); // ldeoral x8, x15, [x21]
695 __ ldorral(Assembler::xword, r2, r13, r1); // ldsetal x2, x13, [x1]
696 __ ldsminal(Assembler::xword, r17, r29, r25); // ldsminal x17, x29, [x25]
697 __ ldsmaxal(Assembler::xword, r25, r18, r14); // ldsmaxal x25, x18, [x14]
698 __ lduminal(Assembler::xword, zr, r6, r27); // lduminal xzr, x6, [x27]
699 __ ldumaxal(Assembler::xword, r16, r5, r15); // ldumaxal x16, x5, [x15]
700
701 // LSEOp
702 __ swpl(Assembler::xword, r11, r18, r3); // swpl x11, x18, [x3]
703 __ ldaddl(Assembler::xword, r26, r20, r2); // ldaddl x26, x20, [x2]
704 __ ldbicl(Assembler::xword, r11, r4, r11); // ldclrl x11, x4, [x11]
705 __ ldeorl(Assembler::xword, r30, r19, r23); // ldeorl x30, x19, [x23]
706 __ ldorrl(Assembler::xword, r3, r15, r14); // ldsetl x3, x15, [x14]
707 __ ldsminl(Assembler::xword, r30, r22, r20); // ldsminl x30, x22, [x20]
708 __ ldsmaxl(Assembler::xword, r7, r5, r24); // ldsmaxl x7, x5, [x24]
709 __ lduminl(Assembler::xword, r23, r16, r15); // lduminl x23, x16, [x15]
710 __ ldumaxl(Assembler::xword, r11, r19, r0); // ldumaxl x11, x19, [x0]
711
712 // LSEOp
713 __ swp(Assembler::word, r28, r28, r1); // swp w28, w28, [x1]
714 __ ldadd(Assembler::word, r11, r21, r12); // ldadd w11, w21, [x12]
715 __ ldbic(Assembler::word, r29, r0, r18); // ldclr w29, w0, [x18]
716 __ ldeor(Assembler::word, r5, r0, r25); // ldeor w5, w0, [x25]
717 __ ldorr(Assembler::word, r14, r0, r26); // ldset w14, w0, [x26]
718 __ ldsmin(Assembler::word, r28, r18, r29); // ldsmin w28, w18, [x29]
719 __ ldsmax(Assembler::word, r15, r1, r29); // ldsmax w15, w1, [x29]
720 __ ldumin(Assembler::word, r8, r26, r28); // ldumin w8, w26, [x28]
721 __ ldumax(Assembler::word, r17, r14, r4); // ldumax w17, w14, [x4]
722
723 // LSEOp
724 __ swpa(Assembler::word, r24, r25, r1); // swpa w24, w25, [x1]
725 __ ldadda(Assembler::word, r10, r17, r17); // ldadda w10, w17, [x17]
726 __ ldbica(Assembler::word, r29, r20, r21); // ldclra w29, w20, [x21]
727 __ ldeora(Assembler::word, r29, r9, r12); // ldeora w29, w9, [x12]
728 __ ldorra(Assembler::word, r11, r6, r5); // ldseta w11, w6, [x5]
729 __ ldsmina(Assembler::word, r21, r7, r21); // ldsmina w21, w7, [x21]
730 __ ldsmaxa(Assembler::word, r10, r23, r12); // ldsmaxa w10, w23, [x12]
731 __ ldumina(Assembler::word, r21, r5, r10); // ldumina w21, w5, [x10]
732 __ ldumaxa(Assembler::word, r30, r20, r18); // ldumaxa w30, w20, [x18]
733
734 // LSEOp
735 __ swpal(Assembler::word, r13, r23, r5); // swpal w13, w23, [x5]
736 __ ldaddal(Assembler::word, r15, r24, r5); // ldaddal w15, w24, [x5]
737 __ ldbical(Assembler::word, r9, r10, r25); // ldclral w9, w10, [x25]
738 __ ldeoral(Assembler::word, r20, r17, r17); // ldeoral w20, w17, [x17]
739 __ ldorral(Assembler::word, r12, r18, r30); // ldsetal w12, w18, [x30]
740 __ ldsminal(Assembler::word, r3, r3, r25); // ldsminal w3, w3, [x25]
741 __ ldsmaxal(Assembler::word, r26, r25, r10); // ldsmaxal w26, w25, [x10]
742 __ lduminal(Assembler::word, r2, r11, sp); // lduminal w2, w11, [sp]
743 __ ldumaxal(Assembler::word, r7, r2, r5); // ldumaxal w7, w2, [x5]
744
745 // LSEOp
746 __ swpl(Assembler::word, r0, r7, r20); // swpl w0, w7, [x20]
747 __ ldaddl(Assembler::word, r5, zr, r2); // ldaddl w5, wzr, [x2]
748 __ ldbicl(Assembler::word, r27, r25, r27); // ldclrl w27, w25, [x27]
749 __ ldeorl(Assembler::word, r30, r24, r26); // ldeorl w30, w24, [x26]
750 __ ldorrl(Assembler::word, r15, r2, r22); // ldsetl w15, w2, [x22]
751 __ ldsminl(Assembler::word, r0, r3, sp); // ldsminl w0, w3, [sp]
752 __ ldsmaxl(Assembler::word, r15, r20, r10); // ldsmaxl w15, w20, [x10]
753 __ lduminl(Assembler::word, r22, r21, r14); // lduminl w22, w21, [x14]
754 __ ldumaxl(Assembler::word, r6, r30, r2); // ldumaxl w6, w30, [x2]
755
756 __ bind(forth);
757
758 /*
759 aarch64ops.o: file format elf64-littleaarch64
760
761
762 Disassembly of section .text:
763
764 0000000000000000 <back>:
765 0: 8b50798f add x15, x12, x16, lsr #30
766 4: cb4381e1 sub x1, x15, x3, lsr #32
767 8: ab05372d adds x13, x25, x5, lsl #13
768 c: eb864796 subs x22, x28, x6, asr #17
769 10: 0b961920 add w0, w9, w22, asr #6
770 14: 4b195473 sub w19, w3, w25, lsl #21
771 18: 2b0b5264 adds w4, w19, w11, lsl #20
772 1c: 6b9300f8 subs w24, w7, w19, asr #0
773 20: 8a0bc0fe and x30, x7, x11, lsl #48
774 24: aa0f3118 orr x24, x8, x15, lsl #12
775 28: ca170531 eor x17, x9, x23, lsl #1
776 2c: ea44dd6e ands x14, x11, x4, lsr #55
777 30: 0a4c44f3 and w19, w7, w12, lsr #17
778 34: 2a8b7373 orr w19, w27, w11, asr #28
779 38: 4a567c7e eor w30, w3, w22, lsr #31
780 3c: 6a9c0353 ands w19, w26, w28, asr #0
781 40: 8a3accdd bic x29, x6, x26, lsl #51
782 44: aa318f7a orn x26, x27, x17, lsl #35
783 48: ca2e1495 eon x21, x4, x14, lsl #5
784 4c: eaa015e2 bics x2, x15, x0, asr #5
785 50: 0a2274e2 bic w2, w7, w2, lsl #29
786 54: 2a751598 orn w24, w12, w21, lsr #5
787 58: 4a3309fe eon w30, w15, w19, lsl #2
788 5c: 6ab172fe bics w30, w23, w17, asr #28
789 60: 110a5284 add w4, w20, #0x294
790 64: 310b1942 adds w2, w10, #0x2c6
791 68: 5103d353 sub w19, w26, #0xf4
792 6c: 710125bc subs w28, w13, #0x49
793 70: 910d7bc2 add x2, x30, #0x35e
794 74: b108fa1b adds x27, x16, #0x23e
795 78: d1093536 sub x22, x9, #0x24d
796 7c: f10ae824 subs x4, x1, #0x2ba
797 80: 120e667c and w28, w19, #0xfffc0fff
798 84: 321f6cbb orr w27, w5, #0x1ffffffe
799 88: 520f6a9e eor w30, w20, #0xfffe0fff
800 8c: 72136f56 ands w22, w26, #0xffffe1ff
801 90: 927e4ce5 and x5, x7, #0x3ffffc
802 94: b278b4ed orr x13, x7, #0x3fffffffffff00
803 98: d24c6527 eor x7, x9, #0xfff0000000003fff
804 9c: f2485803 ands x3, x0, #0xff00000000007fff
805 a0: 14000000 b a0 <back+0xa0>
806 a4: 17ffffd7 b 0 <back>
807 a8: 140001ee b 860 <forth>
808 ac: 94000000 bl ac <back+0xac>
809 b0: 97ffffd4 bl 0 <back>
810 b4: 940001eb bl 860 <forth>
811 b8: 34000010 cbz w16, b8 <back+0xb8>
812 bc: 34fffa30 cbz w16, 0 <back>
813 c0: 34003d10 cbz w16, 860 <forth>
814 c4: 35000013 cbnz w19, c4 <back+0xc4>
815 c8: 35fff9d3 cbnz w19, 0 <back>
816 cc: 35003cb3 cbnz w19, 860 <forth>
817 d0: b4000005 cbz x5, d0 <back+0xd0>
818 d4: b4fff965 cbz x5, 0 <back>
819 d8: b4003c45 cbz x5, 860 <forth>
820 dc: b5000004 cbnz x4, dc <back+0xdc>
821 e0: b5fff904 cbnz x4, 0 <back>
822 e4: b5003be4 cbnz x4, 860 <forth>
823 e8: 1000001b adr x27, e8 <back+0xe8>
824 ec: 10fff8bb adr x27, 0 <back>
825 f0: 10003b9b adr x27, 860 <forth>
826 f4: 90000010 adrp x16, 0 <back>
827 f8: 3640001c tbz w28, #8, f8 <back+0xf8>
828 fc: 3647f83c tbz w28, #8, 0 <back>
829 100: 36403b1c tbz w28, #8, 860 <forth>
830 104: 37080001 tbnz w1, #1, 104 <back+0x104>
831 108: 370ff7c1 tbnz w1, #1, 0 <back>
832 10c: 37083aa1 tbnz w1, #1, 860 <forth>
833 110: 12a437f4 mov w20, #0xde40ffff // #-566165505
834 114: 528c9d67 mov w7, #0x64eb // #25835
835 118: 72838bb1 movk w17, #0x1c5d
836 11c: 92c1062e mov x14, #0xfffff7ceffffffff // #-9006546419713
837 120: d287da49 mov x9, #0x3ed2 // #16082
838 124: f2a6d153 movk x19, #0x368a, lsl #16
839 128: 93465ac9 sbfx x9, x22, #6, #17
840 12c: 330b0013 bfi w19, w0, #21, #1
841 130: 530b4e6a ubfx w10, w19, #11, #9
842 134: 934545e4 sbfx x4, x15, #5, #13
843 138: b35370a3 bfxil x3, x5, #19, #10
844 13c: d3510b8c ubfiz x12, x28, #47, #3
845 140: 13960c0f extr w15, w0, w22, #3
846 144: 93ceddc6 ror x6, x14, #55
847 148: 54000000 b.eq 148 <back+0x148> // b.none
848 14c: 54fff5a0 b.eq 0 <back> // b.none
849 150: 54003880 b.eq 860 <forth> // b.none
850 154: 54000001 b.ne 154 <back+0x154> // b.any
851 158: 54fff541 b.ne 0 <back> // b.any
852 15c: 54003821 b.ne 860 <forth> // b.any
853 160: 54000002 b.cs 160 <back+0x160> // b.hs, b.nlast
854 164: 54fff4e2 b.cs 0 <back> // b.hs, b.nlast
855 168: 540037c2 b.cs 860 <forth> // b.hs, b.nlast
856 16c: 54000002 b.cs 16c <back+0x16c> // b.hs, b.nlast
857 170: 54fff482 b.cs 0 <back> // b.hs, b.nlast
858 174: 54003762 b.cs 860 <forth> // b.hs, b.nlast
859 178: 54000003 b.cc 178 <back+0x178> // b.lo, b.ul, b.last
860 17c: 54fff423 b.cc 0 <back> // b.lo, b.ul, b.last
861 180: 54003703 b.cc 860 <forth> // b.lo, b.ul, b.last
862 184: 54000003 b.cc 184 <back+0x184> // b.lo, b.ul, b.last
863 188: 54fff3c3 b.cc 0 <back> // b.lo, b.ul, b.last
864 18c: 540036a3 b.cc 860 <forth> // b.lo, b.ul, b.last
865 190: 54000004 b.mi 190 <back+0x190> // b.first
866 194: 54fff364 b.mi 0 <back> // b.first
867 198: 54003644 b.mi 860 <forth> // b.first
868 19c: 54000005 b.pl 19c <back+0x19c> // b.nfrst
869 1a0: 54fff305 b.pl 0 <back> // b.nfrst
870 1a4: 540035e5 b.pl 860 <forth> // b.nfrst
871 1a8: 54000006 b.vs 1a8 <back+0x1a8>
872 1ac: 54fff2a6 b.vs 0 <back>
873 1b0: 54003586 b.vs 860 <forth>
874 1b4: 54000007 b.vc 1b4 <back+0x1b4>
875 1b8: 54fff247 b.vc 0 <back>
876 1bc: 54003527 b.vc 860 <forth>
877 1c0: 54000008 b.hi 1c0 <back+0x1c0> // b.pmore
878 1c4: 54fff1e8 b.hi 0 <back> // b.pmore
879 1c8: 540034c8 b.hi 860 <forth> // b.pmore
880 1cc: 54000009 b.ls 1cc <back+0x1cc> // b.plast
881 1d0: 54fff189 b.ls 0 <back> // b.plast
882 1d4: 54003469 b.ls 860 <forth> // b.plast
883 1d8: 5400000a b.ge 1d8 <back+0x1d8> // b.tcont
884 1dc: 54fff12a b.ge 0 <back> // b.tcont
885 1e0: 5400340a b.ge 860 <forth> // b.tcont
886 1e4: 5400000b b.lt 1e4 <back+0x1e4> // b.tstop
887 1e8: 54fff0cb b.lt 0 <back> // b.tstop
888 1ec: 540033ab b.lt 860 <forth> // b.tstop
889 1f0: 5400000c b.gt 1f0 <back+0x1f0>
890 1f4: 54fff06c b.gt 0 <back>
891 1f8: 5400334c b.gt 860 <forth>
892 1fc: 5400000d b.le 1fc <back+0x1fc>
893 200: 54fff00d b.le 0 <back>
894 204: 540032ed b.le 860 <forth>
895 208: 5400000e b.al 208 <back+0x208>
896 20c: 54ffefae b.al 0 <back>
897 210: 5400328e b.al 860 <forth>
898 214: 5400000f b.nv 214 <back+0x214>
899 218: 54ffef4f b.nv 0 <back>
900 21c: 5400322f b.nv 860 <forth>
901 220: d40ac601 svc #0x5630
902 224: d40042a2 hvc #0x215
903 228: d404dac3 smc #0x26d6
904 22c: d4224d40 brk #0x126a
905 230: d44219c0 hlt #0x10ce
906 234: d503201f nop
907 238: d69f03e0 eret
908 23c: d6bf03e0 drps
909 240: d5033fdf isb
910 244: d503339f dsb osh
911 248: d50335bf dmb nshld
912 24c: d61f0280 br x20
913 250: d63f0040 blr x2
914 254: c8127c17 stxr w18, x23, [x0]
915 258: c81efec5 stlxr w30, x5, [x22]
916 25c: c85f7d05 ldxr x5, [x8]
917 260: c85ffe14 ldaxr x20, [x16]
918 264: c89ffd66 stlr x6, [x11]
919 268: c8dfff66 ldar x6, [x27]
920 26c: 880a7cb1 stxr w10, w17, [x5]
921 270: 8816fd89 stlxr w22, w9, [x12]
922 274: 885f7d1b ldxr w27, [x8]
923 278: 885ffc57 ldaxr w23, [x2]
924 27c: 889fffba stlr w26, [x29]
925 280: 88dffd4d ldar w13, [x10]
926 284: 48197f7c stxrh w25, w28, [x27]
927 288: 481dfd96 stlxrh w29, w22, [x12]
928 28c: 485f7f96 ldxrh w22, [x28]
929 290: 485fffc3 ldaxrh w3, [x30]
930 294: 489ffdf8 stlrh w24, [x15]
931 298: 48dfff5b ldarh w27, [x26]
932 29c: 080b7e6a stxrb w11, w10, [x19]
933 2a0: 0817fedb stlxrb w23, w27, [x22]
934 2a4: 085f7e18 ldxrb w24, [x16]
935 2a8: 085ffc38 ldaxrb w24, [x1]
936 2ac: 089fffa5 stlrb w5, [x29]
937 2b0: 08dffe18 ldarb w24, [x16]
938 2b4: c87f6239 ldxp x25, x24, [x17]
939 2b8: c87fb276 ldaxp x22, x12, [x19]
940 2bc: c820573a stxp w0, x26, x21, [x25]
941 2c0: c821aca6 stlxp w1, x6, x11, [x5]
942 2c4: 887f388d ldxp w13, w14, [x4]
943 2c8: 887f88d1 ldaxp w17, w2, [x6]
944 2cc: 882f2643 stxp w15, w3, w9, [x18]
945 2d0: 88329131 stlxp w18, w17, w4, [x9]
946 2d4: f81cf2b7 stur x23, [x21, #-49]
947 2d8: b803f055 stur w21, [x2, #63]
948 2dc: 39002f9b strb w27, [x28, #11]
949 2e0: 781f31fd sturh w29, [x15, #-13]
950 2e4: f85d33ce ldur x14, [x30, #-45]
951 2e8: b843539d ldur w29, [x28, #53]
952 2ec: 39401f54 ldrb w20, [x26, #7]
953 2f0: 785ce059 ldurh w25, [x2, #-50]
954 2f4: 389f1143 ldursb x3, [x10, #-15]
955 2f8: 788131ee ldursh x14, [x15, #19]
956 2fc: 78dfb17d ldursh w29, [x11, #-5]
957 300: b89b90af ldursw x15, [x5, #-71]
958 304: fc403193 ldur d19, [x12, #3]
959 308: bc42a36c ldur s12, [x27, #42]
960 30c: fc07d396 stur d22, [x28, #125]
961 310: bc1ec1f8 stur s24, [x15, #-20]
962 314: f81e8f88 str x8, [x28, #-24]!
963 318: b8025de6 str w6, [x15, #37]!
964 31c: 38007c27 strb w7, [x1, #7]!
965 320: 7801ee20 strh w0, [x17, #30]!
966 324: f8454fb9 ldr x25, [x29, #84]!
967 328: b85cce9a ldr w26, [x20, #-52]!
968 32c: 385e7fba ldrb w26, [x29, #-25]!
969 330: 7841af24 ldrh w4, [x25, #26]!
970 334: 389ebd1c ldrsb x28, [x8, #-21]!
971 338: 789fadd1 ldrsh x17, [x14, #-6]!
972 33c: 78c0aefc ldrsh w28, [x23, #10]!
973 340: b89c0f7e ldrsw x30, [x27, #-64]!
974 344: fc50efd4 ldr d20, [x30, #-242]!
975 348: bc414f71 ldr s17, [x27, #20]!
976 34c: fc011c67 str d7, [x3, #17]!
977 350: bc1f0d6d str s13, [x11, #-16]!
978 354: f81c3526 str x6, [x9], #-61
979 358: b81e34b0 str w16, [x5], #-29
980 35c: 3800f7bd strb w29, [x29], #15
981 360: 78012684 strh w4, [x20], #18
982 364: f842e653 ldr x19, [x18], #46
983 368: b8417456 ldr w22, [x2], #23
984 36c: 385e2467 ldrb w7, [x3], #-30
985 370: 785e358b ldrh w11, [x12], #-29
986 374: 389e34c8 ldrsb x8, [x6], #-29
987 378: 788046f8 ldrsh x24, [x23], #4
988 37c: 78c00611 ldrsh w17, [x16], #0
989 380: b89f8680 ldrsw x0, [x20], #-8
990 384: fc582454 ldr d20, [x2], #-126
991 388: bc5987d3 ldr s19, [x30], #-104
992 38c: fc076624 str d4, [x17], #118
993 390: bc190675 str s21, [x19], #-112
994 394: f833785a str x26, [x2, x19, lsl #3]
995 398: b82fd809 str w9, [x0, w15, sxtw #2]
996 39c: 3821799a strb w26, [x12, x1, lsl #0]
997 3a0: 782a7975 strh w21, [x11, x10, lsl #1]
998 3a4: f870eaf0 ldr x16, [x23, x16, sxtx]
999 3a8: b871d96a ldr w10, [x11, w17, sxtw #2]
1000 3ac: 386b7aed ldrb w13, [x23, x11, lsl #0]
1001 3b0: 7875689b ldrh w27, [x4, x21]
1002 3b4: 38afd91a ldrsb x26, [x8, w15, sxtw #0]
1003 3b8: 78a2c955 ldrsh x21, [x10, w2, sxtw]
1004 3bc: 78ee6bc8 ldrsh w8, [x30, x14]
1005 3c0: b8b4f9dd ldrsw x29, [x14, x20, sxtx #2]
1006 3c4: fc76eb7e ldr d30, [x27, x22, sxtx]
1007 3c8: bc76692d ldr s13, [x9, x22]
1008 3cc: fc31db28 str d8, [x25, w17, sxtw #3]
1009 3d0: bc255b01 str s1, [x24, w5, uxtw #2]
1010 3d4: f91c52aa str x10, [x21, #14496]
1011 3d8: b91c3fb2 str w18, [x29, #7228]
1012 3dc: 391f8877 strb w23, [x3, #2018]
1013 3e0: 791ac97c strh w28, [x11, #3428]
1014 3e4: f95c1758 ldr x24, [x26, #14376]
1015 3e8: b95b3c55 ldr w21, [x2, #6972]
1016 3ec: 395ce0a4 ldrb w4, [x5, #1848]
1017 3f0: 795851ce ldrh w14, [x14, #3112]
1018 3f4: 399e9f64 ldrsb x4, [x27, #1959]
1019 3f8: 79993764 ldrsh x4, [x27, #3226]
1020 3fc: 79d9af8a ldrsh w10, [x28, #3286]
1021 400: b99eea2a ldrsw x10, [x17, #7912]
1022 404: fd5a2f8d ldr d13, [x28, #13400]
1023 408: bd5dac78 ldr s24, [x3, #7596]
1024 40c: fd1e0182 str d2, [x12, #15360]
1025 410: bd195c31 str s17, [x1, #6492]
1026 414: 58000010 ldr x16, 414 <back+0x414>
1027 418: 1800000d ldr w13, 418 <back+0x418>
1028 41c: f8981240 prfum pldl1keep, [x18, #-127]
1029 420: d8ffdf00 prfm pldl1keep, 0 <back>
1030 424: f8a27a80 prfm pldl1keep, [x20, x2, lsl #3]
1031 428: f99af920 prfm pldl1keep, [x9, #13808]
1032 42c: 1a0202e8 adc w8, w23, w2
1033 430: 3a130078 adcs w24, w3, w19
1034 434: 5a1d0316 sbc w22, w24, w29
1035 438: 7a03036c sbcs w12, w27, w3
1036 43c: 9a0102eb adc x11, x23, x1
1037 440: ba1700bd adcs x29, x5, x23
1038 444: da0c0329 sbc x9, x25, x12
1039 448: fa16000c sbcs x12, x0, x22
1040 44c: 0b23459a add w26, w12, w3, uxtw #1
1041 450: 2b328a14 adds w20, w16, w18, sxtb #2
1042 454: cb274bde sub x30, x30, w7, uxtw #2
1043 458: 6b222eab subs w11, w21, w2, uxth #3
1044 45c: 8b214b42 add x2, x26, w1, uxtw #2
1045 460: ab34a7b2 adds x18, x29, w20, sxth #1
1046 464: cb24520e sub x14, x16, w4, uxtw #4
1047 468: eb378e20 subs x0, x17, w23, sxtb #3
1048 46c: 3a565283 ccmn w20, w22, #0x3, pl // pl = nfrst
1049 470: 7a420321 ccmp w25, w2, #0x1, eq // eq = none
1050 474: ba58c247 ccmn x18, x24, #0x7, gt
1051 478: fa4d5106 ccmp x8, x13, #0x6, pl // pl = nfrst
1052 47c: 3a426924 ccmn w9, #0x2, #0x4, vs
1053 480: 7a5b0847 ccmp w2, #0x1b, #0x7, eq // eq = none
1054 484: ba413a02 ccmn x16, #0x1, #0x2, cc // cc = lo, ul, last
1055 488: fa5fba23 ccmp x17, #0x1f, #0x3, lt // lt = tstop
1056 48c: 1a979377 csel w23, w27, w23, ls // ls = plast
1057 490: 1a86640a csinc w10, w0, w6, vs
1058 494: 5a89300b csinv w11, w0, w9, cc // cc = lo, ul, last
1059 498: 5a923771 csneg w17, w27, w18, cc // cc = lo, ul, last
1060 49c: 9a8b720c csel x12, x16, x11, vc
1061 4a0: 9a868786 csinc x6, x28, x6, hi // hi = pmore
1062 4a4: da9a736d csinv x13, x27, x26, vc
1063 4a8: da9256dd csneg x29, x22, x18, pl // pl = nfrst
1064 4ac: 5ac0026c rbit w12, w19
1065 4b0: 5ac00657 rev16 w23, w18
1066 4b4: 5ac00b89 rev w9, w28
1067 4b8: 5ac01262 clz w2, w19
1068 4bc: 5ac017b9 cls w25, w29
1069 4c0: dac002e4 rbit x4, x23
1070 4c4: dac0065d rev16 x29, x18
1071 4c8: dac00907 rev32 x7, x8
1072 4cc: dac00e2d rev x13, x17
1073 4d0: dac01011 clz x17, x0
1074 4d4: dac01752 cls x18, x26
1075 4d8: 1ad0098b udiv w11, w12, w16
1076 4dc: 1ac70d24 sdiv w4, w9, w7
1077 4e0: 1ad020ec lsl w12, w7, w16
1078 4e4: 1ad72613 lsr w19, w16, w23
1079 4e8: 1ac62887 asr w7, w4, w6
1080 4ec: 1ad72e95 ror w21, w20, w23
1081 4f0: 9adc0990 udiv x16, x12, x28
1082 4f4: 9acd0d84 sdiv x4, x12, x13
1083 4f8: 9ac721a9 lsl x9, x13, x7
1084 4fc: 9acf277c lsr x28, x27, x15
1085 500: 9ace2bd4 asr x20, x30, x14
1086 504: 9ade2e4e ror x14, x18, x30
1087 508: 9bc77d63 umulh x3, x11, x7
1088 50c: 9b587e97 smulh x23, x20, x24
1089 510: 1b1524a2 madd w2, w5, w21, w9
1090 514: 1b04a318 msub w24, w24, w4, w8
1091 518: 9b0f4d8b madd x11, x12, x15, x19
1092 51c: 9b0ce73d msub x29, x25, x12, x25
1093 520: 9b2c5971 smaddl x17, w11, w12, x22
1094 524: 9b34c87c smsubl x28, w3, w20, x18
1095 528: 9bbc6887 umaddl x7, w4, w28, x26
1096 52c: 9bb19556 umsubl x22, w10, w17, x5
1097 530: 1e310871 fmul s17, s3, s17
1098 534: 1e261a2b fdiv s11, s17, s6
1099 538: 1e2928fd fadd s29, s7, s9
1100 53c: 1e333987 fsub s7, s12, s19
1101 540: 1e230ae0 fmul s0, s23, s3
1102 544: 1e75087a fmul d26, d3, d21
1103 548: 1e651a60 fdiv d0, d19, d5
1104 54c: 1e692b40 fadd d0, d26, d9
1105 550: 1e753ab9 fsub d25, d21, d21
1106 554: 1e7309b0 fmul d16, d13, d19
1107 558: 1f00425d fmadd s29, s18, s0, s16
1108 55c: 1f1d95b7 fmsub s23, s13, s29, s5
1109 560: 1f2a38e9 fnmadd s9, s7, s10, s14
1110 564: 1f2f5f99 fnmadd s25, s28, s15, s23
1111 568: 1f5545a6 fmadd d6, d13, d21, d17
1112 56c: 1f429ea3 fmsub d3, d21, d2, d7
1113 570: 1f65472a fnmadd d10, d25, d5, d17
1114 574: 1f7449ce fnmadd d14, d14, d20, d18
1115 578: 1e20404f fmov s15, s2
1116 57c: 1e20c0f2 fabs s18, s7
1117 580: 1e2140c3 fneg s3, s6
1118 584: 1e21c02c fsqrt s12, s1
1119 588: 1e22c009 fcvt d9, s0
1120 58c: 1e6040a4 fmov d4, d5
1121 590: 1e60c1e3 fabs d3, d15
1122 594: 1e614331 fneg d17, d25
1123 598: 1e61c30c fsqrt d12, d24
1124 59c: 1e6240b5 fcvt s21, d5
1125 5a0: 1e3802a4 fcvtzs w4, s21
1126 5a4: 9e38007b fcvtzs x27, s3
1127 5a8: 1e78011d fcvtzs w29, d8
1128 5ac: 9e7802a9 fcvtzs x9, d21
1129 5b0: 1e2203b4 scvtf s20, w29
1130 5b4: 9e220107 scvtf s7, x8
1131 5b8: 1e6202ac scvtf d12, w21
1132 5bc: 9e6202b0 scvtf d16, x21
1133 5c0: 1e2600b2 fmov w18, s5
1134 5c4: 9e660119 fmov x25, d8
1135 5c8: 1e270352 fmov s18, w26
1136 5cc: 9e670160 fmov d0, x11
1137 5d0: 1e262200 fcmp s16, s6
1138 5d4: 1e7d2200 fcmp d16, d29
1139 5d8: 1e2023c8 fcmp s30, #0.0
1140 5dc: 1e602128 fcmp d9, #0.0
1141 5e0: 293e119b stp w27, w4, [x12, #-16]
1142 5e4: 294a2543 ldp w3, w9, [x10, #80]
1143 5e8: 69480c70 ldpsw x16, x3, [x3, #64]
1144 5ec: a934726a stp x10, x28, [x19, #-192]
1145 5f0: a97448f3 ldp x19, x18, [x7, #-192]
1146 5f4: 298243ca stp w10, w16, [x30, #16]!
1147 5f8: 29e21242 ldp w2, w4, [x18, #-240]!
1148 5fc: 69c64db8 ldpsw x24, x19, [x13, #48]!
1149 600: a9800311 stp x17, x0, [x24, #0]!
1150 604: a9f4686e ldp x14, x26, [x3, #-192]!
1151 608: 288a0416 stp w22, w1, [x0], #80
1152 60c: 28fe2812 ldp w18, w10, [x0], #-16
1153 610: 68fe62d8 .inst 0x68fe62d8 ; undefined
1154 614: a885308c stp x12, x12, [x4], #80
1155 618: a8f12664 ldp x4, x9, [x19], #-240
1156 61c: 282468d2 stnp w18, w26, [x6, #-224]
1157 620: 284e5035 ldnp w21, w20, [x1, #112]
1158 624: a8327699 stnp x25, x29, [x20, #-224]
1159 628: a84716e1 ldnp x1, x5, [x23, #112]
1160 62c: 0c407284 ld1 {v4.8b}, [x20]
1161 630: 4cdfa158 ld1 {v24.16b, v25.16b}, [x10], #32
1162 634: 0ccf6cd8 ld1 {v24.1d-v26.1d}, [x6], x15
1163 638: 4cdf2483 ld1 {v3.8h-v6.8h}, [x4], #64
1164 63c: 0d40c0c2 ld1r {v2.8b}, [x6]
1165 640: 4ddfc9cd ld1r {v13.4s}, [x14], #4
1166 644: 0dd8ceaf ld1r {v15.1d}, [x21], x24
1167 648: 4c408ea9 ld2 {v9.2d, v10.2d}, [x21]
1168 64c: 0cdf86bd ld2 {v29.4h, v30.4h}, [x21], #16
1169 650: 4d60c1c8 ld2r {v8.16b, v9.16b}, [x14]
1170 654: 0dffca87 ld2r {v7.2s, v8.2s}, [x20], #8
1171 658: 4de3cc7c ld2r {v28.2d, v29.2d}, [x3], x3
1172 65c: 4cdd497b ld3 {v27.4s-v29.4s}, [x11], x29
1173 660: 0c404950 ld3 {v16.2s-v18.2s}, [x10]
1174 664: 4d40e595 ld3r {v21.8h-v23.8h}, [x12]
1175 668: 4ddfeba4 ld3r {v4.4s-v6.4s}, [x29], #12
1176 66c: 0dd3ed38 ld3r {v24.1d-v26.1d}, [x9], x19
1177 670: 4cdf046a ld4 {v10.8h-v13.8h}, [x3], #64
1178 674: 0cc9039b ld4 {v27.8b-v30.8b}, [x28], x9
1179 678: 0d60e3d5 ld4r {v21.8b-v24.8b}, [x30]
1180 67c: 0dffe5d7 ld4r {v23.4h-v26.4h}, [x14], #8
1181 680: 0df4e9a4 ld4r {v4.2s-v7.2s}, [x13], x20
1182 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le
1183 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none
1184 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any
1185 690: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt
1186 694: 93df03ff ror xzr, xzr, #0
1187 698: c820ffff stlxp w0, xzr, xzr, [sp]
1188 69c: 8822fc7f stlxp w2, wzr, wzr, [x3]
1189 6a0: c8247cbf stxp w4, xzr, xzr, [x5]
1190 6a4: 88267fff stxp w6, wzr, wzr, [sp]
1191 6a8: 4e010fe0 dup v0.16b, wzr
1192 6ac: 4e081fe1 mov v1.d[0], xzr
1193 6b0: 4e0c1fe1 mov v1.s[1], wzr
1194 6b4: 4e0a1fe1 mov v1.h[2], wzr
1195 6b8: 4e071fe1 mov v1.b[3], wzr
1196 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0
1197 6c0: 1e601000 fmov d0, #2.000000000000000000e+00
1198 6c4: 1e603000 fmov d0, #2.125000000000000000e+00
1199 6c8: 1e621000 fmov d0, #4.000000000000000000e+00
1200 6cc: 1e623000 fmov d0, #4.250000000000000000e+00
1201 6d0: 1e641000 fmov d0, #8.000000000000000000e+00
1202 6d4: 1e643000 fmov d0, #8.500000000000000000e+00
1203 6d8: 1e661000 fmov d0, #1.600000000000000000e+01
1204 6dc: 1e663000 fmov d0, #1.700000000000000000e+01
1205 6e0: 1e681000 fmov d0, #1.250000000000000000e-01
1206 6e4: 1e683000 fmov d0, #1.328125000000000000e-01
1207 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01
1208 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01
1209 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01
1210 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01
1211 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00
1212 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00
1213 700: 1e701000 fmov d0, #-2.000000000000000000e+00
1214 704: 1e703000 fmov d0, #-2.125000000000000000e+00
1215 708: 1e721000 fmov d0, #-4.000000000000000000e+00
1216 70c: 1e723000 fmov d0, #-4.250000000000000000e+00
1217 710: 1e741000 fmov d0, #-8.000000000000000000e+00
1218 714: 1e743000 fmov d0, #-8.500000000000000000e+00
1219 718: 1e761000 fmov d0, #-1.600000000000000000e+01
1220 71c: 1e763000 fmov d0, #-1.700000000000000000e+01
1221 720: 1e781000 fmov d0, #-1.250000000000000000e-01
1222 724: 1e783000 fmov d0, #-1.328125000000000000e-01
1223 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01
1224 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01
1225 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01
1226 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01
1227 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00
1228 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00
1229 740: f8358305 swp x21, x5, [x24]
1230 744: f82d01ed ldadd x13, x13, [x15]
1231 748: f8361353 ldclr x22, x19, [x26]
1232 74c: f839234a ldeor x25, x10, [x26]
1233 750: f82531fb ldset x5, x27, [x15]
1234 754: f8335165 ldsmin x19, x5, [x11]
1235 758: f83a4080 ldsmax x26, x0, [x4]
1236 75c: f83673d7 ldumin x22, x23, [x30]
1237 760: f832611c ldumax x18, x28, [x8]
1238 764: f8ad837d swpa x13, x29, [x27]
1239 768: f8ab01a5 ldadda x11, x5, [x13]
1240 76c: f8a112b8 ldclra x1, x24, [x21]
1241 770: f8bb2311 ldeora x27, x17, [x24]
1242 774: f8b230be ldseta x18, x30, [x5]
1243 778: f8a75336 ldsmina x7, x22, [x25]
1244 77c: f8a4427a ldsmaxa x4, x26, [x19]
1245 780: f8a6707e ldumina x6, x30, [x3]
1246 784: f8b860b7 ldumaxa x24, x23, [x5]
1247 788: f8f88392 swpal x24, x18, [x28]
1248 78c: f8f300ff ldaddal x19, xzr, [x7]
1249 790: f8ed1386 ldclral x13, x6, [x28]
1250 794: f8e822af ldeoral x8, x15, [x21]
1251 798: f8e2302d ldsetal x2, x13, [x1]
1252 79c: f8f1533d ldsminal x17, x29, [x25]
1253 7a0: f8f941d2 ldsmaxal x25, x18, [x14]
1254 7a4: f8ff7366 lduminal xzr, x6, [x27]
1255 7a8: f8f061e5 ldumaxal x16, x5, [x15]
1256 7ac: f86b8072 swpl x11, x18, [x3]
1257 7b0: f87a0054 ldaddl x26, x20, [x2]
1258 7b4: f86b1164 ldclrl x11, x4, [x11]
1259 7b8: f87e22f3 ldeorl x30, x19, [x23]
1260 7bc: f86331cf ldsetl x3, x15, [x14]
1261 7c0: f87e5296 ldsminl x30, x22, [x20]
1262 7c4: f8674305 ldsmaxl x7, x5, [x24]
1263 7c8: f87771f0 lduminl x23, x16, [x15]
1264 7cc: f86b6013 ldumaxl x11, x19, [x0]
1265 7d0: b83c803c swp w28, w28, [x1]
1266 7d4: b82b0195 ldadd w11, w21, [x12]
1267 7d8: b83d1240 ldclr w29, w0, [x18]
1268 7dc: b8252320 ldeor w5, w0, [x25]
1269 7e0: b82e3340 ldset w14, w0, [x26]
1270 7e4: b83c53b2 ldsmin w28, w18, [x29]
1271 7e8: b82f43a1 ldsmax w15, w1, [x29]
1272 7ec: b828739a ldumin w8, w26, [x28]
1273 7f0: b831608e ldumax w17, w14, [x4]
1274 7f4: b8b88039 swpa w24, w25, [x1]
1275 7f8: b8aa0231 ldadda w10, w17, [x17]
1276 7fc: b8bd12b4 ldclra w29, w20, [x21]
1277 800: b8bd2189 ldeora w29, w9, [x12]
1278 804: b8ab30a6 ldseta w11, w6, [x5]
1279 808: b8b552a7 ldsmina w21, w7, [x21]
1280 80c: b8aa4197 ldsmaxa w10, w23, [x12]
1281 810: b8b57145 ldumina w21, w5, [x10]
1282 814: b8be6254 ldumaxa w30, w20, [x18]
1283 818: b8ed80b7 swpal w13, w23, [x5]
1284 81c: b8ef00b8 ldaddal w15, w24, [x5]
1285 820: b8e9132a ldclral w9, w10, [x25]
1286 824: b8f42231 ldeoral w20, w17, [x17]
1287 828: b8ec33d2 ldsetal w12, w18, [x30]
1288 82c: b8e35323 ldsminal w3, w3, [x25]
1289 830: b8fa4159 ldsmaxal w26, w25, [x10]
1290 834: b8e273eb lduminal w2, w11, [sp]
1291 838: b8e760a2 ldumaxal w7, w2, [x5]
1292 83c: b8608287 swpl w0, w7, [x20]
1293 840: b865005f staddl w5, [x2]
1294 844: b87b1379 ldclrl w27, w25, [x27]
1295 848: b87e2358 ldeorl w30, w24, [x26]
1296 84c: b86f32c2 ldsetl w15, w2, [x22]
1297 850: b86053e3 ldsminl w0, w3, [sp]
1298 854: b86f4154 ldsmaxl w15, w20, [x10]
1299 858: b87671d5 lduminl w22, w21, [x14]
1300 85c: b866605e ldumaxl w6, w30, [x2]
1301 */
1302
1303 static const unsigned int insns[] =
1304 {
1305 0x8b50798f, 0xcb4381e1, 0xab05372d, 0xeb864796,
1306 0x0b961920, 0x4b195473, 0x2b0b5264, 0x6b9300f8,
1307 0x8a0bc0fe, 0xaa0f3118, 0xca170531, 0xea44dd6e,
1308 0x0a4c44f3, 0x2a8b7373, 0x4a567c7e, 0x6a9c0353,
1309 0x8a3accdd, 0xaa318f7a, 0xca2e1495, 0xeaa015e2,
1310 0x0a2274e2, 0x2a751598, 0x4a3309fe, 0x6ab172fe,
1311 0x110a5284, 0x310b1942, 0x5103d353, 0x710125bc,
1312 0x910d7bc2, 0xb108fa1b, 0xd1093536, 0xf10ae824,
1313 0x120e667c, 0x321f6cbb, 0x520f6a9e, 0x72136f56,
1314 0x927e4ce5, 0xb278b4ed, 0xd24c6527, 0xf2485803,
1315 0x14000000, 0x17ffffd7, 0x140001ee, 0x94000000,
1316 0x97ffffd4, 0x940001eb, 0x34000010, 0x34fffa30,
1317 0x34003d10, 0x35000013, 0x35fff9d3, 0x35003cb3,
1318 0xb4000005, 0xb4fff965, 0xb4003c45, 0xb5000004,
1319 0xb5fff904, 0xb5003be4, 0x1000001b, 0x10fff8bb,
1320 0x10003b9b, 0x90000010, 0x3640001c, 0x3647f83c,
1321 0x36403b1c, 0x37080001, 0x370ff7c1, 0x37083aa1,
1322 0x12a437f4, 0x528c9d67, 0x72838bb1, 0x92c1062e,
1323 0xd287da49, 0xf2a6d153, 0x93465ac9, 0x330b0013,
1324 0x530b4e6a, 0x934545e4, 0xb35370a3, 0xd3510b8c,
1325 0x13960c0f, 0x93ceddc6, 0x54000000, 0x54fff5a0,
1326 0x54003880, 0x54000001, 0x54fff541, 0x54003821,
1327 0x54000002, 0x54fff4e2, 0x540037c2, 0x54000002,
1328 0x54fff482, 0x54003762, 0x54000003, 0x54fff423,
1329 0x54003703, 0x54000003, 0x54fff3c3, 0x540036a3,
1330 0x54000004, 0x54fff364, 0x54003644, 0x54000005,
1331 0x54fff305, 0x540035e5, 0x54000006, 0x54fff2a6,
1332 0x54003586, 0x54000007, 0x54fff247, 0x54003527,
1333 0x54000008, 0x54fff1e8, 0x540034c8, 0x54000009,
1334 0x54fff189, 0x54003469, 0x5400000a, 0x54fff12a,
1335 0x5400340a, 0x5400000b, 0x54fff0cb, 0x540033ab,
1336 0x5400000c, 0x54fff06c, 0x5400334c, 0x5400000d,
1337 0x54fff00d, 0x540032ed, 0x5400000e, 0x54ffefae,
1338 0x5400328e, 0x5400000f, 0x54ffef4f, 0x5400322f,
1339 0xd40ac601, 0xd40042a2, 0xd404dac3, 0xd4224d40,
1340 0xd44219c0, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
1341 0xd5033fdf, 0xd503339f, 0xd50335bf, 0xd61f0280,
1342 0xd63f0040, 0xc8127c17, 0xc81efec5, 0xc85f7d05,
1343 0xc85ffe14, 0xc89ffd66, 0xc8dfff66, 0x880a7cb1,
1344 0x8816fd89, 0x885f7d1b, 0x885ffc57, 0x889fffba,
1345 0x88dffd4d, 0x48197f7c, 0x481dfd96, 0x485f7f96,
1346 0x485fffc3, 0x489ffdf8, 0x48dfff5b, 0x080b7e6a,
1347 0x0817fedb, 0x085f7e18, 0x085ffc38, 0x089fffa5,
1348 0x08dffe18, 0xc87f6239, 0xc87fb276, 0xc820573a,
1349 0xc821aca6, 0x887f388d, 0x887f88d1, 0x882f2643,
1350 0x88329131, 0xf81cf2b7, 0xb803f055, 0x39002f9b,
1351 0x781f31fd, 0xf85d33ce, 0xb843539d, 0x39401f54,
1352 0x785ce059, 0x389f1143, 0x788131ee, 0x78dfb17d,
1353 0xb89b90af, 0xfc403193, 0xbc42a36c, 0xfc07d396,
1354 0xbc1ec1f8, 0xf81e8f88, 0xb8025de6, 0x38007c27,
1355 0x7801ee20, 0xf8454fb9, 0xb85cce9a, 0x385e7fba,
1356 0x7841af24, 0x389ebd1c, 0x789fadd1, 0x78c0aefc,
1357 0xb89c0f7e, 0xfc50efd4, 0xbc414f71, 0xfc011c67,
1358 0xbc1f0d6d, 0xf81c3526, 0xb81e34b0, 0x3800f7bd,
1359 0x78012684, 0xf842e653, 0xb8417456, 0x385e2467,
1360 0x785e358b, 0x389e34c8, 0x788046f8, 0x78c00611,
1361 0xb89f8680, 0xfc582454, 0xbc5987d3, 0xfc076624,
1362 0xbc190675, 0xf833785a, 0xb82fd809, 0x3821799a,
1363 0x782a7975, 0xf870eaf0, 0xb871d96a, 0x386b7aed,
1364 0x7875689b, 0x38afd91a, 0x78a2c955, 0x78ee6bc8,
1365 0xb8b4f9dd, 0xfc76eb7e, 0xbc76692d, 0xfc31db28,
1366 0xbc255b01, 0xf91c52aa, 0xb91c3fb2, 0x391f8877,
1367 0x791ac97c, 0xf95c1758, 0xb95b3c55, 0x395ce0a4,
1368 0x795851ce, 0x399e9f64, 0x79993764, 0x79d9af8a,
1369 0xb99eea2a, 0xfd5a2f8d, 0xbd5dac78, 0xfd1e0182,
1370 0xbd195c31, 0x58000010, 0x1800000d, 0xf8981240,
1371 0xd8ffdf00, 0xf8a27a80, 0xf99af920, 0x1a0202e8,
1372 0x3a130078, 0x5a1d0316, 0x7a03036c, 0x9a0102eb,
1373 0xba1700bd, 0xda0c0329, 0xfa16000c, 0x0b23459a,
1374 0x2b328a14, 0xcb274bde, 0x6b222eab, 0x8b214b42,
1375 0xab34a7b2, 0xcb24520e, 0xeb378e20, 0x3a565283,
1376 0x7a420321, 0xba58c247, 0xfa4d5106, 0x3a426924,
1377 0x7a5b0847, 0xba413a02, 0xfa5fba23, 0x1a979377,
1378 0x1a86640a, 0x5a89300b, 0x5a923771, 0x9a8b720c,
1379 0x9a868786, 0xda9a736d, 0xda9256dd, 0x5ac0026c,
1380 0x5ac00657, 0x5ac00b89, 0x5ac01262, 0x5ac017b9,
1381 0xdac002e4, 0xdac0065d, 0xdac00907, 0xdac00e2d,
1382 0xdac01011, 0xdac01752, 0x1ad0098b, 0x1ac70d24,
1383 0x1ad020ec, 0x1ad72613, 0x1ac62887, 0x1ad72e95,
1384 0x9adc0990, 0x9acd0d84, 0x9ac721a9, 0x9acf277c,
1385 0x9ace2bd4, 0x9ade2e4e, 0x9bc77d63, 0x9b587e97,
1386 0x1b1524a2, 0x1b04a318, 0x9b0f4d8b, 0x9b0ce73d,
1387 0x9b2c5971, 0x9b34c87c, 0x9bbc6887, 0x9bb19556,
1388 0x1e310871, 0x1e261a2b, 0x1e2928fd, 0x1e333987,
1389 0x1e230ae0, 0x1e75087a, 0x1e651a60, 0x1e692b40,
1390 0x1e753ab9, 0x1e7309b0, 0x1f00425d, 0x1f1d95b7,
1391 0x1f2a38e9, 0x1f2f5f99, 0x1f5545a6, 0x1f429ea3,
1392 0x1f65472a, 0x1f7449ce, 0x1e20404f, 0x1e20c0f2,
1393 0x1e2140c3, 0x1e21c02c, 0x1e22c009, 0x1e6040a4,
1394 0x1e60c1e3, 0x1e614331, 0x1e61c30c, 0x1e6240b5,
1395 0x1e3802a4, 0x9e38007b, 0x1e78011d, 0x9e7802a9,
1396 0x1e2203b4, 0x9e220107, 0x1e6202ac, 0x9e6202b0,
1397 0x1e2600b2, 0x9e660119, 0x1e270352, 0x9e670160,
1398 0x1e262200, 0x1e7d2200, 0x1e2023c8, 0x1e602128,
1399 0x293e119b, 0x294a2543, 0x69480c70, 0xa934726a,
1400 0xa97448f3, 0x298243ca, 0x29e21242, 0x69c64db8,
1401 0xa9800311, 0xa9f4686e, 0x288a0416, 0x28fe2812,
1402 0x68fe62d8, 0xa885308c, 0xa8f12664, 0x282468d2,
1403 0x284e5035, 0xa8327699, 0xa84716e1, 0x0c407284,
1404 0x4cdfa158, 0x0ccf6cd8, 0x4cdf2483, 0x0d40c0c2,
1405 0x4ddfc9cd, 0x0dd8ceaf, 0x4c408ea9, 0x0cdf86bd,
1406 0x4d60c1c8, 0x0dffca87, 0x4de3cc7c, 0x4cdd497b,
1407 0x0c404950, 0x4d40e595, 0x4ddfeba4, 0x0dd3ed38,
1408 0x4cdf046a, 0x0cc9039b, 0x0d60e3d5, 0x0dffe5d7,
1409 0x0df4e9a4, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4,
1410 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f,
1411 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1,
1412 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f,
1413 0x1e601000, 0x1e603000, 0x1e621000, 0x1e623000,
1414 0x1e641000, 0x1e643000, 0x1e661000, 0x1e663000,
1415 0x1e681000, 0x1e683000, 0x1e6a1000, 0x1e6a3000,
1416 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, 0x1e6e3000,
1417 0x1e701000, 0x1e703000, 0x1e721000, 0x1e723000,
1418 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000,
1419 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000,
1420 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000,
1421 0xf8358305, 0xf82d01ed, 0xf8361353, 0xf839234a,
1422 0xf82531fb, 0xf8335165, 0xf83a4080, 0xf83673d7,
1423 0xf832611c, 0xf8ad837d, 0xf8ab01a5, 0xf8a112b8,
1424 0xf8bb2311, 0xf8b230be, 0xf8a75336, 0xf8a4427a,
1425 0xf8a6707e, 0xf8b860b7, 0xf8f88392, 0xf8f300ff,
1426 0xf8ed1386, 0xf8e822af, 0xf8e2302d, 0xf8f1533d,
1427 0xf8f941d2, 0xf8ff7366, 0xf8f061e5, 0xf86b8072,
1428 0xf87a0054, 0xf86b1164, 0xf87e22f3, 0xf86331cf,
1429 0xf87e5296, 0xf8674305, 0xf87771f0, 0xf86b6013,
1430 0xb83c803c, 0xb82b0195, 0xb83d1240, 0xb8252320,
1431 0xb82e3340, 0xb83c53b2, 0xb82f43a1, 0xb828739a,
1432 0xb831608e, 0xb8b88039, 0xb8aa0231, 0xb8bd12b4,
1433 0xb8bd2189, 0xb8ab30a6, 0xb8b552a7, 0xb8aa4197,
1434 0xb8b57145, 0xb8be6254, 0xb8ed80b7, 0xb8ef00b8,
1435 0xb8e9132a, 0xb8f42231, 0xb8ec33d2, 0xb8e35323,
1436 0xb8fa4159, 0xb8e273eb, 0xb8e760a2, 0xb8608287,
1437 0xb865005f, 0xb87b1379, 0xb87e2358, 0xb86f32c2,
1438 0xb86053e3, 0xb86f4154, 0xb87671d5, 0xb866605e,
1439
1440 };
1441 // END Generated code -- do not edit
1442
1443 asm_check((unsigned int *)entry, insns, sizeof insns / sizeof insns[0]);
1444
1445 {
1446 address PC = __ pc();
1447 __ ld1(v0, __ T16B, Address(r16)); // No offset
1448 __ ld1(v0, __ T8H, __ post(r16, 16)); // Post-index
1449 __ ld2(v0, v1, __ T8H, __ post(r24, 16 * 2)); // Post-index
1450 __ ld1(v0, __ T16B, __ post(r16, r17)); // Register post-index
1451 static const unsigned int vector_insns[] = {
1452 0x4c407200, // ld1 {v0.16b}, [x16]
1453 0x4cdf7600, // ld1 {v0.8h}, [x16], #16
1454 0x4cdf8700, // ld2 {v0.8h, v1.8h}, [x24], #32
1455 0x4cd17200, // ld1 {v0.16b}, [x16], x17
1456 };
1457 asm_check((unsigned int *)PC, vector_insns,
1458 sizeof vector_insns / sizeof vector_insns[0]);
1459 }
1460 }
1461 #endif // ASSERT
1462
1463 #undef __
1464
emit_data64(jlong data,relocInfo::relocType rtype,int format)1465 void Assembler::emit_data64(jlong data,
1466 relocInfo::relocType rtype,
1467 int format) {
1468 if (rtype == relocInfo::none) {
1469 emit_int64(data);
1470 } else {
1471 emit_data64(data, Relocation::spec_simple(rtype), format);
1472 }
1473 }
1474
emit_data64(jlong data,RelocationHolder const & rspec,int format)1475 void Assembler::emit_data64(jlong data,
1476 RelocationHolder const& rspec,
1477 int format) {
1478
1479 assert(inst_mark() != NULL, "must be inside InstructionMark");
1480 // Do not use AbstractAssembler::relocate, which is not intended for
1481 // embedded words. Instead, relocate to the enclosing instruction.
1482 code_section()->relocate(inst_mark(), rspec, format);
1483 emit_int64(data);
1484 }
1485
1486 extern "C" {
das(uint64_t start,int len)1487 void das(uint64_t start, int len) {
1488 ResourceMark rm;
1489 len <<= 2;
1490 if (len < 0)
1491 Disassembler::decode((address)start + len, (address)start);
1492 else
1493 Disassembler::decode((address)start, (address)start + len);
1494 }
1495
das1(unsigned long insn)1496 JNIEXPORT void das1(unsigned long insn) {
1497 das(insn, 1);
1498 }
1499 }
1500
1501 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1502
1503 #define __ as->
1504
lea(MacroAssembler * as,Register r) const1505 void Address::lea(MacroAssembler *as, Register r) const {
1506 Relocation* reloc = _rspec.reloc();
1507 relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1508
1509 switch(_mode) {
1510 case base_plus_offset: {
1511 if (_offset == 0 && _base == r) // it's a nop
1512 break;
1513 if (_offset > 0)
1514 __ add(r, _base, _offset);
1515 else
1516 __ sub(r, _base, -_offset);
1517 break;
1518 }
1519 case base_plus_offset_reg: {
1520 __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0));
1521 break;
1522 }
1523 case literal: {
1524 if (rtype == relocInfo::none)
1525 __ mov(r, target());
1526 else
1527 __ movptr(r, (uint64_t)target());
1528 break;
1529 }
1530 default:
1531 ShouldNotReachHere();
1532 }
1533 }
1534
adrp(Register reg1,const Address & dest,unsigned long & byte_offset)1535 void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
1536 ShouldNotReachHere();
1537 }
1538
1539 #undef __
1540
1541 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1542
adr(Register Rd,address adr)1543 void Assembler::adr(Register Rd, address adr) {
1544 long offset = adr - pc();
1545 int offset_lo = offset & 3;
1546 offset >>= 2;
1547 starti;
1548 f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1549 rf(Rd, 0);
1550 }
1551
_adrp(Register Rd,address adr)1552 void Assembler::_adrp(Register Rd, address adr) {
1553 uint64_t pc_page = (uint64_t)pc() >> 12;
1554 uint64_t adr_page = (uint64_t)adr >> 12;
1555 long offset = adr_page - pc_page;
1556 int offset_lo = offset & 3;
1557 offset >>= 2;
1558 starti;
1559 f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1560 rf(Rd, 0);
1561 }
1562
1563 #undef starti
1564
Address(address target,relocInfo::relocType rtype)1565 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1566 _is_lval = false;
1567 _target = target;
1568 switch (rtype) {
1569 case relocInfo::oop_type:
1570 case relocInfo::metadata_type:
1571 // Oops are a special case. Normally they would be their own section
1572 // but in cases like icBuffer they are literals in the code stream that
1573 // we don't have a section for. We use none so that we get a literal address
1574 // which is always patchable.
1575 break;
1576 case relocInfo::external_word_type:
1577 _rspec = external_word_Relocation::spec(target);
1578 break;
1579 case relocInfo::internal_word_type:
1580 _rspec = internal_word_Relocation::spec(target);
1581 break;
1582 case relocInfo::opt_virtual_call_type:
1583 _rspec = opt_virtual_call_Relocation::spec();
1584 break;
1585 case relocInfo::static_call_type:
1586 _rspec = static_call_Relocation::spec();
1587 break;
1588 case relocInfo::runtime_call_type:
1589 _rspec = runtime_call_Relocation::spec();
1590 break;
1591 case relocInfo::poll_type:
1592 case relocInfo::poll_return_type:
1593 _rspec = Relocation::spec_simple(rtype);
1594 break;
1595 case relocInfo::none:
1596 _rspec = RelocationHolder::none;
1597 break;
1598 default:
1599 ShouldNotReachHere();
1600 break;
1601 }
1602 }
1603
b(const Address & dest)1604 void Assembler::b(const Address &dest) {
1605 code_section()->relocate(pc(), dest.rspec());
1606 b(dest.target());
1607 }
1608
bl(const Address & dest)1609 void Assembler::bl(const Address &dest) {
1610 code_section()->relocate(pc(), dest.rspec());
1611 bl(dest.target());
1612 }
1613
adr(Register r,const Address & dest)1614 void Assembler::adr(Register r, const Address &dest) {
1615 code_section()->relocate(pc(), dest.rspec());
1616 adr(r, dest.target());
1617 }
1618
br(Condition cc,Label & L)1619 void Assembler::br(Condition cc, Label &L) {
1620 if (L.is_bound()) {
1621 br(cc, target(L));
1622 } else {
1623 L.add_patch_at(code(), locator());
1624 br(cc, pc());
1625 }
1626 }
1627
wrap_label(Label & L,Assembler::uncond_branch_insn insn)1628 void Assembler::wrap_label(Label &L,
1629 Assembler::uncond_branch_insn insn) {
1630 if (L.is_bound()) {
1631 (this->*insn)(target(L));
1632 } else {
1633 L.add_patch_at(code(), locator());
1634 (this->*insn)(pc());
1635 }
1636 }
1637
wrap_label(Register r,Label & L,compare_and_branch_insn insn)1638 void Assembler::wrap_label(Register r, Label &L,
1639 compare_and_branch_insn insn) {
1640 if (L.is_bound()) {
1641 (this->*insn)(r, target(L));
1642 } else {
1643 L.add_patch_at(code(), locator());
1644 (this->*insn)(r, pc());
1645 }
1646 }
1647
wrap_label(Register r,int bitpos,Label & L,test_and_branch_insn insn)1648 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1649 test_and_branch_insn insn) {
1650 if (L.is_bound()) {
1651 (this->*insn)(r, bitpos, target(L));
1652 } else {
1653 L.add_patch_at(code(), locator());
1654 (this->*insn)(r, bitpos, pc());
1655 }
1656 }
1657
wrap_label(Label & L,prfop op,prefetch_insn insn)1658 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1659 if (L.is_bound()) {
1660 (this->*insn)(target(L), op);
1661 } else {
1662 L.add_patch_at(code(), locator());
1663 (this->*insn)(pc(), op);
1664 }
1665 }
1666
1667 // An "all-purpose" add/subtract immediate, per ARM documentation:
1668 // A "programmer-friendly" assembler may accept a negative immediate
1669 // between -(2^24 -1) and -1 inclusive, causing it to convert a
1670 // requested ADD operation to a SUB, or vice versa, and then encode
1671 // the absolute value of the immediate as for uimm24.
add_sub_immediate(Register Rd,Register Rn,unsigned uimm,int op,int negated_op)1672 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1673 int negated_op) {
1674 bool sets_flags = op & 1; // this op sets flags
1675 union {
1676 unsigned u;
1677 int imm;
1678 };
1679 u = uimm;
1680 bool shift = false;
1681 bool neg = imm < 0;
1682 if (neg) {
1683 imm = -imm;
1684 op = negated_op;
1685 }
1686 assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1687 if (imm >= (1 << 11)
1688 && ((imm >> 12) << 12 == imm)) {
1689 imm >>= 12;
1690 shift = true;
1691 }
1692 f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
1693
1694 // add/subtract immediate ops with the S bit set treat r31 as zr;
1695 // with S unset they use sp.
1696 if (sets_flags)
1697 zrf(Rd, 0);
1698 else
1699 srf(Rd, 0);
1700
1701 srf(Rn, 5);
1702 }
1703
operand_valid_for_add_sub_immediate(long imm)1704 bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
1705 bool shift = false;
1706 unsigned long uimm = uabs(imm);
1707 if (uimm < (1 << 12))
1708 return true;
1709 if (uimm < (1 << 24)
1710 && ((uimm >> 12) << 12 == uimm)) {
1711 return true;
1712 }
1713 return false;
1714 }
1715
operand_valid_for_logical_immediate(bool is32,uint64_t imm)1716 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
1717 return encode_logical_immediate(is32, imm) != 0xffffffff;
1718 }
1719
doubleTo64Bits(jdouble d)1720 static uint64_t doubleTo64Bits(jdouble d) {
1721 union {
1722 jdouble double_value;
1723 uint64_t double_bits;
1724 };
1725
1726 double_value = d;
1727 return double_bits;
1728 }
1729
operand_valid_for_float_immediate(double imm)1730 bool Assembler::operand_valid_for_float_immediate(double imm) {
1731 // If imm is all zero bits we can use ZR as the source of a
1732 // floating-point value.
1733 if (doubleTo64Bits(imm) == 0)
1734 return true;
1735
1736 // Otherwise try to encode imm then convert the encoded value back
1737 // and make sure it's the exact same bit pattern.
1738 unsigned result = encoding_for_fp_immediate(imm);
1739 return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
1740 }
1741
code_fill_byte()1742 int AbstractAssembler::code_fill_byte() {
1743 return 0;
1744 }
1745
1746 // n.b. this is implemented in subclass MacroAssembler
bang_stack_with_offset(int offset)1747 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
1748
1749
1750 // and now the routines called by the assembler which encapsulate the
1751 // above encode and decode functions
1752
1753 uint32_t
encode_logical_immediate(bool is32,uint64_t imm)1754 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
1755 {
1756 if (is32) {
1757 /* Allow all zeros or all ones in top 32-bits, so that
1758 constant expressions like ~1 are permitted. */
1759 if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
1760 return 0xffffffff;
1761 /* Replicate the 32 lower bits to the 32 upper bits. */
1762 imm &= 0xffffffff;
1763 imm |= imm << 32;
1764 }
1765
1766 return encoding_for_logical_immediate(imm);
1767 }
1768
pack(double value)1769 unsigned Assembler::pack(double value) {
1770 float val = (float)value;
1771 unsigned result = encoding_for_fp_immediate(val);
1772 guarantee(unpack(result) == value,
1773 "Invalid floating-point immediate operand");
1774 return result;
1775 }
1776
1777 // Packed operands for Floating-point Move (immediate)
1778
unpack(unsigned value)1779 static float unpack(unsigned value) {
1780 union {
1781 unsigned ival;
1782 float val;
1783 };
1784 ival = fp_immediate_for_encoding(value, 0);
1785 return val;
1786 }
1787