1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2020 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "jvm.h"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/globals_extension.hpp"
33 #include "runtime/java.hpp"
34 #include "runtime/os.hpp"
35 #include "runtime/stubCodeGenerator.hpp"
36 #include "runtime/vm_version.hpp"
37 #include "utilities/align.hpp"
38 #include "utilities/defaultStream.hpp"
39 #include "utilities/globalDefinitions.hpp"
40 #include "utilities/powerOfTwo.hpp"
41
42 #ifndef _ALLBSD_SOURCE
43 #include <sys/sysinfo.h>
44 #endif
45
46 #if defined(_AIX)
47 #include <libperfstat.h>
48 #endif
49
50 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
51 #include <sys/auxv.h>
52
53 #ifndef PPC_FEATURE2_HTM_NOSC
54 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
55 #endif
56 #endif
57
58 bool VM_Version::_is_determine_features_test_running = false;
59 uint64_t VM_Version::_dscr_val = 0;
60
61 #define MSG(flag) \
62 if (flag && !FLAG_IS_DEFAULT(flag)) \
63 jio_fprintf(defaultStream::error_stream(), \
64 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
65 " -XX:+" #flag " will be disabled!\n");
66
initialize()67 void VM_Version::initialize() {
68
69 // Test which instructions are supported and measure cache line size.
70 determine_features();
71
72 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
73 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
74 if (VM_Version::has_brw()) {
75 FLAG_SET_ERGO(PowerArchitecturePPC64, 10);
76 } else if (VM_Version::has_darn()) {
77 FLAG_SET_ERGO(PowerArchitecturePPC64, 9);
78 } else if (VM_Version::has_lqarx()) {
79 FLAG_SET_ERGO(PowerArchitecturePPC64, 8);
80 } else if (VM_Version::has_popcntw()) {
81 FLAG_SET_ERGO(PowerArchitecturePPC64, 7);
82 } else if (VM_Version::has_cmpb()) {
83 FLAG_SET_ERGO(PowerArchitecturePPC64, 6);
84 } else if (VM_Version::has_popcntb()) {
85 FLAG_SET_ERGO(PowerArchitecturePPC64, 5);
86 } else {
87 FLAG_SET_ERGO(PowerArchitecturePPC64, 0);
88 }
89 }
90
91 bool PowerArchitecturePPC64_ok = false;
92 switch (PowerArchitecturePPC64) {
93 case 10: if (!VM_Version::has_brw() ) break;
94 case 9: if (!VM_Version::has_darn() ) break;
95 case 8: if (!VM_Version::has_lqarx() ) break;
96 case 7: if (!VM_Version::has_popcntw()) break;
97 case 6: if (!VM_Version::has_cmpb() ) break;
98 case 5: if (!VM_Version::has_popcntb()) break;
99 case 0: PowerArchitecturePPC64_ok = true; break;
100 default: break;
101 }
102 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
103 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
104
105 // Power 8: Configure Data Stream Control Register.
106 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
107 config_dscr();
108 }
109
110 if (!UseSIGTRAP) {
111 MSG(TrapBasedICMissChecks);
112 MSG(TrapBasedNullChecks);
113 FLAG_SET_ERGO(TrapBasedNullChecks, false);
114 FLAG_SET_ERGO(TrapBasedICMissChecks, false);
115 }
116
117 #ifdef COMPILER2
118 if (!UseSIGTRAP) {
119 MSG(TrapBasedRangeChecks);
120 FLAG_SET_ERGO(TrapBasedRangeChecks, false);
121 }
122
123 if (PowerArchitecturePPC64 >= 8) {
124 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
125 FLAG_SET_ERGO(SuperwordUseVSX, true);
126 }
127 } else {
128 if (SuperwordUseVSX) {
129 warning("SuperwordUseVSX specified, but needs at least Power8.");
130 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
131 }
132 }
133 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
134
135 if (PowerArchitecturePPC64 >= 9) {
136 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionsPPC64)) {
137 FLAG_SET_ERGO(UseCountTrailingZerosInstructionsPPC64, true);
138 }
139 if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
140 FLAG_SET_ERGO(UseCharacterCompareIntrinsics, true);
141 }
142 if (SuperwordUseVSX) {
143 if (FLAG_IS_DEFAULT(UseVectorByteReverseInstructionsPPC64)) {
144 FLAG_SET_ERGO(UseVectorByteReverseInstructionsPPC64, true);
145 }
146 } else if (UseVectorByteReverseInstructionsPPC64) {
147 warning("UseVectorByteReverseInstructionsPPC64 specified, but needs SuperwordUseVSX.");
148 FLAG_SET_DEFAULT(UseVectorByteReverseInstructionsPPC64, false);
149 }
150 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
151 FLAG_SET_ERGO(UseBASE64Intrinsics, true);
152 }
153 } else {
154 if (UseCountTrailingZerosInstructionsPPC64) {
155 warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
156 FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionsPPC64, false);
157 }
158 if (UseCharacterCompareIntrinsics) {
159 warning("UseCharacterCompareIntrinsics specified, but needs at least Power9.");
160 FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false);
161 }
162 if (UseVectorByteReverseInstructionsPPC64) {
163 warning("UseVectorByteReverseInstructionsPPC64 specified, but needs at least Power9.");
164 FLAG_SET_DEFAULT(UseVectorByteReverseInstructionsPPC64, false);
165 }
166 if (UseBASE64Intrinsics) {
167 warning("UseBASE64Intrinsics specified, but needs at least Power9.");
168 FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
169 }
170 }
171
172 if (PowerArchitecturePPC64 >= 10) {
173 if (FLAG_IS_DEFAULT(UseByteReverseInstructions)) {
174 FLAG_SET_ERGO(UseByteReverseInstructions, true);
175 }
176 } else {
177 if (UseByteReverseInstructions) {
178 warning("UseByteReverseInstructions specified, but needs at least Power10.");
179 FLAG_SET_DEFAULT(UseByteReverseInstructions, false);
180 }
181 }
182 #endif
183
184 // Create and print feature-string.
185 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
186 jio_snprintf(buf, sizeof(buf),
187 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
188 (has_fsqrt() ? " fsqrt" : ""),
189 (has_isel() ? " isel" : ""),
190 (has_lxarxeh() ? " lxarxeh" : ""),
191 (has_cmpb() ? " cmpb" : ""),
192 (has_popcntb() ? " popcntb" : ""),
193 (has_popcntw() ? " popcntw" : ""),
194 (has_fcfids() ? " fcfids" : ""),
195 (has_vand() ? " vand" : ""),
196 (has_lqarx() ? " lqarx" : ""),
197 (has_vcipher() ? " aes" : ""),
198 (has_vpmsumb() ? " vpmsumb" : ""),
199 (has_mfdscr() ? " mfdscr" : ""),
200 (has_vsx() ? " vsx" : ""),
201 (has_ldbrx() ? " ldbrx" : ""),
202 (has_stdbrx() ? " stdbrx" : ""),
203 (has_vshasig() ? " sha" : ""),
204 (has_tm() ? " rtm" : ""),
205 (has_darn() ? " darn" : ""),
206 (has_brw() ? " brw" : "")
207 // Make sure number of %s matches num_features!
208 );
209 _features_string = os::strdup(buf);
210 if (Verbose) {
211 print_features();
212 }
213
214 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
215 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
216 _supports_cx8 = true;
217
218 // Used by C1.
219 _supports_atomic_getset4 = true;
220 _supports_atomic_getadd4 = true;
221 _supports_atomic_getset8 = true;
222 _supports_atomic_getadd8 = true;
223
224 intx cache_line_size = L1_data_cache_line_size();
225
226 if (PowerArchitecturePPC64 >= 9) {
227 if (os::supports_map_sync() == true) {
228 _data_cache_line_flush_size = cache_line_size;
229 }
230 }
231
232 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
233
234 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
235 // PPC processors have an automatic prefetch engine.
236 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 1;
237 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3 * cache_line_size;
238
239 assert(AllocatePrefetchLines > 0, "invalid value");
240 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
241 AllocatePrefetchLines = 1; // Conservative value.
242 }
243
244 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
245 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
246 }
247
248 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
249
250 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (cache_line_size > ContendedPaddingWidth)) {
251 ContendedPaddingWidth = cache_line_size;
252 }
253
254 // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
255 // In all other cases, the implementation uses only generally available instructions.
256 if (!UseCRC32Intrinsics) {
257 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
258 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
259 }
260 }
261
262 // Implementation does not use any of the vector instructions available with Power8.
263 // Their exploitation is still pending (aka "work in progress").
264 if (!UseCRC32CIntrinsics) {
265 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
266 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
267 }
268 }
269
270 // TODO: Provide implementation.
271 if (UseAdler32Intrinsics) {
272 warning("Adler32Intrinsics not available on this CPU.");
273 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
274 }
275
276 // The AES intrinsic stubs require AES instruction support.
277 if (has_vcipher()) {
278 if (FLAG_IS_DEFAULT(UseAES)) {
279 UseAES = true;
280 }
281 } else if (UseAES) {
282 if (!FLAG_IS_DEFAULT(UseAES))
283 warning("AES instructions are not available on this CPU");
284 FLAG_SET_DEFAULT(UseAES, false);
285 }
286
287 if (UseAES && has_vcipher()) {
288 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
289 UseAESIntrinsics = true;
290 }
291 } else if (UseAESIntrinsics) {
292 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
293 warning("AES intrinsics are not available on this CPU");
294 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
295 }
296
297 if (UseAESCTRIntrinsics) {
298 warning("AES/CTR intrinsics are not available on this CPU");
299 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
300 }
301
302 if (UseGHASHIntrinsics) {
303 warning("GHASH intrinsics are not available on this CPU");
304 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
305 }
306
307 if (FLAG_IS_DEFAULT(UseFMA)) {
308 FLAG_SET_DEFAULT(UseFMA, true);
309 }
310
311 if (UseMD5Intrinsics) {
312 warning("MD5 intrinsics are not available on this CPU");
313 FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
314 }
315
316 if (has_vshasig()) {
317 if (FLAG_IS_DEFAULT(UseSHA)) {
318 UseSHA = true;
319 }
320 } else if (UseSHA) {
321 if (!FLAG_IS_DEFAULT(UseSHA))
322 warning("SHA instructions are not available on this CPU");
323 FLAG_SET_DEFAULT(UseSHA, false);
324 }
325
326 if (UseSHA1Intrinsics) {
327 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
328 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
329 }
330
331 if (UseSHA && has_vshasig()) {
332 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
333 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
334 }
335 } else if (UseSHA256Intrinsics) {
336 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
337 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
338 }
339
340 if (UseSHA && has_vshasig()) {
341 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
342 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
343 }
344 } else if (UseSHA512Intrinsics) {
345 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
346 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
347 }
348
349 if (UseSHA3Intrinsics) {
350 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
351 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
352 }
353
354 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
355 FLAG_SET_DEFAULT(UseSHA, false);
356 }
357
358 #ifdef COMPILER2
359 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
360 UseSquareToLenIntrinsic = true;
361 }
362 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
363 UseMulAddIntrinsic = true;
364 }
365 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
366 UseMultiplyToLenIntrinsic = true;
367 }
368 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
369 UseMontgomeryMultiplyIntrinsic = true;
370 }
371 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
372 UseMontgomerySquareIntrinsic = true;
373 }
374 #endif
375
376 if (UseVectorizedMismatchIntrinsic) {
377 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
378 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
379 }
380
381
382 // Adjust RTM (Restricted Transactional Memory) flags.
383 if (UseRTMLocking) {
384 // If CPU or OS do not support TM:
385 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
386 // setting during arguments processing. See use_biased_locking().
387 // VM_Version_init() is executed after UseBiasedLocking is used
388 // in Thread::allocate().
389 if (PowerArchitecturePPC64 < 8) {
390 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
391 }
392
393 if (!has_tm()) {
394 vm_exit_during_initialization("RTM is not supported on this OS version.");
395 }
396
397 #if INCLUDE_RTM_OPT
398 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
399 // RTM locking should be used only for applications with
400 // high lock contention. For now we do not use it by default.
401 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
402 }
403 #else
404 // Only C2 does RTM locking optimization.
405 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
406 // setting during arguments processing. See use_biased_locking().
407 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
408 #endif
409 } else { // !UseRTMLocking
410 if (UseRTMForStackLocks) {
411 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
412 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
413 }
414 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
415 }
416 if (UseRTMDeopt) {
417 FLAG_SET_DEFAULT(UseRTMDeopt, false);
418 }
419 #ifdef COMPILER2
420 if (PrintPreciseRTMLockingStatistics) {
421 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
422 }
423 #endif
424 }
425
426 // This machine allows unaligned memory accesses
427 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
428 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
429 }
430
431 check_virtualizations();
432 }
433
check_virtualizations()434 void VM_Version::check_virtualizations() {
435 #if defined(_AIX)
436 int rc = 0;
437 perfstat_partition_total_t pinfo;
438 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
439 if (rc == 1) {
440 Abstract_VM_Version::_detected_virtualization = PowerVM;
441 }
442 #else
443 const char* info_file = "/proc/ppc64/lparcfg";
444 // system_type=...qemu indicates PowerKVM
445 // e.g. system_type=IBM pSeries (emulated by qemu)
446 char line[500];
447 FILE* fp = fopen(info_file, "r");
448 if (fp == NULL) {
449 return;
450 }
451 const char* system_type="system_type="; // in case this line contains qemu, it is KVM
452 const char* num_lpars="NumLpars="; // in case of non-KVM : if this line is found it is PowerVM
453 bool num_lpars_found = false;
454
455 while (fgets(line, sizeof(line), fp) != NULL) {
456 if (strncmp(line, system_type, strlen(system_type)) == 0) {
457 if (strstr(line, "qemu") != 0) {
458 Abstract_VM_Version::_detected_virtualization = PowerKVM;
459 fclose(fp);
460 return;
461 }
462 }
463 if (strncmp(line, num_lpars, strlen(num_lpars)) == 0) {
464 num_lpars_found = true;
465 }
466 }
467 if (num_lpars_found) {
468 Abstract_VM_Version::_detected_virtualization = PowerVM;
469 } else {
470 Abstract_VM_Version::_detected_virtualization = PowerFullPartitionMode;
471 }
472 fclose(fp);
473 #endif
474 }
475
print_platform_virtualization_info(outputStream * st)476 void VM_Version::print_platform_virtualization_info(outputStream* st) {
477 #if defined(_AIX)
478 // more info about perfstat API see
479 // https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.prftools/idprftools_perfstat_glob_partition.htm
480 int rc = 0;
481 perfstat_partition_total_t pinfo;
482 memset(&pinfo, 0, sizeof(perfstat_partition_total_t));
483 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
484 if (rc != 1) {
485 return;
486 } else {
487 st->print_cr("Virtualization type : PowerVM");
488 }
489 // CPU information
490 perfstat_cpu_total_t cpuinfo;
491 memset(&cpuinfo, 0, sizeof(perfstat_cpu_total_t));
492 rc = perfstat_cpu_total(NULL, &cpuinfo, sizeof(perfstat_cpu_total_t), 1);
493 if (rc != 1) {
494 return;
495 }
496
497 st->print_cr("Processor description : %s", cpuinfo.description);
498 st->print_cr("Processor speed : %llu Hz", cpuinfo.processorHZ);
499
500 st->print_cr("LPAR partition name : %s", pinfo.name);
501 st->print_cr("LPAR partition number : %u", pinfo.lpar_id);
502 st->print_cr("LPAR partition type : %s", pinfo.type.b.shared_enabled ? "shared" : "dedicated");
503 st->print_cr("LPAR mode : %s", pinfo.type.b.donate_enabled ? "donating" : pinfo.type.b.capped ? "capped" : "uncapped");
504 st->print_cr("LPAR partition group ID : %u", pinfo.group_id);
505 st->print_cr("LPAR shared pool ID : %u", pinfo.pool_id);
506
507 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_capable ? "capable" : "not capable");
508 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_enabled ? "on" : "off");
509 st->print_cr("AME (active memory expansion) : %s", pinfo.type.b.ame_enabled ? "on" : "off");
510
511 if (pinfo.type.b.ame_enabled) {
512 st->print_cr("AME true memory in bytes : %llu", pinfo.true_memory);
513 st->print_cr("AME expanded memory in bytes : %llu", pinfo.expanded_memory);
514 }
515
516 st->print_cr("SMT : %s", pinfo.type.b.smt_capable ? "capable" : "not capable");
517 st->print_cr("SMT : %s", pinfo.type.b.smt_enabled ? "on" : "off");
518 int ocpus = pinfo.online_cpus > 0 ? pinfo.online_cpus : 1;
519 st->print_cr("LPAR threads : %d", cpuinfo.ncpus/ocpus);
520 st->print_cr("LPAR online virtual cpus : %d", pinfo.online_cpus);
521 st->print_cr("LPAR logical cpus : %d", cpuinfo.ncpus);
522 st->print_cr("LPAR maximum virtual cpus : %u", pinfo.max_cpus);
523 st->print_cr("LPAR minimum virtual cpus : %u", pinfo.min_cpus);
524 st->print_cr("LPAR entitled capacity : %4.2f", (double) (pinfo.entitled_proc_capacity/100.0));
525 st->print_cr("LPAR online memory : %llu MB", pinfo.online_memory);
526 st->print_cr("LPAR maximum memory : %llu MB", pinfo.max_memory);
527 st->print_cr("LPAR minimum memory : %llu MB", pinfo.min_memory);
528 #else
529 const char* info_file = "/proc/ppc64/lparcfg";
530 const char* kw[] = { "system_type=", // qemu indicates PowerKVM
531 "partition_entitled_capacity=", // entitled processor capacity percentage
532 "partition_max_entitled_capacity=",
533 "capacity_weight=", // partition CPU weight
534 "partition_active_processors=",
535 "partition_potential_processors=",
536 "entitled_proc_capacity_available=",
537 "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage
538 "shared_processor_mode=", // (non)dedicated partition
539 "system_potential_processors=",
540 "pool=", // CPU-pool number
541 "pool_capacity=",
542 "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines
543 NULL };
544 if (!print_matching_lines_from_file(info_file, st, kw)) {
545 st->print_cr(" <%s Not Available>", info_file);
546 }
547 #endif
548 }
549
use_biased_locking()550 bool VM_Version::use_biased_locking() {
551 #if INCLUDE_RTM_OPT
552 // RTM locking is most useful when there is high lock contention and
553 // low data contention. With high lock contention the lock is usually
554 // inflated and biased locking is not suitable for that case.
555 // RTM locking code requires that biased locking is off.
556 // Note: we can't switch off UseBiasedLocking in get_processor_features()
557 // because it is used by Thread::allocate() which is called before
558 // VM_Version::initialize().
559 if (UseRTMLocking && UseBiasedLocking) {
560 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
561 FLAG_SET_DEFAULT(UseBiasedLocking, false);
562 } else {
563 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
564 UseBiasedLocking = false;
565 }
566 }
567 #endif
568 return UseBiasedLocking;
569 }
570
print_features()571 void VM_Version::print_features() {
572 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
573
574 if (Verbose) {
575 if (ContendedPaddingWidth > 0) {
576 tty->cr();
577 tty->print_cr("ContendedPaddingWidth " INTX_FORMAT, ContendedPaddingWidth);
578 }
579 }
580 }
581
determine_features()582 void VM_Version::determine_features() {
583 #if defined(ABI_ELFv2)
584 // 1 InstWord per call for the blr instruction.
585 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
586 #else
587 // 7 InstWords for each call (function descriptor + blr instruction).
588 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
589 #endif
590 int features = 0;
591
592 // create test area
593 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
594 char test_area[BUFFER_SIZE];
595 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
596
597 // Allocate space for the code.
598 ResourceMark rm;
599 CodeBuffer cb("detect_cpu_features", code_size, 0);
600 MacroAssembler* a = new MacroAssembler(&cb);
601
602 // Must be set to true so we can generate the test code.
603 _features = VM_Version::all_features_m;
604
605 // Emit code.
606 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
607 uint32_t *code = (uint32_t *)a->pc();
608 // Don't use R0 in ldarx.
609 // Keep R3_ARG1 unmodified, it contains &field (see below).
610 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
611 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
612 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
613 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
614 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
615 a->cmpb(R7, R5, R6); // code[4] -> cmpb
616 a->popcntb(R7, R5); // code[5] -> popcntb
617 a->popcntw(R7, R5); // code[6] -> popcntw
618 a->fcfids(F3, F4); // code[7] -> fcfids
619 a->vand(VR0, VR0, VR0); // code[8] -> vand
620 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
621 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
622 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
623 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
624 a->mfdscr(R0); // code[12] -> mfdscr
625 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
626 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
627 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
628 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
629 // rtm is determined by OS
630 a->darn(R7); // code[17] -> darn
631 a->brw(R5, R6); // code[18] -> brw
632 a->blr();
633
634 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
635 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
636 a->dcbz(R3_ARG1); // R3_ARG1 = addr
637 a->blr();
638
639 uint32_t *code_end = (uint32_t *)a->pc();
640 a->flush();
641 _features = VM_Version::unknown_m;
642
643 // Print the detection code.
644 if (PrintAssembly) {
645 ttyLocker ttyl;
646 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
647 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
648 }
649
650 // Measure cache line size.
651 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
652 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
653 int count = 0; // count zeroed bytes
654 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
655 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
656 _L1_data_cache_line_size = count;
657
658 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
659 VM_Version::_is_determine_features_test_running = true;
660 // We must align the first argument to 16 bytes because of the lqarx check.
661 (*test)(align_up((address)mid_of_test_area, 16), 0);
662 VM_Version::_is_determine_features_test_running = false;
663
664 // determine which instructions are legal.
665 int feature_cntr = 0;
666 if (code[feature_cntr++]) features |= fsqrt_m;
667 if (code[feature_cntr++]) features |= fsqrts_m;
668 if (code[feature_cntr++]) features |= isel_m;
669 if (code[feature_cntr++]) features |= lxarxeh_m;
670 if (code[feature_cntr++]) features |= cmpb_m;
671 if (code[feature_cntr++]) features |= popcntb_m;
672 if (code[feature_cntr++]) features |= popcntw_m;
673 if (code[feature_cntr++]) features |= fcfids_m;
674 if (code[feature_cntr++]) features |= vand_m;
675 if (code[feature_cntr++]) features |= lqarx_m;
676 if (code[feature_cntr++]) features |= vcipher_m;
677 if (code[feature_cntr++]) features |= vpmsumb_m;
678 if (code[feature_cntr++]) features |= mfdscr_m;
679 if (code[feature_cntr++]) features |= vsx_m;
680 if (code[feature_cntr++]) features |= ldbrx_m;
681 if (code[feature_cntr++]) features |= stdbrx_m;
682 if (code[feature_cntr++]) features |= vshasig_m;
683 // feature rtm_m is determined by OS
684 if (code[feature_cntr++]) features |= darn_m;
685 if (code[feature_cntr++]) features |= brw_m;
686
687 // Print the detection code.
688 if (PrintAssembly) {
689 ttyLocker ttyl;
690 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
691 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
692 }
693
694 _features = features;
695
696 #ifdef AIX
697 // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
698 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
699 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
700 // The Java property os.version, which is used in RTM tests to decide
701 // whether the feature is available, only knows major and minor versions.
702 // We don't want to change this property, as user code might depend on it.
703 // So the tests can not check on subversion 3.30, and we only enable RTM
704 // with AIX 7.2.
705 if (has_lqarx()) { // POWER8 or above
706 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
707 _features |= rtm_m;
708 }
709 }
710 #endif
711 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
712 unsigned long auxv = getauxval(AT_HWCAP2);
713
714 if (auxv & PPC_FEATURE2_HTM_NOSC) {
715 if (auxv & PPC_FEATURE2_HAS_HTM) {
716 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
717 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
718 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
719 // and kernel workarounds, so there is a new mode only supported
720 // on non-virtualized P9 machines called HTM with no Suspend Mode).
721 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
722 _features |= rtm_m;
723 }
724 }
725 #endif
726 }
727
728 // Power 8: Configure Data Stream Control Register.
config_dscr()729 void VM_Version::config_dscr() {
730 // 7 InstWords for each call (function descriptor + blr instruction).
731 const int code_size = (2+2*7)*BytesPerInstWord;
732
733 // Allocate space for the code.
734 ResourceMark rm;
735 CodeBuffer cb("config_dscr", code_size, 0);
736 MacroAssembler* a = new MacroAssembler(&cb);
737
738 // Emit code.
739 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
740 uint32_t *code = (uint32_t *)a->pc();
741 a->mfdscr(R3);
742 a->blr();
743
744 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
745 a->mtdscr(R3);
746 a->blr();
747
748 uint32_t *code_end = (uint32_t *)a->pc();
749 a->flush();
750
751 // Print the detection code.
752 if (PrintAssembly) {
753 ttyLocker ttyl;
754 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
755 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
756 }
757
758 // Apply the configuration if needed.
759 _dscr_val = (*get_dscr)();
760 if (Verbose) {
761 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
762 }
763 bool change_requested = false;
764 if (DSCR_PPC64 != (uintx)-1) {
765 _dscr_val = DSCR_PPC64;
766 change_requested = true;
767 }
768 if (DSCR_DPFD_PPC64 <= 7) {
769 uint64_t mask = 0x7;
770 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
771 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
772 change_requested = true;
773 }
774 }
775 if (DSCR_URG_PPC64 <= 7) {
776 uint64_t mask = 0x7 << 6;
777 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
778 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
779 change_requested = true;
780 }
781 }
782 if (change_requested) {
783 (*set_dscr)(_dscr_val);
784 if (Verbose) {
785 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
786 }
787 }
788 }
789
790 static uint64_t saved_features = 0;
791
allow_all()792 void VM_Version::allow_all() {
793 saved_features = _features;
794 _features = all_features_m;
795 }
796
revert()797 void VM_Version::revert() {
798 _features = saved_features;
799 }
800