1 /* 2 * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_VERSION_X86_HPP 26 #define CPU_X86_VM_VERSION_X86_HPP 27 28 #include "memory/universe.hpp" 29 #include "runtime/abstract_vm_version.hpp" 30 #include "utilities/macros.hpp" 31 32 class VM_Version : public Abstract_VM_Version { 33 friend class VMStructs; 34 friend class JVMCIVMStructs; 35 36 public: 37 // cpuid result register layouts. These are all unions of a uint32_t 38 // (in case anyone wants access to the register as a whole) and a bitfield. 39 40 union StdCpuid1Eax { 41 uint32_t value; 42 struct { 43 uint32_t stepping : 4, 44 model : 4, 45 family : 4, 46 proc_type : 2, 47 : 2, 48 ext_model : 4, 49 ext_family : 8, 50 : 4; 51 } bits; 52 }; 53 54 union StdCpuid1Ebx { // example, unused 55 uint32_t value; 56 struct { 57 uint32_t brand_id : 8, 58 clflush_size : 8, 59 threads_per_cpu : 8, 60 apic_id : 8; 61 } bits; 62 }; 63 64 union StdCpuid1Ecx { 65 uint32_t value; 66 struct { 67 uint32_t sse3 : 1, 68 clmul : 1, 69 : 1, 70 monitor : 1, 71 : 1, 72 vmx : 1, 73 : 1, 74 est : 1, 75 : 1, 76 ssse3 : 1, 77 cid : 1, 78 : 1, 79 fma : 1, 80 cmpxchg16: 1, 81 : 4, 82 dca : 1, 83 sse4_1 : 1, 84 sse4_2 : 1, 85 : 2, 86 popcnt : 1, 87 : 1, 88 aes : 1, 89 : 1, 90 osxsave : 1, 91 avx : 1, 92 : 2, 93 hv : 1; 94 } bits; 95 }; 96 97 union StdCpuid1Edx { 98 uint32_t value; 99 struct { 100 uint32_t : 4, 101 tsc : 1, 102 : 3, 103 cmpxchg8 : 1, 104 : 6, 105 cmov : 1, 106 : 3, 107 clflush : 1, 108 : 3, 109 mmx : 1, 110 fxsr : 1, 111 sse : 1, 112 sse2 : 1, 113 : 1, 114 ht : 1, 115 : 3; 116 } bits; 117 }; 118 119 union DcpCpuid4Eax { 120 uint32_t value; 121 struct { 122 uint32_t cache_type : 5, 123 : 21, 124 cores_per_cpu : 6; 125 } bits; 126 }; 127 128 union DcpCpuid4Ebx { 129 uint32_t value; 130 struct { 131 uint32_t L1_line_size : 12, 132 partitions : 10, 133 associativity : 10; 134 } bits; 135 }; 136 137 union TplCpuidBEbx { 138 uint32_t value; 139 struct { 140 uint32_t logical_cpus : 16, 141 : 16; 142 } bits; 143 }; 144 145 union ExtCpuid1Ecx { 146 uint32_t value; 147 struct { 148 uint32_t LahfSahf : 1, 149 CmpLegacy : 1, 150 : 3, 151 lzcnt_intel : 1, 152 lzcnt : 1, 153 sse4a : 1, 154 misalignsse : 1, 155 prefetchw : 1, 156 : 22; 157 } bits; 158 }; 159 160 union ExtCpuid1Edx { 161 uint32_t value; 162 struct { 163 uint32_t : 22, 164 mmx_amd : 1, 165 mmx : 1, 166 fxsr : 1, 167 : 4, 168 long_mode : 1, 169 tdnow2 : 1, 170 tdnow : 1; 171 } bits; 172 }; 173 174 union ExtCpuid5Ex { 175 uint32_t value; 176 struct { 177 uint32_t L1_line_size : 8, 178 L1_tag_lines : 8, 179 L1_assoc : 8, 180 L1_size : 8; 181 } bits; 182 }; 183 184 union ExtCpuid7Edx { 185 uint32_t value; 186 struct { 187 uint32_t : 8, 188 tsc_invariance : 1, 189 : 23; 190 } bits; 191 }; 192 193 union ExtCpuid8Ecx { 194 uint32_t value; 195 struct { 196 uint32_t cores_per_cpu : 8, 197 : 24; 198 } bits; 199 }; 200 201 union SefCpuid7Eax { 202 uint32_t value; 203 }; 204 205 union SefCpuid7Ebx { 206 uint32_t value; 207 struct { 208 uint32_t fsgsbase : 1, 209 : 2, 210 bmi1 : 1, 211 : 1, 212 avx2 : 1, 213 : 2, 214 bmi2 : 1, 215 erms : 1, 216 : 1, 217 rtm : 1, 218 : 4, 219 avx512f : 1, 220 avx512dq : 1, 221 : 1, 222 adx : 1, 223 : 3, 224 clflushopt : 1, 225 clwb : 1, 226 : 1, 227 avx512pf : 1, 228 avx512er : 1, 229 avx512cd : 1, 230 sha : 1, 231 avx512bw : 1, 232 avx512vl : 1; 233 } bits; 234 }; 235 236 union SefCpuid7Ecx { 237 uint32_t value; 238 struct { 239 uint32_t prefetchwt1 : 1, 240 avx512_vbmi : 1, 241 umip : 1, 242 pku : 1, 243 ospke : 1, 244 : 1, 245 avx512_vbmi2 : 1, 246 : 1, 247 gfni : 1, 248 vaes : 1, 249 avx512_vpclmulqdq : 1, 250 avx512_vnni : 1, 251 avx512_bitalg : 1, 252 : 1, 253 avx512_vpopcntdq : 1, 254 : 17; 255 } bits; 256 }; 257 258 union SefCpuid7Edx { 259 uint32_t value; 260 struct { 261 uint32_t : 2, 262 avx512_4vnniw : 1, 263 avx512_4fmaps : 1, 264 : 28; 265 } bits; 266 }; 267 268 union ExtCpuid1EEbx { 269 uint32_t value; 270 struct { 271 uint32_t : 8, 272 threads_per_core : 8, 273 : 16; 274 } bits; 275 }; 276 277 union XemXcr0Eax { 278 uint32_t value; 279 struct { 280 uint32_t x87 : 1, 281 sse : 1, 282 ymm : 1, 283 bndregs : 1, 284 bndcsr : 1, 285 opmask : 1, 286 zmm512 : 1, 287 zmm32 : 1, 288 : 24; 289 } bits; 290 }; 291 292 protected: 293 static int _cpu; 294 static int _model; 295 static int _stepping; 296 297 static bool _has_intel_jcc_erratum; 298 299 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV 300 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV 301 302 enum Feature_Flag : uint64_t { 303 #define CPU_FEATURE_FLAGS(decl) \ 304 decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \ 305 decl(CMOV, "cmov", 1) \ 306 decl(FXSR, "fxsr", 2) \ 307 decl(HT, "ht", 3) \ 308 \ 309 decl(MMX, "mmx", 4) \ 310 decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ 311 /* may not necessarily support other 3dnow instructions */ \ 312 decl(SSE, "sse", 6) \ 313 decl(SSE2, "sse2", 7) \ 314 \ 315 decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \ 316 decl(SSSE3, "ssse3", 9 ) \ 317 decl(SSE4A, "sse4a", 10) \ 318 decl(SSE4_1, "sse4.1", 11) \ 319 \ 320 decl(SSE4_2, "sse4.2", 12) \ 321 decl(POPCNT, "popcnt", 13) \ 322 decl(LZCNT, "lzcnt", 14) \ 323 decl(TSC, "tsc", 15) \ 324 \ 325 decl(TSCINV_BIT, "tscinvbit", 16) \ 326 decl(TSCINV, "tscinv", 17) \ 327 decl(AVX, "avx", 18) \ 328 decl(AVX2, "avx2", 19) \ 329 \ 330 decl(AES, "aes", 20) \ 331 decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \ 332 decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \ 333 decl(BMI1, "bmi1", 23) \ 334 \ 335 decl(BMI2, "bmi2", 24) \ 336 decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \ 337 decl(ADX, "adx", 26) \ 338 decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \ 339 \ 340 decl(AVX512DQ, "avx512dq", 28) \ 341 decl(AVX512PF, "avx512pf", 29) \ 342 decl(AVX512ER, "avx512er", 30) \ 343 decl(AVX512CD, "avx512cd", 31) \ 344 \ 345 decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \ 346 decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \ 347 decl(SHA, "sha", 34) /* SHA instructions */ \ 348 decl(FMA, "fma", 35) /* FMA instructions */ \ 349 \ 350 decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \ 351 decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \ 352 decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \ 353 decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \ 354 \ 355 decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \ 356 decl(FLUSH, "clflush", 41) /* flush instruction */ \ 357 decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \ 358 decl(CLWB, "clwb", 43) /* clwb instruction */ \ 359 \ 360 decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \ 361 decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \ 362 decl(HV, "hv", 46) /* Hypervisor instructions */ 363 364 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit), 365 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) 366 #undef DECLARE_CPU_FEATURE_FLAG 367 }; 368 369 static const char* _features_names[]; 370 371 enum Extended_Family { 372 // AMD 373 CPU_FAMILY_AMD_11H = 0x11, 374 // ZX 375 CPU_FAMILY_ZX_CORE_F6 = 6, 376 CPU_FAMILY_ZX_CORE_F7 = 7, 377 // Intel 378 CPU_FAMILY_INTEL_CORE = 6, 379 CPU_MODEL_NEHALEM = 0x1e, 380 CPU_MODEL_NEHALEM_EP = 0x1a, 381 CPU_MODEL_NEHALEM_EX = 0x2e, 382 CPU_MODEL_WESTMERE = 0x25, 383 CPU_MODEL_WESTMERE_EP = 0x2c, 384 CPU_MODEL_WESTMERE_EX = 0x2f, 385 CPU_MODEL_SANDYBRIDGE = 0x2a, 386 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, 387 CPU_MODEL_IVYBRIDGE_EP = 0x3a, 388 CPU_MODEL_HASWELL_E3 = 0x3c, 389 CPU_MODEL_HASWELL_E7 = 0x3f, 390 CPU_MODEL_BROADWELL = 0x3d, 391 CPU_MODEL_SKYLAKE = 0x55 392 }; 393 394 // cpuid information block. All info derived from executing cpuid with 395 // various function numbers is stored here. Intel and AMD info is 396 // merged in this block: accessor methods disentangle it. 397 // 398 // The info block is laid out in subblocks of 4 dwords corresponding to 399 // eax, ebx, ecx and edx, whether or not they contain anything useful. 400 struct CpuidInfo { 401 // cpuid function 0 402 uint32_t std_max_function; 403 uint32_t std_vendor_name_0; 404 uint32_t std_vendor_name_1; 405 uint32_t std_vendor_name_2; 406 407 // cpuid function 1 408 StdCpuid1Eax std_cpuid1_eax; 409 StdCpuid1Ebx std_cpuid1_ebx; 410 StdCpuid1Ecx std_cpuid1_ecx; 411 StdCpuid1Edx std_cpuid1_edx; 412 413 // cpuid function 4 (deterministic cache parameters) 414 DcpCpuid4Eax dcp_cpuid4_eax; 415 DcpCpuid4Ebx dcp_cpuid4_ebx; 416 uint32_t dcp_cpuid4_ecx; // unused currently 417 uint32_t dcp_cpuid4_edx; // unused currently 418 419 // cpuid function 7 (structured extended features) 420 SefCpuid7Eax sef_cpuid7_eax; 421 SefCpuid7Ebx sef_cpuid7_ebx; 422 SefCpuid7Ecx sef_cpuid7_ecx; 423 SefCpuid7Edx sef_cpuid7_edx; 424 425 // cpuid function 0xB (processor topology) 426 // ecx = 0 427 uint32_t tpl_cpuidB0_eax; 428 TplCpuidBEbx tpl_cpuidB0_ebx; 429 uint32_t tpl_cpuidB0_ecx; // unused currently 430 uint32_t tpl_cpuidB0_edx; // unused currently 431 432 // ecx = 1 433 uint32_t tpl_cpuidB1_eax; 434 TplCpuidBEbx tpl_cpuidB1_ebx; 435 uint32_t tpl_cpuidB1_ecx; // unused currently 436 uint32_t tpl_cpuidB1_edx; // unused currently 437 438 // ecx = 2 439 uint32_t tpl_cpuidB2_eax; 440 TplCpuidBEbx tpl_cpuidB2_ebx; 441 uint32_t tpl_cpuidB2_ecx; // unused currently 442 uint32_t tpl_cpuidB2_edx; // unused currently 443 444 // cpuid function 0x80000000 // example, unused 445 uint32_t ext_max_function; 446 uint32_t ext_vendor_name_0; 447 uint32_t ext_vendor_name_1; 448 uint32_t ext_vendor_name_2; 449 450 // cpuid function 0x80000001 451 uint32_t ext_cpuid1_eax; // reserved 452 uint32_t ext_cpuid1_ebx; // reserved 453 ExtCpuid1Ecx ext_cpuid1_ecx; 454 ExtCpuid1Edx ext_cpuid1_edx; 455 456 // cpuid functions 0x80000002 thru 0x80000004: example, unused 457 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; 458 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; 459 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; 460 461 // cpuid function 0x80000005 // AMD L1, Intel reserved 462 uint32_t ext_cpuid5_eax; // unused currently 463 uint32_t ext_cpuid5_ebx; // reserved 464 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) 465 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) 466 467 // cpuid function 0x80000007 468 uint32_t ext_cpuid7_eax; // reserved 469 uint32_t ext_cpuid7_ebx; // reserved 470 uint32_t ext_cpuid7_ecx; // reserved 471 ExtCpuid7Edx ext_cpuid7_edx; // tscinv 472 473 // cpuid function 0x80000008 474 uint32_t ext_cpuid8_eax; // unused currently 475 uint32_t ext_cpuid8_ebx; // reserved 476 ExtCpuid8Ecx ext_cpuid8_ecx; 477 uint32_t ext_cpuid8_edx; // reserved 478 479 // cpuid function 0x8000001E // AMD 17h 480 uint32_t ext_cpuid1E_eax; 481 ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h) 482 uint32_t ext_cpuid1E_ecx; 483 uint32_t ext_cpuid1E_edx; // unused currently 484 485 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) 486 XemXcr0Eax xem_xcr0_eax; 487 uint32_t xem_xcr0_edx; // reserved 488 489 // Space to save ymm registers after signal handle 490 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 491 492 // Space to save zmm registers after signal handle 493 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31 494 }; 495 496 // The actual cpuid info block 497 static CpuidInfo _cpuid_info; 498 499 // Extractors and predicates extended_cpu_family()500 static uint32_t extended_cpu_family() { 501 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; 502 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; 503 return result; 504 } 505 extended_cpu_model()506 static uint32_t extended_cpu_model() { 507 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; 508 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; 509 return result; 510 } 511 cpu_stepping()512 static uint32_t cpu_stepping() { 513 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; 514 return result; 515 } 516 logical_processor_count()517 static uint logical_processor_count() { 518 uint result = threads_per_core(); 519 return result; 520 } 521 522 static bool compute_has_intel_jcc_erratum(); 523 feature_flags()524 static uint64_t feature_flags() { 525 uint64_t result = 0; 526 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) 527 result |= CPU_CX8; 528 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) 529 result |= CPU_CMOV; 530 if (_cpuid_info.std_cpuid1_edx.bits.clflush != 0) 531 result |= CPU_FLUSH; 532 #ifdef _LP64 533 // clflush should always be available on x86_64 534 // if not we are in real trouble because we rely on it 535 // to flush the code cache. 536 assert ((result & CPU_FLUSH) != 0, "clflush should be available"); 537 #endif 538 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() && 539 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) 540 result |= CPU_FXSR; 541 // HT flag is set for multi-core processors also. 542 if (threads_per_core() > 1) 543 result |= CPU_HT; 544 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() && 545 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) 546 result |= CPU_MMX; 547 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) 548 result |= CPU_SSE; 549 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) 550 result |= CPU_SSE2; 551 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) 552 result |= CPU_SSE3; 553 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) 554 result |= CPU_SSSE3; 555 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) 556 result |= CPU_SSE4_1; 557 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) 558 result |= CPU_SSE4_2; 559 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) 560 result |= CPU_POPCNT; 561 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && 562 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && 563 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && 564 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { 565 result |= CPU_AVX; 566 result |= CPU_VZEROUPPER; 567 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) 568 result |= CPU_AVX2; 569 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 && 570 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 && 571 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 && 572 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) { 573 result |= CPU_AVX512F; 574 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0) 575 result |= CPU_AVX512CD; 576 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0) 577 result |= CPU_AVX512DQ; 578 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0) 579 result |= CPU_AVX512PF; 580 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0) 581 result |= CPU_AVX512ER; 582 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0) 583 result |= CPU_AVX512BW; 584 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0) 585 result |= CPU_AVX512VL; 586 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0) 587 result |= CPU_AVX512_VPOPCNTDQ; 588 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpclmulqdq != 0) 589 result |= CPU_AVX512_VPCLMULQDQ; 590 if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0) 591 result |= CPU_AVX512_VAES; 592 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0) 593 result |= CPU_AVX512_VNNI; 594 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi != 0) 595 result |= CPU_AVX512_VBMI; 596 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi2 != 0) 597 result |= CPU_AVX512_VBMI2; 598 } 599 } 600 if (_cpuid_info.std_cpuid1_ecx.bits.hv != 0) 601 result |= CPU_HV; 602 if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) 603 result |= CPU_BMI1; 604 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) 605 result |= CPU_TSC; 606 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) 607 result |= CPU_TSCINV_BIT; 608 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) 609 result |= CPU_AES; 610 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) 611 result |= CPU_ERMS; 612 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) 613 result |= CPU_CLMUL; 614 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) 615 result |= CPU_RTM; 616 if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0) 617 result |= CPU_ADX; 618 if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) 619 result |= CPU_BMI2; 620 if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0) 621 result |= CPU_SHA; 622 if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0) 623 result |= CPU_FMA; 624 if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0) 625 result |= CPU_FLUSHOPT; 626 627 // AMD|Hygon features. 628 if (is_amd_family()) { 629 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || 630 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) 631 result |= CPU_3DNOW_PREFETCH; 632 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 633 result |= CPU_LZCNT; 634 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 635 result |= CPU_SSE4A; 636 } 637 638 // Intel features. 639 if (is_intel()) { 640 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 641 result |= CPU_LZCNT; 642 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw 643 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { 644 result |= CPU_3DNOW_PREFETCH; 645 } 646 if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) { 647 result |= CPU_CLWB; 648 } 649 } 650 651 // ZX features. 652 if (is_zx()) { 653 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 654 result |= CPU_LZCNT; 655 // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw 656 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { 657 result |= CPU_3DNOW_PREFETCH; 658 } 659 } 660 661 // Composite features. 662 if (supports_tscinv_bit() && 663 ((is_amd_family() && !is_amd_Barcelona()) || 664 is_intel_tsc_synched_at_init())) { 665 result |= CPU_TSCINV; 666 } 667 668 return result; 669 } 670 os_supports_avx_vectors()671 static bool os_supports_avx_vectors() { 672 bool retVal = false; 673 int nreg = 2 LP64_ONLY(+2); 674 if (supports_evex()) { 675 // Verify that OS save/restore all bits of EVEX registers 676 // during signal processing. 677 retVal = true; 678 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register 679 if (_cpuid_info.zmm_save[i] != ymm_test_value()) { 680 retVal = false; 681 break; 682 } 683 } 684 } else if (supports_avx()) { 685 // Verify that OS save/restore all bits of AVX registers 686 // during signal processing. 687 retVal = true; 688 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register 689 if (_cpuid_info.ymm_save[i] != ymm_test_value()) { 690 retVal = false; 691 break; 692 } 693 } 694 // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen 695 if (retVal == false) { 696 // Verify that OS save/restore all bits of EVEX registers 697 // during signal processing. 698 retVal = true; 699 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register 700 if (_cpuid_info.zmm_save[i] != ymm_test_value()) { 701 retVal = false; 702 break; 703 } 704 } 705 } 706 } 707 return retVal; 708 } 709 710 static void get_processor_features(); 711 712 public: 713 // Offsets for cpuid asm stub std_cpuid0_offset()714 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } std_cpuid1_offset()715 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } dcp_cpuid4_offset()716 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } sef_cpuid7_offset()717 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } ext_cpuid1_offset()718 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } ext_cpuid5_offset()719 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } ext_cpuid7_offset()720 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } ext_cpuid8_offset()721 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } ext_cpuid1E_offset()722 static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); } tpl_cpuidB0_offset()723 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } tpl_cpuidB1_offset()724 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } tpl_cpuidB2_offset()725 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } xem_xcr0_offset()726 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } ymm_save_offset()727 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } zmm_save_offset()728 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); } 729 730 // The value used to check ymm register after signal handle ymm_test_value()731 static int ymm_test_value() { return 0xCAFEBABE; } 732 733 static void get_cpu_info_wrapper(); set_cpuinfo_segv_addr(address pc)734 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } is_cpuinfo_segv_addr(address pc)735 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } set_cpuinfo_cont_addr(address pc)736 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } cpuinfo_cont_addr()737 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } 738 clean_cpuFeatures()739 static void clean_cpuFeatures() { _features = 0; } set_avx_cpuFeatures()740 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); } set_evex_cpuFeatures()741 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); } 742 743 744 // Initialization 745 static void initialize(); 746 747 // Override Abstract_VM_Version implementation 748 static void print_platform_virtualization_info(outputStream*); 749 750 // Override Abstract_VM_Version implementation 751 static bool use_biased_locking(); 752 753 // Asserts assert_is_initialized()754 static void assert_is_initialized() { 755 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); 756 } 757 758 // 759 // Processor family: 760 // 3 - 386 761 // 4 - 486 762 // 5 - Pentium 763 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, 764 // Pentium M, Core Solo, Core Duo, Core2 Duo 765 // family 6 model: 9, 13, 14, 15 766 // 0x0f - Pentium 4, Opteron 767 // 768 // Note: The cpu family should be used to select between 769 // instruction sequences which are valid on all Intel 770 // processors. Use the feature test functions below to 771 // determine whether a particular instruction is supported. 772 // cpu_family()773 static int cpu_family() { return _cpu;} is_P6()774 static bool is_P6() { return cpu_family() >= 6; } is_amd()775 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' is_hygon()776 static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH' is_amd_family()777 static bool is_amd_family() { return is_amd() || is_hygon(); } is_intel()778 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' is_zx()779 static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS ' is_atom_family()780 static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton is_knights_family()781 static bool is_knights_family() { return UseKNLSetting || ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi 782 supports_processor_topology()783 static bool supports_processor_topology() { 784 return (_cpuid_info.std_max_function >= 0xB) && 785 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. 786 // Some cpus have max cpuid >= 0xB but do not support processor topology. 787 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); 788 } 789 cores_per_cpu()790 static uint cores_per_cpu() { 791 uint result = 1; 792 if (is_intel()) { 793 bool supports_topology = supports_processor_topology(); 794 if (supports_topology) { 795 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 796 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 797 } 798 if (!supports_topology || result == 0) { 799 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 800 } 801 } else if (is_amd_family()) { 802 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); 803 } else if (is_zx()) { 804 bool supports_topology = supports_processor_topology(); 805 if (supports_topology) { 806 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 807 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 808 } 809 if (!supports_topology || result == 0) { 810 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 811 } 812 } 813 return result; 814 } 815 threads_per_core()816 static uint threads_per_core() { 817 uint result = 1; 818 if (is_intel() && supports_processor_topology()) { 819 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 820 } else if (is_zx() && supports_processor_topology()) { 821 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 822 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { 823 if (cpu_family() >= 0x17) { 824 result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1; 825 } else { 826 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / 827 cores_per_cpu(); 828 } 829 } 830 return (result == 0 ? 1 : result); 831 } 832 L1_line_size()833 static intx L1_line_size() { 834 intx result = 0; 835 if (is_intel()) { 836 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 837 } else if (is_amd_family()) { 838 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; 839 } else if (is_zx()) { 840 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 841 } 842 if (result < 32) // not defined ? 843 result = 32; // 32 bytes by default on x86 and other x64 844 return result; 845 } 846 prefetch_data_size()847 static intx prefetch_data_size() { 848 return L1_line_size(); 849 } 850 851 // 852 // Feature identification 853 // supports_cpuid()854 static bool supports_cpuid() { return _features != 0; } supports_cmpxchg8()855 static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; } supports_cmov()856 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; } supports_fxsr()857 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; } supports_ht()858 static bool supports_ht() { return (_features & CPU_HT) != 0; } supports_mmx()859 static bool supports_mmx() { return (_features & CPU_MMX) != 0; } supports_sse()860 static bool supports_sse() { return (_features & CPU_SSE) != 0; } supports_sse2()861 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; } supports_sse3()862 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; } supports_ssse3()863 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; } supports_sse4_1()864 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; } supports_sse4_2()865 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; } supports_popcnt()866 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; } supports_avx()867 static bool supports_avx() { return (_features & CPU_AVX) != 0; } supports_avx2()868 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; } supports_tsc()869 static bool supports_tsc() { return (_features & CPU_TSC) != 0; } supports_aes()870 static bool supports_aes() { return (_features & CPU_AES) != 0; } supports_erms()871 static bool supports_erms() { return (_features & CPU_ERMS) != 0; } supports_clmul()872 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; } supports_rtm()873 static bool supports_rtm() { return (_features & CPU_RTM) != 0; } supports_bmi1()874 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; } supports_bmi2()875 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; } supports_adx()876 static bool supports_adx() { return (_features & CPU_ADX) != 0; } supports_evex()877 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; } supports_avx512dq()878 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; } supports_avx512pf()879 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; } supports_avx512er()880 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; } supports_avx512cd()881 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; } supports_avx512bw()882 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; } supports_avx512vl()883 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; } supports_avx512vlbw()884 static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); } supports_avx512vldq()885 static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); } supports_avx512vlbwdq()886 static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() && 887 supports_avx512bw() && supports_avx512dq()); } supports_avx512novl()888 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); } supports_avx512nobw()889 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); } supports_avx256only()890 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); } supports_avxonly()891 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); } supports_sha()892 static bool supports_sha() { return (_features & CPU_SHA) != 0; } supports_fma()893 static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); } supports_vzeroupper()894 static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; } supports_avx512_vpopcntdq()895 static bool supports_avx512_vpopcntdq() { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; } supports_avx512_vpclmulqdq()896 static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; } supports_avx512_vaes()897 static bool supports_avx512_vaes() { return (_features & CPU_AVX512_VAES) != 0; } supports_avx512_vnni()898 static bool supports_avx512_vnni() { return (_features & CPU_AVX512_VNNI) != 0; } supports_avx512_vbmi()899 static bool supports_avx512_vbmi() { return (_features & CPU_AVX512_VBMI) != 0; } supports_avx512_vbmi2()900 static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; } supports_hv()901 static bool supports_hv() { return (_features & CPU_HV) != 0; } 902 903 // Intel features is_intel_family_core()904 static bool is_intel_family_core() { return is_intel() && 905 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 906 is_intel_skylake()907 static bool is_intel_skylake() { return is_intel_family_core() && 908 extended_cpu_model() == CPU_MODEL_SKYLAKE; } 909 is_intel_tsc_synched_at_init()910 static bool is_intel_tsc_synched_at_init() { 911 if (is_intel_family_core()) { 912 uint32_t ext_model = extended_cpu_model(); 913 if (ext_model == CPU_MODEL_NEHALEM_EP || 914 ext_model == CPU_MODEL_WESTMERE_EP || 915 ext_model == CPU_MODEL_SANDYBRIDGE_EP || 916 ext_model == CPU_MODEL_IVYBRIDGE_EP) { 917 // <= 2-socket invariant tsc support. EX versions are usually used 918 // in > 2-socket systems and likely don't synchronize tscs at 919 // initialization. 920 // Code that uses tsc values must be prepared for them to arbitrarily 921 // jump forward or backward. 922 return true; 923 } 924 } 925 return false; 926 } 927 928 // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102) 929 // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode 930 // mitigation causes regressions when jumps or fused conditional branches cross or end at 931 // 32 byte boundaries. has_intel_jcc_erratum()932 static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; } 933 934 // AMD features supports_3dnow_prefetch()935 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; } supports_lzcnt()936 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; } supports_sse4a()937 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; } 938 is_amd_Barcelona()939 static bool is_amd_Barcelona() { return is_amd() && 940 extended_cpu_family() == CPU_FAMILY_AMD_11H; } 941 942 // Intel and AMD newer cores support fast timestamps well supports_tscinv_bit()943 static bool supports_tscinv_bit() { 944 return (_features & CPU_TSCINV_BIT) != 0; 945 } supports_tscinv()946 static bool supports_tscinv() { 947 return (_features & CPU_TSCINV) != 0; 948 } 949 950 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). has_fast_idiv()951 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 952 supports_sse3() && _model != 0x1C; } 953 supports_compare_and_exchange()954 static bool supports_compare_and_exchange() { return true; } 955 allocate_prefetch_distance(bool use_watermark_prefetch)956 static intx allocate_prefetch_distance(bool use_watermark_prefetch) { 957 // Hardware prefetching (distance/size in bytes): 958 // Pentium 3 - 64 / 32 959 // Pentium 4 - 256 / 128 960 // Athlon - 64 / 32 ???? 961 // Opteron - 128 / 64 only when 2 sequential cache lines accessed 962 // Core - 128 / 64 963 // 964 // Software prefetching (distance in bytes / instruction with best score): 965 // Pentium 3 - 128 / prefetchnta 966 // Pentium 4 - 512 / prefetchnta 967 // Athlon - 128 / prefetchnta 968 // Opteron - 256 / prefetchnta 969 // Core - 256 / prefetchnta 970 // It will be used only when AllocatePrefetchStyle > 0 971 972 if (is_amd_family()) { // AMD | Hygon 973 if (supports_sse2()) { 974 return 256; // Opteron 975 } else { 976 return 128; // Athlon 977 } 978 } else { // Intel 979 if (supports_sse3() && cpu_family() == 6) { 980 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus 981 return 192; 982 } else if (use_watermark_prefetch) { // watermark prefetching on Core 983 #ifdef _LP64 984 return 384; 985 #else 986 return 320; 987 #endif 988 } 989 } 990 if (supports_sse2()) { 991 if (cpu_family() == 6) { 992 return 256; // Pentium M, Core, Core2 993 } else { 994 return 512; // Pentium 4 995 } 996 } else { 997 return 128; // Pentium 3 (and all other old CPUs) 998 } 999 } 1000 } 1001 1002 // SSE2 and later processors implement a 'pause' instruction 1003 // that can be used for efficient implementation of 1004 // the intrinsic for java.lang.Thread.onSpinWait() supports_on_spin_wait()1005 static bool supports_on_spin_wait() { return supports_sse2(); } 1006 1007 // x86_64 supports fast class initialization checks for static methods. supports_fast_class_init_checks()1008 static bool supports_fast_class_init_checks() { 1009 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32 1010 } 1011 supports_stack_watermark_barrier()1012 constexpr static bool supports_stack_watermark_barrier() { 1013 return true; 1014 } 1015 1016 // there are several insns to force cache line sync to memory which 1017 // we can use to ensure mapped non-volatile memory is up to date with 1018 // pending in-cache changes. 1019 // 1020 // 64 bit cpus always support clflush which writes back and evicts 1021 // on 32 bit cpus support is recorded via a feature flag 1022 // 1023 // clflushopt is optional and acts like clflush except it does 1024 // not synchronize with other memory ops. it needs a preceding 1025 // and trailing StoreStore fence 1026 // 1027 // clwb is an optional intel-specific instruction which 1028 // writes back without evicting the line. it also does not 1029 // synchronize with other memory ops. so, it needs preceding 1030 // and trailing StoreStore fences. 1031 1032 #ifdef _LP64 supports_clflush()1033 static bool supports_clflush() { 1034 // clflush should always be available on x86_64 1035 // if not we are in real trouble because we rely on it 1036 // to flush the code cache. 1037 // Unfortunately, Assembler::clflush is currently called as part 1038 // of generation of the code cache flush routine. This happens 1039 // under Universe::init before the processor features are set 1040 // up. Assembler::flush calls this routine to check that clflush 1041 // is allowed. So, we give the caller a free pass if Universe init 1042 // is still in progress. 1043 assert ((!Universe::is_fully_initialized() || (_features & CPU_FLUSH) != 0), "clflush should be available"); 1044 return true; 1045 } 1046 #else supports_clflush()1047 static bool supports_clflush() { return ((_features & CPU_FLUSH) != 0); } 1048 #endif // _LP64 1049 // Note: CPU_FLUSHOPT and CPU_CLWB bits should always be zero for 32-bit supports_clflushopt()1050 static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); } supports_clwb()1051 static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); } 1052 1053 #ifdef __APPLE__ 1054 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64) 1055 static bool is_cpu_emulated(); 1056 #endif 1057 1058 // support functions for virtualization detection 1059 private: 1060 static void check_virtualizations(); 1061 }; 1062 1063 #endif // CPU_X86_VM_VERSION_X86_HPP 1064