1 /*
2 * Copyright © 2009 Corbin Simpson
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 #ifndef RADEON_DRM_WINSYS_H
28 #define RADEON_DRM_WINSYS_H
29
30 #include "gallium/drivers/radeon/radeon_winsys.h"
31 #include "pipebuffer/pb_cache.h"
32 #include "pipebuffer/pb_slab.h"
33 #include "util/u_queue.h"
34 #include "util/list.h"
35 #include <radeon_drm.h>
36
37 struct radeon_drm_cs;
38
39 enum radeon_generation {
40 DRV_R300,
41 DRV_R600,
42 DRV_SI
43 };
44
45 #define RADEON_SLAB_MIN_SIZE_LOG2 9
46 #define RADEON_SLAB_MAX_SIZE_LOG2 14
47
48 struct radeon_vm_heap {
49 mtx_t mutex;
50 uint64_t start;
51 uint64_t end;
52 struct list_head holes;
53 };
54
55 struct radeon_drm_winsys {
56 struct radeon_winsys base;
57 struct pipe_reference reference;
58 struct pb_cache bo_cache;
59 struct pb_slabs bo_slabs;
60
61 int fd; /* DRM file descriptor */
62 int num_cs; /* The number of command streams created. */
63 uint64_t allocated_vram;
64 uint64_t allocated_gtt;
65 uint64_t mapped_vram;
66 uint64_t mapped_gtt;
67 uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
68 uint64_t num_gfx_IBs;
69 uint64_t num_sdma_IBs;
70 uint64_t num_mapped_buffers;
71 uint32_t next_bo_hash;
72
73 enum radeon_generation gen;
74 struct radeon_info info;
75 uint32_t va_start;
76 uint32_t va_unmap_working;
77 uint32_t accel_working2;
78
79 /* List of buffer GEM names. Protected by bo_handles_mutex. */
80 struct hash_table *bo_names;
81 /* List of buffer handles. Protected by bo_handles_mutex. */
82 struct hash_table *bo_handles;
83 /* List of buffer virtual memory ranges. Protected by bo_handles_mutex. */
84 struct hash_table_u64 *bo_vas;
85 mtx_t bo_handles_mutex;
86 mtx_t bo_fence_lock;
87
88 struct radeon_vm_heap vm32;
89 struct radeon_vm_heap vm64;
90
91 bool check_vm;
92 bool noop_cs;
93
94 struct radeon_surface_manager *surf_man;
95
96 uint32_t num_cpus; /* Number of CPUs. */
97
98 struct radeon_drm_cs *hyperz_owner;
99 mtx_t hyperz_owner_mutex;
100 struct radeon_drm_cs *cmask_owner;
101 mtx_t cmask_owner_mutex;
102
103 /* multithreaded command submission */
104 struct util_queue cs_queue;
105 };
106
radeon_drm_winsys(struct radeon_winsys * base)107 static inline struct radeon_drm_winsys *radeon_drm_winsys(struct radeon_winsys *base)
108 {
109 return (struct radeon_drm_winsys*)base;
110 }
111
112 uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws);
113 void radeon_surface_init_functions(struct radeon_drm_winsys *ws);
114
115 #endif
116