1{$IFDEF OGC_INTERFACE} 2 3{$ifdef _LANGUAGE_ASSEMBLY} 4(* Condition Register Bit Fields *) 5 6const 7 cr0 = 0; 8 cr1 = 1; 9 cr2 = 2; 10 cr3 = 3; 11 cr4 = 4; 12 cr5 = 5; 13 cr6 = 6; 14 cr7 = 7; 15 16 (* General Purpose Registers (GPRs) *) 17 r0 = 0; 18 r1 = 1; 19 sp = 1; 20 r2 = 2; 21 toc = 2; 22 r3 = 3; 23 r4 = 4; 24 r5 = 5; 25 r6 = 6; 26 r7 = 7; 27 r8 = 8; 28 r9 = 9; 29 r10 = 10; 30 r11 = 11; 31 r12 = 12; 32 r13 = 13; 33 r14 = 14; 34 r15 = 15; 35 r16 = 16; 36 r17 = 17; 37 r18 = 18; 38 r19 = 19; 39 r20 = 20; 40 r21 = 21; 41 r22 = 22; 42 r23 = 23; 43 r24 = 24; 44 r25 = 25; 45 r26 = 26; 46 r27 = 27; 47 r28 = 28; 48 r29 = 29; 49 r30 = 30; 50 r31 = 31; 51 52 (* Floating Point Registers (FPRs) *) 53 fr0 = 0; 54 fr1 = 1; 55 fr2 = 2; 56 fr3 = 3; 57 fr4 = 4; 58 fr5 = 5; 59 fr6 = 6; 60 fr7 = 7; 61 fr8 = 8; 62 fr9 = 9; 63 fr10 = 10; 64 fr11 = 11; 65 fr12 = 12; 66 fr13 = 13; 67 fr14 = 14; 68 fr15 = 15; 69 fr16 = 16; 70 fr17 = 17; 71 fr18 = 18; 72 fr19 = 19; 73 fr20 = 20; 74 fr21 = 21; 75 fr22 = 22; 76 fr23 = 23; 77 fr24 = 24; 78 fr25 = 25; 79 fr26 = 26; 80 fr27 = 27; 81 fr28 = 28; 82 fr29 = 29; 83 fr30 = 30; 84 fr31 = 31; 85 vr0 = 0; 86 vr1 = 1; 87 vr2 = 2; 88 vr3 = 3; 89 vr4 = 4; 90 vr5 = 5; 91 vr6 = 6; 92 vr7 = 7; 93 vr8 = 8; 94 vr9 = 9; 95 vr10 = 10; 96 vr11 = 11; 97 vr12 = 12; 98 vr13 = 13; 99 vr14 = 14; 100 vr15 = 15; 101 vr16 = 16; 102 vr17 = 17; 103 vr18 = 18; 104 vr19 = 19; 105 vr20 = 20; 106 vr21 = 21; 107 vr22 = 22; 108 vr23 = 23; 109 vr24 = 24; 110 vr25 = 25; 111 vr26 = 26; 112 vr27 = 27; 113 vr28 = 28; 114 vr29 = 29; 115 vr30 = 30; 116 vr31 = 31; 117{$endif _LANGUAGE_ASSEMBLY} 118 119const 120 SPRG0 = 272; 121 SPRG1 = 273; 122 SPRG2 = 274; 123 SPRG3 = 275; 124 PMC1 = 953; 125 PMC2 = 954; 126 PMC3 = 957; 127 PMC4 = 958; 128 MMCR0 = 952; 129 MMCR1 = 956; 130 LINK_REGISTER_CALLEE_UPDATE_ROOM = 4; 131 EXCEPTION_NUMBER = 8; 132 SRR0_OFFSET = 12; 133 SRR1_OFFSET = 16; 134 GPR0_OFFSET = 20; 135 GPR1_OFFSET = 24; 136 GPR2_OFFSET = 28; 137 GPR3_OFFSET = 32; 138 GPR4_OFFSET = 36; 139 GPR5_OFFSET = 40; 140 GPR6_OFFSET = 44; 141 GPR7_OFFSET = 48; 142 GPR8_OFFSET = 52; 143 GPR9_OFFSET = 56; 144 GPR10_OFFSET = 60; 145 GPR11_OFFSET = 64; 146 GPR12_OFFSET = 68; 147 GPR13_OFFSET = 72; 148 GPR14_OFFSET = 76; 149 GPR15_OFFSET = 80; 150 GPR16_OFFSET = 84; 151 GPR17_OFFSET = 88; 152 GPR18_OFFSET = 92; 153 GPR19_OFFSET = 96; 154 GPR20_OFFSET = 100; 155 GPR21_OFFSET = 104; 156 GPR22_OFFSET = 108; 157 GPR23_OFFSET = 112; 158 GPR24_OFFSET = 116; 159 GPR25_OFFSET = 120; 160 GPR26_OFFSET = 124; 161 GPR27_OFFSET = 128; 162 GPR28_OFFSET = 132; 163 GPR29_OFFSET = 136; 164 GPR30_OFFSET = 140; 165 GPR31_OFFSET = 144; 166 GQR0_OFFSET = 148; 167 GQR1_OFFSET = 152; 168 GQR2_OFFSET = 156; 169 GQR3_OFFSET = 160; 170 GQR4_OFFSET = 164; 171 GQR5_OFFSET = 168; 172 GQR6_OFFSET = 172; 173 GQR7_OFFSET = 176; 174 CR_OFFSET = 180; 175 LR_OFFSET = 184; 176 CTR_OFFSET = 188; 177 XER_OFFSET = 192; 178 MSR_OFFSET = 196; 179 DAR_OFFSET = 200; 180 STATE_OFFSET = 204; 181 MODE_OFFSET = 206; 182 183 FPR0_OFFSET = 208; 184 FPR1_OFFSET = 216; 185 FPR2_OFFSET = 224; 186 FPR3_OFFSET = 232; 187 FPR4_OFFSET = 240; 188 FPR5_OFFSET = 248; 189 FPR6_OFFSET = 256; 190 FPR7_OFFSET = 264; 191 FPR8_OFFSET = 272; 192 FPR9_OFFSET = 280; 193 FPR10_OFFSET = 288; 194 FPR11_OFFSET = 296; 195 FPR12_OFFSET = 304; 196 FPR13_OFFSET = 312; 197 FPR14_OFFSET = 320; 198 FPR15_OFFSET = 328; 199 FPR16_OFFSET = 336; 200 FPR17_OFFSET = 344; 201 FPR18_OFFSET = 352; 202 FPR19_OFFSET = 360; 203 FPR20_OFFSET = 368; 204 FPR21_OFFSET = 376; 205 FPR22_OFFSET = 384; 206 FPR23_OFFSET = 392; 207 FPR24_OFFSET = 400; 208 FPR25_OFFSET = 408; 209 FPR26_OFFSET = 416; 210 FPR27_OFFSET = 424; 211 FPR28_OFFSET = 432; 212 FPR29_OFFSET = 440; 213 FPR30_OFFSET = 448; 214 FPR31_OFFSET = 456; 215 FPSCR_OFFSET = 464; 216 PSR0_OFFSET = 472; 217 PSR1_OFFSET = 480; 218 PSR2_OFFSET = 488; 219 PSR3_OFFSET = 496; 220 PSR4_OFFSET = 504; 221 PSR5_OFFSET = 512; 222 PSR6_OFFSET = 520; 223 PSR7_OFFSET = 528; 224 PSR8_OFFSET = 536; 225 PSR9_OFFSET = 544; 226 PSR10_OFFSET = 552; 227 PSR11_OFFSET = 560; 228 PSR12_OFFSET = 568; 229 PSR13_OFFSET = 576; 230 PSR14_OFFSET = 584; 231 PSR15_OFFSET = 592; 232 PSR16_OFFSET = 600; 233 PSR17_OFFSET = 608; 234 PSR18_OFFSET = 616; 235 PSR19_OFFSET = 624; 236 PSR20_OFFSET = 632; 237 PSR21_OFFSET = 640; 238 PSR22_OFFSET = 648; 239 PSR23_OFFSET = 656; 240 PSR24_OFFSET = 664; 241 PSR25_OFFSET = 672; 242 PSR26_OFFSET = 680; 243 PSR27_OFFSET = 688; 244 PSR28_OFFSET = 696; 245 PSR29_OFFSET = 704; 246 PSR30_OFFSET = 712; 247 PSR31_OFFSET = 720; 248 (* 249 * maintain the EABI requested 8 bytes aligment 250 * As SVR4 ABI requires 16, make it 16 (as some 251 * exception may need more registers to be processed...) 252 *) 253 254 EXCEPTION_FRAME_END = 728; 255 IBAT0U = 528; 256 IBAT0L = 529; 257 IBAT1U = 530; 258 IBAT1L = 531; 259 IBAT2U = 532; 260 IBAT2L = 533; 261 IBAT3U = 534; 262 IBAT3L = 535; 263 IBAT4U = 560; 264 IBAT4L = 561; 265 IBAT5U = 562; 266 IBAT5L = 563; 267 IBAT6U = 564; 268 IBAT6L = 565; 269 IBAT7U = 566; 270 IBAT7L = 567; 271 DBAT0U = 536; 272 DBAT0L = 537; 273 DBAT1U = 538; 274 DBAT1L = 539; 275 DBAT2U = 540; 276 DBAT2L = 541; 277 DBAT3U = 542; 278 DBAT3L = 543; 279 DBAT4U = 568; 280 DBAT4L = 569; 281 DBAT5U = 570; 282 DBAT5L = 571; 283 DBAT6U = 572; 284 DBAT6L = 573; 285 DBAT7U = 574; 286 DBAT7L = 575; 287 HID0 = 1008; 288 HID1 = 1009; 289 HID2 = 920; 290 HID4 = 1011; 291 GQR0 = 912; 292 GQR1 = 913; 293 GQR2 = 914; 294 GQR3 = 915; 295 GQR4 = 916; 296 GQR5 = 917; 297 GQR6 = 918; 298 GQR7 = 919; 299 L2CR = 1017; 300 WPAR = 921; 301 DMAU = 922; 302 DMAL = 923; 303 MSR_RI = $00000002; 304 MSR_DR = $00000010; 305 MSR_IR = $00000020; 306 MSR_IP = $00000040; 307 MSR_SE = $00000400; 308 MSR_ME = $00001000; 309 MSR_FP = $00002000; 310 MSR_POW = $00004000; 311 MSR_EE = $00008000; 312 PPC_ALIGNMENT = 8; 313 PPC_CACHE_ALIGNMENT = 32; 314{$ENDIF OGC_INTERFACE} 315 316