1unit stm32f429xx; 2interface 3{$PACKRECORDS 2} 4{$GOTO ON} 5{$MODESWITCH ADVANCEDRECORDS} 6// * 7// ****************************************************************************** 8// * @file stm32f429xx.h 9// * @author MCD Application Team 10// * @version V2.4.0 11// * @date 14-August-2015 12// CMSIS STM32F429xx Device Peripheral Access Layer Header File. 13// * 14// * This file contains: 15// * - Data structures and the address mapping for all peripherals 16// * - Peripheral's registers declarations and bits definition 17// * - Macros to access peripheral�s registers hardware 18// * 19// ****************************************************************************** 20// * @attention 21// * 22// * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 23// * 24// * Redistribution and use in source and binary forms, with or without modification, 25// * are permitted provided that the following conditions are met: 26// * 1. Redistributions of source code must retain the above copyright notice, 27// * this list of conditions and the following disclaimer. 28// * 2. Redistributions in binary form must reproduce the above copyright notice, 29// * this list of conditions and the following disclaimer in the documentation 30// * and/or other materials provided with the distribution. 31// * 3. Neither the name of STMicroelectronics nor the names of its contributors 32// * may be used to endorse or promote products derived from this software 33// * without specific prior written permission. 34// * 35// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 36// * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37// * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 38// * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 39// * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40// * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 41// * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 42// * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 43// * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44// * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45// * 46// ****************************************************************************** 47// Configuration of the Cortex-M4 Processor and Core Peripherals 48// STM32F4XX Interrupt Number Definition, according to the selected device 49// * in @ref Library_configuration_section 50 51type 52 TIRQn_Enum = ( 53 NonMaskableInt_IRQn = -14, // 2 Non Maskable Interrupt 54 MemoryManagement_IRQn = -12, // 4 Cortex-M4 Memory Management Interrupt 55 BusFault_IRQn = -11, // 5 Cortex-M4 Bus Fault Interrupt 56 UsageFault_IRQn = -10, // 6 Cortex-M4 Usage Fault Interrupt 57 SVCall_IRQn = -5, // 11 Cortex-M4 SV Call Interrupt 58 DebugMonitor_IRQn = -4, // 12 Cortex-M4 Debug Monitor Interrupt 59 PendSV_IRQn = -2, // 14 Cortex-M4 Pend SV Interrupt 60 SysTick_IRQn = -1, // 15 Cortex-M4 System Tick Interrupt 61 WWDG_IRQn = 0, // Window WatchDog Interrupt 62 PVD_IRQn = 1, // PVD through EXTI Line detection Interrupt 63 TAMP_STAMP_IRQn = 2, // Tamper and TimeStamp interrupts through the EXTI line 64 RTC_WKUP_IRQn = 3, // RTC Wakeup interrupt through the EXTI line 65 FLASH_IRQn = 4, // FLASH global Interrupt 66 RCC_IRQn = 5, // RCC global Interrupt 67 EXTI0_IRQn = 6, // EXTI Line0 Interrupt 68 EXTI1_IRQn = 7, // EXTI Line1 Interrupt 69 EXTI2_IRQn = 8, // EXTI Line2 Interrupt 70 EXTI3_IRQn = 9, // EXTI Line3 Interrupt 71 EXTI4_IRQn = 10, // EXTI Line4 Interrupt 72 DMA1_Stream0_IRQn = 11, // DMA1 Stream 0 global Interrupt 73 DMA1_Stream1_IRQn = 12, // DMA1 Stream 1 global Interrupt 74 DMA1_Stream2_IRQn = 13, // DMA1 Stream 2 global Interrupt 75 DMA1_Stream3_IRQn = 14, // DMA1 Stream 3 global Interrupt 76 DMA1_Stream4_IRQn = 15, // DMA1 Stream 4 global Interrupt 77 DMA1_Stream5_IRQn = 16, // DMA1 Stream 5 global Interrupt 78 DMA1_Stream6_IRQn = 17, // DMA1 Stream 6 global Interrupt 79 ADC_IRQn = 18, // ADC1, ADC2 and ADC3 global Interrupts 80 CAN1_TX_IRQn = 19, // CAN1 TX Interrupt 81 CAN1_RX0_IRQn = 20, // CAN1 RX0 Interrupt 82 CAN1_RX1_IRQn = 21, // CAN1 RX1 Interrupt 83 CAN1_SCE_IRQn = 22, // CAN1 SCE Interrupt 84 EXTI9_5_IRQn = 23, // External Line[9:5] Interrupts 85 TIM1_BRK_TIM9_IRQn = 24, // TIM1 Break interrupt and TIM9 global interrupt 86 TIM1_UP_TIM10_IRQn = 25, // TIM1 Update Interrupt and TIM10 global interrupt 87 TIM1_TRG_COM_TIM11_IRQn = 26, // TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt 88 TIM1_CC_IRQn = 27, // TIM1 Capture Compare Interrupt 89 TIM2_IRQn = 28, // TIM2 global Interrupt 90 TIM3_IRQn = 29, // TIM3 global Interrupt 91 TIM4_IRQn = 30, // TIM4 global Interrupt 92 I2C1_EV_IRQn = 31, // I2C1 Event Interrupt 93 I2C1_ER_IRQn = 32, // I2C1 Error Interrupt 94 I2C2_EV_IRQn = 33, // I2C2 Event Interrupt 95 I2C2_ER_IRQn = 34, // I2C2 Error Interrupt 96 SPI1_IRQn = 35, // SPI1 global Interrupt 97 SPI2_IRQn = 36, // SPI2 global Interrupt 98 USART1_IRQn = 37, // USART1 global Interrupt 99 USART2_IRQn = 38, // USART2 global Interrupt 100 USART3_IRQn = 39, // USART3 global Interrupt 101 EXTI15_10_IRQn = 40, // External Line[15:10] Interrupts 102 RTC_Alarm_IRQn = 41, // RTC Alarm (A and B) through EXTI Line Interrupt 103 OTG_FS_WKUP_IRQn = 42, // USB OTG FS Wakeup through EXTI line interrupt 104 TIM8_BRK_TIM12_IRQn = 43, // TIM8 Break Interrupt and TIM12 global interrupt 105 TIM8_UP_TIM13_IRQn = 44, // TIM8 Update Interrupt and TIM13 global interrupt 106 TIM8_TRG_COM_TIM14_IRQn = 45, // TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt 107 TIM8_CC_IRQn = 46, // TIM8 Capture Compare Interrupt 108 DMA1_Stream7_IRQn = 47, // DMA1 Stream7 Interrupt 109 FMC_IRQn = 48, // FMC global Interrupt 110 SDIO_IRQn = 49, // SDIO global Interrupt 111 TIM5_IRQn = 50, // TIM5 global Interrupt 112 SPI3_IRQn = 51, // SPI3 global Interrupt 113 UART4_IRQn = 52, // UART4 global Interrupt 114 UART5_IRQn = 53, // UART5 global Interrupt 115 TIM6_DAC_IRQn = 54, // TIM6 global and DAC1&2 underrun error interrupts 116 TIM7_IRQn = 55, // TIM7 global interrupt 117 DMA2_Stream0_IRQn = 56, // DMA2 Stream 0 global Interrupt 118 DMA2_Stream1_IRQn = 57, // DMA2 Stream 1 global Interrupt 119 DMA2_Stream2_IRQn = 58, // DMA2 Stream 2 global Interrupt 120 DMA2_Stream3_IRQn = 59, // DMA2 Stream 3 global Interrupt 121 DMA2_Stream4_IRQn = 60, // DMA2 Stream 4 global Interrupt 122 ETH_IRQn = 61, // Ethernet global Interrupt 123 ETH_WKUP_IRQn = 62, // Ethernet Wakeup through EXTI line Interrupt 124 CAN2_TX_IRQn = 63, // CAN2 TX Interrupt 125 CAN2_RX0_IRQn = 64, // CAN2 RX0 Interrupt 126 CAN2_RX1_IRQn = 65, // CAN2 RX1 Interrupt 127 CAN2_SCE_IRQn = 66, // CAN2 SCE Interrupt 128 OTG_FS_IRQn = 67, // USB OTG FS global Interrupt 129 DMA2_Stream5_IRQn = 68, // DMA2 Stream 5 global interrupt 130 DMA2_Stream6_IRQn = 69, // DMA2 Stream 6 global interrupt 131 DMA2_Stream7_IRQn = 70, // DMA2 Stream 7 global interrupt 132 USART6_IRQn = 71, // USART6 global interrupt 133 I2C3_EV_IRQn = 72, // I2C3 event interrupt 134 I2C3_ER_IRQn = 73, // I2C3 error interrupt 135 OTG_HS_EP1_OUT_IRQn = 74, // USB OTG HS End Point 1 Out global interrupt 136 OTG_HS_EP1_IN_IRQn = 75, // USB OTG HS End Point 1 In global interrupt 137 OTG_HS_WKUP_IRQn = 76, // USB OTG HS Wakeup through EXTI interrupt 138 OTG_HS_IRQn = 77, // USB OTG HS global interrupt 139 DCMI_IRQn = 78, // DCMI global interrupt 140 HASH_RNG_IRQn = 80, // Hash and RNG global interrupt 141 FPU_IRQn = 81, // FPU global interrupt 142 UART7_IRQn = 82, // UART7 global interrupt 143 UART8_IRQn = 83, // UART8 global interrupt 144 SPI4_IRQn = 84, // SPI4 global Interrupt 145 SPI5_IRQn = 85, // SPI5 global Interrupt 146 SPI6_IRQn = 86, // SPI6 global Interrupt 147 SAI1_IRQn = 87, // SAI1 global Interrupt 148 LTDC_IRQn = 88, // LTDC global Interrupt 149 LTDC_ER_IRQn = 89, // LTDC Error global Interrupt 150 DMA2D_IRQn = 90 // DMA2D global Interrupt 151 ); 152 153 TADC_Registers = record 154 SR : longword; // ADC status register 155 CR1 : longword; // ADC control register 1 156 CR2 : longword; // ADC control register 2 157 SMPR1 : longword; // ADC sample time register 1 158 SMPR2 : longword; // ADC sample time register 2 159 JOFR1 : longword; // ADC injected channel data offset register 1 160 JOFR2 : longword; // ADC injected channel data offset register 2 161 JOFR3 : longword; // ADC injected channel data offset register 3 162 JOFR4 : longword; // ADC injected channel data offset register 4 163 HTR : longword; // ADC watchdog higher threshold register 164 LTR : longword; // ADC watchdog lower threshold register 165 SQR1 : longword; // ADC regular sequence register 1 166 SQR2 : longword; // ADC regular sequence register 2 167 SQR3 : longword; // ADC regular sequence register 3 168 JSQR : longword; // ADC injected sequence register 169 JDR1 : longword; // ADC injected data register 1 170 JDR2 : longword; // ADC injected data register 2 171 JDR3 : longword; // ADC injected data register 3 172 JDR4 : longword; // ADC injected data register 4 173 DR : longword; // ADC regular data register 174 end; 175 176 TADC_COMMON_Registers = record 177 CSR : longword; // ADC Common status register 178 CCR : longword; // ADC common control register 179 CDR : longword; // ADC common regular data register for dual 180 end; 181 182 TCAN_TXMAILBOX_Registers = record 183 TIR : longword; // CAN TX mailbox identifier register 184 TDTR : longword; // CAN mailbox data length control and time stamp register 185 TDLR : longword; // CAN mailbox data low register 186 TDHR : longword; // CAN mailbox data high register 187 end; 188 189 TCAN_FIFOMAILBOX_Registers = record 190 RIR : longword; // CAN receive FIFO mailbox identifier register 191 RDTR : longword; // CAN receive FIFO mailbox data length control and time stamp register 192 RDLR : longword; // CAN receive FIFO mailbox data low register 193 RDHR : longword; // CAN receive FIFO mailbox data high register 194 end; 195 196 TCAN_FILTERREGISTER_Registers = record 197 FR1 : longword; // CAN Filter bank register 1 198 FR2 : longword; // CAN Filter bank register 1 199 end; 200 201 TCAN_Registers = record 202 MCR : longword; // CAN master control register 203 MSR : longword; // CAN master status register 204 TSR : longword; // CAN transmit status register 205 RF0R : longword; // CAN receive FIFO 0 register 206 RF1R : longword; // CAN receive FIFO 1 register 207 IER : longword; // CAN interrupt enable register 208 ESR : longword; // CAN error status register 209 BTR : longword; // CAN bit timing register 210 RESERVED0 : array[0..87] of longword; // Reserved, 0x020 - 0x17F 211 sTxMailBox : array[0..2] of TCAN_TXMAILBOX_Registers; // CAN Tx MailBox 212 sFIFOMailBox : array[0..1] of TCAN_FIFOMAILBOX_Registers; // CAN FIFO MailBox 213 RESERVED1 : array[0..11] of longword; // Reserved, 0x1D0 - 0x1FF 214 FMR : longword; // CAN filter master register 215 FM1R : longword; // CAN filter mode register 216 RESERVED2 : longword; // Reserved, 0x208 217 FS1R : longword; // CAN filter scale register 218 RESERVED3 : longword; // Reserved, 0x210 219 FFA1R : longword; // CAN filter FIFO assignment register 220 RESERVED4 : longword; // Reserved, 0x218 221 FA1R : longword; // CAN filter activation register 222 RESERVED5 : array[0..7] of longword; // Reserved, 0x220-0x23F 223 sFilterRegister : array[0..27] of TCAN_FILTERREGISTER_Registers; // CAN Filter Register 224 end; 225 226 TCRC_Registers = record 227 DR : longword; // CRC Data register 228 IDR : byte; // CRC Independent data register 229 RESERVED0 : byte; // Reserved, 0x05 230 RESERVED1 : word; // Reserved, 0x06 231 CR : longword; // CRC Control register 232 end; 233 234 TDAC_Registers = record 235 CR : longword; // DAC control register 236 SWTRIGR : longword; // DAC software trigger register 237 DHR12R1 : longword; // DAC channel1 12-bit right-aligned data holding register 238 DHR12L1 : longword; // DAC channel1 12-bit left aligned data holding register 239 DHR8R1 : longword; // DAC channel1 8-bit right aligned data holding register 240 DHR12R2 : longword; // DAC channel2 12-bit right aligned data holding register 241 DHR12L2 : longword; // DAC channel2 12-bit left aligned data holding register 242 DHR8R2 : longword; // DAC channel2 8-bit right-aligned data holding register 243 DHR12RD : longword; // Dual DAC 12-bit right-aligned data holding register 244 DHR12LD : longword; // DUAL DAC 12-bit left aligned data holding register 245 DHR8RD : longword; // DUAL DAC 8-bit right aligned data holding register 246 DOR1 : longword; // DAC channel1 data output register 247 DOR2 : longword; // DAC channel2 data output register 248 SR : longword; // DAC status register 249 end; 250 251 TDBGMCU_Registers = record 252 IDCODE : longword; // MCU device ID code 253 CR : longword; // Debug MCU configuration register 254 APB1FZ : longword; // Debug MCU APB1 freeze register 255 APB2FZ : longword; // Debug MCU APB2 freeze register 256 end; 257 258 TDCMI_Registers = record 259 CR : longword; // DCMI control register 1 260 SR : longword; // DCMI status register 261 RISR : longword; // DCMI raw interrupt status register 262 IER : longword; // DCMI interrupt enable register 263 MISR : longword; // DCMI masked interrupt status register 264 ICR : longword; // DCMI interrupt clear register 265 ESCR : longword; // DCMI embedded synchronization code register 266 ESUR : longword; // DCMI embedded synchronization unmask register 267 CWSTRTR : longword; // DCMI crop window start 268 CWSIZER : longword; // DCMI crop window size 269 DR : longword; // DCMI data register 270 end; 271 272 TDMA_STREAM_Registers = record 273 CR : longword; // DMA stream x configuration register 274 NDTR : longword; // DMA stream x number of data register 275 PAR : longword; // DMA stream x peripheral address register 276 M0AR : longword; // DMA stream x memory 0 address register 277 M1AR : longword; // DMA stream x memory 1 address register 278 FCR : longword; // DMA stream x FIFO control register 279 end; 280 281 TDMA_Registers = record 282 LISR : longword; // DMA low interrupt status register 283 HISR : longword; // DMA high interrupt status register 284 LIFCR : longword; // DMA low interrupt flag clear register 285 HIFCR : longword; // DMA high interrupt flag clear register 286 end; 287 288 TDMA2D_Registers = record 289 CR : longword; // DMA2D Control Register 290 ISR : longword; // DMA2D Interrupt Status Register 291 IFCR : longword; // DMA2D Interrupt Flag Clear Register 292 FGMAR : longword; // DMA2D Foreground Memory Address Register 293 FGOR : longword; // DMA2D Foreground Offset Register 294 BGMAR : longword; // DMA2D Background Memory Address Register 295 BGOR : longword; // DMA2D Background Offset Register 296 FGPFCCR : longword; // DMA2D Foreground PFC Control Register 297 FGCOLR : longword; // DMA2D Foreground Color Register 298 BGPFCCR : longword; // DMA2D Background PFC Control Register 299 BGCOLR : longword; // DMA2D Background Color Register 300 FGCMAR : longword; // DMA2D Foreground CLUT Memory Address Register 301 BGCMAR : longword; // DMA2D Background CLUT Memory Address Register 302 OPFCCR : longword; // DMA2D Output PFC Control Register 303 OCOLR : longword; // DMA2D Output Color Register 304 OMAR : longword; // DMA2D Output Memory Address Register 305 OOR : longword; // DMA2D Output Offset Register 306 NLR : longword; // DMA2D Number of Line Register 307 LWR : longword; // DMA2D Line Watermark Register 308 AMTCR : longword; // DMA2D AHB Master Timer Configuration Register 309 RESERVED : array[0..235] of longword; // Reserved, 0x50-0x3FF 310 FGCLUT : array[0..255] of longword; // DMA2D Foreground CLUT 311 BGCLUT : array[0..255] of longword; // DMA2D Background CLUT 312 end; 313 314 TETH_Registers = record 315 MACCR : longword; 316 MACFFR : longword; 317 MACHTHR : longword; 318 MACHTLR : longword; 319 MACMIIAR : longword; 320 MACMIIDR : longword; 321 MACFCR : longword; 322 MACVLANTR : longword; // 8 323 RESERVED0 : array[0..1] of longword; 324 MACRWUFFR : longword; // 11 325 MACPMTCSR : longword; 326 RESERVED1 : array[0..1] of longword; 327 MACSR : longword; // 15 328 MACIMR : longword; 329 MACA0HR : longword; 330 MACA0LR : longword; 331 MACA1HR : longword; 332 MACA1LR : longword; 333 MACA2HR : longword; 334 MACA2LR : longword; 335 MACA3HR : longword; 336 MACA3LR : longword; // 24 337 RESERVED2 : array[0..39] of longword; 338 MMCCR : longword; // 65 339 MMCRIR : longword; 340 MMCTIR : longword; 341 MMCRIMR : longword; 342 MMCTIMR : longword; // 69 343 RESERVED3 : array[0..13] of longword; 344 MMCTGFSCCR : longword; // 84 345 MMCTGFMSCCR : longword; 346 RESERVED4 : array[0..4] of longword; 347 MMCTGFCR : longword; 348 RESERVED5 : array[0..9] of longword; 349 MMCRFCECR : longword; 350 MMCRFAECR : longword; 351 RESERVED6 : array[0..9] of longword; 352 MMCRGUFCR : longword; 353 RESERVED7 : array[0..333] of longword; 354 PTPTSCR : longword; 355 PTPSSIR : longword; 356 PTPTSHR : longword; 357 PTPTSLR : longword; 358 PTPTSHUR : longword; 359 PTPTSLUR : longword; 360 PTPTSAR : longword; 361 PTPTTHR : longword; 362 PTPTTLR : longword; 363 RESERVED8 : longword; 364 PTPTSSR : longword; 365 RESERVED9 : array[0..564] of longword; 366 DMABMR : longword; 367 DMATPDR : longword; 368 DMARPDR : longword; 369 DMARDLAR : longword; 370 DMATDLAR : longword; 371 DMASR : longword; 372 DMAOMR : longword; 373 DMAIER : longword; 374 DMAMFBOCR : longword; 375 DMARSWTR : longword; 376 RESERVED10 : array[0..7] of longword; 377 DMACHTDR : longword; 378 DMACHRDR : longword; 379 DMACHTBAR : longword; 380 DMACHRBAR : longword; 381 end; 382 383 TEXTI_Registers = record 384 IMR : longword; // EXTI Interrupt mask register 385 EMR : longword; // EXTI Event mask register 386 RTSR : longword; // EXTI Rising trigger selection register 387 FTSR : longword; // EXTI Falling trigger selection register 388 SWIER : longword; // EXTI Software interrupt event register 389 PR : longword; // EXTI Pending register 390 end; 391 392 TFLASH_Registers = record 393 ACR : longword; // FLASH access control register 394 KEYR : longword; // FLASH key register 395 OPTKEYR : longword; // FLASH option key register 396 SR : longword; // FLASH status register 397 CR : longword; // FLASH control register 398 OPTCR : longword; // FLASH option control register 399 OPTCR1 : longword; // FLASH option control register 1 400 end; 401 402 TFMC_BANK1_Registers = record 403 BTCR : array[0..7] of longword; // NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 404 end; 405 406 TFMC_BANK1E_Registers = record 407 BWTR : array[0..6] of longword; // NOR/PSRAM write timing registers 408 end; 409 410 TFMC_BANK2_3_Registers = record 411 PCR2 : longword; // NAND Flash control register 2 412 SR2 : longword; // NAND Flash FIFO status and interrupt register 2 413 PMEM2 : longword; // NAND Flash Common memory space timing register 2 414 PATT2 : longword; // NAND Flash Attribute memory space timing register 2 415 RESERVED0 : longword; // Reserved, 0x70 416 ECCR2 : longword; // NAND Flash ECC result registers 2 417 RESERVED1 : longword; // Reserved, 0x78 418 RESERVED2 : longword; // Reserved, 0x7C 419 PCR3 : longword; // NAND Flash control register 3 420 SR3 : longword; // NAND Flash FIFO status and interrupt register 3 421 PMEM3 : longword; // NAND Flash Common memory space timing register 3 422 PATT3 : longword; // NAND Flash Attribute memory space timing register 3 423 RESERVED3 : longword; // Reserved, 0x90 424 ECCR3 : longword; // NAND Flash ECC result registers 3 425 end; 426 427 TFMC_BANK4_Registers = record 428 PCR4 : longword; // PC Card control register 4 429 SR4 : longword; // PC Card FIFO status and interrupt register 4 430 PMEM4 : longword; // PC Card Common memory space timing register 4 431 PATT4 : longword; // PC Card Attribute memory space timing register 4 432 PIO4 : longword; // PC Card I/O space timing register 4 433 end; 434 435 TFMC_BANK5_6_Registers = record 436 SDCR : array[0..1] of longword; // SDRAM Control registers 437 SDTR : array[0..1] of longword; // SDRAM Timing registers 438 SDCMR : longword; // SDRAM Command Mode register 439 SDRTR : longword; // SDRAM Refresh Timer register 440 SDSR : longword; // SDRAM Status register 441 end; 442 443 TGPIO_Registers = record 444 MODER : longword; // GPIO port mode register 445 OTYPER : longword; // GPIO port output type register 446 OSPEEDR : longword; // GPIO port output speed register 447 PUPDR : longword; // GPIO port pull-up/pull-down register 448 IDR : longword; // GPIO port input data register 449 ODR : longword; // GPIO port output data register 450 BSRR : longword; // GPIO port bit set/reset register 451 LCKR : longword; // GPIO port configuration lock register 452 AFR : array[0..1] of longword; // GPIO alternate function registers 453 end; 454 455 TSYSCFG_Registers = record 456 MEMRMP : longword; // SYSCFG memory remap register 457 PMC : longword; // SYSCFG peripheral mode configuration register 458 EXTICR : array[0..3] of longword; // SYSCFG external interrupt configuration registers 459 RESERVED : array[0..1] of longword; // Reserved, 0x18-0x1C 460 CMPCR : longword; // SYSCFG Compensation cell control register 461 end; 462 463 TI2C_Registers = record 464 CR1 : longword; // I2C Control register 1 465 CR2 : longword; // I2C Control register 2 466 OAR1 : longword; // I2C Own address register 1 467 OAR2 : longword; // I2C Own address register 2 468 DR : longword; // I2C Data register 469 SR1 : longword; // I2C Status register 1 470 SR2 : longword; // I2C Status register 2 471 CCR : longword; // I2C Clock control register 472 TRISE : longword; // I2C TRISE register 473 FLTR : longword; // I2C FLTR register 474 end; 475 476 TIWDG_Registers = record 477 KR : longword; // IWDG Key register 478 PR : longword; // IWDG Prescaler register 479 RLR : longword; // IWDG Reload register 480 SR : longword; // IWDG Status register 481 end; 482 483 TLTDC_Registers = record 484 RESERVED0 : array[0..1] of longword; // Reserved, 0x00-0x04 485 SSCR : longword; // LTDC Synchronization Size Configuration Register 486 BPCR : longword; // LTDC Back Porch Configuration Register 487 AWCR : longword; // LTDC Active Width Configuration Register 488 TWCR : longword; // LTDC Total Width Configuration Register 489 GCR : longword; // LTDC Global Control Register 490 RESERVED1 : array[0..1] of longword; // Reserved, 0x1C-0x20 491 SRCR : longword; // LTDC Shadow Reload Configuration Register 492 RESERVED2 : longWord; // Reserved, 0x28 493 BCCR : longword; // LTDC Background Color Configuration Register 494 RESERVED3 : longWord; // Reserved, 0x30 495 IER : longword; // LTDC Interrupt Enable Register 496 ISR : longword; // LTDC Interrupt Status Register 497 ICR : longword; // LTDC Interrupt Clear Register 498 LIPCR : longword; // LTDC Line Interrupt Position Configuration Register 499 CPSR : longword; // LTDC Current Position Status Register 500 CDSR : longword; // LTDC Current Display Status Register 501 end; 502 503 TLTDC_LAYER_Registers = record 504 CR : longword; // LTDC Layerx Control Register 505 WHPCR : longword; // LTDC Layerx Window Horizontal Position Configuration Register 506 WVPCR : longword; // LTDC Layerx Window Vertical Position Configuration Register 507 CKCR : longword; // LTDC Layerx Color Keying Configuration Register 508 PFCR : longword; // LTDC Layerx Pixel Format Configuration Register 509 CACR : longword; // LTDC Layerx Constant Alpha Configuration Register 510 DCCR : longword; // LTDC Layerx Default Color Configuration Register 511 BFCR : longword; // LTDC Layerx Blending Factors Configuration Register 512 RESERVED0 : array[0..1] of longword; // Reserved 513 CFBAR : longword; // LTDC Layerx Color Frame Buffer Address Register 514 CFBLR : longword; // LTDC Layerx Color Frame Buffer Length Register 515 CFBLNR : longword; // LTDC Layerx ColorFrame Buffer Line Number Register 516 RESERVED1 : array[0..2] of longword; // Reserved 517 CLUTWR : longword; // LTDC Layerx CLUT Write Register 518 end; 519 520 TPWR_Registers = record 521 CR : longword; // PWR power control register 522 CSR : longword; // PWR power control/status register 523 end; 524 525 TRCC_Registers = record 526 CR : longword; // RCC clock control register 527 PLLCFGR : longword; // RCC PLL configuration register 528 CFGR : longword; // RCC clock configuration register 529 CIR : longword; // RCC clock interrupt register 530 AHB1RSTR : longword; // RCC AHB1 peripheral reset register 531 AHB2RSTR : longword; // RCC AHB2 peripheral reset register 532 AHB3RSTR : longword; // RCC AHB3 peripheral reset register 533 RESERVED0 : longword; // Reserved, 0x1C 534 APB1RSTR : longword; // RCC APB1 peripheral reset register 535 APB2RSTR : longword; // RCC APB2 peripheral reset register 536 RESERVED1 : array[0..1] of longword; // Reserved, 0x28-0x2C 537 AHB1ENR : longword; // RCC AHB1 peripheral clock register 538 AHB2ENR : longword; // RCC AHB2 peripheral clock register 539 AHB3ENR : longword; // RCC AHB3 peripheral clock register 540 RESERVED2 : longword; // Reserved, 0x3C 541 APB1ENR : longword; // RCC APB1 peripheral clock enable register 542 APB2ENR : longword; // RCC APB2 peripheral clock enable register 543 RESERVED3 : array[0..1] of longword; // Reserved, 0x48-0x4C 544 AHB1LPENR : longword; // RCC AHB1 peripheral clock enable in low power mode register 545 AHB2LPENR : longword; // RCC AHB2 peripheral clock enable in low power mode register 546 AHB3LPENR : longword; // RCC AHB3 peripheral clock enable in low power mode register 547 RESERVED4 : longword; // Reserved, 0x5C 548 APB1LPENR : longword; // RCC APB1 peripheral clock enable in low power mode register 549 APB2LPENR : longword; // RCC APB2 peripheral clock enable in low power mode register 550 RESERVED5 : array[0..1] of longword; // Reserved, 0x68-0x6C 551 BDCR : longword; // RCC Backup domain control register 552 CSR : longword; // RCC clock control & status register 553 RESERVED6 : array[0..1] of longword; // Reserved, 0x78-0x7C 554 SSCGR : longword; // RCC spread spectrum clock generation register 555 PLLI2SCFGR : longword; // RCC PLLI2S configuration register 556 PLLSAICFGR : longword; // RCC PLLSAI configuration register 557 DCKCFGR : longword; // RCC Dedicated Clocks configuration register 558 end; 559 560 TRTC_Registers = record 561 TR : longword; // RTC time register 562 DR : longword; // RTC date register 563 CR : longword; // RTC control register 564 ISR : longword; // RTC initialization and status register 565 PRER : longword; // RTC prescaler register 566 WUTR : longword; // RTC wakeup timer register 567 CALIBR : longword; // RTC calibration register 568 ALRMAR : longword; // RTC alarm A register 569 ALRMBR : longword; // RTC alarm B register 570 WPR : longword; // RTC write protection register 571 SSR : longword; // RTC sub second register 572 SHIFTR : longword; // RTC shift control register 573 TSTR : longword; // RTC time stamp time register 574 TSDR : longword; // RTC time stamp date register 575 TSSSR : longword; // RTC time-stamp sub second register 576 CALR : longword; // RTC calibration register 577 TAFCR : longword; // RTC tamper and alternate function configuration register 578 ALRMASSR : longword; // RTC alarm A sub second register 579 ALRMBSSR : longword; // RTC alarm B sub second register 580 RESERVED7 : longword; // Reserved, 0x4C 581 BKP0R : longword; // RTC backup register 1 582 BKP1R : longword; // RTC backup register 1 583 BKP2R : longword; // RTC backup register 2 584 BKP3R : longword; // RTC backup register 3 585 BKP4R : longword; // RTC backup register 4 586 BKP5R : longword; // RTC backup register 5 587 BKP6R : longword; // RTC backup register 6 588 BKP7R : longword; // RTC backup register 7 589 BKP8R : longword; // RTC backup register 8 590 BKP9R : longword; // RTC backup register 9 591 BKP10R : longword; // RTC backup register 10 592 BKP11R : longword; // RTC backup register 11 593 BKP12R : longword; // RTC backup register 12 594 BKP13R : longword; // RTC backup register 13 595 BKP14R : longword; // RTC backup register 14 596 BKP15R : longword; // RTC backup register 15 597 BKP16R : longword; // RTC backup register 16 598 BKP17R : longword; // RTC backup register 17 599 BKP18R : longword; // RTC backup register 18 600 BKP19R : longword; // RTC backup register 19 601 end; 602 603 TSAI_Registers = record 604 GCR : longword; // SAI global configuration register 605 end; 606 607 TSAI_BLOCK_Registers = record 608 CR1 : longword; // SAI block x configuration register 1 609 CR2 : longword; // SAI block x configuration register 2 610 FRCR : longword; // SAI block x frame configuration register 611 SLOTR : longword; // SAI block x slot register 612 IMR : longword; // SAI block x interrupt mask register 613 SR : longword; // SAI block x status register 614 CLRFR : longword; // SAI block x clear flag register 615 DR : longword; // SAI block x data register 616 end; 617 618 TSDIO_Registers = record 619 POWER : longword; // SDIO power control register 620 CLKCR : longword; // SDI clock control register 621 ARG : longword; // SDIO argument register 622 CMD : longword; // SDIO command register 623 RESPCMD : longword; // SDIO command response register 624 RESP1 : longword; // SDIO response 1 register 625 RESP2 : longword; // SDIO response 2 register 626 RESP3 : longword; // SDIO response 3 register 627 RESP4 : longword; // SDIO response 4 register 628 DTIMER : longword; // SDIO data timer register 629 DLEN : longword; // SDIO data length register 630 DCTRL : longword; // SDIO data control register 631 DCOUNT : longword; // SDIO data counter register 632 STA : longword; // SDIO status register 633 ICR : longword; // SDIO interrupt clear register 634 MASK : longword; // SDIO mask register 635 RESERVED0 : array[0..1] of longword; // Reserved, 0x40-0x44 636 FIFOCNT : longword; // SDIO FIFO counter register 637 RESERVED1 : array[0..12] of longword; // Reserved, 0x4C-0x7C 638 FIFO : longword; // SDIO data FIFO register 639 end; 640 641 TSPI_Registers = record 642 CR1 : longword; // SPI control register 1 (not used in I2S mode) 643 CR2 : longword; // SPI control register 2 644 SR : longword; // SPI status register 645 DR : longword; // SPI data register 646 CRCPR : longword; // SPI CRC polynomial register (not used in I2S mode) 647 RXCRCR : longword; // SPI RX CRC register (not used in I2S mode) 648 TXCRCR : longword; // SPI TX CRC register (not used in I2S mode) 649 I2SCFGR : longword; // SPI_I2S configuration register 650 I2SPR : longword; // SPI_I2S prescaler register 651 end; 652 653 TTIM_Registers = record 654 CR1 : longword; // TIM control register 1 655 CR2 : longword; // TIM control register 2 656 SMCR : longword; // TIM slave mode control register 657 DIER : longword; // TIM DMA/interrupt enable register 658 SR : longword; // TIM status register 659 EGR : longword; // TIM event generation register 660 CCMR1 : longword; // TIM capture/compare mode register 1 661 CCMR2 : longword; // TIM capture/compare mode register 2 662 CCER : longword; // TIM capture/compare enable register 663 CNT : longword; // TIM counter register 664 PSC : longword; // TIM prescaler 665 ARR : longword; // TIM auto-reload register 666 RCR : longword; // TIM repetition counter register 667 CCR1 : longword; // TIM capture/compare register 1 668 CCR2 : longword; // TIM capture/compare register 2 669 CCR3 : longword; // TIM capture/compare register 3 670 CCR4 : longword; // TIM capture/compare register 4 671 BDTR : longword; // TIM break and dead-time register 672 DCR : longword; // TIM DMA control register 673 DMAR : longword; // TIM DMA address for full transfer 674 &OR : longword; // TIM option register 675 end; 676 677 TUSART_Registers = record 678 SR : longword; // USART Status register 679 DR : longword; // USART Data register 680 BRR : longword; // USART Baud rate register 681 CR1 : longword; // USART Control register 1 682 CR2 : longword; // USART Control register 2 683 CR3 : longword; // USART Control register 3 684 GTPR : longword; // USART Guard time and prescaler register 685 end; 686 687 TWWDG_Registers = record 688 CR : longword; // WWDG Control register 689 CFR : longword; // WWDG Configuration register 690 SR : longword; // WWDG Status register 691 end; 692 693 TRNG_Registers = record 694 CR : longword; // RNG control register 695 SR : longword; // RNG status register 696 DR : longword; // RNG data register 697 end; 698 699 TUSB_OTG_GLOBAL_Registers = record 700 GOTGCTL : longword; // USB_OTG Control and Status Register 000h 701 GOTGINT : longword; // USB_OTG Interrupt Register 004h 702 GAHBCFG : longword; // Core AHB Configuration Register 008h 703 GUSBCFG : longword; // Core USB Configuration Register 00Ch 704 GRSTCTL : longword; // Core Reset Register 010h 705 GINTSTS : longword; // Core Interrupt Register 014h 706 GINTMSK : longword; // Core Interrupt Mask Register 018h 707 GRXSTSR : longword; // Receive Sts Q Read Register 01Ch 708 GRXSTSP : longword; // Receive Sts Q Read & POP Register 020h 709 GRXFSIZ : longword; // Receive FIFO Size Register 024h 710 DIEPTXF0_HNPTXFSIZ : longword; // EP0 / Non Periodic Tx FIFO Size Register 028h 711 HNPTXSTS : longword; // Non Periodic Tx FIFO/Queue Sts reg 02Ch 712 RESERVED30 : array[0..1] of longword; // Reserved 030h 713 GCCFG : longword; // General Purpose IO Register 038h 714 CID : longword; // User ID Register 03Ch 715 RESERVED40 : array[0..47] of longword; // Reserved 040h-0FFh 716 HPTXFSIZ : longword; // Host Periodic Tx FIFO Size Reg 100h 717 DIEPTXF : array[0..14] of longword; // dev Periodic Transmit FIFO 718 end; 719 720 TUSB_OTG_DEVICE_Registers = record 721 DCFG : longword; // dev Configuration Register 800h 722 DCTL : longword; // dev Control Register 804h 723 DSTS : longword; // dev Status Register (RO) 808h 724 RESERVED0C : longword; // Reserved 80Ch 725 DIEPMSK : longword; // dev IN Endpoint Mask 810h 726 DOEPMSK : longword; // dev OUT Endpoint Mask 814h 727 DAINT : longword; // dev All Endpoints Itr Reg 818h 728 DAINTMSK : longword; // dev All Endpoints Itr Mask 81Ch 729 RESERVED20 : longword; // Reserved 820h 730 RESERVED9 : longword; // Reserved 824h 731 DVBUSDIS : longword; // dev VBUS discharge Register 828h 732 DVBUSPULSE : longword; // dev VBUS Pulse Register 82Ch 733 DTHRCTL : longword; // dev thr 830h 734 DIEPEMPMSK : longword; // dev empty msk 834h 735 DEACHINT : longword; // dedicated EP interrupt 838h 736 DEACHMSK : longword; // dedicated EP msk 83Ch 737 RESERVED40 : longword; // dedicated EP mask 840h 738 DINEP1MSK : longword; // dedicated EP mask 844h 739 RESERVED44 : array[0..14] of longword; // Reserved 844-87Ch 740 DOUTEP1MSK : longword; // dedicated EP msk 884h 741 end; 742 743 TUSB_OTG_INENDPOINT_Registers = record 744 DIEPCTL : longword; // dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h 745 RESERVED04 : longword; // Reserved 900h + (ep_num * 20h) + 04h 746 DIEPINT : longword; // dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h 747 RESERVED0C : longword; // Reserved 900h + (ep_num * 20h) + 0Ch 748 DIEPTSIZ : longword; // IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h 749 DIEPDMA : longword; // IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h 750 DTXFSTS : longword; // IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h 751 RESERVED18 : longword; // Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch 752 end; 753 754 TUSB_OTG_OUTENDPOINT_Registers = record 755 DOEPCTL : longword; // dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h 756 RESERVED04 : longword; // Reserved B00h + (ep_num * 20h) + 04h 757 DOEPINT : longword; // dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h 758 RESERVED0C : longword; // Reserved B00h + (ep_num * 20h) + 0Ch 759 DOEPTSIZ : longword; // dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h 760 DOEPDMA : longword; // dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h 761 RESERVED18 : array[0..1] of longword; // Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch 762 end; 763 764 TUSB_OTG_HOST_Registers = record 765 HCFG : longword; // Host Configuration Register 400h 766 HFIR : longword; // Host Frame Interval Register 404h 767 HFNUM : longword; // Host Frame Nbr/Frame Remaining 408h 768 RESERVED40C : longword; // Reserved 40Ch 769 HPTXSTS : longword; // Host Periodic Tx FIFO/ Queue Status 410h 770 HAINT : longword; // Host All Channels Interrupt Register 414h 771 HAINTMSK : longword; // Host All Channels Interrupt Mask 418h 772 end; 773 774 TUSB_OTG_HOSTCHANNEL_Registers = record 775 HCCHAR : longword; 776 HCSPLT : longword; 777 HCINT : longword; 778 HCINTMSK : longword; 779 HCTSIZ : longword; 780 HCDMA : longword; 781 RESERVED : array[0..1] of longword; 782 end; 783 784const 785 FLASH_BASE = $08000000; // FLASH(up to 2 MB) base address in the alias region 786 CCMDATARAM_BASE = $10000000; // CCM(core coupled memory) data RAM(64 KB) base address in the alias region 787 SRAM1_BASE = $20000000; // SRAM1(112 KB) base address in the alias region 788 SRAM2_BASE = $2001C000; // SRAM2(16 KB) base address in the alias region 789 SRAM3_BASE = $20020000; // SRAM3(64 KB) base address in the alias region 790 PERIPH_BASE = $40000000; // Peripheral base address in the alias region 791 BKPSRAM_BASE = $40024000; // Backup SRAM(4 KB) base address in the alias region 792 FMC_R_BASE = $A0000000; // FMC registers base address 793 SRAM1_BB_BASE = $22000000; // SRAM1(112 KB) base address in the bit-band region 794 SRAM2_BB_BASE = $22380000; // SRAM2(16 KB) base address in the bit-band region 795 SRAM3_BB_BASE = $22400000; // SRAM3(64 KB) base address in the bit-band region 796 PERIPH_BB_BASE = $42000000; // Peripheral base address in the bit-band region 797 BKPSRAM_BB_BASE = $42480000; // Backup SRAM(4 KB) base address in the bit-band region 798 SRAM_BASE = $20000000; 799 SRAM_BB_BASE = $22000000; 800 APB1PERIPH_BASE = $40000000; 801 APB2PERIPH_BASE = PERIPH_BASE + $00010000; 802 AHB1PERIPH_BASE = PERIPH_BASE + $00020000; 803 AHB2PERIPH_BASE = PERIPH_BASE + $10000000; 804 TIM2_BASE = APB1PERIPH_BASE + $0000; 805 TIM3_BASE = APB1PERIPH_BASE + $0400; 806 TIM4_BASE = APB1PERIPH_BASE + $0800; 807 TIM5_BASE = APB1PERIPH_BASE + $0C00; 808 TIM6_BASE = APB1PERIPH_BASE + $1000; 809 TIM7_BASE = APB1PERIPH_BASE + $1400; 810 TIM12_BASE = APB1PERIPH_BASE + $1800; 811 TIM13_BASE = APB1PERIPH_BASE + $1C00; 812 TIM14_BASE = APB1PERIPH_BASE + $2000; 813 RTC_BASE = APB1PERIPH_BASE + $2800; 814 WWDG_BASE = APB1PERIPH_BASE + $2C00; 815 IWDG_BASE = APB1PERIPH_BASE + $3000; 816 I2S2ext_BASE = APB1PERIPH_BASE + $3400; 817 SPI2_BASE = APB1PERIPH_BASE + $3800; 818 SPI3_BASE = APB1PERIPH_BASE + $3C00; 819 I2S3ext_BASE = APB1PERIPH_BASE + $4000; 820 USART2_BASE = APB1PERIPH_BASE + $4400; 821 USART3_BASE = APB1PERIPH_BASE + $4800; 822 UART4_BASE = APB1PERIPH_BASE + $4C00; 823 UART5_BASE = APB1PERIPH_BASE + $5000; 824 I2C1_BASE = APB1PERIPH_BASE + $5400; 825 I2C2_BASE = APB1PERIPH_BASE + $5800; 826 I2C3_BASE = APB1PERIPH_BASE + $5C00; 827 CAN1_BASE = APB1PERIPH_BASE + $6400; 828 CAN2_BASE = APB1PERIPH_BASE + $6800; 829 PWR_BASE = APB1PERIPH_BASE + $7000; 830 DAC_BASE = APB1PERIPH_BASE + $7400; 831 UART7_BASE = APB1PERIPH_BASE + $7800; 832 UART8_BASE = APB1PERIPH_BASE + $7C00; 833 TIM1_BASE = APB2PERIPH_BASE + $0000; 834 TIM8_BASE = APB2PERIPH_BASE + $0400; 835 USART1_BASE = APB2PERIPH_BASE + $1000; 836 USART6_BASE = APB2PERIPH_BASE + $1400; 837 ADC1_BASE = APB2PERIPH_BASE + $2000; 838 ADC2_BASE = APB2PERIPH_BASE + $2100; 839 ADC3_BASE = APB2PERIPH_BASE + $2200; 840 ADC_BASE = APB2PERIPH_BASE + $2300; 841 SDIO_BASE = APB2PERIPH_BASE + $2C00; 842 SPI1_BASE = APB2PERIPH_BASE + $3000; 843 SPI4_BASE = APB2PERIPH_BASE + $3400; 844 SYSCFG_BASE = APB2PERIPH_BASE + $3800; 845 EXTI_BASE = APB2PERIPH_BASE + $3C00; 846 TIM9_BASE = APB2PERIPH_BASE + $4000; 847 TIM10_BASE = APB2PERIPH_BASE + $4400; 848 TIM11_BASE = APB2PERIPH_BASE + $4800; 849 SPI5_BASE = APB2PERIPH_BASE + $5000; 850 SPI6_BASE = APB2PERIPH_BASE + $5400; 851 SAI1_BASE = APB2PERIPH_BASE + $5800; 852 SAI1_Block_A_BASE = SAI1_BASE + $004; 853 SAI1_Block_B_BASE = SAI1_BASE + $024; 854 LTDC_BASE = APB2PERIPH_BASE + $6800; 855 LTDC_Layer1_BASE = LTDC_BASE + $84; 856 LTDC_Layer2_BASE = LTDC_BASE + $104; 857 GPIOA_BASE = AHB1PERIPH_BASE + $0000; 858 GPIOB_BASE = AHB1PERIPH_BASE + $0400; 859 GPIOC_BASE = AHB1PERIPH_BASE + $0800; 860 GPIOD_BASE = AHB1PERIPH_BASE + $0C00; 861 GPIOE_BASE = AHB1PERIPH_BASE + $1000; 862 GPIOF_BASE = AHB1PERIPH_BASE + $1400; 863 GPIOG_BASE = AHB1PERIPH_BASE + $1800; 864 GPIOH_BASE = AHB1PERIPH_BASE + $1C00; 865 GPIOI_BASE = AHB1PERIPH_BASE + $2000; 866 GPIOJ_BASE = AHB1PERIPH_BASE + $2400; 867 GPIOK_BASE = AHB1PERIPH_BASE + $2800; 868 CRC_BASE = AHB1PERIPH_BASE + $3000; 869 RCC_BASE = AHB1PERIPH_BASE + $3800; 870 FLASH_R_BASE = AHB1PERIPH_BASE + $3C00; 871 DMA1_BASE = AHB1PERIPH_BASE + $6000; 872 DMA1_Stream0_BASE = DMA1_BASE + $010; 873 DMA1_Stream1_BASE = DMA1_BASE + $028; 874 DMA1_Stream2_BASE = DMA1_BASE + $040; 875 DMA1_Stream3_BASE = DMA1_BASE + $058; 876 DMA1_Stream4_BASE = DMA1_BASE + $070; 877 DMA1_Stream5_BASE = DMA1_BASE + $088; 878 DMA1_Stream6_BASE = DMA1_BASE + $0A0; 879 DMA1_Stream7_BASE = DMA1_BASE + $0B8; 880 DMA2_BASE = AHB1PERIPH_BASE + $6400; 881 DMA2_Stream0_BASE = DMA2_BASE + $010; 882 DMA2_Stream1_BASE = DMA2_BASE + $028; 883 DMA2_Stream2_BASE = DMA2_BASE + $040; 884 DMA2_Stream3_BASE = DMA2_BASE + $058; 885 DMA2_Stream4_BASE = DMA2_BASE + $070; 886 DMA2_Stream5_BASE = DMA2_BASE + $088; 887 DMA2_Stream6_BASE = DMA2_BASE + $0A0; 888 DMA2_Stream7_BASE = DMA2_BASE + $0B8; 889 ETH_BASE = AHB1PERIPH_BASE + $8000; 890 ETH_MAC_BASE = AHB1PERIPH_BASE + $8000; 891 ETH_MMC_BASE = ETH_BASE + $0100; 892 ETH_PTP_BASE = ETH_BASE + $0700; 893 ETH_DMA_BASE = ETH_BASE + $1000; 894 DMA2D_BASE = AHB1PERIPH_BASE + $B000; 895 DCMI_BASE = AHB2PERIPH_BASE + $50000; 896 RNG_BASE = AHB2PERIPH_BASE + $60800; 897 FMC_Bank1_R_BASE = FMC_R_BASE + $0000; 898 FMC_Bank1E_R_BASE = FMC_R_BASE + $0104; 899 FMC_Bank2_3_R_BASE = FMC_R_BASE + $0060; 900 FMC_Bank4_R_BASE = FMC_R_BASE + $00A0; 901 FMC_Bank5_6_R_BASE = FMC_R_BASE + $0140; 902 DBGMCU_BASE = $E0042000; 903 USB_OTG_HS_PERIPH_BASE = $40040000; 904 USB_OTG_FS_PERIPH_BASE = $50000000; 905 USB_OTG_GLOBAL_BASE = $000; 906 USB_OTG_DEVICE_BASE = $800; 907 USB_OTG_IN_ENDPOINT_BASE = $900; 908 USB_OTG_OUT_ENDPOINT_BASE = $B00; 909 USB_OTG_HOST_BASE = $400; 910 USB_OTG_HOST_PORT_BASE = $440; 911 USB_OTG_HOST_CHANNEL_BASE = $500; 912 USB_OTG_PCGCCTL_BASE = $E00; 913 USB_OTG_FIFO_BASE = $1000; 914 915var 916 TIM2 : TTIM_Registers absolute TIM2_BASE; 917 TIM3 : TTIM_Registers absolute TIM3_BASE; 918 TIM4 : TTIM_Registers absolute TIM4_BASE; 919 TIM5 : TTIM_Registers absolute TIM5_BASE; 920 TIM6 : TTIM_Registers absolute TIM6_BASE; 921 TIM7 : TTIM_Registers absolute TIM7_BASE; 922 TIM12 : TTIM_Registers absolute TIM12_BASE; 923 TIM13 : TTIM_Registers absolute TIM13_BASE; 924 TIM14 : TTIM_Registers absolute TIM14_BASE; 925 RTC : TRTC_Registers absolute RTC_BASE; 926 WWDG : TWWDG_Registers absolute WWDG_BASE; 927 IWDG : TIWDG_Registers absolute IWDG_BASE; 928 I2S2ext : TSPI_Registers absolute I2S2ext_BASE; 929 SPI2 : TSPI_Registers absolute SPI2_BASE; 930 SPI3 : TSPI_Registers absolute SPI3_BASE; 931 I2S3ext : TSPI_Registers absolute I2S3ext_BASE; 932 USART2 : TUSART_Registers absolute USART2_BASE; 933 USART3 : TUSART_Registers absolute USART3_BASE; 934 UART4 : TUSART_Registers absolute UART4_BASE; 935 UART5 : TUSART_Registers absolute UART5_BASE; 936 I2C1 : TI2C_Registers absolute I2C1_BASE; 937 I2C2 : TI2C_Registers absolute I2C2_BASE; 938 I2C3 : TI2C_Registers absolute I2C3_BASE; 939 CAN1 : TCAN_Registers absolute CAN1_BASE; 940 CAN2 : TCAN_Registers absolute CAN2_BASE; 941 PWR : TPWR_Registers absolute PWR_BASE; 942 DAC : TDAC_Registers absolute DAC_BASE; 943 UART7 : TUSART_Registers absolute UART7_BASE; 944 UART8 : TUSART_Registers absolute UART8_BASE; 945 TIM1 : TTIM_Registers absolute TIM1_BASE; 946 TIM8 : TTIM_Registers absolute TIM8_BASE; 947 USART1 : TUSART_Registers absolute USART1_BASE; 948 USART6 : TUSART_Registers absolute USART6_BASE; 949 ADC : TADC_Common_Registers absolute ADC_BASE; 950 ADC1 : TADC_Registers absolute ADC1_BASE; 951 ADC2 : TADC_Registers absolute ADC2_BASE; 952 ADC3 : TADC_Registers absolute ADC3_BASE; 953 SDIO : TSDIO_Registers absolute SDIO_BASE; 954 SPI1 : TSPI_Registers absolute SPI1_BASE; 955 SPI4 : TSPI_Registers absolute SPI4_BASE; 956 SYSCFG : TSYSCFG_Registers absolute SYSCFG_BASE; 957 EXTI : TEXTI_Registers absolute EXTI_BASE; 958 TIM9 : TTIM_Registers absolute TIM9_BASE; 959 TIM10 : TTIM_Registers absolute TIM10_BASE; 960 TIM11 : TTIM_Registers absolute TIM11_BASE; 961 SPI5 : TSPI_Registers absolute SPI5_BASE; 962 SPI6 : TSPI_Registers absolute SPI6_BASE; 963 SAI1 : TSAI_Registers absolute SAI1_BASE; 964 SAI1_Block_A : TSAI_Block_Registers absolute SAI1_Block_A_BASE; 965 SAI1_Block_B : TSAI_Block_Registers absolute SAI1_Block_B_BASE; 966 LTDC : TLTDC_Registers absolute LTDC_BASE; 967 LTDC_Layer1 : TLTDC_Layer_Registers absolute LTDC_Layer1_BASE; 968 LTDC_Layer2 : TLTDC_Layer_Registers absolute LTDC_Layer2_BASE; 969 GPIOA : TGPIO_Registers absolute GPIOA_BASE; 970 GPIOB : TGPIO_Registers absolute GPIOB_BASE; 971 GPIOC : TGPIO_Registers absolute GPIOC_BASE; 972 GPIOD : TGPIO_Registers absolute GPIOD_BASE; 973 GPIOE : TGPIO_Registers absolute GPIOE_BASE; 974 GPIOF : TGPIO_Registers absolute GPIOF_BASE; 975 GPIOG : TGPIO_Registers absolute GPIOG_BASE; 976 GPIOH : TGPIO_Registers absolute GPIOH_BASE; 977 GPIOI : TGPIO_Registers absolute GPIOI_BASE; 978 GPIOJ : TGPIO_Registers absolute GPIOJ_BASE; 979 GPIOK : TGPIO_Registers absolute GPIOK_BASE; 980 CRC : TCRC_Registers absolute CRC_BASE; 981 RCC : TRCC_Registers absolute RCC_BASE; 982 FLASH : TFLASH_Registers absolute FLASH_R_BASE; 983 DMA1 : TDMA_Registers absolute DMA1_BASE; 984 DMA1_Stream0 : TDMA_Stream_Registers absolute DMA1_Stream0_BASE; 985 DMA1_Stream1 : TDMA_Stream_Registers absolute DMA1_Stream1_BASE; 986 DMA1_Stream2 : TDMA_Stream_Registers absolute DMA1_Stream2_BASE; 987 DMA1_Stream3 : TDMA_Stream_Registers absolute DMA1_Stream3_BASE; 988 DMA1_Stream4 : TDMA_Stream_Registers absolute DMA1_Stream4_BASE; 989 DMA1_Stream5 : TDMA_Stream_Registers absolute DMA1_Stream5_BASE; 990 DMA1_Stream6 : TDMA_Stream_Registers absolute DMA1_Stream6_BASE; 991 DMA1_Stream7 : TDMA_Stream_Registers absolute DMA1_Stream7_BASE; 992 DMA2 : TDMA_Registers absolute DMA2_BASE; 993 DMA2_Stream0 : TDMA_Stream_Registers absolute DMA2_Stream0_BASE; 994 DMA2_Stream1 : TDMA_Stream_Registers absolute DMA2_Stream1_BASE; 995 DMA2_Stream2 : TDMA_Stream_Registers absolute DMA2_Stream2_BASE; 996 DMA2_Stream3 : TDMA_Stream_Registers absolute DMA2_Stream3_BASE; 997 DMA2_Stream4 : TDMA_Stream_Registers absolute DMA2_Stream4_BASE; 998 DMA2_Stream5 : TDMA_Stream_Registers absolute DMA2_Stream5_BASE; 999 DMA2_Stream6 : TDMA_Stream_Registers absolute DMA2_Stream6_BASE; 1000 DMA2_Stream7 : TDMA_Stream_Registers absolute DMA2_Stream7_BASE; 1001 ETH : TETH_Registers absolute ETH_BASE; 1002 DMA2D : TDMA2D_Registers absolute DMA2D_BASE; 1003 DCMI : TDCMI_Registers absolute DCMI_BASE; 1004 RNG : TRNG_Registers absolute RNG_BASE; 1005 FMC_Bank1 : TFMC_Bank1_Registers absolute FMC_Bank1_R_BASE; 1006 FMC_Bank1E : TFMC_Bank1E_Registers absolute FMC_Bank1E_R_BASE; 1007 FMC_Bank2_3 : TFMC_Bank2_3_Registers absolute FMC_Bank2_3_R_BASE; 1008 FMC_Bank4 : TFMC_Bank4_Registers absolute FMC_Bank4_R_BASE; 1009 FMC_Bank5_6 : TFMC_Bank5_6_Registers absolute FMC_Bank5_6_R_BASE; 1010 DBGMCU : TDBGMCU_Registers absolute DBGMCU_BASE; 1011 1012implementation 1013 1014procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt'; 1015procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt'; 1016procedure BusFault_interrupt; external name 'BusFault_interrupt'; 1017procedure UsageFault_interrupt; external name 'UsageFault_interrupt'; 1018procedure SVCall_interrupt; external name 'SVCall_interrupt'; 1019procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt'; 1020procedure PendSV_interrupt; external name 'PendSV_interrupt'; 1021procedure SysTick_interrupt; external name 'SysTick_interrupt'; 1022procedure WWDG_interrupt; external name 'WWDG_interrupt'; 1023procedure PVD_interrupt; external name 'PVD_interrupt'; 1024procedure TAMP_STAMP_interrupt; external name 'TAMP_STAMP_interrupt'; 1025procedure RTC_WKUP_interrupt; external name 'RTC_WKUP_interrupt'; 1026procedure FLASH_interrupt; external name 'FLASH_interrupt'; 1027procedure RCC_interrupt; external name 'RCC_interrupt'; 1028procedure EXTI0_interrupt; external name 'EXTI0_interrupt'; 1029procedure EXTI1_interrupt; external name 'EXTI1_interrupt'; 1030procedure EXTI2_interrupt; external name 'EXTI2_interrupt'; 1031procedure EXTI3_interrupt; external name 'EXTI3_interrupt'; 1032procedure EXTI4_interrupt; external name 'EXTI4_interrupt'; 1033procedure DMA1_Stream0_interrupt; external name 'DMA1_Stream0_interrupt'; 1034procedure DMA1_Stream1_interrupt; external name 'DMA1_Stream1_interrupt'; 1035procedure DMA1_Stream2_interrupt; external name 'DMA1_Stream2_interrupt'; 1036procedure DMA1_Stream3_interrupt; external name 'DMA1_Stream3_interrupt'; 1037procedure DMA1_Stream4_interrupt; external name 'DMA1_Stream4_interrupt'; 1038procedure DMA1_Stream5_interrupt; external name 'DMA1_Stream5_interrupt'; 1039procedure DMA1_Stream6_interrupt; external name 'DMA1_Stream6_interrupt'; 1040procedure ADC_interrupt; external name 'ADC_interrupt'; 1041procedure CAN1_TX_interrupt; external name 'CAN1_TX_interrupt'; 1042procedure CAN1_RX0_interrupt; external name 'CAN1_RX0_interrupt'; 1043procedure CAN1_RX1_interrupt; external name 'CAN1_RX1_interrupt'; 1044procedure CAN1_SCE_interrupt; external name 'CAN1_SCE_interrupt'; 1045procedure EXTI9_5_interrupt; external name 'EXTI9_5_interrupt'; 1046procedure TIM1_BRK_TIM9_interrupt; external name 'TIM1_BRK_TIM9_interrupt'; 1047procedure TIM1_UP_TIM10_interrupt; external name 'TIM1_UP_TIM10_interrupt'; 1048procedure TIM1_TRG_COM_TIM11_interrupt; external name 'TIM1_TRG_COM_TIM11_interrupt'; 1049procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt'; 1050procedure TIM2_interrupt; external name 'TIM2_interrupt'; 1051procedure TIM3_interrupt; external name 'TIM3_interrupt'; 1052procedure TIM4_interrupt; external name 'TIM4_interrupt'; 1053procedure I2C1_EV_interrupt; external name 'I2C1_EV_interrupt'; 1054procedure I2C1_ER_interrupt; external name 'I2C1_ER_interrupt'; 1055procedure I2C2_EV_interrupt; external name 'I2C2_EV_interrupt'; 1056procedure I2C2_ER_interrupt; external name 'I2C2_ER_interrupt'; 1057procedure SPI1_interrupt; external name 'SPI1_interrupt'; 1058procedure SPI2_interrupt; external name 'SPI2_interrupt'; 1059procedure USART1_interrupt; external name 'USART1_interrupt'; 1060procedure USART2_interrupt; external name 'USART2_interrupt'; 1061procedure USART3_interrupt; external name 'USART3_interrupt'; 1062procedure EXTI15_10_interrupt; external name 'EXTI15_10_interrupt'; 1063procedure RTC_Alarm_interrupt; external name 'RTC_Alarm_interrupt'; 1064procedure OTG_FS_WKUP_interrupt; external name 'OTG_FS_WKUP_interrupt'; 1065procedure TIM8_BRK_TIM12_interrupt; external name 'TIM8_BRK_TIM12_interrupt'; 1066procedure TIM8_UP_TIM13_interrupt; external name 'TIM8_UP_TIM13_interrupt'; 1067procedure TIM8_TRG_COM_TIM14_interrupt; external name 'TIM8_TRG_COM_TIM14_interrupt'; 1068procedure TIM8_CC_interrupt; external name 'TIM8_CC_interrupt'; 1069procedure DMA1_Stream7_interrupt; external name 'DMA1_Stream7_interrupt'; 1070procedure FMC_interrupt; external name 'FMC_interrupt'; 1071procedure SDIO_interrupt; external name 'SDIO_interrupt'; 1072procedure TIM5_interrupt; external name 'TIM5_interrupt'; 1073procedure SPI3_interrupt; external name 'SPI3_interrupt'; 1074procedure UART4_interrupt; external name 'UART4_interrupt'; 1075procedure UART5_interrupt; external name 'UART5_interrupt'; 1076procedure TIM6_DAC_interrupt; external name 'TIM6_DAC_interrupt'; 1077procedure TIM7_interrupt; external name 'TIM7_interrupt'; 1078procedure DMA2_Stream0_interrupt; external name 'DMA2_Stream0_interrupt'; 1079procedure DMA2_Stream1_interrupt; external name 'DMA2_Stream1_interrupt'; 1080procedure DMA2_Stream2_interrupt; external name 'DMA2_Stream2_interrupt'; 1081procedure DMA2_Stream3_interrupt; external name 'DMA2_Stream3_interrupt'; 1082procedure DMA2_Stream4_interrupt; external name 'DMA2_Stream4_interrupt'; 1083procedure ETH_interrupt; external name 'ETH_interrupt'; 1084procedure ETH_WKUP_interrupt; external name 'ETH_WKUP_interrupt'; 1085procedure CAN2_TX_interrupt; external name 'CAN2_TX_interrupt'; 1086procedure CAN2_RX0_interrupt; external name 'CAN2_RX0_interrupt'; 1087procedure CAN2_RX1_interrupt; external name 'CAN2_RX1_interrupt'; 1088procedure CAN2_SCE_interrupt; external name 'CAN2_SCE_interrupt'; 1089procedure OTG_FS_interrupt; external name 'OTG_FS_interrupt'; 1090procedure DMA2_Stream5_interrupt; external name 'DMA2_Stream5_interrupt'; 1091procedure DMA2_Stream6_interrupt; external name 'DMA2_Stream6_interrupt'; 1092procedure DMA2_Stream7_interrupt; external name 'DMA2_Stream7_interrupt'; 1093procedure USART6_interrupt; external name 'USART6_interrupt'; 1094procedure I2C3_EV_interrupt; external name 'I2C3_EV_interrupt'; 1095procedure I2C3_ER_interrupt; external name 'I2C3_ER_interrupt'; 1096procedure OTG_HS_EP1_OUT_interrupt; external name 'OTG_HS_EP1_OUT_interrupt'; 1097procedure OTG_HS_EP1_IN_interrupt; external name 'OTG_HS_EP1_IN_interrupt'; 1098procedure OTG_HS_WKUP_interrupt; external name 'OTG_HS_WKUP_interrupt'; 1099procedure OTG_HS_interrupt; external name 'OTG_HS_interrupt'; 1100procedure DCMI_interrupt; external name 'DCMI_interrupt'; 1101procedure HASH_RNG_interrupt; external name 'HASH_RNG_interrupt'; 1102procedure FPU_interrupt; external name 'FPU_interrupt'; 1103procedure UART7_interrupt; external name 'UART7_interrupt'; 1104procedure UART8_interrupt; external name 'UART8_interrupt'; 1105procedure SPI4_interrupt; external name 'SPI4_interrupt'; 1106procedure SPI5_interrupt; external name 'SPI5_interrupt'; 1107procedure SPI6_interrupt; external name 'SPI6_interrupt'; 1108procedure SAI1_interrupt; external name 'SAI1_interrupt'; 1109procedure LTDC_interrupt; external name 'LTDC_interrupt'; 1110procedure LTDC_ER_interrupt; external name 'LTDC_ER_interrupt'; 1111procedure DMA2D_interrupt; external name 'DMA2D_interrupt'; 1112 1113{$i cortexm4f_start.inc} 1114 1115procedure Vectors; assembler; nostackframe; 1116label interrupt_vectors; 1117asm 1118 .section ".init.interrupt_vectors" 1119 interrupt_vectors: 1120 .long _stack_top 1121 .long Startup 1122 .long NonMaskableInt_interrupt 1123 .long 0 1124 .long MemoryManagement_interrupt 1125 .long BusFault_interrupt 1126 .long UsageFault_interrupt 1127 .long 0 1128 .long 0 1129 .long 0 1130 .long 0 1131 .long SVCall_interrupt 1132 .long DebugMonitor_interrupt 1133 .long 0 1134 .long PendSV_interrupt 1135 .long SysTick_interrupt 1136 .long WWDG_interrupt 1137 .long PVD_interrupt 1138 .long TAMP_STAMP_interrupt 1139 .long RTC_WKUP_interrupt 1140 .long FLASH_interrupt 1141 .long RCC_interrupt 1142 .long EXTI0_interrupt 1143 .long EXTI1_interrupt 1144 .long EXTI2_interrupt 1145 .long EXTI3_interrupt 1146 .long EXTI4_interrupt 1147 .long DMA1_Stream0_interrupt 1148 .long DMA1_Stream1_interrupt 1149 .long DMA1_Stream2_interrupt 1150 .long DMA1_Stream3_interrupt 1151 .long DMA1_Stream4_interrupt 1152 .long DMA1_Stream5_interrupt 1153 .long DMA1_Stream6_interrupt 1154 .long ADC_interrupt 1155 .long CAN1_TX_interrupt 1156 .long CAN1_RX0_interrupt 1157 .long CAN1_RX1_interrupt 1158 .long CAN1_SCE_interrupt 1159 .long EXTI9_5_interrupt 1160 .long TIM1_BRK_TIM9_interrupt 1161 .long TIM1_UP_TIM10_interrupt 1162 .long TIM1_TRG_COM_TIM11_interrupt 1163 .long TIM1_CC_interrupt 1164 .long TIM2_interrupt 1165 .long TIM3_interrupt 1166 .long TIM4_interrupt 1167 .long I2C1_EV_interrupt 1168 .long I2C1_ER_interrupt 1169 .long I2C2_EV_interrupt 1170 .long I2C2_ER_interrupt 1171 .long SPI1_interrupt 1172 .long SPI2_interrupt 1173 .long USART1_interrupt 1174 .long USART2_interrupt 1175 .long USART3_interrupt 1176 .long EXTI15_10_interrupt 1177 .long RTC_Alarm_interrupt 1178 .long OTG_FS_WKUP_interrupt 1179 .long TIM8_BRK_TIM12_interrupt 1180 .long TIM8_UP_TIM13_interrupt 1181 .long TIM8_TRG_COM_TIM14_interrupt 1182 .long TIM8_CC_interrupt 1183 .long DMA1_Stream7_interrupt 1184 .long FMC_interrupt 1185 .long SDIO_interrupt 1186 .long TIM5_interrupt 1187 .long SPI3_interrupt 1188 .long UART4_interrupt 1189 .long UART5_interrupt 1190 .long TIM6_DAC_interrupt 1191 .long TIM7_interrupt 1192 .long DMA2_Stream0_interrupt 1193 .long DMA2_Stream1_interrupt 1194 .long DMA2_Stream2_interrupt 1195 .long DMA2_Stream3_interrupt 1196 .long DMA2_Stream4_interrupt 1197 .long ETH_interrupt 1198 .long ETH_WKUP_interrupt 1199 .long CAN2_TX_interrupt 1200 .long CAN2_RX0_interrupt 1201 .long CAN2_RX1_interrupt 1202 .long CAN2_SCE_interrupt 1203 .long OTG_FS_interrupt 1204 .long DMA2_Stream5_interrupt 1205 .long DMA2_Stream6_interrupt 1206 .long DMA2_Stream7_interrupt 1207 .long USART6_interrupt 1208 .long I2C3_EV_interrupt 1209 .long I2C3_ER_interrupt 1210 .long OTG_HS_EP1_OUT_interrupt 1211 .long OTG_HS_EP1_IN_interrupt 1212 .long OTG_HS_WKUP_interrupt 1213 .long OTG_HS_interrupt 1214 .long DCMI_interrupt 1215 .long 0 1216 .long HASH_RNG_interrupt 1217 .long FPU_interrupt 1218 .long UART7_interrupt 1219 .long UART8_interrupt 1220 .long SPI4_interrupt 1221 .long SPI5_interrupt 1222 .long SPI6_interrupt 1223 .long SAI1_interrupt 1224 .long LTDC_interrupt 1225 .long LTDC_ER_interrupt 1226 .long DMA2D_interrupt 1227 .weak NonMaskableInt_interrupt 1228 .weak MemoryManagement_interrupt 1229 .weak BusFault_interrupt 1230 .weak UsageFault_interrupt 1231 .weak SVCall_interrupt 1232 .weak DebugMonitor_interrupt 1233 .weak PendSV_interrupt 1234 .weak SysTick_interrupt 1235 .weak WWDG_interrupt 1236 .weak PVD_interrupt 1237 .weak TAMP_STAMP_interrupt 1238 .weak RTC_WKUP_interrupt 1239 .weak FLASH_interrupt 1240 .weak RCC_interrupt 1241 .weak EXTI0_interrupt 1242 .weak EXTI1_interrupt 1243 .weak EXTI2_interrupt 1244 .weak EXTI3_interrupt 1245 .weak EXTI4_interrupt 1246 .weak DMA1_Stream0_interrupt 1247 .weak DMA1_Stream1_interrupt 1248 .weak DMA1_Stream2_interrupt 1249 .weak DMA1_Stream3_interrupt 1250 .weak DMA1_Stream4_interrupt 1251 .weak DMA1_Stream5_interrupt 1252 .weak DMA1_Stream6_interrupt 1253 .weak ADC_interrupt 1254 .weak CAN1_TX_interrupt 1255 .weak CAN1_RX0_interrupt 1256 .weak CAN1_RX1_interrupt 1257 .weak CAN1_SCE_interrupt 1258 .weak EXTI9_5_interrupt 1259 .weak TIM1_BRK_TIM9_interrupt 1260 .weak TIM1_UP_TIM10_interrupt 1261 .weak TIM1_TRG_COM_TIM11_interrupt 1262 .weak TIM1_CC_interrupt 1263 .weak TIM2_interrupt 1264 .weak TIM3_interrupt 1265 .weak TIM4_interrupt 1266 .weak I2C1_EV_interrupt 1267 .weak I2C1_ER_interrupt 1268 .weak I2C2_EV_interrupt 1269 .weak I2C2_ER_interrupt 1270 .weak SPI1_interrupt 1271 .weak SPI2_interrupt 1272 .weak USART1_interrupt 1273 .weak USART2_interrupt 1274 .weak USART3_interrupt 1275 .weak EXTI15_10_interrupt 1276 .weak RTC_Alarm_interrupt 1277 .weak OTG_FS_WKUP_interrupt 1278 .weak TIM8_BRK_TIM12_interrupt 1279 .weak TIM8_UP_TIM13_interrupt 1280 .weak TIM8_TRG_COM_TIM14_interrupt 1281 .weak TIM8_CC_interrupt 1282 .weak DMA1_Stream7_interrupt 1283 .weak FMC_interrupt 1284 .weak SDIO_interrupt 1285 .weak TIM5_interrupt 1286 .weak SPI3_interrupt 1287 .weak UART4_interrupt 1288 .weak UART5_interrupt 1289 .weak TIM6_DAC_interrupt 1290 .weak TIM7_interrupt 1291 .weak DMA2_Stream0_interrupt 1292 .weak DMA2_Stream1_interrupt 1293 .weak DMA2_Stream2_interrupt 1294 .weak DMA2_Stream3_interrupt 1295 .weak DMA2_Stream4_interrupt 1296 .weak ETH_interrupt 1297 .weak ETH_WKUP_interrupt 1298 .weak CAN2_TX_interrupt 1299 .weak CAN2_RX0_interrupt 1300 .weak CAN2_RX1_interrupt 1301 .weak CAN2_SCE_interrupt 1302 .weak OTG_FS_interrupt 1303 .weak DMA2_Stream5_interrupt 1304 .weak DMA2_Stream6_interrupt 1305 .weak DMA2_Stream7_interrupt 1306 .weak USART6_interrupt 1307 .weak I2C3_EV_interrupt 1308 .weak I2C3_ER_interrupt 1309 .weak OTG_HS_EP1_OUT_interrupt 1310 .weak OTG_HS_EP1_IN_interrupt 1311 .weak OTG_HS_WKUP_interrupt 1312 .weak OTG_HS_interrupt 1313 .weak DCMI_interrupt 1314 .weak HASH_RNG_interrupt 1315 .weak FPU_interrupt 1316 .weak UART7_interrupt 1317 .weak UART8_interrupt 1318 .weak SPI4_interrupt 1319 .weak SPI5_interrupt 1320 .weak SPI6_interrupt 1321 .weak SAI1_interrupt 1322 .weak LTDC_interrupt 1323 .weak LTDC_ER_interrupt 1324 .weak DMA2D_interrupt 1325 .set NonMaskableInt_interrupt, HaltProc 1326 .set MemoryManagement_interrupt, HaltProc 1327 .set BusFault_interrupt, HaltProc 1328 .set UsageFault_interrupt, HaltProc 1329 .set SVCall_interrupt, HaltProc 1330 .set DebugMonitor_interrupt, HaltProc 1331 .set PendSV_interrupt, HaltProc 1332 .set SysTick_interrupt, HaltProc 1333 .set WWDG_interrupt, HaltProc 1334 .set PVD_interrupt, HaltProc 1335 .set TAMP_STAMP_interrupt, HaltProc 1336 .set RTC_WKUP_interrupt, HaltProc 1337 .set FLASH_interrupt, HaltProc 1338 .set RCC_interrupt, HaltProc 1339 .set EXTI0_interrupt, HaltProc 1340 .set EXTI1_interrupt, HaltProc 1341 .set EXTI2_interrupt, HaltProc 1342 .set EXTI3_interrupt, HaltProc 1343 .set EXTI4_interrupt, HaltProc 1344 .set DMA1_Stream0_interrupt, HaltProc 1345 .set DMA1_Stream1_interrupt, HaltProc 1346 .set DMA1_Stream2_interrupt, HaltProc 1347 .set DMA1_Stream3_interrupt, HaltProc 1348 .set DMA1_Stream4_interrupt, HaltProc 1349 .set DMA1_Stream5_interrupt, HaltProc 1350 .set DMA1_Stream6_interrupt, HaltProc 1351 .set ADC_interrupt, HaltProc 1352 .set CAN1_TX_interrupt, HaltProc 1353 .set CAN1_RX0_interrupt, HaltProc 1354 .set CAN1_RX1_interrupt, HaltProc 1355 .set CAN1_SCE_interrupt, HaltProc 1356 .set EXTI9_5_interrupt, HaltProc 1357 .set TIM1_BRK_TIM9_interrupt, HaltProc 1358 .set TIM1_UP_TIM10_interrupt, HaltProc 1359 .set TIM1_TRG_COM_TIM11_interrupt, HaltProc 1360 .set TIM1_CC_interrupt, HaltProc 1361 .set TIM2_interrupt, HaltProc 1362 .set TIM3_interrupt, HaltProc 1363 .set TIM4_interrupt, HaltProc 1364 .set I2C1_EV_interrupt, HaltProc 1365 .set I2C1_ER_interrupt, HaltProc 1366 .set I2C2_EV_interrupt, HaltProc 1367 .set I2C2_ER_interrupt, HaltProc 1368 .set SPI1_interrupt, HaltProc 1369 .set SPI2_interrupt, HaltProc 1370 .set USART1_interrupt, HaltProc 1371 .set USART2_interrupt, HaltProc 1372 .set USART3_interrupt, HaltProc 1373 .set EXTI15_10_interrupt, HaltProc 1374 .set RTC_Alarm_interrupt, HaltProc 1375 .set OTG_FS_WKUP_interrupt, HaltProc 1376 .set TIM8_BRK_TIM12_interrupt, HaltProc 1377 .set TIM8_UP_TIM13_interrupt, HaltProc 1378 .set TIM8_TRG_COM_TIM14_interrupt, HaltProc 1379 .set TIM8_CC_interrupt, HaltProc 1380 .set DMA1_Stream7_interrupt, HaltProc 1381 .set FMC_interrupt, HaltProc 1382 .set SDIO_interrupt, HaltProc 1383 .set TIM5_interrupt, HaltProc 1384 .set SPI3_interrupt, HaltProc 1385 .set UART4_interrupt, HaltProc 1386 .set UART5_interrupt, HaltProc 1387 .set TIM6_DAC_interrupt, HaltProc 1388 .set TIM7_interrupt, HaltProc 1389 .set DMA2_Stream0_interrupt, HaltProc 1390 .set DMA2_Stream1_interrupt, HaltProc 1391 .set DMA2_Stream2_interrupt, HaltProc 1392 .set DMA2_Stream3_interrupt, HaltProc 1393 .set DMA2_Stream4_interrupt, HaltProc 1394 .set ETH_interrupt, HaltProc 1395 .set ETH_WKUP_interrupt, HaltProc 1396 .set CAN2_TX_interrupt, HaltProc 1397 .set CAN2_RX0_interrupt, HaltProc 1398 .set CAN2_RX1_interrupt, HaltProc 1399 .set CAN2_SCE_interrupt, HaltProc 1400 .set OTG_FS_interrupt, HaltProc 1401 .set DMA2_Stream5_interrupt, HaltProc 1402 .set DMA2_Stream6_interrupt, HaltProc 1403 .set DMA2_Stream7_interrupt, HaltProc 1404 .set USART6_interrupt, HaltProc 1405 .set I2C3_EV_interrupt, HaltProc 1406 .set I2C3_ER_interrupt, HaltProc 1407 .set OTG_HS_EP1_OUT_interrupt, HaltProc 1408 .set OTG_HS_EP1_IN_interrupt, HaltProc 1409 .set OTG_HS_WKUP_interrupt, HaltProc 1410 .set OTG_HS_interrupt, HaltProc 1411 .set DCMI_interrupt, HaltProc 1412 .set HASH_RNG_interrupt, HaltProc 1413 .set FPU_interrupt, HaltProc 1414 .set UART7_interrupt, HaltProc 1415 .set UART8_interrupt, HaltProc 1416 .set SPI4_interrupt, HaltProc 1417 .set SPI5_interrupt, HaltProc 1418 .set SPI6_interrupt, HaltProc 1419 .set SAI1_interrupt, HaltProc 1420 .set LTDC_interrupt, HaltProc 1421 .set LTDC_ER_interrupt, HaltProc 1422 .set DMA2D_interrupt, HaltProc 1423 .text 1424end; 1425end. 1426