1{ 2Register definitions and utility code for STM32F745 3 4Created by Jeppe Johansen 2015 - jeppe@j-software.dk 5} 6unit stm32f745; 7 8{$goto on} 9 10interface 11 12{$PACKRECORDS C} 13 14(** 15 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals 16 *) 17 18const 19 __CM7_REV = $0000; (*!< Cortex-M7 revision r0p1 *) 20 __MPU_PRESENT = true; (*!< CM7 provides an MPU *) 21 __NVIC_PRIO_BITS = 4; (*!< CM7 uses 4 Bits for the Priority Levels *) 22 __Vendor_SysTickConfig = 0; (*!< Set to 1 if different SysTick Config is used *) 23 __FPU_PRESENT = true; (*!< FPU present *) 24 CACHE_PRESENT = true; (*!< CM7 instruction cache present *) 25 __DCACHE_PRESENT = true; (*!< CM7 data cache present *) 26 27 28 (** @addtogroup Peripheral_registers_structures 29 * @{ 30 *) 31 32 (** 33 * @brief Analog to Digital Converter 34 *) 35 36type 37 ADC_TypeDef = record 38 SR: longword; (*!< ADC status register, Address offset: 0x00 *) 39 CR1: longword; (*!< ADC control register 1, Address offset: 0x04 *) 40 CR2: longword; (*!< ADC control register 2, Address offset: 0x08 *) 41 SMPR1: longword; (*!< ADC sample time register 1, Address offset: 0x0C *) 42 SMPR2: longword; (*!< ADC sample time register 2, Address offset: 0x10 *) 43 JOFR1: longword; (*!< ADC injected channel data offset register 1, Address offset: 0x14 *) 44 JOFR2: longword; (*!< ADC injected channel data offset register 2, Address offset: 0x18 *) 45 JOFR3: longword; (*!< ADC injected channel data offset register 3, Address offset: 0x1C *) 46 JOFR4: longword; (*!< ADC injected channel data offset register 4, Address offset: 0x20 *) 47 HTR: longword; (*!< ADC watchdog higher threshold register, Address offset: 0x24 *) 48 LTR: longword; (*!< ADC watchdog lower threshold register, Address offset: 0x28 *) 49 SQR1: longword; (*!< ADC regular sequence register 1, Address offset: 0x2C *) 50 SQR2: longword; (*!< ADC regular sequence register 2, Address offset: 0x30 *) 51 SQR3: longword; (*!< ADC regular sequence register 3, Address offset: 0x34 *) 52 JSQR: longword; (*!< ADC injected sequence register, Address offset: 0x38 *) 53 JDR1: longword; (*!< ADC injected data register 1, Address offset: 0x3C *) 54 JDR2: longword; (*!< ADC injected data register 2, Address offset: 0x40 *) 55 JDR3: longword; (*!< ADC injected data register 3, Address offset: 0x44 *) 56 JDR4: longword; (*!< ADC injected data register 4, Address offset: 0x48 *) 57 DR: longword; (*!< ADC regular data register, Address offset: 0x4C *) 58 end; 59 60 ADC_Common_TypeDef = record 61 CSR: longword; (*!< ADC Common status register, Address offset: ADC1 base address + 0x300 *) 62 CCR: longword; (*!< ADC common control register, Address offset: ADC1 base address + 0x304 *) 63 CDR: longword; (*!< ADC common regular data register for dual 64 AND triple modes, Address offset: ADC1 base address + 0x308 *) 65 end; 66 67 68 (** 69 * @brief Controller Area Network TxMailBox 70 *) 71 72 CAN_TxMailBox_TypeDef = record 73 TIR: longword; (*!< CAN TX mailbox identifier register *) 74 TDTR: longword; (*!< CAN mailbox data length control and time stamp register *) 75 TDLR: longword; (*!< CAN mailbox data low register *) 76 TDHR: longword; (*!< CAN mailbox data high register *) 77 end; 78 79 (** 80 * @brief Controller Area Network FIFOMailBox 81 *) 82 83 CAN_FIFOMailBox_TypeDef = record 84 RIR: longword; (*!< CAN receive FIFO mailbox identifier register *) 85 RDTR: longword; (*!< CAN receive FIFO mailbox data length control and time stamp register *) 86 RDLR: longword; (*!< CAN receive FIFO mailbox data low register *) 87 RDHR: longword; (*!< CAN receive FIFO mailbox data high register *) 88 end; 89 90 (** 91 * @brief Controller Area Network FilterRegister 92 *) 93 94 CAN_FilterRegister_TypeDef = record 95 FR1: longword; (*!< CAN Filter bank register 1 *) 96 FR2: longword; (*!< CAN Filter bank register 1 *) 97 end; 98 99 (** 100 * @brief Controller Area Network 101 *) 102 103 CAN_TypeDef = record 104 MCR: longword; (*!< CAN master control register, Address offset: 0x00 *) 105 MSR: longword; (*!< CAN master status register, Address offset: 0x04 *) 106 TSR: longword; (*!< CAN transmit status register, Address offset: 0x08 *) 107 RF0R: longword; (*!< CAN receive FIFO 0 register, Address offset: 0x0C *) 108 RF1R: longword; (*!< CAN receive FIFO 1 register, Address offset: 0x10 *) 109 IER: longword; (*!< CAN interrupt enable register, Address offset: 0x14 *) 110 ESR: longword; (*!< CAN error status register, Address offset: 0x18 *) 111 BTR: longword; (*!< CAN bit timing register, Address offset: 0x1C *) 112 RESERVED0: array [0..87] of longword; (*!< Reserved, 0x020 - 0x17F *) 113 sTxMailBox: array [0..2] of CAN_TxMailBox_TypeDef; (*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC *) 114 sFIFOMailBox: array [0..1] of CAN_FIFOMailBox_TypeDef; (*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC *) 115 RESERVED1: array [0..11] of longword; (*!< Reserved, 0x1D0 - 0x1FF *) 116 FMR: longword; (*!< CAN filter master register, Address offset: 0x200 *) 117 FM1R: longword; (*!< CAN filter mode register, Address offset: 0x204 *) 118 RESERVED2: longword; (*!< Reserved, 0x208 *) 119 FS1R: longword; (*!< CAN filter scale register, Address offset: 0x20C *) 120 RESERVED3: longword; (*!< Reserved, 0x210 *) 121 FFA1R: longword; (*!< CAN filter FIFO assignment register, Address offset: 0x214 *) 122 RESERVED4: longword; (*!< Reserved, 0x218 *) 123 FA1R: longword; (*!< CAN filter activation register, Address offset: 0x21C *) 124 RESERVED5: array [0..7] of longword; (*!< Reserved, 0x220-0x23F *) 125 sFilterRegister: array [0..27] of CAN_FilterRegister_TypeDef; (*!< CAN Filter Register, Address offset: 0x240-0x31C *) 126 end; 127 128 (** 129 * @brief HDMI-CEC 130 *) 131 132 CEC_TypeDef = record 133 CR: longword; (*!< CEC control register, Address offset:0x00 *) 134 CFGR: longword; (*!< CEC configuration register, Address offset:0x04 *) 135 TXDR: longword; (*!< CEC Tx data register , Address offset:0x08 *) 136 RXDR: longword; (*!< CEC Rx Data Register, Address offset:0x0C *) 137 ISR: longword; (*!< CEC Interrupt and Status Register, Address offset:0x10 *) 138 IER: longword; (*!< CEC interrupt enable register, Address offset:0x14 *) 139 end; 140 141 142 (** 143 * @brief CRC calculation unit 144 *) 145 146 CRC_TypeDef = record 147 DR: longword; (*!< CRC Data register, Address offset: 0x00 *) 148 IDR: byte; (*!< CRC Independent data register, Address offset: 0x04 *) 149 RESERVED0: byte; (*!< Reserved, 0x05 *) 150 RESERVED1: word; (*!< Reserved, 0x06 *) 151 CR: longword; (*!< CRC Control register, Address offset: 0x08 *) 152 RESERVED2: longword; (*!< Reserved, 0x0C *) 153 INIT: longword; (*!< Initial CRC value register, Address offset: 0x10 *) 154 POL: longword; (*!< CRC polynomial register, Address offset: 0x14 *) 155 end; 156 157 (** 158 * @brief Digital to Analog Converter 159 *) 160 161 DAC_TypeDef = record 162 CR: longword; (*!< DAC control register, Address offset: 0x00 *) 163 SWTRIGR: longword; (*!< DAC software trigger register, Address offset: 0x04 *) 164 DHR12R1: longword; (*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 *) 165 DHR12L1: longword; (*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C *) 166 DHR8R1: longword; (*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 *) 167 DHR12R2: longword; (*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 *) 168 DHR12L2: longword; (*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 *) 169 DHR8R2: longword; (*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C *) 170 DHR12RD: longword; (*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 *) 171 DHR12LD: longword; (*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 *) 172 DHR8RD: longword; (*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 *) 173 DOR1: longword; (*!< DAC channel1 data output register, Address offset: 0x2C *) 174 DOR2: longword; (*!< DAC channel2 data output register, Address offset: 0x30 *) 175 SR: longword; (*!< DAC status register, Address offset: 0x34 *) 176 end; 177 178 (** 179 * @brief Debug MCU 180 *) 181 182 DBGMCU_TypeDef = record 183 IDCODE: longword; (*!< MCU device ID code, Address offset: 0x00 *) 184 CR: longword; (*!< Debug MCU configuration register, Address offset: 0x04 *) 185 APB1FZ: longword; (*!< Debug MCU APB1 freeze register, Address offset: 0x08 *) 186 APB2FZ: longword; (*!< Debug MCU APB2 freeze register, Address offset: 0x0C *) 187 end; 188 189 (** 190 * @brief DCMI 191 *) 192 193 DCMI_TypeDef = record 194 CR: longword; (*!< DCMI control register 1, Address offset: 0x00 *) 195 SR: longword; (*!< DCMI status register, Address offset: 0x04 *) 196 RISR: longword; (*!< DCMI raw interrupt status register, Address offset: 0x08 *) 197 IER: longword; (*!< DCMI interrupt enable register, Address offset: 0x0C *) 198 MISR: longword; (*!< DCMI masked interrupt status register, Address offset: 0x10 *) 199 ICR: longword; (*!< DCMI interrupt clear register, Address offset: 0x14 *) 200 ESCR: longword; (*!< DCMI embedded synchronization code register, Address offset: 0x18 *) 201 ESUR: longword; (*!< DCMI embedded synchronization unmask register, Address offset: 0x1C *) 202 CWSTRTR: longword; (*!< DCMI crop window start, Address offset: 0x20 *) 203 CWSIZER: longword; (*!< DCMI crop window size, Address offset: 0x24 *) 204 DR: longword; (*!< DCMI data register, Address offset: 0x28 *) 205 end; 206 207 (** 208 * @brief DMA Controller 209 *) 210 211 DMA_Stream_TypeDef = record 212 CR: longword; (*!< DMA stream x configuration register *) 213 NDTR: longword; (*!< DMA stream x number of data register *) 214 PAR: longword; (*!< DMA stream x peripheral address register *) 215 M0AR: longword; (*!< DMA stream x memory 0 address register *) 216 M1AR: longword; (*!< DMA stream x memory 1 address register *) 217 FCR: longword; (*!< DMA stream x FIFO control register *) 218 end; 219 220 DMA_TypeDef = record 221 LISR: longword; (*!< DMA low interrupt status register, Address offset: 0x00 *) 222 HISR: longword; (*!< DMA high interrupt status register, Address offset: 0x04 *) 223 LIFCR: longword; (*!< DMA low interrupt flag clear register, Address offset: 0x08 *) 224 HIFCR: longword; (*!< DMA high interrupt flag clear register, Address offset: 0x0C *) 225 end; 226 227 228 (** 229 * @brief DMA2D Controller 230 *) 231 232 DMA2D_TypeDef = record 233 CR: longword; (*!< DMA2D Control Register, Address offset: 0x00 *) 234 ISR: longword; (*!< DMA2D Interrupt Status Register, Address offset: 0x04 *) 235 IFCR: longword; (*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 *) 236 FGMAR: longword; (*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C *) 237 FGOR: longword; (*!< DMA2D Foreground Offset Register, Address offset: 0x10 *) 238 BGMAR: longword; (*!< DMA2D Background Memory Address Register, Address offset: 0x14 *) 239 BGOR: longword; (*!< DMA2D Background Offset Register, Address offset: 0x18 *) 240 FGPFCCR: longword; (*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C *) 241 FGCOLR: longword; (*!< DMA2D Foreground Color Register, Address offset: 0x20 *) 242 BGPFCCR: longword; (*!< DMA2D Background PFC Control Register, Address offset: 0x24 *) 243 BGCOLR: longword; (*!< DMA2D Background Color Register, Address offset: 0x28 *) 244 FGCMAR: longword; (*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C *) 245 BGCMAR: longword; (*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 *) 246 OPFCCR: longword; (*!< DMA2D Output PFC Control Register, Address offset: 0x34 *) 247 OCOLR: longword; (*!< DMA2D Output Color Register, Address offset: 0x38 *) 248 OMAR: longword; (*!< DMA2D Output Memory Address Register, Address offset: 0x3C *) 249 OOR: longword; (*!< DMA2D Output Offset Register, Address offset: 0x40 *) 250 NLR: longword; (*!< DMA2D Number of Line Register, Address offset: 0x44 *) 251 LWR: longword; (*!< DMA2D Line Watermark Register, Address offset: 0x48 *) 252 AMTCR: longword; (*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C *) 253 RESERVED: array [0..235] of longword; (*!< Reserved, 0x50-0x3FF *) 254 FGCLUT: array [0..255] of longword; (*!< DMA2D Foreground CLUT, Address offset:400-7FF *) 255 BGCLUT: array [0..255] of longword; (*!< DMA2D Background CLUT, Address offset:800-BFF *) 256 end; 257 258 259 (** 260 * @brief Ethernet MAC 261 *) 262 263 ETH_TypeDef = record 264 MACCR: longword; 265 MACFFR: longword; 266 MACHTHR: longword; 267 MACHTLR: longword; 268 MACMIIAR: longword; 269 MACMIIDR: longword; 270 MACFCR: longword; 271 MACVLANTR: longword; (* 8 *) 272 RESERVED0: array [0..1] of longword; 273 MACRWUFFR: longword; (* 11 *) 274 MACPMTCSR: longword; 275 RESERVED1: array [0..1] of longword; 276 MACSR: longword; (* 15 *) 277 MACIMR: longword; 278 MACA0HR: longword; 279 MACA0LR: longword; 280 MACA1HR: longword; 281 MACA1LR: longword; 282 MACA2HR: longword; 283 MACA2LR: longword; 284 MACA3HR: longword; 285 MACA3LR: longword; (* 24 *) 286 RESERVED2: array [0..39] of longword; 287 MMCCR: longword; (* 65 *) 288 MMCRIR: longword; 289 MMCTIR: longword; 290 MMCRIMR: longword; 291 MMCTIMR: longword; (* 69 *) 292 RESERVED3: array [0..13] of longword; 293 MMCTGFSCCR: longword; (* 84 *) 294 MMCTGFMSCCR: longword; 295 RESERVED4: array [0..4] of longword; 296 MMCTGFCR: longword; 297 RESERVED5: array [0..9] of longword; 298 MMCRFCECR: longword; 299 MMCRFAECR: longword; 300 RESERVED6: array [0..9] of longword; 301 MMCRGUFCR: longword; 302 RESERVED7: array [0..333] of longword; 303 PTPTSCR: longword; 304 PTPSSIR: longword; 305 PTPTSHR: longword; 306 PTPTSLR: longword; 307 PTPTSHUR: longword; 308 PTPTSLUR: longword; 309 PTPTSAR: longword; 310 PTPTTHR: longword; 311 PTPTTLR: longword; 312 RESERVED8: longword; 313 PTPTSSR: longword; 314 RESERVED9: array [0..564] of longword; 315 DMABMR: longword; 316 DMATPDR: longword; 317 DMARPDR: longword; 318 DMARDLAR: longword; 319 DMATDLAR: longword; 320 DMASR: longword; 321 DMAOMR: longword; 322 DMAIER: longword; 323 DMAMFBOCR: longword; 324 DMARSWTR: longword; 325 RESERVED10: array [0..7] of longword; 326 DMACHTDR: longword; 327 DMACHRDR: longword; 328 DMACHTBAR: longword; 329 DMACHRBAR: longword; 330 end; 331 332 (** 333 * @brief External Interrupt/Event Controller 334 *) 335 336 EXTI_TypeDef = record 337 IMR: longword; (*!< EXTI Interrupt mask register, Address offset: 0x00 *) 338 EMR: longword; (*!< EXTI Event mask register, Address offset: 0x04 *) 339 RTSR: longword; (*!< EXTI Rising trigger selection register, Address offset: 0x08 *) 340 FTSR: longword; (*!< EXTI Falling trigger selection register, Address offset: 0x0C *) 341 SWIER: longword; (*!< EXTI Software interrupt event register, Address offset: 0x10 *) 342 PR: longword; (*!< EXTI Pending register, Address offset: 0x14 *) 343 end; 344 345 (** 346 * @brief FLASH Registers 347 *) 348 349 FLASH_TypeDef = record 350 ACR: longword; (*!< FLASH access control register, Address offset: 0x00 *) 351 KEYR: longword; (*!< FLASH key register, Address offset: 0x04 *) 352 OPTKEYR: longword; (*!< FLASH option key register, Address offset: 0x08 *) 353 SR: longword; (*!< FLASH status register, Address offset: 0x0C *) 354 CR: longword; (*!< FLASH control register, Address offset: 0x10 *) 355 OPTCR: longword; (*!< FLASH option control register , Address offset: 0x14 *) 356 OPTCR1: longword; (*!< FLASH option control register 1 , Address offset: 0x18 *) 357 end; 358 359 360 (** 361 * @brief Flexible Memory Controller 362 *) 363 364 FMC_Bank1_TypeDef = record 365 BTCR: array [0..7] of longword; (*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C *) 366 end; 367 368 (** 369 * @brief Flexible Memory Controller Bank1E 370 *) 371 372 FMC_Bank1E_TypeDef = record 373 BWTR: array [0..6] of longword; (*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C *) 374 end; 375 376 (** 377 * @brief Flexible Memory Controller Bank3 378 *) 379 380 FMC_Bank3_TypeDef = record 381 PCR: longword; (*!< NAND Flash control register, Address offset: 0x80 *) 382 SR: longword; (*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 *) 383 PMEM: longword; (*!< NAND Flash Common memory space timing register, Address offset: 0x88 *) 384 PATT: longword; (*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C *) 385 RESERVED0: longword; (*!< Reserved, 0x90 *) 386 ECCR: longword; (*!< NAND Flash ECC result registers, Address offset: 0x94 *) 387 end; 388 389 (** 390 * @brief Flexible Memory Controller Bank5_6 391 *) 392 393 FMC_Bank5_6_TypeDef = record 394 SDCR: array [0..1] of longword; (*!< SDRAM Control registers , Address offset: 0x140-0x144 *) 395 SDTR: array [0..1] of longword; (*!< SDRAM Timing registers , Address offset: 0x148-0x14C *) 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *) 397 SDRTR: longword; (*!< SDRAM Refresh Timer register, Address offset: 0x154 *) 398 SDSR: longword; (*!< SDRAM Status register, Address offset: 0x158 *) 399 end; 400 401 402 (** 403 * @brief General Purpose I/O 404 *) 405 406 GPIO_TypeDef = record 407 MODER: longword; (*!< GPIO port mode register, Address offset: 0x00 *) 408 OTYPER: longword; (*!< GPIO port output type register, Address offset: 0x04 *) 409 OSPEEDR: longword; (*!< GPIO port output speed register, Address offset: 0x08 *) 410 PUPDR: longword; (*!< GPIO port pull-up/pull-down register, Address offset: 0x0C *) 411 IDR: longword; (*!< GPIO port input data register, Address offset: 0x10 *) 412 ODR: longword; (*!< GPIO port output data register, Address offset: 0x14 *) 413 BSRR: longword; (*!< GPIO port bit set/reset register, Address offset: 0x18 *) 414 LCKR: longword; (*!< GPIO port configuration lock register, Address offset: 0x1C *) 415 AFR: array [0..1] of longword; (*!< GPIO alternate function registers, Address offset: 0x20-0x24 *) 416 end; 417 418 (** 419 * @brief System configuration controller 420 *) 421 422 SYSCFG_TypeDef = record 423 MEMRMP: longword; (*!< SYSCFG memory remap register, Address offset: 0x00 *) 424 PMC: longword; (*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 *) 425 EXTICR: array [0..3] of longword; (*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 *) 426 RESERVED: array [0..1] of longword; (*!< Reserved, 0x18-0x1C *) 427 CMPCR: longword; (*!< SYSCFG Compensation cell control register, Address offset: 0x20 *) 428 end; 429 430 (** 431 * @brief Inter-integrated Circuit Interface 432 *) 433 434 I2C_TypeDef = record 435 CR1: longword; (*!< I2C Control register 1, Address offset: 0x00 *) 436 CR2: longword; (*!< I2C Control register 2, Address offset: 0x04 *) 437 OAR1: longword; (*!< I2C Own address 1 register, Address offset: 0x08 *) 438 OAR2: longword; (*!< I2C Own address 2 register, Address offset: 0x0C *) 439 TIMINGR: longword; (*!< I2C Timing register, Address offset: 0x10 *) 440 TIMEOUTR: longword; (*!< I2C Timeout register, Address offset: 0x14 *) 441 ISR: longword; (*!< I2C Interrupt and status register, Address offset: 0x18 *) 442 ICR: longword; (*!< I2C Interrupt clear register, Address offset: 0x1C *) 443 PECR: longword; (*!< I2C PEC register, Address offset: 0x20 *) 444 RXDR: longword; (*!< I2C Receive data register, Address offset: 0x24 *) 445 TXDR: longword; (*!< I2C Transmit data register, Address offset: 0x28 *) 446 end; 447 448 (** 449 * @brief Independent WATCHDOG 450 *) 451 452 IWDG_TypeDef = record 453 KR: longword; (*!< IWDG Key register, Address offset: 0x00 *) 454 PR: longword; (*!< IWDG Prescaler register, Address offset: 0x04 *) 455 RLR: longword; (*!< IWDG Reload register, Address offset: 0x08 *) 456 SR: longword; (*!< IWDG Status register, Address offset: 0x0C *) 457 WINR: longword; (*!< IWDG Window register, Address offset: 0x10 *) 458 end; 459 460 461 (** 462 * @brief Power Control 463 *) 464 465 PWR_TypeDef = record 466 CR1: longword; (*!< PWR power control register 1, Address offset: 0x00 *) 467 CSR1: longword; (*!< PWR power control/status register 2, Address offset: 0x04 *) 468 CR2: longword; (*!< PWR power control register 2, Address offset: 0x08 *) 469 CSR2: longword; (*!< PWR power control/status register 2, Address offset: 0x0C *) 470 end; 471 472 473 (** 474 * @brief Reset and Clock Control 475 *) 476 477 RCC_TypeDef = record 478 CR: longword; (*!< RCC clock control register, Address offset: 0x00 *) 479 PLLCFGR: longword; (*!< RCC PLL configuration register, Address offset: 0x04 *) 480 CFGR: longword; (*!< RCC clock configuration register, Address offset: 0x08 *) 481 CIR: longword; (*!< RCC clock interrupt register, Address offset: 0x0C *) 482 AHB1RSTR: longword; (*!< RCC AHB1 peripheral reset register, Address offset: 0x10 *) 483 AHB2RSTR: longword; (*!< RCC AHB2 peripheral reset register, Address offset: 0x14 *) 484 AHB3RSTR: longword; (*!< RCC AHB3 peripheral reset register, Address offset: 0x18 *) 485 RESERVED0: longword; (*!< Reserved, 0x1C *) 486 APB1RSTR: longword; (*!< RCC APB1 peripheral reset register, Address offset: 0x20 *) 487 APB2RSTR: longword; (*!< RCC APB2 peripheral reset register, Address offset: 0x24 *) 488 RESERVED1: array [0..1] of longword; (*!< Reserved, 0x28-0x2C *) 489 AHB1ENR: longword; (*!< RCC AHB1 peripheral clock register, Address offset: 0x30 *) 490 AHB2ENR: longword; (*!< RCC AHB2 peripheral clock register, Address offset: 0x34 *) 491 AHB3ENR: longword; (*!< RCC AHB3 peripheral clock register, Address offset: 0x38 *) 492 RESERVED2: longword; (*!< Reserved, 0x3C *) 493 APB1ENR: longword; (*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 *) 494 APB2ENR: longword; (*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 *) 495 RESERVED3: array [0..1] of longword; (*!< Reserved, 0x48-0x4C *) 496 AHB1LPENR: longword; (*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 *) 497 AHB2LPENR: longword; (*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 *) 498 AHB3LPENR: longword; (*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 *) 499 RESERVED4: longword; (*!< Reserved, 0x5C *) 500 APB1LPENR: longword; (*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 *) 501 APB2LPENR: longword; (*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 *) 502 RESERVED5: array [0..1] of longword; (*!< Reserved, 0x68-0x6C *) 503 BDCR: longword; (*!< RCC Backup domain control register, Address offset: 0x70 *) 504 CSR: longword; (*!< RCC clock control & status register, Address offset: 0x74 *) 505 RESERVED6: array [0..1] of longword; (*!< Reserved, 0x78-0x7C *) 506 SSCGR: longword; (*!< RCC spread spectrum clock generation register, Address offset: 0x80 *) 507 PLLI2SCFGR: longword; (*!< RCC PLLI2S configuration register, Address offset: 0x84 *) 508 PLLSAICFGR: longword; (*!< RCC PLLSAI configuration register, Address offset: 0x88 *) 509 DCKCFGR1: longword; (*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C *) 510 DCKCFGR2: longword; (*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 *) 511 end; 512 513 (** 514 * @brief Real-Time Clock 515 *) 516 517 RTC_TypeDef = record 518 TR: longword; (*!< RTC time register, Address offset: 0x00 *) 519 DR: longword; (*!< RTC date register, Address offset: 0x04 *) 520 CR: longword; (*!< RTC control register, Address offset: 0x08 *) 521 ISR: longword; (*!< RTC initialization and status register, Address offset: 0x0C *) 522 PRER: longword; (*!< RTC prescaler register, Address offset: 0x10 *) 523 WUTR: longword; (*!< RTC wakeup timer register, Address offset: 0x14 *) 524 reserved: longword; (*!< Reserved *) 525 ALRMAR: longword; (*!< RTC alarm A register, Address offset: 0x1C *) 526 ALRMBR: longword; (*!< RTC alarm B register, Address offset: 0x20 *) 527 WPR: longword; (*!< RTC write protection register, Address offset: 0x24 *) 528 SSR: longword; (*!< RTC sub second register, Address offset: 0x28 *) 529 SHIFTR: longword; (*!< RTC shift control register, Address offset: 0x2C *) 530 TSTR: longword; (*!< RTC time stamp time register, Address offset: 0x30 *) 531 TSDR: longword; (*!< RTC time stamp date register, Address offset: 0x34 *) 532 TSSSR: longword; (*!< RTC time-stamp sub second register, Address offset: 0x38 *) 533 CALR: longword; (*!< RTC calibration register, Address offset: 0x3C *) 534 TAMPCR: longword; (*!< RTC tamper configuration register, Address offset: 0x40 *) 535 ALRMASSR: longword; (*!< RTC alarm A sub second register, Address offset: 0x44 *) 536 ALRMBSSR: longword; (*!< RTC alarm B sub second register, Address offset: 0x48 *) 537 OR_: longword; (*!< RTC option register, Address offset: 0x4C *) 538 BKP0R: longword; (*!< RTC backup register 0, Address offset: 0x50 *) 539 BKP1R: longword; (*!< RTC backup register 1, Address offset: 0x54 *) 540 BKP2R: longword; (*!< RTC backup register 2, Address offset: 0x58 *) 541 BKP3R: longword; (*!< RTC backup register 3, Address offset: 0x5C *) 542 BKP4R: longword; (*!< RTC backup register 4, Address offset: 0x60 *) 543 BKP5R: longword; (*!< RTC backup register 5, Address offset: 0x64 *) 544 BKP6R: longword; (*!< RTC backup register 6, Address offset: 0x68 *) 545 BKP7R: longword; (*!< RTC backup register 7, Address offset: 0x6C *) 546 BKP8R: longword; (*!< RTC backup register 8, Address offset: 0x70 *) 547 BKP9R: longword; (*!< RTC backup register 9, Address offset: 0x74 *) 548 BKP10R: longword; (*!< RTC backup register 10, Address offset: 0x78 *) 549 BKP11R: longword; (*!< RTC backup register 11, Address offset: 0x7C *) 550 BKP12R: longword; (*!< RTC backup register 12, Address offset: 0x80 *) 551 BKP13R: longword; (*!< RTC backup register 13, Address offset: 0x84 *) 552 BKP14R: longword; (*!< RTC backup register 14, Address offset: 0x88 *) 553 BKP15R: longword; (*!< RTC backup register 15, Address offset: 0x8C *) 554 BKP16R: longword; (*!< RTC backup register 16, Address offset: 0x90 *) 555 BKP17R: longword; (*!< RTC backup register 17, Address offset: 0x94 *) 556 BKP18R: longword; (*!< RTC backup register 18, Address offset: 0x98 *) 557 BKP19R: longword; (*!< RTC backup register 19, Address offset: 0x9C *) 558 BKP20R: longword; (*!< RTC backup register 20, Address offset: 0xA0 *) 559 BKP21R: longword; (*!< RTC backup register 21, Address offset: 0xA4 *) 560 BKP22R: longword; (*!< RTC backup register 22, Address offset: 0xA8 *) 561 BKP23R: longword; (*!< RTC backup register 23, Address offset: 0xAC *) 562 BKP24R: longword; (*!< RTC backup register 24, Address offset: 0xB0 *) 563 BKP25R: longword; (*!< RTC backup register 25, Address offset: 0xB4 *) 564 BKP26R: longword; (*!< RTC backup register 26, Address offset: 0xB8 *) 565 BKP27R: longword; (*!< RTC backup register 27, Address offset: 0xBC *) 566 BKP28R: longword; (*!< RTC backup register 28, Address offset: 0xC0 *) 567 BKP29R: longword; (*!< RTC backup register 29, Address offset: 0xC4 *) 568 BKP30R: longword; (*!< RTC backup register 30, Address offset: 0xC8 *) 569 BKP31R: longword; (*!< RTC backup register 31, Address offset: 0xCC *) 570 end; 571 572 573 (** 574 * @brief Serial Audio Interface 575 *) 576 577 SAI_TypeDef = record 578 GCR: longword; (*!< SAI global configuration register, Address offset: 0x00 *) 579 end; 580 581 SAI_Block_TypeDef = record 582 CR1: longword; (*!< SAI block x configuration register 1, Address offset: 0x04 *) 583 CR2: longword; (*!< SAI block x configuration register 2, Address offset: 0x08 *) 584 FRCR: longword; (*!< SAI block x frame configuration register, Address offset: 0x0C *) 585 SLOTR: longword; (*!< SAI block x slot register, Address offset: 0x10 *) 586 IMR: longword; (*!< SAI block x interrupt mask register, Address offset: 0x14 *) 587 SR: longword; (*!< SAI block x status register, Address offset: 0x18 *) 588 CLRFR: longword; (*!< SAI block x clear flag register, Address offset: 0x1C *) 589 DR: longword; (*!< SAI block x data register, Address offset: 0x20 *) 590 end; 591 592 (** 593 * @brief SPDIF-RX Interface 594 *) 595 596 SPDIFRX_TypeDef = record 597 CR: longword; (*!< Control register, Address offset: 0x00 *) 598 IMR: longword; (*!< Interrupt mask register, Address offset: 0x04 *) 599 SR: longword; (*!< Status register, Address offset: 0x08 *) 600 IFCR: longword; (*!< Interrupt Flag Clear register, Address offset: 0x0C *) 601 DR: longword; (*!< Data input register, Address offset: 0x10 *) 602 CSR: longword; (*!< Channel Status register, Address offset: 0x14 *) 603 DIR: longword; (*!< Debug Information register, Address offset: 0x18 *) 604 end; 605 606 607 (** 608 * @brief SD host Interface 609 *) 610 611 SDMMC_TypeDef = record 612 POWER: longword; (*!< SDMMC power control register, Address offset: 0x00 *) 613 CLKCR: longword; (*!< SDMMClock control register, Address offset: 0x04 *) 614 ARG: longword; (*!< SDMMC argument register, Address offset: 0x08 *) 615 CMD: longword; (*!< SDMMC command register, Address offset: 0x0C *) 616 RESPCMD: longword; (*!< SDMMC command response register, Address offset: 0x10 *) 617 RESP1: longword; (*!< SDMMC response 1 register, Address offset: 0x14 *) 618 RESP2: longword; (*!< SDMMC response 2 register, Address offset: 0x18 *) 619 RESP3: longword; (*!< SDMMC response 3 register, Address offset: 0x1C *) 620 RESP4: longword; (*!< SDMMC response 4 register, Address offset: 0x20 *) 621 DTIMER: longword; (*!< SDMMC data timer register, Address offset: 0x24 *) 622 DLEN: longword; (*!< SDMMC data length register, Address offset: 0x28 *) 623 DCTRL: longword; (*!< SDMMC data control register, Address offset: 0x2C *) 624 DCOUNT: longword; (*!< SDMMC data counter register, Address offset: 0x30 *) 625 STA: longword; (*!< SDMMC status register, Address offset: 0x34 *) 626 ICR: longword; (*!< SDMMC interrupt clear register, Address offset: 0x38 *) 627 MASK: longword; (*!< SDMMC mask register, Address offset: 0x3C *) 628 RESERVED0: array [0..1] of longword; (*!< Reserved, 0x40-0x44 *) 629 FIFOCNT: longword; (*!< SDMMC FIFO counter register, Address offset: 0x48 *) 630 RESERVED1: array [0..12] of longword; (*!< Reserved, 0x4C-0x7C *) 631 FIFO: longword; (*!< SDMMC data FIFO register, Address offset: 0x80 *) 632 end; 633 634 (** 635 * @brief Serial Peripheral Interface 636 *) 637 638 SPI_TypeDef = record 639 CR1: longword; (*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 *) 640 CR2: longword; (*!< SPI control register 2, Address offset: 0x04 *) 641 SR: longword; (*!< SPI status register, Address offset: 0x08 *) 642 DR: longword; (*!< SPI data register, Address offset: 0x0C *) 643 CRCPR: longword; (*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 *) 644 RXCRCR: longword; (*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 *) 645 TXCRCR: longword; (*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 *) 646 I2SCFGR: longword; (*!< SPI_I2S configuration register, Address offset: 0x1C *) 647 I2SPR: longword; (*!< SPI_I2S prescaler register, Address offset: 0x20 *) 648 end; 649 650 (** 651 * @brief QUAD Serial Peripheral Interface 652 *) 653 654 QUADSPI_TypeDef = record 655 CR: longword; (*!< QUADSPI Control register, Address offset: 0x00 *) 656 DCR: longword; (*!< QUADSPI Device Configuration register, Address offset: 0x04 *) 657 SR: longword; (*!< QUADSPI Status register, Address offset: 0x08 *) 658 FCR: longword; (*!< QUADSPI Flag Clear register, Address offset: 0x0C *) 659 DLR: longword; (*!< QUADSPI Data Length register, Address offset: 0x10 *) 660 CCR: longword; (*!< QUADSPI Communication Configuration register, Address offset: 0x14 *) 661 AR: longword; (*!< QUADSPI Address register, Address offset: 0x18 *) 662 ABR: longword; (*!< QUADSPI Alternate Bytes register, Address offset: 0x1C *) 663 DR: longword; (*!< QUADSPI Data register, Address offset: 0x20 *) 664 PSMKR: longword; (*!< QUADSPI Polling Status Mask register, Address offset: 0x24 *) 665 PSMAR: longword; (*!< QUADSPI Polling Status Match register, Address offset: 0x28 *) 666 PIR: longword; (*!< QUADSPI Polling Interval register, Address offset: 0x2C *) 667 LPTR: longword; (*!< QUADSPI Low Power Timeout register, Address offset: 0x30 *) 668 end; 669 670 (** 671 * @brief TIM 672 *) 673 674 TIM_TypeDef = record 675 CR1: longword; (*!< TIM control register 1, Address offset: 0x00 *) 676 CR2: longword; (*!< TIM control register 2, Address offset: 0x04 *) 677 SMCR: longword; (*!< TIM slave mode control register, Address offset: 0x08 *) 678 DIER: longword; (*!< TIM DMA/interrupt enable register, Address offset: 0x0C *) 679 SR: longword; (*!< TIM status register, Address offset: 0x10 *) 680 EGR: longword; (*!< TIM event generation register, Address offset: 0x14 *) 681 CCMR1: longword; (*!< TIM capture/compare mode register 1, Address offset: 0x18 *) 682 CCMR2: longword; (*!< TIM capture/compare mode register 2, Address offset: 0x1C *) 683 CCER: longword; (*!< TIM capture/compare enable register, Address offset: 0x20 *) 684 CNT: longword; (*!< TIM counter register, Address offset: 0x24 *) 685 PSC: longword; (*!< TIM prescaler, Address offset: 0x28 *) 686 ARR: longword; (*!< TIM auto-reload register, Address offset: 0x2C *) 687 RCR: longword; (*!< TIM repetition counter register, Address offset: 0x30 *) 688 CCR1: longword; (*!< TIM capture/compare register 1, Address offset: 0x34 *) 689 CCR2: longword; (*!< TIM capture/compare register 2, Address offset: 0x38 *) 690 CCR3: longword; (*!< TIM capture/compare register 3, Address offset: 0x3C *) 691 CCR4: longword; (*!< TIM capture/compare register 4, Address offset: 0x40 *) 692 BDTR: longword; (*!< TIM break and dead-time register, Address offset: 0x44 *) 693 DCR: longword; (*!< TIM DMA control register, Address offset: 0x48 *) 694 DMAR: longword; (*!< TIM DMA address for full transfer, Address offset: 0x4C *) 695 OR_: longword; (*!< TIM option register, Address offset: 0x50 *) 696 CCMR3: longword; (*!< TIM capture/compare mode register 3, Address offset: 0x54 *) 697 CCR5: longword; (*!< TIM capture/compare mode register5, Address offset: 0x58 *) 698 CCR6: longword; (*!< TIM capture/compare mode register6, Address offset: 0x5C *) 699 end; 700 701 (** 702 * @brief LPTIMIMER 703 *) 704 705 LPTIM_TypeDef = record 706 ISR: longword; (*!< LPTIM Interrupt and Status register, Address offset: 0x00 *) 707 ICR: longword; (*!< LPTIM Interrupt Clear register, Address offset: 0x04 *) 708 IER: longword; (*!< LPTIM Interrupt Enable register, Address offset: 0x08 *) 709 CFGR: longword; (*!< LPTIM Configuration register, Address offset: 0x0C *) 710 CR: longword; (*!< LPTIM Control register, Address offset: 0x10 *) 711 CMP: longword; (*!< LPTIM Compare register, Address offset: 0x14 *) 712 ARR: longword; (*!< LPTIM Autoreload register, Address offset: 0x18 *) 713 CNT: longword; (*!< LPTIM Counter register, Address offset: 0x1C *) 714 OR_: longword; (*!< LPTIM Option register, Address offset: 0x20 *) 715 end; 716 717 718 (** 719 * @brief Universal Synchronous Asynchronous Receiver Transmitter 720 *) 721 722 USART_TypeDef = record 723 CR1: longword; (*!< USART Control register 1, Address offset: 0x00 *) 724 CR2: longword; (*!< USART Control register 2, Address offset: 0x04 *) 725 CR3: longword; (*!< USART Control register 3, Address offset: 0x08 *) 726 BRR: longword; (*!< USART Baud rate register, Address offset: 0x0C *) 727 GTPR: longword; (*!< USART Guard time and prescaler register, Address offset: 0x10 *) 728 RTOR: longword; (*!< USART Receiver Time Out register, Address offset: 0x14 *) 729 RQR: longword; (*!< USART Request register, Address offset: 0x18 *) 730 ISR: longword; (*!< USART Interrupt and status register, Address offset: 0x1C *) 731 ICR: longword; (*!< USART Interrupt flag Clear register, Address offset: 0x20 *) 732 RDR: longword; (*!< USART Receive Data register, Address offset: 0x24 *) 733 TDR: longword; (*!< USART Transmit Data register, Address offset: 0x28 *) 734 end; 735 736 737 (** 738 * @brief Window WATCHDOG 739 *) 740 741 WWDG_TypeDef = record 742 CR: longword; (*!< WWDG Control register, Address offset: 0x00 *) 743 CFR: longword; (*!< WWDG Configuration register, Address offset: 0x04 *) 744 SR: longword; (*!< WWDG Status register, Address offset: 0x08 *) 745 end; 746 747 (** 748 * @brief RNG 749 *) 750 751 RNG_TypeDef = record 752 CR: longword; (*!< RNG control register, Address offset: 0x00 *) 753 SR: longword; (*!< RNG status register, Address offset: 0x04 *) 754 DR: longword; (*!< RNG data register, Address offset: 0x08 *) 755 end; 756 757 (** 758 * @} 759 *) 760 761 (** 762 * @brief USB_OTG_Core_Registers 763 *) 764 765 USB_OTG_GlobalTypeDef = record 766 GOTGCTL: longword; (*!< USB_OTG Control and Status Register 000h *) 767 GOTGINT: longword; (*!< USB_OTG Interrupt Register 004h *) 768 GAHBCFG: longword; (*!< Core AHB Configuration Register 008h *) 769 GUSBCFG: longword; (*!< Core USB Configuration Register 00Ch *) 770 GRSTCTL: longword; (*!< Core Reset Register 010h *) 771 GINTSTS: longword; (*!< Core Interrupt Register 014h *) 772 GINTMSK: longword; (*!< Core Interrupt Mask Register 018h *) 773 GRXSTSR: longword; (*!< Receive Sts Q Read Register 01Ch *) 774 GRXSTSP: longword; (*!< Receive Sts Q Read & POP Register 020h *) 775 GRXFSIZ: longword; (*!< Receive FIFO Size Register 024h *) 776 DIEPTXF0_HNPTXFSIZ: longword; (*!< EP0 / Non Periodic Tx FIFO Size Register 028h *) 777 HNPTXSTS: longword; (*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch *) 778 Reserved30: array [0..1] of longword; (*!< Reserved 030h *) 779 GCCFG: longword; (*!< General Purpose IO Register 038h *) 780 CID: longword; (*!< User ID Register 03Ch *) 781 Reserved5: array [0..2] of longword; (*!< Reserved 040h-048h *) 782 GHWCFG3: longword; (*!< User HW config3 04Ch *) 783 Reserved6: longword; (*!< Reserved 050h *) 784 GLPMCFG: longword; (*!< LPM Register 054h *) 785 GPWRDN: longword; (*!< Power Down Register 058h *) 786 GDFIFOCFG: longword; (*!< DFIFO Software Config Register 05Ch *) 787 GADPCTL: longword; (*!< ADP Timer, Control and Status Register 60Ch *) 788 Reserved43: array [0..38] of longword; (*!< Reserved 058h-0FFh *) 789 HPTXFSIZ: longword; (*!< Host Periodic Tx FIFO Size Reg 100h *) 790 DIEPTXF: array [0..14] of longword; (*!< dev Periodic Transmit FIFO *) 791 end; 792 793 794 (** 795 * @brief USB_OTG_device_Registers 796 *) 797 798 USB_OTG_DeviceTypeDef = record 799 DCFG: longword; (*!< dev Configuration Register 800h *) 800 DCTL: longword; (*!< dev Control Register 804h *) 801 DSTS: longword; (*!< dev Status Register (RO) 808h *) 802 Reserved0C: longword; (*!< Reserved 80Ch *) 803 DIEPMSK: longword; (*!< dev IN Endpoint Mask 810h *) 804 DOEPMSK: longword; (*!< dev OUT Endpoint Mask 814h *) 805 DAINT: longword; (*!< dev All Endpoints Itr Reg 818h *) 806 DAINTMSK: longword; (*!< dev All Endpoints Itr Mask 81Ch *) 807 Reserved20: longword; (*!< Reserved 820h *) 808 Reserved9: longword; (*!< Reserved 824h *) 809 DVBUSDIS: longword; (*!< dev VBUS discharge Register 828h *) 810 DVBUSPULSE: longword; (*!< dev VBUS Pulse Register 82Ch *) 811 DTHRCTL: longword; (*!< dev threshold 830h *) 812 DIEPEMPMSK: longword; (*!< dev empty msk 834h *) 813 DEACHINT: longword; (*!< dedicated EP interrupt 838h *) 814 DEACHMSK: longword; (*!< dedicated EP msk 83Ch *) 815 Reserved40: longword; (*!< dedicated EP mask 840h *) 816 DINEP1MSK: longword; (*!< dedicated EP mask 844h *) 817 Reserved44: array [0..14] of longword; (*!< Reserved 844-87Ch *) 818 DOUTEP1MSK: longword; (*!< dedicated EP msk 884h *) 819 end; 820 821 822 (** 823 * @brief USB_OTG_IN_Endpoint-Specific_Register 824 *) 825 826 USB_OTG_INEndpointTypeDef = record 827 DIEPCTL: longword; (*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h *) 828 Reserved04: longword; (*!< Reserved 900h + (ep_num * 20h) + 04h *) 829 DIEPINT: longword; (*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h *) 830 Reserved0C: longword; (*!< Reserved 900h + (ep_num * 20h) + 0Ch *) 831 DIEPTSIZ: longword; (*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h *) 832 DIEPDMA: longword; (*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h *) 833 DTXFSTS: longword; (*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h *) 834 Reserved18: longword; (*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch *) 835 end; 836 837 838 (** 839 * @brief USB_OTG_OUT_Endpoint-Specific_Registers 840 *) 841 842 USB_OTG_OUTEndpointTypeDef = record 843 DOEPCTL: longword; (*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h *) 844 Reserved04: longword; (*!< Reserved B00h + (ep_num * 20h) + 04h *) 845 DOEPINT: longword; (*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h *) 846 Reserved0C: longword; (*!< Reserved B00h + (ep_num * 20h) + 0Ch *) 847 DOEPTSIZ: longword; (*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h *) 848 DOEPDMA: longword; (*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h *) 849 Reserved18: array [0..1] of longword; (*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch *) 850 end; 851 852 853 (** 854 * @brief USB_OTG_Host_Mode_Register_Structures 855 *) 856 857 USB_OTG_HostTypeDef = record 858 HCFG: longword; (*!< Host Configuration Register 400h *) 859 HFIR: longword; (*!< Host Frame Interval Register 404h *) 860 HFNUM: longword; (*!< Host Frame Nbr/Frame Remaining 408h *) 861 Reserved40C: longword; (*!< Reserved 40Ch *) 862 HPTXSTS: longword; (*!< Host Periodic Tx FIFO/ Queue Status 410h *) 863 HAINT: longword; (*!< Host All Channels Interrupt Register 414h *) 864 HAINTMSK: longword; (*!< Host All Channels Interrupt Mask 418h *) 865 end; 866 867 (** 868 * @brief USB_OTG_Host_Channel_Specific_Registers 869 *) 870 871 USB_OTG_HostChannelTypeDef = record 872 HCCHAR: longword; (*!< Host Channel Characteristics Register 500h *) 873 HCSPLT: longword; (*!< Host Channel Split Control Register 504h *) 874 HCINT: longword; (*!< Host Channel Interrupt Register 508h *) 875 HCINTMSK: longword; (*!< Host Channel Interrupt Mask Register 50Ch *) 876 HCTSIZ: longword; (*!< Host Channel Transfer Size Register 510h *) 877 HCDMA: longword; (*!< Host Channel DMA Address Register 514h *) 878 Reserved: array [0..1] of longword; (*!< Reserved *) 879 end; 880 881 (** 882 * @} 883 *) 884 885 886 (** @addtogroup Peripheral_memory_map 887 * @{ 888 *) 889 890const 891 RAMITCM_BASE = $00000000; (*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM *) 892 FLASHITCM_BASE = $00200000; (*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM *) 893 FLASHAXI_BASE = $08000000; (*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI *) 894 RAMDTCM_BASE = $20000000; (*!< Base address of : 64KB system data RAM accessible over DTCM *) 895 SRAM1_BASE = $20010000; (*!< Base address of : 240KB RAM1 accessible over AXI/AHB *) 896 SRAM2_BASE = $2004C000; (*!< Base address of : 16KB RAM2 accessible over AXI/AHB *) 897 PERIPH_BASE = $40000000; (*!< Base address of : AHB/ABP Peripherals *) 898 BKPSRAM_BASE = $40024000; (*!< Base address of : Backup SRAM(4 KB) *) 899 QSPI_BASE = $90000000; (*!< Base address of : QSPI memories accessible over AXI *) 900 FMC_R_BASE = $A0000000; (*!< Base address of : FMC Control registers *) 901 QSPI_R_BASE = $A0001000; (*!< Base address of : QSPI Control registers *) 902 FLASH_END = $080FFFFF; (*!< FLASH end address *) 903 (* Legacy define *) 904 905 FLASH_BASE = FLASHAXI_BASE; 906 (*!< Peripheral memory map *) 907 908 APB1PERIPH_BASE = PERIPH_BASE; 909 APB2PERIPH_BASE = (PERIPH_BASE + $00010000); 910 AHB1PERIPH_BASE = (PERIPH_BASE + $00020000); 911 AHB2PERIPH_BASE = (PERIPH_BASE + $10000000); 912 (*!< APB1 peripherals *) 913 914 TIM2_BASE = (APB1PERIPH_BASE + $0000); 915 TIM3_BASE = (APB1PERIPH_BASE + $0400); 916 TIM4_BASE = (APB1PERIPH_BASE + $0800); 917 TIM5_BASE = (APB1PERIPH_BASE + $0C00); 918 TIM6_BASE = (APB1PERIPH_BASE + $1000); 919 TIM7_BASE = (APB1PERIPH_BASE + $1400); 920 TIM12_BASE = (APB1PERIPH_BASE + $1800); 921 TIM13_BASE = (APB1PERIPH_BASE + $1C00); 922 TIM14_BASE = (APB1PERIPH_BASE + $2000); 923 LPTIM1_BASE = (APB1PERIPH_BASE + $2400); 924 RTC_BASE = (APB1PERIPH_BASE + $2800); 925 WWDG_BASE = (APB1PERIPH_BASE + $2C00); 926 IWDG_BASE = (APB1PERIPH_BASE + $3000); 927 SPI2_BASE = (APB1PERIPH_BASE + $3800); 928 SPI3_BASE = (APB1PERIPH_BASE + $3C00); 929 SPDIFRX_BASE = (APB1PERIPH_BASE + $4000); 930 USART2_BASE = (APB1PERIPH_BASE + $4400); 931 USART3_BASE = (APB1PERIPH_BASE + $4800); 932 UART4_BASE = (APB1PERIPH_BASE + $4C00); 933 UART5_BASE = (APB1PERIPH_BASE + $5000); 934 I2C1_BASE = (APB1PERIPH_BASE + $5400); 935 I2C2_BASE = (APB1PERIPH_BASE + $5800); 936 I2C3_BASE = (APB1PERIPH_BASE + $5C00); 937 I2C4_BASE = (APB1PERIPH_BASE + $6000); 938 CAN1_BASE = (APB1PERIPH_BASE + $6400); 939 CAN2_BASE = (APB1PERIPH_BASE + $6800); 940 CEC_BASE = (APB1PERIPH_BASE + $6C00); 941 PWR_BASE = (APB1PERIPH_BASE + $7000); 942 DAC_BASE = (APB1PERIPH_BASE + $7400); 943 UART7_BASE = (APB1PERIPH_BASE + $7800); 944 UART8_BASE = (APB1PERIPH_BASE + $7C00); 945 (*!< APB2 peripherals *) 946 947 TIM1_BASE = (APB2PERIPH_BASE + $0000); 948 TIM8_BASE = (APB2PERIPH_BASE + $0400); 949 USART1_BASE = (APB2PERIPH_BASE + $1000); 950 USART6_BASE = (APB2PERIPH_BASE + $1400); 951 ADC1_BASE = (APB2PERIPH_BASE + $2000); 952 ADC2_BASE = (APB2PERIPH_BASE + $2100); 953 ADC3_BASE = (APB2PERIPH_BASE + $2200); 954 ADC_BASE = (APB2PERIPH_BASE + $2300); 955 SDMMC1_BASE = (APB2PERIPH_BASE + $2C00); 956 SPI1_BASE = (APB2PERIPH_BASE + $3000); 957 SPI4_BASE = (APB2PERIPH_BASE + $3400); 958 SYSCFG_BASE = (APB2PERIPH_BASE + $3800); 959 EXTI_BASE = (APB2PERIPH_BASE + $3C00); 960 TIM9_BASE = (APB2PERIPH_BASE + $4000); 961 TIM10_BASE = (APB2PERIPH_BASE + $4400); 962 TIM11_BASE = (APB2PERIPH_BASE + $4800); 963 SPI5_BASE = (APB2PERIPH_BASE + $5000); 964 SPI6_BASE = (APB2PERIPH_BASE + $5400); 965 SAI1_BASE = (APB2PERIPH_BASE + $5800); 966 SAI2_BASE = (APB2PERIPH_BASE + $5C00); 967 SAI1_Block_A_BASE = (SAI1_BASE + $004); 968 SAI1_Block_B_BASE = (SAI1_BASE + $024); 969 SAI2_Block_A_BASE = (SAI2_BASE + $004); 970 SAI2_Block_B_BASE = (SAI2_BASE + $024); 971 (*!< AHB1 peripherals *) 972 973 GPIOA_BASE = (AHB1PERIPH_BASE + $0000); 974 GPIOB_BASE = (AHB1PERIPH_BASE + $0400); 975 GPIOC_BASE = (AHB1PERIPH_BASE + $0800); 976 GPIOD_BASE = (AHB1PERIPH_BASE + $0C00); 977 GPIOE_BASE = (AHB1PERIPH_BASE + $1000); 978 GPIOF_BASE = (AHB1PERIPH_BASE + $1400); 979 GPIOG_BASE = (AHB1PERIPH_BASE + $1800); 980 GPIOH_BASE = (AHB1PERIPH_BASE + $1C00); 981 GPIOI_BASE = (AHB1PERIPH_BASE + $2000); 982 GPIOJ_BASE = (AHB1PERIPH_BASE + $2400); 983 GPIOK_BASE = (AHB1PERIPH_BASE + $2800); 984 CRC_BASE = (AHB1PERIPH_BASE + $3000); 985 RCC_BASE = (AHB1PERIPH_BASE + $3800); 986 FLASH_R_BASE = (AHB1PERIPH_BASE + $3C00); 987 DMA1_BASE = (AHB1PERIPH_BASE + $6000); 988 DMA1_Stream0_BASE = (DMA1_BASE + $010); 989 DMA1_Stream1_BASE = (DMA1_BASE + $028); 990 DMA1_Stream2_BASE = (DMA1_BASE + $040); 991 DMA1_Stream3_BASE = (DMA1_BASE + $058); 992 DMA1_Stream4_BASE = (DMA1_BASE + $070); 993 DMA1_Stream5_BASE = (DMA1_BASE + $088); 994 DMA1_Stream6_BASE = (DMA1_BASE + $0A0); 995 DMA1_Stream7_BASE = (DMA1_BASE + $0B8); 996 DMA2_BASE = (AHB1PERIPH_BASE + $6400); 997 DMA2_Stream0_BASE = (DMA2_BASE + $010); 998 DMA2_Stream1_BASE = (DMA2_BASE + $028); 999 DMA2_Stream2_BASE = (DMA2_BASE + $040); 1000 DMA2_Stream3_BASE = (DMA2_BASE + $058); 1001 DMA2_Stream4_BASE = (DMA2_BASE + $070); 1002 DMA2_Stream5_BASE = (DMA2_BASE + $088); 1003 DMA2_Stream6_BASE = (DMA2_BASE + $0A0); 1004 DMA2_Stream7_BASE = (DMA2_BASE + $0B8); 1005 ETH_BASE = (AHB1PERIPH_BASE + $8000); 1006 ETH_MAC_BASE = (ETH_BASE); 1007 ETH_MMC_BASE = (ETH_BASE + $0100); 1008 ETH_PTP_BASE = (ETH_BASE + $0700); 1009 ETH_DMA_BASE = (ETH_BASE + $1000); 1010 DMA2D_BASE = (AHB1PERIPH_BASE + $B000); 1011 (*!< AHB2 peripherals *) 1012 1013 DCMI_BASE = (AHB2PERIPH_BASE + $50000); 1014 RNG_BASE = (AHB2PERIPH_BASE + $60800); 1015 (*!< FMC Bankx registers base address *) 1016 1017 FMC_Bank1_R_BASE = (FMC_R_BASE + $0000); 1018 FMC_Bank1E_R_BASE = (FMC_R_BASE + $0104); 1019 FMC_Bank3_R_BASE = (FMC_R_BASE + $0080); 1020 FMC_Bank5_6_R_BASE = (FMC_R_BASE + $0140); 1021 (* Debug MCU registers base address *) 1022 1023 DBGMCU_BASE = $E0042000; 1024 (*!< USB registers base address *) 1025 1026 USB_OTG_HS_PERIPH_BASE = $40040000; 1027 USB_OTG_FS_PERIPH_BASE = $50000000; 1028 USB_OTG_GLOBAL_BASE = $000; 1029 USB_OTG_DEVICE_BASE = $800; 1030 USB_OTG_IN_ENDPOINT_BASE = $900; 1031 USB_OTG_OUT_ENDPOINT_BASE = $B00; 1032 USB_OTG_EP_REG_SIZE = $20; 1033 USB_OTG_HOST_BASE = $400; 1034 USB_OTG_HOST_PORT_BASE = $440; 1035 USB_OTG_HOST_CHANNEL_BASE = $500; 1036 USB_OTG_HOST_CHANNEL_SIZE = $20; 1037 USB_OTG_PCGCCTL_BASE = $E00; 1038 USB_OTG_FIFO_BASE = $1000; 1039 USB_OTG_FIFO_SIZE = $1000; 1040 1041var 1042 TIM2: TIM_TypeDef absolute TIM2_BASE; 1043 TIM3: TIM_TypeDef absolute TIM3_BASE; 1044 TIM4: TIM_TypeDef absolute TIM4_BASE; 1045 TIM5: TIM_TypeDef absolute TIM5_BASE; 1046 TIM6: TIM_TypeDef absolute TIM6_BASE; 1047 TIM7: TIM_TypeDef absolute TIM7_BASE; 1048 TIM12: TIM_TypeDef absolute TIM12_BASE; 1049 TIM13: TIM_TypeDef absolute TIM13_BASE; 1050 TIM14: TIM_TypeDef absolute TIM14_BASE; 1051 LPTIM1: LPTIM_TypeDef absolute LPTIM1_BASE; 1052 RTC: RTC_TypeDef absolute RTC_BASE; 1053 WWDG: WWDG_TypeDef absolute WWDG_BASE; 1054 IWDG: IWDG_TypeDef absolute IWDG_BASE; 1055 SPI2: SPI_TypeDef absolute SPI2_BASE; 1056 SPI3: SPI_TypeDef absolute SPI3_BASE; 1057 SPDIFRX: SPDIFRX_TypeDef absolute SPDIFRX_BASE; 1058 USART2: USART_TypeDef absolute USART2_BASE; 1059 USART3: USART_TypeDef absolute USART3_BASE; 1060 UART4: USART_TypeDef absolute UART4_BASE; 1061 UART5: USART_TypeDef absolute UART5_BASE; 1062 I2C1: I2C_TypeDef absolute I2C1_BASE; 1063 I2C2: I2C_TypeDef absolute I2C2_BASE; 1064 I2C3: I2C_TypeDef absolute I2C3_BASE; 1065 I2C4: I2C_TypeDef absolute I2C4_BASE; 1066 CAN1: CAN_TypeDef absolute CAN1_BASE; 1067 CAN2: CAN_TypeDef absolute CAN2_BASE; 1068 CEC: CEC_TypeDef absolute CEC_BASE; 1069 PWR: PWR_TypeDef absolute PWR_BASE; 1070 DAC: DAC_TypeDef absolute DAC_BASE; 1071 UART7: USART_TypeDef absolute UART7_BASE; 1072 UART8: USART_TypeDef absolute UART8_BASE; 1073 TIM1: TIM_TypeDef absolute TIM1_BASE; 1074 TIM8: TIM_TypeDef absolute TIM8_BASE; 1075 USART1: USART_TypeDef absolute USART1_BASE; 1076 USART6: USART_TypeDef absolute USART6_BASE; 1077 ADC: ADC_Common_TypeDef absolute ADC_BASE; 1078 ADC1: ADC_TypeDef absolute ADC1_BASE; 1079 ADC2: ADC_TypeDef absolute ADC2_BASE; 1080 ADC3: ADC_TypeDef absolute ADC3_BASE; 1081 SDMMC1: SDMMC_TypeDef absolute SDMMC1_BASE; 1082 SPI1: SPI_TypeDef absolute SPI1_BASE; 1083 SPI4: SPI_TypeDef absolute SPI4_BASE; 1084 SYSCFG: SYSCFG_TypeDef absolute SYSCFG_BASE; 1085 EXTI: EXTI_TypeDef absolute EXTI_BASE; 1086 TIM9: TIM_TypeDef absolute TIM9_BASE; 1087 TIM10: TIM_TypeDef absolute TIM10_BASE; 1088 TIM11: TIM_TypeDef absolute TIM11_BASE; 1089 SPI5: SPI_TypeDef absolute SPI5_BASE; 1090 SPI6: SPI_TypeDef absolute SPI6_BASE; 1091 SAI1: SAI_TypeDef absolute SAI1_BASE; 1092 SAI2: SAI_TypeDef absolute SAI2_BASE; 1093 SAI1_Block_A: SAI_Block_TypeDef absolute SAI1_Block_A_BASE; 1094 SAI1_Block_B: SAI_Block_TypeDef absolute SAI1_Block_B_BASE; 1095 SAI2_Block_A: SAI_Block_TypeDef absolute SAI2_Block_A_BASE; 1096 SAI2_Block_B: SAI_Block_TypeDef absolute SAI2_Block_B_BASE; 1097 GPIOA: GPIO_TypeDef absolute GPIOA_BASE; 1098 GPIOB: GPIO_TypeDef absolute GPIOB_BASE; 1099 GPIOC: GPIO_TypeDef absolute GPIOC_BASE; 1100 GPIOD: GPIO_TypeDef absolute GPIOD_BASE; 1101 GPIOE: GPIO_TypeDef absolute GPIOE_BASE; 1102 GPIOF: GPIO_TypeDef absolute GPIOF_BASE; 1103 GPIOG: GPIO_TypeDef absolute GPIOG_BASE; 1104 GPIOH: GPIO_TypeDef absolute GPIOH_BASE; 1105 GPIOI: GPIO_TypeDef absolute GPIOI_BASE; 1106 GPIOJ: GPIO_TypeDef absolute GPIOJ_BASE; 1107 GPIOK: GPIO_TypeDef absolute GPIOK_BASE; 1108 CRC: CRC_TypeDef absolute CRC_BASE; 1109 RCC: RCC_TypeDef absolute RCC_BASE; 1110 FLASH: FLASH_TypeDef absolute FLASH_R_BASE; 1111 DMA1: DMA_TypeDef absolute DMA1_BASE; 1112 DMA1_Stream0: DMA_Stream_TypeDef absolute DMA1_Stream0_BASE; 1113 DMA1_Stream1: DMA_Stream_TypeDef absolute DMA1_Stream1_BASE; 1114 DMA1_Stream2: DMA_Stream_TypeDef absolute DMA1_Stream2_BASE; 1115 DMA1_Stream3: DMA_Stream_TypeDef absolute DMA1_Stream3_BASE; 1116 DMA1_Stream4: DMA_Stream_TypeDef absolute DMA1_Stream4_BASE; 1117 DMA1_Stream5: DMA_Stream_TypeDef absolute DMA1_Stream5_BASE; 1118 DMA1_Stream6: DMA_Stream_TypeDef absolute DMA1_Stream6_BASE; 1119 DMA1_Stream7: DMA_Stream_TypeDef absolute DMA1_Stream7_BASE; 1120 DMA2: DMA_TypeDef absolute DMA2_BASE; 1121 DMA2_Stream0: DMA_Stream_TypeDef absolute DMA2_Stream0_BASE; 1122 DMA2_Stream1: DMA_Stream_TypeDef absolute DMA2_Stream1_BASE; 1123 DMA2_Stream2: DMA_Stream_TypeDef absolute DMA2_Stream2_BASE; 1124 DMA2_Stream3: DMA_Stream_TypeDef absolute DMA2_Stream3_BASE; 1125 DMA2_Stream4: DMA_Stream_TypeDef absolute DMA2_Stream4_BASE; 1126 DMA2_Stream5: DMA_Stream_TypeDef absolute DMA2_Stream5_BASE; 1127 DMA2_Stream6: DMA_Stream_TypeDef absolute DMA2_Stream6_BASE; 1128 DMA2_Stream7: DMA_Stream_TypeDef absolute DMA2_Stream7_BASE; 1129 ETH: ETH_TypeDef absolute ETH_BASE; 1130 DMA2D: DMA2D_TypeDef absolute DMA2D_BASE; 1131 DCMI: DCMI_TypeDef absolute DCMI_BASE; 1132 RNG: RNG_TypeDef absolute RNG_BASE; 1133 FMC_Bank1: FMC_Bank1_TypeDef absolute FMC_Bank1_R_BASE; 1134 FMC_Bank1E: FMC_Bank1E_TypeDef absolute FMC_Bank1E_R_BASE; 1135 FMC_Bank3: FMC_Bank3_TypeDef absolute FMC_Bank3_R_BASE; 1136 FMC_Bank5_6: FMC_Bank5_6_TypeDef absolute FMC_Bank5_6_R_BASE; 1137 QUADSPI: QUADSPI_TypeDef absolute QSPI_R_BASE; 1138 DBGMCU: DBGMCU_TypeDef absolute DBGMCU_BASE; 1139 USB_OTG_FS: USB_OTG_GlobalTypeDef absolute USB_OTG_FS_PERIPH_BASE; 1140 USB_OTG_HS: USB_OTG_GlobalTypeDef absolute USB_OTG_HS_PERIPH_BASE; 1141 1142implementation 1143 1144procedure NMI_Interrupt; external name 'NMI_Interrupt'; 1145procedure HardFault_Interrupt; external name 'HardFault_Interrupt'; 1146procedure MemManage_Interrupt; external name 'MemManage_Interrupt'; 1147procedure BusFault_Interrupt; external name 'BusFault_Interrupt'; 1148procedure UsageFault_Interrupt; external name 'UsageFault_Interrupt'; 1149procedure SVC_Interrupt; external name 'SVC_Interrupt'; 1150procedure DebugMon_Interrupt; external name 'DebugMon_Interrupt'; 1151procedure PendSV_Interrupt; external name 'PendSV_Interrupt'; 1152procedure SysTick_Interrupt; external name 'SysTick_Interrupt'; 1153procedure WWDG_Interrupt; external name 'WWDG_Interrupt'; 1154procedure PVD_Interrupt; external name 'PVD_Interrupt'; 1155procedure TAMP_STAMP_Interrupt; external name 'TAMP_STAMP_Interrupt'; 1156procedure RTC_WKUP_Interrupt; external name 'RTC_WKUP_Interrupt'; 1157procedure FLASH_Interrupt; external name 'FLASH_Interrupt'; 1158procedure RCC_Interrupt; external name 'RCC_Interrupt'; 1159procedure EXTI0_Interrupt; external name 'EXTI0_Interrupt'; 1160procedure EXTI1_Interrupt; external name 'EXTI1_Interrupt'; 1161procedure EXTI2_Interrupt; external name 'EXTI2_Interrupt'; 1162procedure EXTI3_Interrupt; external name 'EXTI3_Interrupt'; 1163procedure EXTI4_Interrupt; external name 'EXTI4_Interrupt'; 1164procedure DMA1_Stream0_Interrupt; external name 'DMA1_Stream0_Interrupt'; 1165procedure DMA1_Stream1_Interrupt; external name 'DMA1_Stream1_Interrupt'; 1166procedure DMA1_Stream2_Interrupt; external name 'DMA1_Stream2_Interrupt'; 1167procedure DMA1_Stream3_Interrupt; external name 'DMA1_Stream3_Interrupt'; 1168procedure DMA1_Stream4_Interrupt; external name 'DMA1_Stream4_Interrupt'; 1169procedure DMA1_Stream5_Interrupt; external name 'DMA1_Stream5_Interrupt'; 1170procedure DMA1_Stream6_Interrupt; external name 'DMA1_Stream6_Interrupt'; 1171procedure ADC_Interrupt; external name 'ADC_Interrupt'; 1172procedure CAN1_TX_Interrupt; external name 'CAN1_TX_Interrupt'; 1173procedure CAN1_RX0_Interrupt; external name 'CAN1_RX0_Interrupt'; 1174procedure CAN1_RX1_Interrupt; external name 'CAN1_RX1_Interrupt'; 1175procedure CAN1_SCE_Interrupt; external name 'CAN1_SCE_Interrupt'; 1176procedure EXTI9_5_Interrupt; external name 'EXTI9_5_Interrupt'; 1177procedure TIM1_BRK_TIM9_Interrupt; external name 'TIM1_BRK_TIM9_Interrupt'; 1178procedure TIM1_UP_TIM10_Interrupt; external name 'TIM1_UP_TIM10_Interrupt'; 1179procedure TIM1_TRG_COM_TIM11_Interrupt; external name 'TIM1_TRG_COM_TIM11_Interrupt'; 1180procedure TIM1_CC_Interrupt; external name 'TIM1_CC_Interrupt'; 1181procedure TIM2_Interrupt; external name 'TIM2_Interrupt'; 1182procedure TIM3_Interrupt; external name 'TIM3_Interrupt'; 1183procedure TIM4_Interrupt; external name 'TIM4_Interrupt'; 1184procedure I2C1_EV_Interrupt; external name 'I2C1_EV_Interrupt'; 1185procedure I2C1_ER_Interrupt; external name 'I2C1_ER_Interrupt'; 1186procedure I2C2_EV_Interrupt; external name 'I2C2_EV_Interrupt'; 1187procedure I2C2_ER_Interrupt; external name 'I2C2_ER_Interrupt'; 1188procedure SPI1_Interrupt; external name 'SPI1_Interrupt'; 1189procedure SPI2_Interrupt; external name 'SPI2_Interrupt'; 1190procedure USART1_Interrupt; external name 'USART1_Interrupt'; 1191procedure USART2_Interrupt; external name 'USART2_Interrupt'; 1192procedure USART3_Interrupt; external name 'USART3_Interrupt'; 1193procedure EXTI15_10_Interrupt; external name 'EXTI15_10_Interrupt'; 1194procedure RTC_Alarm_Interrupt; external name 'RTC_Alarm_Interrupt'; 1195procedure OTG_FS_WKUP_Interrupt; external name 'OTG_FS_WKUP_Interrupt'; 1196procedure TIM8_BRK_TIM12_Interrupt; external name 'TIM8_BRK_TIM12_Interrupt'; 1197procedure TIM8_UP_TIM13_Interrupt; external name 'TIM8_UP_TIM13_Interrupt'; 1198procedure TIM8_TRG_COM_TIM14_Interrupt; external name 'TIM8_TRG_COM_TIM14_Interrupt'; 1199procedure TIM8_CC_Interrupt; external name 'TIM8_CC_Interrupt'; 1200procedure DMA1_Stream7_Interrupt; external name 'DMA1_Stream7_Interrupt'; 1201procedure FMC_Interrupt; external name 'FMC_Interrupt'; 1202procedure SDMMC1_Interrupt; external name 'SDMMC1_Interrupt'; 1203procedure TIM5_Interrupt; external name 'TIM5_Interrupt'; 1204procedure SPI3_Interrupt; external name 'SPI3_Interrupt'; 1205procedure UART4_Interrupt; external name 'UART4_Interrupt'; 1206procedure UART5_Interrupt; external name 'UART5_Interrupt'; 1207procedure TIM6_DAC_Interrupt; external name 'TIM6_DAC_Interrupt'; 1208procedure TIM7_Interrupt; external name 'TIM7_Interrupt'; 1209procedure DMA2_Stream0_Interrupt; external name 'DMA2_Stream0_Interrupt'; 1210procedure DMA2_Stream1_Interrupt; external name 'DMA2_Stream1_Interrupt'; 1211procedure DMA2_Stream2_Interrupt; external name 'DMA2_Stream2_Interrupt'; 1212procedure DMA2_Stream3_Interrupt; external name 'DMA2_Stream3_Interrupt'; 1213procedure DMA2_Stream4_Interrupt; external name 'DMA2_Stream4_Interrupt'; 1214procedure ETH_Interrupt; external name 'ETH_Interrupt'; 1215procedure ETH_WKUP_Interrupt; external name 'ETH_WKUP_Interrupt'; 1216procedure CAN2_TX_Interrupt; external name 'CAN2_TX_Interrupt'; 1217procedure CAN2_RX0_Interrupt; external name 'CAN2_RX0_Interrupt'; 1218procedure CAN2_RX1_Interrupt; external name 'CAN2_RX1_Interrupt'; 1219procedure CAN2_SCE_Interrupt; external name 'CAN2_SCE_Interrupt'; 1220procedure OTG_FS_Interrupt; external name 'OTG_FS_Interrupt'; 1221procedure DMA2_Stream5_Interrupt; external name 'DMA2_Stream5_Interrupt'; 1222procedure DMA2_Stream6_Interrupt; external name 'DMA2_Stream6_Interrupt'; 1223procedure DMA2_Stream7_Interrupt; external name 'DMA2_Stream7_Interrupt'; 1224procedure USART6_Interrupt; external name 'USART6_Interrupt'; 1225procedure I2C3_EV_Interrupt; external name 'I2C3_EV_Interrupt'; 1226procedure I2C3_ER_Interrupt; external name 'I2C3_ER_Interrupt'; 1227procedure OTG_HS_EP1_OUT_Interrupt; external name 'OTG_HS_EP1_OUT_Interrupt'; 1228procedure OTG_HS_EP1_IN_Interrupt; external name 'OTG_HS_EP1_IN_Interrupt'; 1229procedure OTG_HS_WKUP_Interrupt; external name 'OTG_HS_WKUP_Interrupt'; 1230procedure OTG_HS_Interrupt; external name 'OTG_HS_Interrupt'; 1231procedure DCMI_Interrupt; external name 'DCMI_Interrupt'; 1232procedure RNG_Interrupt; external name 'RNG_Interrupt'; 1233procedure FPU_Interrupt; external name 'FPU_Interrupt'; 1234procedure UART7_Interrupt; external name 'UART7_Interrupt'; 1235procedure UART8_Interrupt; external name 'UART8_Interrupt'; 1236procedure SPI4_Interrupt; external name 'SPI4_Interrupt'; 1237procedure SPI5_Interrupt; external name 'SPI5_Interrupt'; 1238procedure SPI6_Interrupt; external name 'SPI6_Interrupt'; 1239procedure SAI1_Interrupt; external name 'SAI1_Interrupt'; 1240procedure DMA2D_Interrupt; external name 'DMA2D_Interrupt'; 1241procedure SAI2_Interrupt; external name 'SAI2_Interrupt'; 1242procedure QUADSPI_Interrupt; external name 'QUADSPI_Interrupt'; 1243procedure LPTIM1_Interrupt; external name 'LPTIM1_Interrupt'; 1244procedure CEC_Interrupt; external name 'CEC_Interrupt'; 1245procedure I2C4_EV_Interrupt; external name 'I2C4_EV_Interrupt'; 1246procedure I2C4_ER_Interrupt; external name 'I2C4_ER_Interrupt'; 1247procedure SPDIF_RX_Interrupt; external name 'SPDIF_RX_Interrupt'; 1248 1249{$i cortexm4f_start.inc} 1250 1251procedure Vectors; assembler; nostackframe; 1252label interrupt_vectors; 1253asm 1254 .section ".init.interrupt_vectors" 1255interrupt_vectors: 1256 .long _stack_top 1257 .long Startup 1258 1259 .long NMI_Interrupt 1260 .long HardFault_Interrupt 1261 .long MemManage_Interrupt 1262 .long BusFault_Interrupt 1263 .long UsageFault_Interrupt 1264 .long 0 1265 .long 0 1266 .long 0 1267 .long 0 1268 .long SVC_Interrupt 1269 .long DebugMon_Interrupt 1270 .long 0 1271 .long PendSV_Interrupt 1272 .long SysTick_Interrupt 1273 1274 (* External Interrupts *) 1275 .long WWDG_Interrupt 1276 .long PVD_Interrupt 1277 .long TAMP_STAMP_Interrupt 1278 .long RTC_WKUP_Interrupt 1279 .long FLASH_Interrupt 1280 .long RCC_Interrupt 1281 .long EXTI0_Interrupt 1282 .long EXTI1_Interrupt 1283 .long EXTI2_Interrupt 1284 .long EXTI3_Interrupt 1285 .long EXTI4_Interrupt 1286 .long DMA1_Stream0_Interrupt 1287 .long DMA1_Stream1_Interrupt 1288 .long DMA1_Stream2_Interrupt 1289 .long DMA1_Stream3_Interrupt 1290 .long DMA1_Stream4_Interrupt 1291 .long DMA1_Stream5_Interrupt 1292 .long DMA1_Stream6_Interrupt 1293 .long ADC_Interrupt 1294 .long CAN1_TX_Interrupt 1295 .long CAN1_RX0_Interrupt 1296 .long CAN1_RX1_Interrupt 1297 .long CAN1_SCE_Interrupt 1298 .long EXTI9_5_Interrupt 1299 .long TIM1_BRK_TIM9_Interrupt 1300 .long TIM1_UP_TIM10_Interrupt 1301 .long TIM1_TRG_COM_TIM11_Interrupt 1302 .long TIM1_CC_Interrupt 1303 .long TIM2_Interrupt 1304 .long TIM3_Interrupt 1305 .long TIM4_Interrupt 1306 .long I2C1_EV_Interrupt 1307 .long I2C1_ER_Interrupt 1308 .long I2C2_EV_Interrupt 1309 .long I2C2_ER_Interrupt 1310 .long SPI1_Interrupt 1311 .long SPI2_Interrupt 1312 .long USART1_Interrupt 1313 .long USART2_Interrupt 1314 .long USART3_Interrupt 1315 .long EXTI15_10_Interrupt 1316 .long RTC_Alarm_Interrupt 1317 .long OTG_FS_WKUP_Interrupt 1318 .long TIM8_BRK_TIM12_Interrupt 1319 .long TIM8_UP_TIM13_Interrupt 1320 .long TIM8_TRG_COM_TIM14_Interrupt 1321 .long TIM8_CC_Interrupt 1322 .long DMA1_Stream7_Interrupt 1323 .long FMC_Interrupt 1324 .long SDMMC1_Interrupt 1325 .long TIM5_Interrupt 1326 .long SPI3_Interrupt 1327 .long UART4_Interrupt 1328 .long UART5_Interrupt 1329 .long TIM6_DAC_Interrupt 1330 .long TIM7_Interrupt 1331 .long DMA2_Stream0_Interrupt 1332 .long DMA2_Stream1_Interrupt 1333 .long DMA2_Stream2_Interrupt 1334 .long DMA2_Stream3_Interrupt 1335 .long DMA2_Stream4_Interrupt 1336 .long ETH_Interrupt 1337 .long ETH_WKUP_Interrupt 1338 .long CAN2_TX_Interrupt 1339 .long CAN2_RX0_Interrupt 1340 .long CAN2_RX1_Interrupt 1341 .long CAN2_SCE_Interrupt 1342 .long OTG_FS_Interrupt 1343 .long DMA2_Stream5_Interrupt 1344 .long DMA2_Stream6_Interrupt 1345 .long DMA2_Stream7_Interrupt 1346 .long USART6_Interrupt 1347 .long I2C3_EV_Interrupt 1348 .long I2C3_ER_Interrupt 1349 .long OTG_HS_EP1_OUT_Interrupt 1350 .long OTG_HS_EP1_IN_Interrupt 1351 .long OTG_HS_WKUP_Interrupt 1352 .long OTG_HS_Interrupt 1353 .long DCMI_Interrupt 1354 .long 0 1355 .long RNG_Interrupt 1356 .long FPU_Interrupt 1357 .long UART7_Interrupt 1358 .long UART8_Interrupt 1359 .long SPI4_Interrupt 1360 .long SPI5_Interrupt 1361 .long SPI6_Interrupt 1362 .long SAI1_Interrupt 1363 .long 0 1364 .long 0 1365 .long DMA2D_Interrupt 1366 .long SAI2_Interrupt 1367 .long QUADSPI_Interrupt 1368 .long LPTIM1_Interrupt 1369 .long CEC_Interrupt 1370 .long I2C4_EV_Interrupt 1371 .long I2C4_ER_Interrupt 1372 .long SPDIF_RX_Interrupt 1373 1374 .weak NMI_Interrupt 1375 .weak HardFault_Interrupt 1376 .weak MemManage_Interrupt 1377 .weak BusFault_Interrupt 1378 .weak UsageFault_Interrupt 1379 .weak SVC_Interrupt 1380 .weak DebugMon_Interrupt 1381 .weak PendSV_Interrupt 1382 .weak SysTick_Interrupt 1383 .weak WWDG_Interrupt 1384 .weak PVD_Interrupt 1385 .weak TAMP_STAMP_Interrupt 1386 .weak RTC_WKUP_Interrupt 1387 .weak FLASH_Interrupt 1388 .weak RCC_Interrupt 1389 .weak EXTI0_Interrupt 1390 .weak EXTI1_Interrupt 1391 .weak EXTI2_Interrupt 1392 .weak EXTI3_Interrupt 1393 .weak EXTI4_Interrupt 1394 .weak DMA1_Stream0_Interrupt 1395 .weak DMA1_Stream1_Interrupt 1396 .weak DMA1_Stream2_Interrupt 1397 .weak DMA1_Stream3_Interrupt 1398 .weak DMA1_Stream4_Interrupt 1399 .weak DMA1_Stream5_Interrupt 1400 .weak DMA1_Stream6_Interrupt 1401 .weak ADC_Interrupt 1402 .weak CAN1_TX_Interrupt 1403 .weak CAN1_RX0_Interrupt 1404 .weak CAN1_RX1_Interrupt 1405 .weak CAN1_SCE_Interrupt 1406 .weak EXTI9_5_Interrupt 1407 .weak TIM1_BRK_TIM9_Interrupt 1408 .weak TIM1_UP_TIM10_Interrupt 1409 .weak TIM1_TRG_COM_TIM11_Interrupt 1410 .weak TIM1_CC_Interrupt 1411 .weak TIM2_Interrupt 1412 .weak TIM3_Interrupt 1413 .weak TIM4_Interrupt 1414 .weak I2C1_EV_Interrupt 1415 .weak I2C1_ER_Interrupt 1416 .weak I2C2_EV_Interrupt 1417 .weak I2C2_ER_Interrupt 1418 .weak SPI1_Interrupt 1419 .weak SPI2_Interrupt 1420 .weak USART1_Interrupt 1421 .weak USART2_Interrupt 1422 .weak USART3_Interrupt 1423 .weak EXTI15_10_Interrupt 1424 .weak RTC_Alarm_Interrupt 1425 .weak OTG_FS_WKUP_Interrupt 1426 .weak TIM8_BRK_TIM12_Interrupt 1427 .weak TIM8_UP_TIM13_Interrupt 1428 .weak TIM8_TRG_COM_TIM14_Interrupt 1429 .weak TIM8_CC_Interrupt 1430 .weak DMA1_Stream7_Interrupt 1431 .weak FMC_Interrupt 1432 .weak SDMMC1_Interrupt 1433 .weak TIM5_Interrupt 1434 .weak SPI3_Interrupt 1435 .weak UART4_Interrupt 1436 .weak UART5_Interrupt 1437 .weak TIM6_DAC_Interrupt 1438 .weak TIM7_Interrupt 1439 .weak DMA2_Stream0_Interrupt 1440 .weak DMA2_Stream1_Interrupt 1441 .weak DMA2_Stream2_Interrupt 1442 .weak DMA2_Stream3_Interrupt 1443 .weak DMA2_Stream4_Interrupt 1444 .weak ETH_Interrupt 1445 .weak ETH_WKUP_Interrupt 1446 .weak CAN2_TX_Interrupt 1447 .weak CAN2_RX0_Interrupt 1448 .weak CAN2_RX1_Interrupt 1449 .weak CAN2_SCE_Interrupt 1450 .weak OTG_FS_Interrupt 1451 .weak DMA2_Stream5_Interrupt 1452 .weak DMA2_Stream6_Interrupt 1453 .weak DMA2_Stream7_Interrupt 1454 .weak USART6_Interrupt 1455 .weak I2C3_EV_Interrupt 1456 .weak I2C3_ER_Interrupt 1457 .weak OTG_HS_EP1_OUT_Interrupt 1458 .weak OTG_HS_EP1_IN_Interrupt 1459 .weak OTG_HS_WKUP_Interrupt 1460 .weak OTG_HS_Interrupt 1461 .weak DCMI_Interrupt 1462 .weak RNG_Interrupt 1463 .weak FPU_Interrupt 1464 .weak UART7_Interrupt 1465 .weak UART8_Interrupt 1466 .weak SPI4_Interrupt 1467 .weak SPI5_Interrupt 1468 .weak SPI6_Interrupt 1469 .weak SAI1_Interrupt 1470 .weak DMA2D_Interrupt 1471 .weak SAI2_Interrupt 1472 .weak QUADSPI_Interrupt 1473 .weak LPTIM1_Interrupt 1474 .weak CEC_Interrupt 1475 .weak I2C4_EV_Interrupt 1476 .weak I2C4_ER_Interrupt 1477 .weak SPDIF_RX_Interrupt 1478 1479 .set NMI_Interrupt, HaltProc 1480 .set HardFault_Interrupt, HaltProc 1481 .set MemManage_Interrupt, HaltProc 1482 .set BusFault_Interrupt, HaltProc 1483 .set UsageFault_Interrupt, HaltProc 1484 .set SVC_Interrupt, HaltProc 1485 .set DebugMon_Interrupt, HaltProc 1486 .set PendSV_Interrupt, HaltProc 1487 .set SysTick_Interrupt, HaltProc 1488 .set WWDG_Interrupt, HaltProc 1489 .set PVD_Interrupt, HaltProc 1490 .set TAMP_STAMP_Interrupt, HaltProc 1491 .set RTC_WKUP_Interrupt, HaltProc 1492 .set FLASH_Interrupt, HaltProc 1493 .set RCC_Interrupt, HaltProc 1494 .set EXTI0_Interrupt, HaltProc 1495 .set EXTI1_Interrupt, HaltProc 1496 .set EXTI2_Interrupt, HaltProc 1497 .set EXTI3_Interrupt, HaltProc 1498 .set EXTI4_Interrupt, HaltProc 1499 .set DMA1_Stream0_Interrupt, HaltProc 1500 .set DMA1_Stream1_Interrupt, HaltProc 1501 .set DMA1_Stream2_Interrupt, HaltProc 1502 .set DMA1_Stream3_Interrupt, HaltProc 1503 .set DMA1_Stream4_Interrupt, HaltProc 1504 .set DMA1_Stream5_Interrupt, HaltProc 1505 .set DMA1_Stream6_Interrupt, HaltProc 1506 .set ADC_Interrupt, HaltProc 1507 .set CAN1_TX_Interrupt, HaltProc 1508 .set CAN1_RX0_Interrupt, HaltProc 1509 .set CAN1_RX1_Interrupt, HaltProc 1510 .set CAN1_SCE_Interrupt, HaltProc 1511 .set EXTI9_5_Interrupt, HaltProc 1512 .set TIM1_BRK_TIM9_Interrupt, HaltProc 1513 .set TIM1_UP_TIM10_Interrupt, HaltProc 1514 .set TIM1_TRG_COM_TIM11_Interrupt, HaltProc 1515 .set TIM1_CC_Interrupt, HaltProc 1516 .set TIM2_Interrupt, HaltProc 1517 .set TIM3_Interrupt, HaltProc 1518 .set TIM4_Interrupt, HaltProc 1519 .set I2C1_EV_Interrupt, HaltProc 1520 .set I2C1_ER_Interrupt, HaltProc 1521 .set I2C2_EV_Interrupt, HaltProc 1522 .set I2C2_ER_Interrupt, HaltProc 1523 .set SPI1_Interrupt, HaltProc 1524 .set SPI2_Interrupt, HaltProc 1525 .set USART1_Interrupt, HaltProc 1526 .set USART2_Interrupt, HaltProc 1527 .set USART3_Interrupt, HaltProc 1528 .set EXTI15_10_Interrupt, HaltProc 1529 .set RTC_Alarm_Interrupt, HaltProc 1530 .set OTG_FS_WKUP_Interrupt, HaltProc 1531 .set TIM8_BRK_TIM12_Interrupt, HaltProc 1532 .set TIM8_UP_TIM13_Interrupt, HaltProc 1533 .set TIM8_TRG_COM_TIM14_Interrupt, HaltProc 1534 .set TIM8_CC_Interrupt, HaltProc 1535 .set DMA1_Stream7_Interrupt, HaltProc 1536 .set FMC_Interrupt, HaltProc 1537 .set SDMMC1_Interrupt, HaltProc 1538 .set TIM5_Interrupt, HaltProc 1539 .set SPI3_Interrupt, HaltProc 1540 .set UART4_Interrupt, HaltProc 1541 .set UART5_Interrupt, HaltProc 1542 .set TIM6_DAC_Interrupt, HaltProc 1543 .set TIM7_Interrupt, HaltProc 1544 .set DMA2_Stream0_Interrupt, HaltProc 1545 .set DMA2_Stream1_Interrupt, HaltProc 1546 .set DMA2_Stream2_Interrupt, HaltProc 1547 .set DMA2_Stream3_Interrupt, HaltProc 1548 .set DMA2_Stream4_Interrupt, HaltProc 1549 .set ETH_Interrupt, HaltProc 1550 .set ETH_WKUP_Interrupt, HaltProc 1551 .set CAN2_TX_Interrupt, HaltProc 1552 .set CAN2_RX0_Interrupt, HaltProc 1553 .set CAN2_RX1_Interrupt, HaltProc 1554 .set CAN2_SCE_Interrupt, HaltProc 1555 .set OTG_FS_Interrupt, HaltProc 1556 .set DMA2_Stream5_Interrupt, HaltProc 1557 .set DMA2_Stream6_Interrupt, HaltProc 1558 .set DMA2_Stream7_Interrupt, HaltProc 1559 .set USART6_Interrupt, HaltProc 1560 .set I2C3_EV_Interrupt, HaltProc 1561 .set I2C3_ER_Interrupt, HaltProc 1562 .set OTG_HS_EP1_OUT_Interrupt, HaltProc 1563 .set OTG_HS_EP1_IN_Interrupt, HaltProc 1564 .set OTG_HS_WKUP_Interrupt, HaltProc 1565 .set OTG_HS_Interrupt, HaltProc 1566 .set DCMI_Interrupt, HaltProc 1567 .set RNG_Interrupt, HaltProc 1568 .set FPU_Interrupt, HaltProc 1569 .set UART7_Interrupt, HaltProc 1570 .set UART8_Interrupt, HaltProc 1571 .set SPI4_Interrupt, HaltProc 1572 .set SPI5_Interrupt, HaltProc 1573 .set SPI6_Interrupt, HaltProc 1574 .set SAI1_Interrupt, HaltProc 1575 .set DMA2D_Interrupt, HaltProc 1576 .set SAI2_Interrupt, HaltProc 1577 .set QUADSPI_Interrupt, HaltProc 1578 .set LPTIM1_Interrupt, HaltProc 1579 .set CEC_Interrupt, HaltProc 1580 .set I2C4_EV_Interrupt, HaltProc 1581 .set I2C4_ER_Interrupt, HaltProc 1582 .set SPDIF_RX_Interrupt, HaltProc 1583 1584 .text 1585end; 1586 1587end. 1588