1unit ATmega32HVB; 2 3{$goto on} 4 5interface 6 7var 8 // AD_CONVERTER 9 VADMUX : byte absolute $00+$7C; // The VADC multiplexer Selection Register 10 VADC : word absolute $00+$78; // VADC Data Register Bytes 11 VADCL : byte absolute $00+$78; // VADC Data Register Bytes 12 VADCH : byte absolute $00+$78+1; // VADC Data Register Bytes 13 VADCSR : byte absolute $00+$7A; // The VADC Control and Status register 14 // WATCHDOG 15 WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register 16 // FET 17 FCSR : byte absolute $00+$F0; // FET Control and Status Register 18 // SPI 19 SPCR : byte absolute $00+$4c; // SPI Control Register 20 SPSR : byte absolute $00+$4d; // SPI Status Register 21 SPDR : byte absolute $00+$4e; // SPI Data Register 22 // EEPROM 23 EEAR : word absolute $00+$41; // EEPROM Read/Write Access 24 EEARL : byte absolute $00+$41; // EEPROM Read/Write Access 25 EEARH : byte absolute $00+$41+1; // EEPROM Read/Write Access 26 EEDR : byte absolute $00+$40; // EEPROM Data Register 27 EECR : byte absolute $00+$3F; // EEPROM Control Register 28 // COULOMB_COUNTER 29 CADCSRA : byte absolute $00+$E6; // CC-ADC Control and Status Register A 30 CADCSRB : byte absolute $00+$E7; // CC-ADC Control and Status Register B 31 CADCSRC : byte absolute $00+$E8; // CC-ADC Control and Status Register C 32 CADIC : word absolute $00+$E4; // CC-ADC Instantaneous Current 33 CADICL : byte absolute $00+$E4; // CC-ADC Instantaneous Current 34 CADICH : byte absolute $00+$E4+1; // CC-ADC Instantaneous Current 35 CADAC3 : byte absolute $00+$E3; // ADC Accumulate Current 36 CADAC2 : byte absolute $00+$E2; // ADC Accumulate Current 37 CADAC1 : byte absolute $00+$E1; // ADC Accumulate Current 38 CADAC0 : byte absolute $00+$E0; // ADC Accumulate Current 39 CADRCC : byte absolute $00+$E9; // CC-ADC Regular Charge Current 40 CADRDC : byte absolute $00+$EA; // CC-ADC Regular Discharge Current 41 // TWI 42 TWBCSR : byte absolute $00+$BE; // TWI Bus Control and Status Register 43 TWAMR : byte absolute $00+$BD; // TWI (Slave) Address Mask Register 44 TWBR : byte absolute $00+$B8; // TWI Bit Rate register 45 TWCR : byte absolute $00+$BC; // TWI Control Register 46 TWSR : byte absolute $00+$B9; // TWI Status Register 47 TWDR : byte absolute $00+$BB; // TWI Data register 48 TWAR : byte absolute $00+$BA; // TWI (Slave) Address register 49 // EXTERNAL_INTERRUPT 50 EICRA : byte absolute $00+$69; // External Interrupt Control Register 51 EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register 52 EIFR : byte absolute $00+$3C; // External Interrupt Flag Register 53 PCICR : byte absolute $00+$68; // Pin Change Interrupt Control Register 54 PCIFR : byte absolute $00+$3B; // Pin Change Interrupt Flag Register 55 PCMSK1 : byte absolute $00+$6C; // Pin Change Enable Mask Register 1 56 PCMSK0 : byte absolute $00+$6B; // Pin Change Enable Mask Register 0 57 // TIMER_COUNTER_1 58 TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B 59 TCCR1A : byte absolute $00+$80; // Timer/Counter 1 Control Register A 60 TCNT1 : word absolute $00+$84; // Timer Counter 1 Bytes 61 TCNT1L : byte absolute $00+$84; // Timer Counter 1 Bytes 62 TCNT1H : byte absolute $00+$84+1; // Timer Counter 1 Bytes 63 OCR1A : byte absolute $00+$88; // Output Compare Register 1A 64 OCR1B : byte absolute $00+$89; // Output Compare Register B 65 TIMSK1 : byte absolute $00+$6F; // Timer/Counter Interrupt Mask Register 66 TIFR1 : byte absolute $00+$36; // Timer/Counter Interrupt Flag register 67 GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register 68 // CELL_BALANCING 69 CBCR : byte absolute $00+$F1; // Cell Balancing Control Register 70 // BATTERY_PROTECTION 71 BPPLR : byte absolute $00+$FE; // Battery Protection Parameter Lock Register 72 BPCR : byte absolute $00+$FD; // Battery Protection Control Register 73 BPHCTR : byte absolute $00+$FC; // Battery Protection Short-current Timing Register 74 BPOCTR : byte absolute $00+$FB; // Battery Protection Over-current Timing Register 75 BPSCTR : byte absolute $00+$FA; // Battery Protection Short-current Timing Register 76 BPCHCD : byte absolute $00+$F9; // Battery Protection Charge-High-current Detection Level Register 77 BPDHCD : byte absolute $00+$F8; // Battery Protection Discharge-High-current Detection Level Register 78 BPCOCD : byte absolute $00+$F7; // Battery Protection Charge-Over-current Detection Level Register 79 BPDOCD : byte absolute $00+$F6; // Battery Protection Discharge-Over-current Detection Level Register 80 BPSCD : byte absolute $00+$F5; // Battery Protection Short-Circuit Detection Level Register 81 BPIFR : byte absolute $00+$F3; // Battery Protection Interrupt Flag Register 82 BPIMSK : byte absolute $00+$F2; // Battery Protection Interrupt Mask Register 83 // CHARGER_DETECT 84 CHGDCSR : byte absolute $00+$D4; // Charger Detect Control and Status Register 85 // VOLTAGE_REGULATOR 86 ROCR : byte absolute $00+$C8; // Regulator Operating Condition Register 87 // BANDGAP 88 BGCSR : byte absolute $00+$D2; // Bandgap Control and Status Register 89 BGCRR : byte absolute $00+$D1; // Bandgap Calibration of Resistor Ladder 90 BGCCR : byte absolute $00+$D0; // Bandgap Calibration Register 91 // CPU 92 SREG : byte absolute $00+$5F; // Status Register 93 SP : word absolute $00+$5D; // Stack Pointer 94 SPL : byte absolute $00+$5D; // Stack Pointer 95 SPH : byte absolute $00+$5D+1; // Stack Pointer 96 MCUCR : byte absolute $00+$55; // MCU Control Register 97 MCUSR : byte absolute $00+$54; // MCU Status Register 98 FOSCCAL : byte absolute $00+$66; // Fast Oscillator Calibration Value 99 OSICSR : byte absolute $00+$37; // Oscillator Sampling Interface Control and Status Register 100 SMCR : byte absolute $00+$53; // Sleep Mode Control Register 101 GPIOR2 : byte absolute $00+$4B; // General Purpose IO Register 2 102 GPIOR1 : byte absolute $00+$4A; // General Purpose IO Register 1 103 GPIOR0 : byte absolute $00+$3E; // General Purpose IO Register 0 104 DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 105 PRR0 : byte absolute $00+$64; // Power Reduction Register 0 106 CLKPR : byte absolute $00+$61; // Clock Prescale Register 107 // PORTA 108 PORTA : byte absolute $00+$22; // Port A Data Register 109 DDRA : byte absolute $00+$21; // Port A Data Direction Register 110 PINA : byte absolute $00+$20; // Port A Input Pins 111 // PORTB 112 PORTB : byte absolute $00+$25; // Port B Data Register 113 DDRB : byte absolute $00+$24; // Port B Data Direction Register 114 PINB : byte absolute $00+$23; // Port B Input Pins 115 // PORTC 116 PORTC : byte absolute $00+$28; // Port C Data Register 117 PINC : byte absolute $00+$26; // Port C Input Pins 118 // TIMER_COUNTER_0 119 TCCR0B : byte absolute $00+$45; // Timer/Counter0 Control Register B 120 TCCR0A : byte absolute $00+$44; // Timer/Counter 0 Control Register A 121 TCNT0 : word absolute $00+$46; // Timer Counter 0 Bytes 122 TCNT0L : byte absolute $00+$46; // Timer Counter 0 Bytes 123 TCNT0H : byte absolute $00+$46+1; // Timer Counter 0 Bytes 124 OCR0A : byte absolute $00+$48; // Output Compare Register 0A 125 OCR0B : byte absolute $00+$49; // Output Compare Register B 126 TIMSK0 : byte absolute $00+$6E; // Timer/Counter Interrupt Mask Register 127 TIFR0 : byte absolute $00+$35; // Timer/Counter Interrupt Flag register 128 // BOOT_LOAD 129 SPMCSR : byte absolute $00+$57; // Store Program Memory Control and Status Register 130 131const 132 // VADMUX 133 // VADCSR 134 VADEN = 3; // VADC Enable 135 VADSC = 2; // VADC Satrt Conversion 136 VADCCIF = 1; // VADC Conversion Complete Interrupt Flag 137 VADCCIE = 0; // VADC Conversion Complete Interrupt Enable 138 // WDTCSR 139 WDIF = 7; // Watchdog Timeout Interrupt Flag 140 WDIE = 6; // Watchdog Timeout Interrupt Enable 141 WDP = 0; // Watchdog Timer Prescaler Bits 142 WDCE = 4; // Watchdog Change Enable 143 WDE = 3; // Watch Dog Enable 144 // FCSR 145 DUVRD = 3; // Deep Under-Voltage Recovery Disable 146 CPS = 2; // Current Protection Status 147 DFE = 1; // Discharge FET Enable 148 CFE = 0; // Charge FET Enable 149 // SPCR 150 SPIE = 7; // SPI Interrupt Enable 151 SPE = 6; // SPI Enable 152 DORD = 5; // Data Order 153 MSTR = 4; // Master/Slave Select 154 CPOL = 3; // Clock polarity 155 CPHA = 2; // Clock Phase 156 SPR = 0; // SPI Clock Rate Selects 157 // SPSR 158 SPIF = 7; // SPI Interrupt Flag 159 WCOL = 6; // Write Collision Flag 160 SPI2X = 0; // Double SPI Speed Bit 161 // EECR 162 EEPM = 4; // 163 EERIE = 3; // EEProm Ready Interrupt Enable 164 EEMPE = 2; // EEPROM Master Write Enable 165 EEPE = 1; // EEPROM Write Enable 166 EERE = 0; // EEPROM Read Enable 167 // CADCSRA 168 CADEN = 7; // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. 169 CADPOL = 6; // 170 CADUB = 5; // CC_ADC Update Busy 171 CADAS = 3; // CC_ADC Accumulate Current Select Bits 172 CADSI = 1; // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. 173 CADSE = 0; // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. 174 // CADCSRB 175 CADACIE = 6; // 176 CADRCIE = 5; // Regular Current Interrupt Enable 177 CADICIE = 4; // CAD Instantenous Current Interrupt Enable 178 CADACIF = 2; // CC-ADC Accumulate Current Interrupt Flag 179 CADRCIF = 1; // CC-ADC Accumulate Current Interrupt Flag 180 CADICIF = 0; // CC-ADC Instantaneous Current Interrupt Flag 181 // CADCSRC 182 CADVSE = 0; // CC-ADC Voltage Scaling Enable 183 // TWBCSR 184 TWBCIF = 7; // TWI Bus Connect/Disconnect Interrupt Flag 185 TWBCIE = 6; // TWI Bus Connect/Disconnect Interrupt Enable 186 TWBDT = 1; // TWI Bus Disconnect Time-out Period 187 TWBCIP = 0; // TWI Bus Connect/Disconnect Interrupt Polarity 188 // TWAMR 189 TWAM = 1; // 190 // TWCR 191 TWINT = 7; // TWI Interrupt Flag 192 TWEA = 6; // TWI Enable Acknowledge Bit 193 TWSTA = 5; // TWI Start Condition Bit 194 TWSTO = 4; // TWI Stop Condition Bit 195 TWWC = 3; // TWI Write Collition Flag 196 TWEN = 2; // TWI Enable Bit 197 TWIE = 0; // TWI Interrupt Enable 198 // TWSR 199 TWS = 3; // TWI Status 200 TWPS = 0; // TWI Prescaler 201 // TWAR 202 TWA = 1; // TWI (Slave) Address register Bits 203 TWGCE = 0; // TWI General Call Recognition Enable Bit 204 // EICRA 205 ISC3 = 6; // External Interrupt Sense Control 3 Bits 206 ISC2 = 4; // External Interrupt Sense Control 2 Bits 207 ISC1 = 2; // External Interrupt Sense Control 1 Bits 208 ISC0 = 0; // External Interrupt Sense Control 0 Bits 209 // EIMSK 210 INT = 0; // External Interrupt Request 3 Enable 211 // EIFR 212 INTF = 0; // External Interrupt Flags 213 // PCICR 214 PCIE = 0; // Pin Change Interrupt Enables 215 // PCIFR 216 PCIF = 0; // Pin Change Interrupt Flags 217 // TCCR1B 218 CS = 0; // Clock Select1 bis 219 // TCCR1A 220 TCW1 = 7; // Timer/Counter Width 221 ICEN1 = 6; // Input Capture Mode Enable 222 ICNC1 = 5; // Input Capture Noise Canceler 223 ICES1 = 4; // Input Capture Edge Select 224 ICS1 = 3; // Input Capture Select 225 WGM10 = 0; // Waveform Generation Mode 226 // TIMSK1 227 ICIE1 = 3; // Timer/Counter n Input Capture Interrupt Enable 228 OCIE1B = 2; // Timer/Counter1 Output Compare B Interrupt Enable 229 OCIE1A = 1; // Timer/Counter1 Output Compare A Interrupt Enable 230 TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable 231 // TIFR1 232 ICF1 = 3; // Timer/Counter 1 Input Capture Flag 233 OCF1B = 2; // Timer/Counter1 Output Compare Flag B 234 OCF1A = 1; // Timer/Counter1 Output Compare Flag A 235 TOV1 = 0; // Timer/Counter1 Overflow Flag 236 // GTCCR 237 TSM = 7; // Timer/Counter Synchronization Mode 238 PSRSYNC = 0; // Prescaler Reset 239 // CBCR 240 CBE = 0; // Cell Balancing Enables 241 // BPPLR 242 BPPLE = 1; // Battery Protection Parameter Lock Enable 243 BPPL = 0; // Battery Protection Parameter Lock 244 // BPCR 245 EPID = 5; // External Protection Input Disable 246 SCD = 4; // Short Circuit Protection Disabled 247 DOCD = 3; // Discharge Over-current Protection Disabled 248 COCD = 2; // Charge Over-current Protection Disabled 249 DHCD = 1; // Discharge High-current Protection Disable 250 CHCD = 0; // Charge High-current Protection Disable 251 // BPIFR 252 SCIF = 4; // Short-circuit Protection Activated Interrupt Flag 253 DOCIF = 3; // Discharge Over-current Protection Activated Interrupt Flag 254 COCIF = 2; // Charge Over-current Protection Activated Interrupt Flag 255 DHCIF = 1; // Disharge High-current Protection Activated Interrupt 256 CHCIF = 0; // Charge High-current Protection Activated Interrupt 257 // BPIMSK 258 SCIE = 4; // Short-circuit Protection Activated Interrupt Enable 259 DOCIE = 3; // Discharge Over-current Protection Activated Interrupt Enable 260 COCIE = 2; // Charge Over-current Protection Activated Interrupt Enable 261 DHCIE = 1; // Discharger High-current Protection Activated Interrupt 262 CHCIE = 0; // Charger High-current Protection Activated Interrupt 263 // CHGDCSR 264 BATTPVL = 4; // BATT Pin Voltage Level 265 CHGDISC = 2; // Charger Detect Interrupt Sense Control 266 CHGDIF = 1; // Charger Detect Interrupt Flag 267 CHGDIE = 0; // Charger Detect Interrupt Enable 268 // ROCR 269 ROCS = 7; // ROC Status 270 ROCD = 4; // ROC Disable 271 ROCWIF = 1; // ROC Warning Interrupt Flag 272 ROCWIE = 0; // ROC Warning Interrupt Enable 273 // BGCSR 274 BGD = 5; // Bandgap Disable 275 BGSCDE = 4; // Bandgap Short Circuit Detection Enabled 276 BGSCDIF = 1; // Bandgap Short Circuit Detection Interrupt Flag 277 BGSCDIE = 0; // Bandgap Short Circuit Detection Interrupt Enable 278 // BGCCR 279 BGCC = 0; // BG Calibration of PTAT Current Bits 280 // SREG 281 I = 7; // Global Interrupt Enable 282 T = 6; // Bit Copy Storage 283 H = 5; // Half Carry Flag 284 S = 4; // Sign Bit 285 V = 3; // Two's Complement Overflow Flag 286 N = 2; // Negative Flag 287 Z = 1; // Zero Flag 288 C = 0; // Carry Flag 289 // MCUCR 290 CKOE = 5; // Clock Output Enable 291 PUD = 4; // Pull-up disable 292 IVSEL = 1; // Interrupt Vector Select 293 IVCE = 0; // Interrupt Vector Change Enable 294 // MCUSR 295 OCDRF = 4; // OCD Reset Flag 296 WDRF = 3; // Watchdog Reset Flag 297 BODRF = 2; // Brown-out Reset Flag 298 EXTRF = 1; // External Reset Flag 299 PORF = 0; // Power-on reset flag 300 // OSICSR 301 OSISEL0 = 4; // Oscillator Sampling Interface Select 0 302 OSIST = 1; // Oscillator Sampling Interface Status 303 OSIEN = 0; // Oscillator Sampling Interface Enable 304 // SMCR 305 SM = 1; // Sleep Mode Select bits 306 SE = 0; // Sleep Enable 307 // DIDR0 308 PA1DID = 1; // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. 309 PA0DID = 0; // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. 310 // PRR0 311 PRTWI = 6; // Power Reduction TWI 312 PRVRM = 5; // Power Reduction Voltage Regulator Monitor 313 PRSPI = 3; // Power reduction SPI 314 PRTIM1 = 2; // Power Reduction Timer/Counter1 315 PRTIM0 = 1; // Power Reduction Timer/Counter0 316 PRVADC = 0; // Power Reduction V-ADC 317 // CLKPR 318 CLKPCE = 7; // Clock Prescaler Change Enable 319 CLKPS = 0; // Clock Prescaler Select Bits 320 // TCCR0B 321 CS02 = 2; // Clock Select0 bit 2 322 CS01 = 1; // Clock Select0 bit 1 323 CS00 = 0; // Clock Select0 bit 0 324 // TCCR0A 325 TCW0 = 7; // Timer/Counter Width 326 ICEN0 = 6; // Input Capture Mode Enable 327 ICNC0 = 5; // Input Capture Noise Canceler 328 ICES0 = 4; // Input Capture Edge Select 329 ICS0 = 3; // Input Capture Select 330 WGM00 = 0; // Waveform Generation Mode 331 // TIMSK0 332 ICIE0 = 3; // Timer/Counter n Input Capture Interrupt Enable 333 OCIE0B = 2; // Timer/Counter0 Output Compare B Interrupt Enable 334 OCIE0A = 1; // Timer/Counter0 Output Compare A Interrupt Enable 335 TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable 336 // TIFR0 337 ICF0 = 3; // Timer/Counter 0 Input Capture Flag 338 OCF0B = 2; // Timer/Counter0 Output Compare Flag B 339 OCF0A = 1; // Timer/Counter0 Output Compare Flag A 340 TOV0 = 0; // Timer/Counter0 Overflow Flag 341 // GTCCR 342 // SPMCSR 343 SPMIE = 7; // SPM Interrupt Enable 344 RWWSB = 6; // Read-While-Write Section Busy 345 SIGRD = 5; // Signature Row Read 346 RWWSRE = 4; // Read-While-Write Section Read Enable 347 LBSET = 3; // Lock Bit Set 348 PGWRT = 2; // Page Write 349 PGERS = 1; // Page Erase 350 SPMEN = 0; // Store Program Memory Enable 351 352implementation 353 354{$i avrcommon.inc} 355 356procedure BPINT_ISR; external name 'BPINT_ISR'; // Interrupt 1 Battery Protection Interrupt 357procedure VREGMON_ISR; external name 'VREGMON_ISR'; // Interrupt 2 Voltage regulator monitor interrupt 358procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 3 External Interrupt Request 0 359procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 4 External Interrupt Request 1 360procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 5 External Interrupt Request 2 361procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 6 External Interrupt Request 3 362procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 7 Pin Change Interrupt 0 363procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 8 Pin Change Interrupt 1 364procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 9 Watchdog Timeout Interrupt 365procedure BGSCD_ISR; external name 'BGSCD_ISR'; // Interrupt 10 Bandgap Buffer Short Circuit Detected 366procedure CHDET_ISR; external name 'CHDET_ISR'; // Interrupt 11 Charger Detect 367procedure TIMER1_IC_ISR; external name 'TIMER1_IC_ISR'; // Interrupt 12 Timer 1 Input capture 368procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 13 Timer 1 Compare Match A 369procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 14 Timer 1 Compare Match B 370procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer 1 overflow 371procedure TIMER0_IC_ISR; external name 'TIMER0_IC_ISR'; // Interrupt 16 Timer 0 Input Capture 372procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 17 Timer 0 Comapre Match A 373procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 18 Timer 0 Compare Match B 374procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 19 Timer 0 Overflow 375procedure TWIBUSCD_ISR; external name 'TWIBUSCD_ISR'; // Interrupt 20 Two-Wire Bus Connect/Disconnect 376procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 21 Two-Wire Serial Interface 377procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 22 SPI Serial transfer complete 378procedure VADC_ISR; external name 'VADC_ISR'; // Interrupt 23 Voltage ADC Conversion Complete 379procedure CCADC_CONV_ISR; external name 'CCADC_CONV_ISR'; // Interrupt 24 Coulomb Counter ADC Conversion Complete 380procedure CCADC_REG_CUR_ISR; external name 'CCADC_REG_CUR_ISR'; // Interrupt 25 Coloumb Counter ADC Regular Current 381procedure CCADC_ACC_ISR; external name 'CCADC_ACC_ISR'; // Interrupt 26 Coloumb Counter ADC Accumulator 382procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 27 EEPROM Ready 383procedure SPM_ISR; external name 'SPM_ISR'; // Interrupt 28 SPM Ready 384 385procedure _FPC_start; assembler; nostackframe; 386label 387 _start; 388 asm 389 .init 390 .globl _start 391 392 jmp _start 393 jmp BPINT_ISR 394 jmp VREGMON_ISR 395 jmp INT0_ISR 396 jmp INT1_ISR 397 jmp INT2_ISR 398 jmp INT3_ISR 399 jmp PCINT0_ISR 400 jmp PCINT1_ISR 401 jmp WDT_ISR 402 jmp BGSCD_ISR 403 jmp CHDET_ISR 404 jmp TIMER1_IC_ISR 405 jmp TIMER1_COMPA_ISR 406 jmp TIMER1_COMPB_ISR 407 jmp TIMER1_OVF_ISR 408 jmp TIMER0_IC_ISR 409 jmp TIMER0_COMPA_ISR 410 jmp TIMER0_COMPB_ISR 411 jmp TIMER0_OVF_ISR 412 jmp TWIBUSCD_ISR 413 jmp TWI_ISR 414 jmp SPI_STC_ISR 415 jmp VADC_ISR 416 jmp CCADC_CONV_ISR 417 jmp CCADC_REG_CUR_ISR 418 jmp CCADC_ACC_ISR 419 jmp EE_READY_ISR 420 jmp SPM_ISR 421 422 {$i start.inc} 423 424 .weak BPINT_ISR 425 .weak VREGMON_ISR 426 .weak INT0_ISR 427 .weak INT1_ISR 428 .weak INT2_ISR 429 .weak INT3_ISR 430 .weak PCINT0_ISR 431 .weak PCINT1_ISR 432 .weak WDT_ISR 433 .weak BGSCD_ISR 434 .weak CHDET_ISR 435 .weak TIMER1_IC_ISR 436 .weak TIMER1_COMPA_ISR 437 .weak TIMER1_COMPB_ISR 438 .weak TIMER1_OVF_ISR 439 .weak TIMER0_IC_ISR 440 .weak TIMER0_COMPA_ISR 441 .weak TIMER0_COMPB_ISR 442 .weak TIMER0_OVF_ISR 443 .weak TWIBUSCD_ISR 444 .weak TWI_ISR 445 .weak SPI_STC_ISR 446 .weak VADC_ISR 447 .weak CCADC_CONV_ISR 448 .weak CCADC_REG_CUR_ISR 449 .weak CCADC_ACC_ISR 450 .weak EE_READY_ISR 451 .weak SPM_ISR 452 453 .set BPINT_ISR, Default_IRQ_handler 454 .set VREGMON_ISR, Default_IRQ_handler 455 .set INT0_ISR, Default_IRQ_handler 456 .set INT1_ISR, Default_IRQ_handler 457 .set INT2_ISR, Default_IRQ_handler 458 .set INT3_ISR, Default_IRQ_handler 459 .set PCINT0_ISR, Default_IRQ_handler 460 .set PCINT1_ISR, Default_IRQ_handler 461 .set WDT_ISR, Default_IRQ_handler 462 .set BGSCD_ISR, Default_IRQ_handler 463 .set CHDET_ISR, Default_IRQ_handler 464 .set TIMER1_IC_ISR, Default_IRQ_handler 465 .set TIMER1_COMPA_ISR, Default_IRQ_handler 466 .set TIMER1_COMPB_ISR, Default_IRQ_handler 467 .set TIMER1_OVF_ISR, Default_IRQ_handler 468 .set TIMER0_IC_ISR, Default_IRQ_handler 469 .set TIMER0_COMPA_ISR, Default_IRQ_handler 470 .set TIMER0_COMPB_ISR, Default_IRQ_handler 471 .set TIMER0_OVF_ISR, Default_IRQ_handler 472 .set TWIBUSCD_ISR, Default_IRQ_handler 473 .set TWI_ISR, Default_IRQ_handler 474 .set SPI_STC_ISR, Default_IRQ_handler 475 .set VADC_ISR, Default_IRQ_handler 476 .set CCADC_CONV_ISR, Default_IRQ_handler 477 .set CCADC_REG_CUR_ISR, Default_IRQ_handler 478 .set CCADC_ACC_ISR, Default_IRQ_handler 479 .set EE_READY_ISR, Default_IRQ_handler 480 .set SPM_ISR, Default_IRQ_handler 481 end; 482 483end. 484