1 { 2 Copyright (c) 1998-2002 by Florian Klaempfl 3 4 Contains the base types for the m68k 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20 **************************************************************************** 21 } 22 { This Unit contains the base types for the m68k 23 } 24 unit cpubase; 25 26 {$i fpcdefs.inc} 27 28 interface 29 30 uses 31 globtype,globals, 32 strings,cutils,cclasses,aasmbase,cpuinfo,cgbase; 33 34 {***************************************************************************** 35 Assembler Opcodes 36 *****************************************************************************} 37 38 type 39 { warning: CPU32 opcodes are not fully compatible with the MC68020. } 40 { 68000 only opcodes } 41 tasmop = (a_none, 42 a_abcd,a_add,a_adda,a_addi,a_addq,a_addx,a_and,a_andi, 43 a_asl,a_asr,a_bcc,a_bcs,a_beq,a_bge,a_bgt,a_bhi, 44 a_ble,a_bls,a_blt,a_bmi,a_bne,a_bpl,a_bvc,a_bvs, 45 a_bchg,a_bclr,a_bra,a_bset,a_bsr,a_btst,a_chk, 46 a_clr,a_cmp,a_cmpa,a_cmpi,a_cmpm,a_dbcc,a_dbcs,a_dbeq,a_dbge, 47 a_dbgt,a_dbhi,a_dble,a_dbls,a_dblt,a_dbmi,a_dbne,a_dbra, 48 a_dbpl,a_dbt,a_dbvc,a_dbvs,a_dbf,a_divs,a_divu, 49 a_eor,a_eori,a_exg,a_illegal,a_ext,a_jmp,a_jsr, 50 a_lea,a_link,a_lsl,a_lsr,a_move,a_movea,a_movei,a_moveq, 51 a_movem,a_movep,a_muls,a_mulu,a_nbcd,a_neg,a_negx, 52 a_nop,a_not,a_or,a_ori,a_pea,a_rol,a_ror,a_roxl, 53 a_roxr,a_rtr,a_rts,a_sbcd,a_scc,a_scs,a_seq,a_sge, 54 a_sgt,a_shi,a_sle,a_sls,a_slt,a_smi,a_sne, 55 a_spl,a_st,a_svc,a_svs,a_sf,a_sub,a_suba,a_subi,a_subq, 56 a_subx,a_swap,a_tas,a_trap,a_trapv,a_tst,a_unlk, 57 a_rte,a_reset,a_stop, 58 { mc68010 instructions } 59 a_bkpt,a_movec,a_moves,a_rtd, 60 { mc68020 instructions } 61 a_bfchg,a_bfclr,a_bfexts,a_bfextu,a_bfffo, 62 a_bfins,a_bfset,a_bftst,a_callm,a_cas,a_cas2, 63 a_chk2,a_cmp2,a_divsl,a_divul,a_extb,a_pack,a_rtm, 64 a_trapcc,a_tracs,a_trapeq,a_trapf,a_trapge,a_trapgt, 65 a_traphi,a_traple,a_trapls,a_traplt,a_trapmi,a_trapne, 66 a_trappl,a_trapt,a_trapvc,a_trapvs,a_unpk, 67 { mc64040 instructions } 68 a_move16, 69 { coldfire v4 instructions } 70 a_mov3q,a_mvz,a_mvs,a_sats,a_byterev,a_ff1,a_remu,a_rems, 71 { fpu processor instructions - directly supported } 72 { ieee aware and misc. condition codes not supported } 73 a_fabs,a_fadd, 74 a_fbeq,a_fbne,a_fbngt,a_fbgt,a_fbge,a_fbnge, 75 a_fblt,a_fbnlt,a_fble,a_fbgl,a_fbngl,a_fbgle,a_fbngle, 76 a_fdbeq,a_fdbne,a_fdbgt,a_fdbngt,a_fdbge,a_fdbnge, 77 a_fdblt,a_fdbnlt,a_fdble,a_fdbgl,a_fdbngl,a_fdbgle,a_fdbngle, 78 a_fseq,a_fsne,a_fsgt,a_fsngt,a_fsge,a_fsnge, 79 a_fslt,a_fsnlt,a_fsle,a_fsgl,a_fsngl,a_fsgle,a_fsngle, 80 a_fcmp,a_fdiv,a_fmove,a_fmovem, 81 a_fmul,a_fneg,a_fnop,a_fsqrt,a_fsub,a_fsgldiv, 82 a_fsflmul,a_ftst, 83 a_ftrapeq,a_ftrapne,a_ftrapgt,a_ftrapngt,a_ftrapge,a_ftrapnge, 84 a_ftraplt,a_ftrapnlt,a_ftraple,a_ftrapgl,a_ftrapngl,a_ftrapgle,a_ftrapngle, 85 a_fint,a_fintrz, 86 { fpu instructions - indirectly supported } 87 a_fsin,a_fcos, 88 { protected instructions } 89 a_cprestore,a_cpsave, 90 { fpu unit protected instructions } 91 { and 68030/68851 common mmu instructions } 92 { (this may include 68040 mmu instructions) } 93 a_frestore,a_fsave,a_pflush,a_pflusha,a_pload,a_pmove,a_ptest, 94 { useful for assembly language output } 95 a_label,a_dbxx,a_sxx,a_bxx,a_fsxx,a_fbxx); 96 97 {# This should define the array of instructions as string } 98 op2strtable=array[tasmop] of string[11]; 99 100 Const 101 {# First value of opcode enumeration } 102 firstop = low(tasmop); 103 {# Last value of opcode enumeration } 104 lastop = high(tasmop); 105 106 {***************************************************************************** 107 Registers 108 *****************************************************************************} 109 110 type 111 { Number of registers used for indexing in tables } 112 tregisterindex=0..{$i r68knor.inc}-1; 113 114 const 115 { Available Superregisters } 116 {$i r68ksup.inc} 117 RS_SP = RS_A7; 118 119 R_SUBWHOLE = R_SUBNONE; 120 121 { Available Registers } 122 {$i r68kcon.inc} 123 NR_SP = NR_A7; 124 125 { Integer Super registers first and last } 126 first_int_imreg = RS_D7+1; 127 128 { Float Super register first and last } 129 first_fpu_imreg = RS_FP7+1; 130 131 { Integer Super registers first and last } 132 first_addr_imreg = RS_SP+1; 133 134 { MM Super register first and last } 135 first_mm_supreg = 0; 136 first_mm_imreg = 0; 137 138 maxfpuregs = 8; 139 140 { include regnumber_count_bsstart } 141 {$i r68kbss.inc} 142 143 regnumber_table : array[tregisterindex] of tregister = ( 144 {$i r68knum.inc} 145 ); 146 147 regstabs_table : array[tregisterindex] of shortint = ( 148 {$i r68ksta.inc} 149 ); 150 151 regdwarf_table : array[tregisterindex] of shortint = ( 152 { TODO: reused stabs values!} 153 {$i r68ksta.inc} 154 ); 155 156 { registers which may be destroyed by calls } 157 VOLATILE_INTREGISTERS = [RS_D0,RS_D1]; 158 VOLATILE_FPUREGISTERS = [RS_FP0,RS_FP1]; 159 VOLATILE_ADDRESSREGISTERS = [RS_A0,RS_A1]; 160 161 type 162 totherregisterset = set of tregisterindex; 163 164 165 {***************************************************************************** 166 Conditions 167 *****************************************************************************} 168 169 type 170 TAsmCond=(C_None, 171 C_CC,C_LS,C_CS,C_LT,C_EQ,C_MI,C_F,C_NE, 172 C_GE,C_PL,C_GT,C_T,C_HI,C_VC,C_LE,C_VS 173 ); 174 175 176 const 177 cond2str:array[TAsmCond] of string[3]=('', 178 'cc','ls','cs','lt','eq','mi','f','ne', 179 'ge','pl','gt','t','hi','vc','le','vs' 180 ); 181 182 {***************************************************************************** 183 Flags 184 *****************************************************************************} 185 186 type 187 TResFlags = ( 188 F_E,F_NE, 189 F_G,F_L,F_GE,F_LE,F_C,F_NC,F_A,F_AE,F_B,F_BE, 190 F_FE,F_FNE, 191 F_FG,F_FL,F_FGE,F_FLE 192 ); 193 194 const 195 FloatResFlags = [F_FE..F_FLE]; 196 197 {***************************************************************************** 198 Reference 199 *****************************************************************************} 200 201 type 202 { direction of address register : } 203 { (An) (An)+ -(An) } 204 tdirection = (dir_none,dir_inc,dir_dec); 205 206 207 {***************************************************************************** 208 Operand Sizes 209 *****************************************************************************} 210 211 { S_NO = No Size of operand } 212 { S_B = 8-bit size operand } 213 { S_W = 16-bit size operand } 214 { S_L = 32-bit size operand } 215 { Floating point types } 216 { S_FS = single type (32 bit) } 217 { S_FD = double/64bit integer } 218 { S_FX = Extended type } 219 topsize = (S_NO,S_B,S_W,S_L,S_FS,S_FD,S_FX,S_IQ); 220 221 {***************************************************************************** 222 Constants 223 *****************************************************************************} 224 225 const 226 {# maximum number of operands in assembler instruction } 227 max_operands = 4; 228 229 {***************************************************************************** 230 Default generic sizes 231 *****************************************************************************} 232 233 {# Defines the default address size for a processor, } 234 OS_ADDR = OS_32; 235 {# the natural int size for a processor, 236 has to match osuinttype/ossinttype as initialized in psystem } 237 OS_INT = OS_32; 238 OS_SINT = OS_S32; 239 {# the maximum float size for a processor, } 240 OS_FLOAT = OS_F64; 241 {# the size of a vector register for a processor } 242 OS_VECTOR = OS_M128; 243 244 245 {***************************************************************************** 246 GDB Information 247 *****************************************************************************} 248 249 {# Register indexes for stabs information, when some 250 parameters or variables are stored in registers. 251 252 Taken from m68kelf.h (DBX_REGISTER_NUMBER) 253 from GCC 3.x source code. 254 255 This is not compatible with the m68k-sun 256 implementation. 257 } 258 stab_regindex : array[tregisterindex] of shortint = 259 ( 260 {$i r68ksta.inc} 261 ); 262 263 {***************************************************************************** 264 Generic Register names 265 *****************************************************************************} 266 267 {# Stack pointer register } 268 NR_STACK_POINTER_REG = NR_SP; 269 RS_STACK_POINTER_REG = RS_SP; 270 {# Frame pointer register } 271 272 { Frame pointer register (initialized in tcpuprocinfo.init_framepointer) } 273 RS_FRAME_POINTER_REG: tsuperregister = RS_NO; 274 NR_FRAME_POINTER_REG: tregister = NR_NO; 275 276 {# Register for addressing absolute data in a position independant way, 277 such as in PIC code. The exact meaning is ABI specific. For 278 further information look at GCC source : PIC_OFFSET_TABLE_REGNUM 279 } 280 RS_PIC_OFFSET_REG: tsuperregister = RS_NO; 281 NR_PIC_OFFSET_REG: tregister = NR_NO; 282 283 { Return address for DWARF } 284 NR_RETURN_ADDRESS_REG = NR_A0; 285 RS_RETURN_ADDRESS_REG = RS_A0; 286 { Results are returned in this register (32-bit values) } 287 NR_FUNCTION_RETURN_REG = NR_D0; 288 RS_FUNCTION_RETURN_REG = RS_D0; 289 { Low part of 64bit return value } 290 NR_FUNCTION_RETURN64_LOW_REG = NR_D0; 291 RS_FUNCTION_RETURN64_LOW_REG = RS_D0; 292 { High part of 64bit return value } 293 NR_FUNCTION_RETURN64_HIGH_REG = NR_D1; 294 RS_FUNCTION_RETURN64_HIGH_REG = RS_D1; 295 { The value returned from a function is available in this register } 296 NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG; 297 RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG; 298 { The lowh part of 64bit value returned from a function } 299 NR_FUNCTION_RESULT64_LOW_REG = NR_FUNCTION_RETURN64_LOW_REG; 300 RS_FUNCTION_RESULT64_LOW_REG = RS_FUNCTION_RETURN64_LOW_REG; 301 { The high part of 64bit value returned from a function } 302 NR_FUNCTION_RESULT64_HIGH_REG = NR_FUNCTION_RETURN64_HIGH_REG; 303 RS_FUNCTION_RESULT64_HIGH_REG = RS_FUNCTION_RETURN64_HIGH_REG; 304 305 {# Floating point results will be placed into this register } 306 NR_FPU_RESULT_REG = NR_FP0; 307 308 {# This is m68k C ABI specific. Some ABIs expect the address of the 309 return struct result value in this register. Note that it could be 310 either A0 or A1, so later it must be decided on target/ABI specific 311 basis. We start with A1 now, because that's what Linux/m68k does 312 currently. (KB) } 313 RS_M68K_STRUCT_RESULT_REG: tsuperregister = RS_A1; 314 NR_M68K_STRUCT_RESULT_REG: tregister = NR_A1; 315 316 NR_DEFAULTFLAGS = NR_SR; 317 RS_DEFAULTFLAGS = RS_SR; 318 319 {***************************************************************************** 320 GCC /ABI linking information 321 *****************************************************************************} 322 323 {# Required parameter alignment when calling a routine declared as 324 stdcall and cdecl. The alignment value should be the one defined 325 by GCC or the target ABI. 326 327 The value of this constant is equal to the constant 328 PARM_BOUNDARY / BITS_PER_UNIT in the GCC source. 329 } 330 std_param_align = 4; { for 32-bit version only } 331 332 333 {***************************************************************************** 334 CPU Dependent Constants 335 *****************************************************************************} 336 337 338 {***************************************************************************** 339 Helpers 340 *****************************************************************************} 341 342 const 343 tcgsize2opsize: Array[tcgsize] of topsize = 344 (S_NO,S_B,S_W,S_L,S_L,S_NO,S_B,S_W,S_L,S_L,S_NO, 345 S_FS,S_FD,S_FX,S_NO,S_NO, 346 S_NO,S_NO,S_NO,S_NO,S_NO,S_NO, 347 S_NO,S_NO,S_NO,S_NO,S_NO,S_NO, 348 S_NO,S_NO,S_NO,S_NO,S_NO, 349 S_NO,S_NO,S_NO,S_NO,S_NO); 350 is_calljmpnull351 function is_calljmp(o:tasmop):boolean; 352 353 procedure inverse_flags(var r : TResFlags); flags_to_condnull354 function flags_to_cond(const f: TResFlags) : TAsmCond; cgsize2subregnull355 function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister; reg_cgsizenull356 function reg_cgsize(const reg: tregister): tcgsize; 357 findreg_by_numbernull358 function findreg_by_number(r:Tregister):tregisterindex; std_regnum_searchnull359 function std_regnum_search(const s:string):Tregister; std_regnamenull360 function std_regname(r:Tregister):string; 361 isaddressregisternull362 function isaddressregister(reg : tregister) : boolean; isintregisternull363 function isintregister(reg : tregister) : boolean; fpuregopsizenull364 function fpuregopsize: TOpSize; {$ifdef USEINLINE}inline;{$endif USEINLINE} fpuregsizenull365 function fpuregsize: aint; {$ifdef USEINLINE}inline;{$endif USEINLINE} needs_unalignednull366 function needs_unaligned(const refalignment: aint; const size: tcgsize): boolean; isregoverlapnull367 function isregoverlap(reg1: tregister; reg2: tregister): boolean; 368 inverse_condnull369 function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE} conditions_equalnull370 function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE} dwarf_regnull371 function dwarf_reg(r:tregister):shortint; dwarf_reg_no_errornull372 function dwarf_reg_no_error(r:tregister):shortint; 373 isvalue8bitnull374 function isvalue8bit(val: tcgint): boolean; isvalue16bitnull375 function isvalue16bit(val: tcgint): boolean; isvalueforaddqsubqnull376 function isvalueforaddqsubq(val: tcgint): boolean; 377 378 implementation 379 380 uses 381 verbose, 382 rgbase; 383 384 385 const 386 std_regname_table : TRegNameTable = ( 387 {$i r68kstd.inc} 388 ); 389 390 regnumber_index : array[tregisterindex] of tregisterindex = ( 391 {$i r68krni.inc} 392 ); 393 394 std_regname_index : array[tregisterindex] of tregisterindex = ( 395 {$i r68ksri.inc} 396 ); 397 398 399 {***************************************************************************** 400 Helpers 401 *****************************************************************************} 402 is_calljmpnull403 function is_calljmp(o:tasmop):boolean; 404 begin 405 is_calljmp := 406 o in [A_BXX,A_FBXX,A_DBXX,A_BCC..A_BVS,A_DBCC..A_DBVS,A_FBEQ..A_FSNGLE, 407 A_JSR,A_BSR,A_JMP]; 408 end; 409 410 411 procedure inverse_flags(var r: TResFlags); 412 const flagsinvers : array[F_E..F_FLE] of tresflags = 413 (F_NE,F_E, 414 F_LE,F_GE, 415 F_L,F_G, 416 F_NC,F_C, 417 F_BE,F_B, 418 F_AE,F_A, 419 F_FNE,F_FE, 420 F_FLE,F_FGE, 421 F_FL,F_G); 422 begin 423 r:=flagsinvers[r]; 424 end; 425 426 427 flags_to_condnull428 function flags_to_cond(const f: TResFlags) : TAsmCond; 429 const flags2cond: array[tresflags] of tasmcond = ( 430 C_EQ,{F_E equal} 431 C_NE,{F_NE not equal} 432 C_GT,{F_G gt signed} 433 C_LT,{F_L lt signed} 434 C_GE,{F_GE ge signed} 435 C_LE,{F_LE le signed} 436 C_CS,{F_C carry set} 437 C_CC,{F_NC carry clear} 438 C_HI,{F_A gt unsigned} 439 C_CC,{F_AE ge unsigned} 440 C_CS,{F_B lt unsigned} 441 C_LS,{F_BE le unsigned} 442 C_EQ,{F_FEQ } 443 C_NE,{F_FNE } 444 C_GT,{F_FG } 445 C_LT,{F_FL } 446 C_GE,{F_FGE } 447 C_LE);{F_FLE } 448 begin 449 flags_to_cond := flags2cond[f]; 450 end; 451 cgsize2subregnull452 function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister; 453 var p: pointer; 454 begin 455 case s of 456 OS_NO: begin 457 { TODO: FIX ME!!! results in bad code generation} 458 cgsize2subreg:=R_SUBWHOLE; 459 end; 460 461 OS_8,OS_S8: 462 cgsize2subreg:=R_SUBWHOLE; 463 OS_16,OS_S16: 464 cgsize2subreg:=R_SUBWHOLE; 465 OS_32,OS_S32: 466 cgsize2subreg:=R_SUBWHOLE; 467 OS_64,OS_S64: 468 begin 469 cgsize2subreg:=R_SUBWHOLE; 470 end; 471 OS_F32 : 472 cgsize2subreg:=R_SUBFS; 473 OS_F64 : 474 cgsize2subreg:=R_SUBFD; 475 { 476 begin 477 // is this correct? (KB) 478 cgsize2subreg:=R_SUBNONE; 479 end; 480 } 481 else begin 482 // this supposed to be debug 483 // p:=nil; dword(p^):=0; 484 // internalerror(200301231); 485 cgsize2subreg:=R_SUBWHOLE; 486 end; 487 end; 488 end; 489 490 reg_cgsizenull491 function reg_cgsize(const reg: tregister): tcgsize; 492 { 68881 & compatibles -> 80 bit } 493 { CF FPU -> 64 bit } 494 const 495 fpureg_cgsize: array[boolean] of tcgsize = ( OS_F80, OS_F64 ); 496 begin 497 case getregtype(reg) of 498 R_ADDRESSREGISTER, 499 R_INTREGISTER : 500 result:=OS_32; 501 R_FPUREGISTER : 502 result:=fpureg_cgsize[current_settings.fputype = fpu_coldfire]; 503 else 504 internalerror(200303181); 505 end; 506 end; 507 508 findreg_by_numbernull509 function findreg_by_number(r:Tregister):tregisterindex; 510 begin 511 result:=findreg_by_number_table(r,regnumber_index); 512 end; 513 514 std_regnum_searchnull515 function std_regnum_search(const s:string):Tregister; 516 begin 517 result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)]; 518 end; 519 520 std_regnamenull521 function std_regname(r:Tregister):string; 522 var 523 p : tregisterindex; 524 begin 525 p:=findreg_by_number_table(r,regnumber_index); 526 if p<>0 then 527 result:=std_regname_table[p] 528 else 529 result:=generic_regname(r); 530 end; 531 532 isaddressregisternull533 function isaddressregister(reg : tregister) : boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE} 534 begin 535 result:=getregtype(reg)=R_ADDRESSREGISTER; 536 end; 537 isintregisternull538 function isintregister(reg : tregister) : boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE} 539 begin 540 result:=getregtype(reg)=R_INTREGISTER; 541 end; 542 fpuregopsizenull543 function fpuregopsize: TOpSize; {$ifdef USEINLINE}inline;{$endif USEINLINE} 544 const 545 fpu_regopsize: array[boolean] of TOpSize = ( S_FX, S_FD ); 546 begin 547 result:=fpu_regopsize[current_settings.fputype = fpu_coldfire]; 548 end; 549 fpuregsizenull550 function fpuregsize: aint; {$ifdef USEINLINE}inline;{$endif USEINLINE} 551 const 552 fpu_regsize: array[boolean] of aint = ( 12, 8 ); { S_FX is 12 bytes on '881 } 553 begin 554 result:=fpu_regsize[current_settings.fputype = fpu_coldfire]; 555 end; 556 needs_unalignednull557 function needs_unaligned(const refalignment: aint; const size: tcgsize): boolean; 558 begin 559 result:=not(CPUM68K_HAS_UNALIGNED in cpu_capabilities[current_settings.cputype]) and 560 (refalignment = 1) and 561 (tcgsize2size[size] > 1); 562 end; 563 returnsnull564 // the function returns true, if the registers overlap (subreg of the same superregister and same type) 565 function isregoverlap(reg1: tregister; reg2: tregister): boolean; 566 begin 567 tregisterrec(reg1).subreg:=R_SUBNONE; 568 tregisterrec(reg2).subreg:=R_SUBNONE; 569 result:=reg1=reg2; 570 end; 571 inverse_condnull572 function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE} 573 const 574 inverse:array[TAsmCond] of TAsmCond=(C_None, 575 //C_CC,C_LS,C_CS,C_LT,C_EQ,C_MI,C_F,C_NE, 576 C_CS,C_HI,C_CC,C_GE,C_NE,C_PL,C_T,C_EQ, 577 //C_GE,C_PL,C_GT,C_T,C_HI,C_VC,C_LE,C_VS 578 C_LT,C_MI,C_LE,C_F,C_LS,C_VS,C_GT,C_VC 579 ); 580 begin 581 result := inverse[c]; 582 end; 583 584 conditions_equalnull585 function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE} 586 begin 587 result := c1 = c2; 588 end; 589 590 dwarf_regnull591 function dwarf_reg(r:tregister):shortint; 592 begin 593 result:=regdwarf_table[findreg_by_number(r)]; 594 if result=-1 then 595 internalerror(200603251); 596 end; 597 dwarf_reg_no_errornull598 function dwarf_reg_no_error(r:tregister):shortint; 599 begin 600 result:=regdwarf_table[findreg_by_number(r)]; 601 end; 602 603 { returns true if given value fits to an 8bit signed integer } isvalue8bitnull604 function isvalue8bit(val: tcgint): boolean; 605 begin 606 isvalue8bit := (val >= low(shortint)) and (val <= high(shortint)); 607 end; 608 609 { returns true if given value fits to a 16bit signed integer } isvalue16bitnull610 function isvalue16bit(val: tcgint): boolean; 611 begin 612 isvalue16bit := (val >= low(smallint)) and (val <= high(smallint)); 613 end; 614 615 { returns true if given value fits addq/subq argument, so in 1 - 8 range } isvalueforaddqsubqnull616 function isvalueforaddqsubq(val: tcgint): boolean; 617 begin 618 isvalueforaddqsubq := (val >= 1) and (val <= 8); 619 end; 620 621 end. 622