1unit at91sam7x256; 2 3{$goto on} 4 5 interface 6 7 type 8 AT91_REG = DWord; 9 TBitvector32 = bitpacked array[0..31] of 0..1; 10 11 const 12 // (CKGR) 13 AT91C_CKGR_DIV = dword($000000FF); // Divider Selected 14 AT91C_CKGR_MOSCEN = dword($00000001); // Main Oscillator Enable 15 AT91C_CKGR_MUL = dword($07FF0000); // PLL Multiplier 16 AT91C_CKGR_OSCOUNT = dword($0000FF00); // Main Oscillator Start-up Time 17 AT91C_CKGR_OUT_0 = dword($00000000); // Please refer to the PLL datasheet 18 AT91C_CKGR_PLLCOUNT = dword($00003F00); // PLL Counter 19 20 AT91C_MC_FMCN = dword($00FF0000); // (MC) Flash Microsecond Cycle Number 21 AT91C_MC_FWS_1FWS = dword($00000100); 22 23 AT91C_WDTC_WDDIS = dword($00008000); 24 25 type 26 TAT91C_Low_Lewel_Settings = record 27 osc_div_factor:byte; 28 osc_mul_factor:word; 29 end; 30 31 var 32 AT91C_AIC_SMR : array[0..31] of AT91_REG absolute $FFFFF000; // Source Mode Register 33 AT91C_AIC_SVR : array[0..31] of AT91_REG absolute $FFFFF020; // Source Vector Register 34 AT91C_AIC_IVR : AT91_REG absolute $FFFFF040; // IRQ Vector Register 35 AT91C_AIC_FVR : AT91_REG absolute $FFFFF044; // FIQ Vector Register 36 AT91C_AIC_ISR : AT91_REG absolute $FFFFF048; // Interrupt Status Register 37 AT91C_AIC_IPR : AT91_REG absolute $FFFFF04C; // Interrupt Pending Register 38 AT91C_AIC_IMR : AT91_REG absolute $FFFFF050; // Interrupt Mask Register 39 AT91C_AIC_CISR : AT91_REG absolute $FFFFF054; // Core Interrupt Status Register } 40 // Reserved0 : array[0..1] of AT91_REG; 41 AT91C_AIC_IECR : AT91_REG absolute $FFFFF060; // Interrupt Enable Command Register 42 AT91C_AIC_IDCR : AT91_REG absolute $FFFFF064; // Interrupt Disable Command Register 43 AT91C_AIC_ICCR : AT91_REG absolute $FFFFF068; // Interrupt Clear Command Register 44 AT91C_AIC_ISCR : AT91_REG absolute $FFFFF06C; // Interrupt Set Command Register 45 AT91C_AIC_EOICR : AT91_REG absolute $FFFFF070; // End of Interrupt Command Register 46 AT91C_AIC_SPU : AT91_REG absolute $FFFFF074; // Spurious Vector Register 47 AT91C_AIC_DCR : AT91_REG absolute $FFFFF078; // Debug Control Register (Protect) } 48 // Reserved1 : array[0..0] of AT91_REG; 49 50 // ========== Register definition for PIOA peripheral ========== 51 AT91C_PIOA_IMR : DWord absolute $FFFFF448; // Interrupt Mask Register 52 AT91C_PIOA_IER : DWord absolute $FFFFF440; // Interrupt Enable Register 53 AT91C_PIOA_OWDR : DWord absolute $FFFFF4A4; // Output Write Disable Register 54 AT91C_PIOA_ISR : DWord absolute $FFFFF44C; // Interrupt Status Register 55 AT91C_PIOA_PPUDR : DWord absolute $FFFFF460; // Pull-up Disable Register 56 AT91C_PIOA_MDSR : DWord absolute $FFFFF458; // Multi-driver Status Register 57 AT91C_PIOA_MDER : DWord absolute $FFFFF450; // Multi-driver Enable Register 58 AT91C_PIOA_PER : DWord absolute $FFFFF400; // PIO Enable Register 59 AT91C_PIOA_PSR : DWord absolute $FFFFF408; // PIO Status Register 60 AT91C_PIOA_OER : DWord absolute $FFFFF410; // Output Enable Register 61 AT91C_PIOA_BSR : DWord absolute $FFFFF474; // Select B Register 62 AT91C_PIOA_PPUER : DWord absolute $FFFFF464; // Pull-up Enable Register 63 AT91C_PIOA_MDDR : DWord absolute $FFFFF454; // Multi-driver Disable Register 64 AT91C_PIOA_PDR : DWord absolute $FFFFF404; // PIO Disable Register 65 AT91C_PIOA_ODR : DWord absolute $FFFFF414; // Output Disable Registerr 66 AT91C_PIOA_IFDR : DWord absolute $FFFFF424; // Input Filter Disable Register 67 AT91C_PIOA_ABSR : DWord absolute $FFFFF478; // AB Select Status Register 68 AT91C_PIOA_ASR : DWord absolute $FFFFF470; // Select A Register 69 AT91C_PIOA_PPUSR : DWord absolute $FFFFF468; // Pull-up Status Register 70 AT91C_PIOA_ODSR : DWord absolute $FFFFF438; // Output Data Status Register 71 AT91C_PIOA_SODR : DWord absolute $FFFFF430; // Set Output Data Register 72 AT91C_PIOA_IFSR : DWord absolute $FFFFF428; // Input Filter Status Register 73 AT91C_PIOA_IFER : DWord absolute $FFFFF420; // Input Filter Enable Register 74 AT91C_PIOA_OSR : DWord absolute $FFFFF418; // Output Status Register 75 AT91C_PIOA_IDR : DWord absolute $FFFFF444; // Interrupt Disable Register 76 AT91C_PIOA_PDSR : DWord absolute $FFFFF43C; // Pin Data Status Register 77 AT91C_PIOA_CODR : DWord absolute $FFFFF434; // Clear Output Data Register 78 AT91C_PIOA_OWSR : DWord absolute $FFFFF4A8; // Output Write Status Register 79 AT91C_PIOA_OWER : DWord absolute $FFFFF4A0; // Output Write Enable Register 80 // ========== Register definition for PIOB peripheral ========== 81 AT91C_PIOB_PER : DWord absolute $FFFFF600; // PIO Enable Register 82 AT91C_PIOB_PDR : DWord absolute $FFFFF604; // PIO Disable Register 83 AT91C_PIOB_PSR : DWord absolute $FFFFF608; // PIO Status Register 84 AT91C_PIOB_OER : DWord absolute $FFFFF610; // Output Enable Register 85 AT91C_PIOB_ODR : DWord absolute $FFFFF614; // Output Disable Registerr 86 AT91C_PIOB_OSR : DWord absolute $FFFFF618; // Output Status Register 87 AT91C_PIOB_IFER : DWord absolute $FFFFF620; // Input Filter Enable Register 88 AT91C_PIOB_IFDR : DWord absolute $FFFFF624; // Input Filter Disable Register 89 AT91C_PIOB_IFSR : DWord absolute $FFFFF628; // Input Filter Status Register 90 AT91C_PIOB_SODR : DWord absolute $FFFFF630; // Set Output Data Register 91 AT91C_PIOB_CODR : DWord absolute $FFFFF634; // Clear Output Data Register 92 AT91C_PIOB_ODSR : DWord absolute $FFFFF638; // Output Data Status Register 93 AT91C_PIOB_PDSR : DWord absolute $FFFFF63C; // Pin Data Status Register 94 AT91C_PIOB_IER : DWord absolute $FFFFF640; // Interrupt Enable Register 95 AT91C_PIOB_IDR : DWord absolute $FFFFF644; // Interrupt Disable Register 96 AT91C_PIOB_IMR : DWord absolute $FFFFF648; // Interrupt Mask Register 97 AT91C_PIOB_ISR : DWord absolute $FFFFF64C; // Interrupt Status Register 98 AT91C_PIOB_MDER : DWord absolute $FFFFF650; // Multi-driver Enable Register 99 AT91C_PIOB_MDDR : DWord absolute $FFFFF654; // Multi-driver Disable Register 100 AT91C_PIOB_MDSR : DWord absolute $FFFFF658; // Multi-driver Status Register 101 AT91C_PIOB_PPUDR : DWord absolute $FFFFF660; // Pull-up Disable Register 102 AT91C_PIOB_PPUER : DWord absolute $FFFFF664; // Pull-up Enable Register 103 AT91C_PIOB_PPUSR : DWord absolute $FFFFF668; // Pull-up Status Register 104 AT91C_PIOB_ASR : DWord absolute $FFFFF670; // Select A Register 105 AT91C_PIOB_BSR : DWord absolute $FFFFF674; // Select B Register 106 AT91C_PIOB_ABSR : DWord absolute $FFFFF678; // AB Select Status Register 107 AT91C_PIOB_OWER : DWord absolute $FFFFF6A0; // Output Write Enable Register 108 AT91C_PIOB_OWDR : DWord absolute $FFFFF6A4; // Output Write Disable Register 109 AT91C_PIOB_OWSR : DWord absolute $FFFFF6A8; // Output Write Status Register 110 111 // ========== Register definition for CKGR peripheral ========== 112 AT91C_CKGR_PLLR : DWord absolute $FFFFFC2C; // PLL Register 113 AT91C_CKGR_MCFR : DWord absolute $FFFFFC24; // Main Clock Frequency Register 114 AT91C_CKGR_MOR : DWord absolute $FFFFFC20; // Main Oscillator Register 115 // ========== Register definition for PMC peripheral ========== 116 AT91C_PMC_SCSR : DWord absolute $FFFFFC08; // System Clock Status Register 117 AT91C_PMC_SCER : DWord absolute $FFFFFC00; // System Clock Enable Register 118 AT91C_PMC_IMR : DWord absolute $FFFFFC6C; // Interrupt Mask Register 119 AT91C_PMC_IDR : DWord absolute $FFFFFC64; // Interrupt Disable Register 120 AT91C_PMC_PCDR : DWord absolute $FFFFFC14; // Peripheral Clock Disable Register 121 AT91C_PMC_SCDR : DWord absolute $FFFFFC04; // System Clock Disable Register 122 AT91C_PMC_SR : DWord absolute $FFFFFC68; // Status Register 123 AT91C_PMC_IER : DWord absolute $FFFFFC60; // Interrupt Enable Register 124 AT91C_PMC_MCKR : DWord absolute $FFFFFC30; // Master Clock Register 125 AT91C_PMC_MOR : DWord absolute $FFFFFC20; // Main Oscillator Register 126 AT91C_PMC_PCER : DWord absolute $FFFFFC10; // Peripheral Clock Enable Register 127 AT91C_PMC_PCSR : DWord absolute $FFFFFC18; // Peripheral Clock Status Register 128 AT91C_PMC_PLLR : DWord absolute $FFFFFC2C; // PLL Register 129 AT91C_PMC_MCFR : DWord absolute $FFFFFC24; // Main Clock Frequency Register 130 AT91C_PMC_PCKR : DWord absolute $FFFFFC40; // Programmable Clock Register 131 132 const 133 AT91C_PMC_CSS_PLL_CLK = dword($3); // (PMC) Clock from PLL is selected 134 AT91C_PMC_PRES_CLK_2 = dword($1) shl 2; // (PMC) Selected clock divided by 2 135 AT91C_PMC_MOSCS = dword($1) shl 0; // (PMC) MOSC Status/Enable/Disable/Mask 136 AT91C_PMC_LOCK = dword($1) shl 2; // (PMC) PLL Status/Enable/Disable/Mask 137 AT91C_PMC_MCKRDY = dword($1) shl 3; // (PMC) MCK_RDY Status/Enable/Disable/Mask 138 139 var 140 // ========== Register definition for RSTC peripheral ========== 141 AT91C_RSTC_RSR : DWord absolute $FFFFFD04; // Reset Status Register 142 AT91C_RSTC_RMR : DWord absolute $FFFFFD08; // Reset Mode Register 143 AT91C_RSTC_RCR : DWord absolute $FFFFFD00; // Reset Control Register 144 145 // ========== Register definition for RTTC peripheral ========== 146 AT91C_RTTC_RTMR : DWord absolute $FFFFFD20; // Real-time Mode Register 147 AT91C_RTTC_RTAR : DWord absolute $FFFFFD24; // Real-time Alarm Register 148 AT91C_RTTC_RTVR : DWord absolute $FFFFFD28; // Real-time Value Register 149 AT91C_RTTC_RTSR : DWord absolute $FFFFFD2C; // Real-time Status Register 150 151 // ========== Register definition for PITC peripheral ========== 152 AT91C_PITC_PIMR : DWord absolute $FFFFFD30; // Period Interval Mode Register 153 AT91C_PITC_PISR : DWord absolute $FFFFFD34; // Period Interval Status Register 154 AT91C_PITC_PIVR : DWord absolute $FFFFFD38; // Period Interval Value Register 155 AT91C_PITC_PIIR : DWord absolute $FFFFFD3C; // Period Interval Image Register 156 157 // ========== Register definition for WDTC peripheral ========== 158 AT91C_WDTC_WDMR : DWord absolute $FFFFFD44; // Watchdog Mode Register 159 AT91C_WDTC_WDSR : DWord absolute $FFFFFD48; // Watchdog Status Register 160 AT91C_WDTC_WDCR : DWord absolute $FFFFFD40; // Watchdog Control Register 161 // ========== Register definition for VREG peripheral ========== 162 AT91C_VREG_MR : DWord absolute $FFFFFD60; // Voltage Regulator Mode Register 163 // ========== Register definition for MC peripheral ========== 164 AT91C_MC_FCR : DWord absolute $FFFFFF64; // MC Flash Command Register 165 AT91C_MC_ASR : DWord absolute $FFFFFF04; // MC Abort Status Register 166 AT91C_MC_FSR : DWord absolute $FFFFFF68; // MC Flash Status Register 167 AT91C_MC_FMR : DWord absolute $FFFFFF60; // MC Flash Mode Register 168 AT91C_MC_AASR : DWord absolute $FFFFFF08; // MC Abort Address Status Register 169 AT91C_MC_RCR : DWord absolute $FFFFFF00; // MC Remap Control Register 170 171 172 // ***************************************************************************** 173 // BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 174 // ***************************************************************************** 175 AT91C_BASE_SYS : DWord absolute $FFFFF000; // (SYS) Base Address 176 AT91C_BASE_AIC : DWord absolute $FFFFF000; // (AIC) Base Address 177 AT91C_BASE_PIOA : DWord absolute $FFFFF400; // (PIOA) Base Address 178 AT91C_BASE_CKGR : DWord absolute $FFFFFC20; // (CKGR) Base Address 179 AT91C_BASE_PMC : DWord absolute $FFFFFC00; // (PMC) Base Address 180 AT91C_BASE_WDTC : DWord absolute $FFFFFD40; // (WDTC) Base Address 181 AT91C_BASE_VREG : DWord absolute $FFFFFD60; // (VREG) Base Address 182 AT91C_BASE_MC : DWord absolute $FFFFFF00; // (MC) Base Address 183 184 // ========== Peripheral mapping ========== 185 186 // ========== Register definition for TC0 peripheral ========== 187 AT91C_TC0_CCR : DWord absolute $FFFA0000; // Channel Control Register 188 AT91C_TC0_CMR : DWord absolute $FFFA0004; // Channel Mode Register (Capture Mode / Waveform Mode) 189 AT91C_TC0_CV : DWord absolute $FFFA0010; // Counter Value 190 AT91C_TC0_RA : DWord absolute $FFFA0014; // Register A 191 AT91C_TC0_RB : DWord absolute $FFFA0018; // Register B 192 AT91C_TC0_RC : DWord absolute $FFFA001C; // Register C 193 AT91C_TC0_SR : DWord absolute $FFFA0020; // Status Register 194 AT91C_TC0_IMR : DWord absolute $FFFA002C; // Interrupt Mask Register 195 AT91C_TC0_IER : DWord absolute $FFFA0024; // Interrupt Enable Register 196 AT91C_TC0_IDR : DWord absolute $FFFA0028; // Interrupt Disable Register 197 // ========== Register definition for TC1 peripheral ========== 198 AT91C_TC1_CCR : DWord absolute $FFFA0040; // Channel Control Register 199 AT91C_TC1_CMR : DWord absolute $FFFA0044; // Channel Mode Register (Capture Mode / Waveform Mode) 200 AT91C_TC1_CV : DWord absolute $FFFA0050; // Counter Value 201 AT91C_TC1_RA : DWord absolute $FFFA0054; // Register A 202 AT91C_TC1_RB : DWord absolute $FFFA0058; // Register B 203 AT91C_TC1_RC : DWord absolute $FFFA005C; // Register C 204 AT91C_TC1_SR : DWord absolute $FFFA0060; // Status Register 205 AT91C_TC1_IER : DWord absolute $FFFA0064; // Interrupt Enable Register 206 AT91C_TC1_IDR : DWord absolute $FFFA0068; // Interrupt Disable Register 207 AT91C_TC1_IMR : DWord absolute $FFFA006C; // Interrupt Mask Register 208 // ========== Register definition for TC2 peripheral ========== 209 AT91C_TC2_CCR : DWord absolute $FFFA0080; // Channel Control Register 210 AT91C_TC2_CMR : DWord absolute $FFFA0084; // Channel Mode Register (Capture Mode / Waveform Mode; 211 AT91C_TC2_CV : DWord absolute $FFFA0090; // Counter Value 212 AT91C_TC2_RA : DWord absolute $FFFA0094; // Register A 213 AT91C_TC2_RB : DWord absolute $FFFA0098; // Register B 214 AT91C_TC2_RC : DWord absolute $FFFA009C; // Register C 215 AT91C_TC2_SR : DWord absolute $FFFA00A0; // Status Register 216 AT91C_TC2_IER : DWord absolute $FFFA00A4; // Interrupt Enable Register 217 AT91C_TC2_IDR : DWord absolute $FFFA00A8; // Interrupt Disable Register 218 AT91C_TC2_IMR : DWord absolute $FFFA00AC; // Interrupt Mask Register 219 // ========== Register definition for TCB peripheral ========== 220 AT91C_TCB_BCR : DWord absolute $FFFA00C0; // TC Block Control Register 221 AT91C_TCB_BMR : DWord absolute $FFFA00C4; // TC Block Mode Register 222 // ========== Register definition for UDP peripheral ========== 223 AT91C_UDP_NUM : DWord absolute $FFFB0000; // Frame Number Register 224 AT91C_UDP_GLBSTATE : DWord absolute $FFFB0004; // Global State Register 225 AT91C_UDP_FADDR : DWord absolute $FFFB0008; // Function Address Register 226 AT91C_UDP_IER : DWord absolute $FFFB0010; // Interrupt Enable Register 227 AT91C_UDP_IDR : DWord absolute $FFFB0014; // Interrupt Disable Register 228 AT91C_UDP_IMR : DWord absolute $FFFB0018; // Interrupt Mask Register 229 AT91C_UDP_ISR : DWord absolute $FFFB001C; // Interrupt Status Register 230 AT91C_UDP_ICR : DWord absolute $FFFB0020; // Interrupt Clear Register 231 AT91C_UDP_RSTEP : DWord absolute $FFFB0028; // Reset Endpoint Register 232 AT91C_UDP_CSR : DWord absolute $FFFB0030; // Endpoint Control and Status Register 233 AT91C_UDP_FDR : DWord absolute $FFFB0050; // Endpoint FIFO Data Register 234 AT91C_UDP_TXVC : DWord absolute $FFFB0074; // Transceiver Control Register 235 // ========== Register definition for TWI peripheral ========== 236 AT91C_TWI_CR : DWord absolute $FFFB8000; // Control Register 237 AT91C_TWI_MMR : DWord absolute $FFFB8004; // Master Mode Register 238 AT91C_TWI_IADR : DWord absolute $FFFB800C; // Internal Address Register 239 AT91C_TWI_CWGR : DWord absolute $FFFB8010; // Clock Waveform Generator Register 240 AT91C_TWI_SR : DWord absolute $FFFB8020; // Status Register 241 AT91C_TWI_IER : DWord absolute $FFFB8024; // Interrupt Enable Register 242 AT91C_TWI_IDR : DWord absolute $FFFB8028; // Interrupt Disable Register 243 AT91C_TWI_IMR : DWord absolute $FFFB802C; // Interrupt Mask Register 244 AT91C_TWI_RHR : DWord absolute $FFFB8030; // Receive Holding Register 245 AT91C_TWI_THR : DWord absolute $FFFB8034; // Transmit Holding Register 246 // ========== Register definition for US0 peripheral ========== 247 AT91C_US0_CR : DWord absolute $FFFC0000; // Control Register 248 AT91C_US0_MR : DWord absolute $FFFC0004; // Mode Register 249 AT91C_US0_IER : DWord absolute $FFFC0008; // Interrupt Enable Register 250 AT91C_US0_IDR : DWord absolute $FFFC000C; // Interrupt Disable Register 251 AT91C_US0_IMR : DWord absolute $FFFC0010; // Interrupt Mask Register 252 AT91C_US0_CSR : DWord absolute $FFFC0014; // Channel Status Register 253 AT91C_US0_RHR : DWord absolute $FFFC0018; // Receiver Holding Register 254 AT91C_US0_THR : DWord absolute $FFFC001C; // Transmitter Holding Register 255 AT91C_US0_BRGR : DWord absolute $FFFC0020; // Baud Rate Generator Register 256 AT91C_US0_RTOR : DWord absolute $FFFC0024; // Receiver Time-out Register 257 AT91C_US0_TTGR : DWord absolute $FFFC0028; // Transmitter Time-guard Register 258 AT91C_US0_FIDI : DWord absolute $FFFC0040; // FI_DI_Ratio Register 259 AT91C_US0_NER : DWord absolute $FFFC0044; // Nb Errors Register 260 AT91C_US0_IF : DWord absolute $FFFC004C; // IRDA_FILTER Register 261 // ========== Register definition for PDC_US0 peripheral ========== 262 AT91C_US0_RPR : DWord absolute $FFFC0100; // Receive Pointer Register 263 AT91C_US0_RCR : DWord absolute $FFFC0104; // Receive Counter Register 264 AT91C_US0_TPR : DWord absolute $FFFC0108; // Transmit Pointer Register 265 AT91C_US0_TCR : DWord absolute $FFFC010C; // Transmit Counter Register 266 AT91C_US0_RNPR : DWord absolute $FFFC0110; // Receive Next Pointer Register 267 AT91C_US0_RNCR : DWord absolute $FFFC0114; // Receive Next Counter Register 268 AT91C_US0_TNPR : DWord absolute $FFFC0118; // Transmit Next Pointer Register 269 AT91C_US0_TNCR : DWord absolute $FFFC011C; // Transmit Next Counter Register 270 AT91C_US0_PTCR : DWord absolute $FFFC0120; // PDC Transfer Control Register 271 AT91C_US0_PTSR : DWord absolute $FFFC0124; // PDC Transfer Status Register 272 // ========== Register definition for US1 peripheral ========== 273 AT91C_US1_CR : DWord absolute $FFFC4000; // Control Register 274 AT91C_US1_MR : DWord absolute $FFFC4004; // Mode Register 275 AT91C_US1_IER : DWord absolute $FFFC4008; // Interrupt Enable Register 276 AT91C_US1_IDR : DWord absolute $FFFC400C; // Interrupt Disable Register 277 AT91C_US1_IMR : DWord absolute $FFFC4010; // Interrupt Mask Register 278 AT91C_US1_CSR : DWord absolute $FFFC4014; // Channel Status Register 279 AT91C_US1_THR : DWord absolute $FFFC401C; // Transmitter Holding Register 280 AT91C_US1_RHR : DWord absolute $FFFC4018; // Receiver Holding Register 281 AT91C_US1_BRGR : DWord absolute $FFFC4020; // Baud Rate Generator Register 282 AT91C_US1_RTOR : DWord absolute $FFFC4024; // Receiver Time-out Register 283 AT91C_US1_TTGR : DWord absolute $FFFC4028; // Transmitter Time-guard Register 284 AT91C_US1_FIDI : DWord absolute $FFFC4040; // FI_DI_Ratio Register 285 AT91C_US1_NER : DWord absolute $FFFC4044; // Nb Errors Register 286 AT91C_US1_IF : DWord absolute $FFFC404C; // IRDA_FILTER Register 287 // ========== Register definition for PDC_US1 peripheral ========== 288 AT91C_US1_RPR : DWord absolute $FFFC4100; // Receive Pointer Register 289 AT91C_US1_RCR : DWord absolute $FFFC4104; // Receive Counter Register 290 AT91C_US1_TPR : DWord absolute $FFFC4108; // Transmit Pointer Register 291 AT91C_US1_TCR : DWord absolute $FFFC410C; // Transmit Counter Register 292 AT91C_US1_RNPR : DWord absolute $FFFC4110; // Receive Next Pointer Register 293 AT91C_US1_RNCR : DWord absolute $FFFC4114; // Receive Next Counter Register 294 AT91C_US1_TNPR : DWord absolute $FFFC4118; // Transmit Next Pointer Register 295 AT91C_US1_TNCR : DWord absolute $FFFC411C; // Transmit Next Counter Register 296 AT91C_US1_PTCR : DWord absolute $FFFC4120; // PDC Transfer Control Register 297 AT91C_US1_PTSR : DWord absolute $FFFC4124; // PDC Transfer Status Register 298 // ========== Register definition for PWMC peripheral ========== 299 AT91C_PWMC_MR : DWord absolute $FFFCC000; // PWMC Mode Register 300 AT91C_PWMC_ENA : DWord absolute $FFFCC004; // PWMC Enable Register 301 AT91C_PWMC_DIS : DWord absolute $FFFCC008; // PWMC Disable Register 302 AT91C_PWMC_SR : DWord absolute $FFFCC00C; // PWMC Status Register 303 AT91C_PWMC_IER : DWord absolute $FFFCC010; // PWMC Interrupt Enable Register 304 AT91C_PWMC_ISR : DWord absolute $FFFCC01C; // PWMC Interrupt Status Register 305 AT91C_PWMC_IDR : DWord absolute $FFFCC014; // PWMC Interrupt Disable Register 306 AT91C_PWMC_IMR : DWord absolute $FFFCC018; // PWMC Interrupt Mask Register 307 AT91C_PWMC_VR : DWord absolute $FFFCC0FC; // PWMC Version Register 308 // ========== Register definition for PWMC_CH0 peripheral ========== 309 AT91C_PWMC_CH0_CMR : DWord absolute $FFFCC200; // Channel Mode Register 310 AT91C_PWMC_CH0_CDTYR : DWord absolute $FFFCC204; // Channel Duty Cycle Register 311 AT91C_PWMC_CH0_CPRDR : DWord absolute $FFFCC208; // Channel Period Register 312 AT91C_PWMC_CH0_CCNTR : DWord absolute $FFFCC20C; // Channel Counter Register 313 AT91C_PWMC_CH0_CUPDR : DWord absolute $FFFCC210; // Channel Update Register 314 // ========== Register definition for PWMC_CH1 peripheral ========== 315 AT91C_PWMC_CH1_CMR : DWord absolute $FFFCC220; // Channel Mode Register 316 AT91C_PWMC_CH1_CDTYR : DWord absolute $FFFCC224; // Channel Duty Cycle Register 317 AT91C_PWMC_CH1_CPRDR : DWord absolute $FFFCC228; // Channel Period Register 318 AT91C_PWMC_CH1_CCNTR : DWord absolute $FFFCC22C; // Channel Counter Register 319 AT91C_PWMC_CH1_CUPDR : DWord absolute $FFFCC230; // Channel Update Register 320 // ========== Register definition for PWMC_CH2 peripheral ========== 321 AT91C_PWMC_CH2_CMR : DWord absolute $FFFCC240; // Channel Mode Register 322 AT91C_PWMC_CH2_CDTYR : DWord absolute $FFFCC244; // Channel Duty Cycle Register 323 AT91C_PWMC_CH2_CPRDR : DWord absolute $FFFCC248; // Channel Period Register 324 AT91C_PWMC_CH2_CCNTR : DWord absolute $FFFCC24C; // Channel Counter Register 325 AT91C_PWMC_CH2_CUPDR : DWord absolute $FFFCC250; // Channel Update Register 326 // ========== Register definition for PWMC_CH3 peripheral ========== 327 AT91C_PWMC_CH3_CMR : DWord absolute $FFFCC260; // Channel Mode Register 328 AT91C_PWMC_CH3_CDTYR : DWord absolute $FFFCC264; // Channel Duty Cycle Register 329 AT91C_PWMC_CH3_CPRDR : DWord absolute $FFFCC268; // Channel Period Register 330 AT91C_PWMC_CH3_CCNTR : DWord absolute $FFFCC26C; // Channel Counter Register 331 AT91C_PWMC_CH3_CUPDR : DWord absolute $FFFCC270; // Channel Update Register 332 // ========== Register definition for ADC peripheral ========== 333 AT91C_ADC_CR : DWord absolute $FFFD8000; // ADC Control Register 334 AT91C_ADC_MR : DWord absolute $FFFD8004; // ADC Mode Register 335 AT91C_ADC_CHER : DWord absolute $FFFD8010; // ADC Channel Enable Register 336 AT91C_ADC_CHDR : DWord absolute $FFFD8014; // ADC Channel Disable Register 337 AT91C_ADC_CHSR : DWord absolute $FFFD8018; // ADC Channel Status Register 338 AT91C_ADC_SR : DWord absolute $FFFD801C; // ADC Status Register 339 AT91C_ADC_LCDR : DWord absolute $FFFD8020; // ADC Last Converted Data Register 340 AT91C_ADC_IER : DWord absolute $FFFD8024; // ADC Interrupt Enable Register 341 AT91C_ADC_IDR : DWord absolute $FFFD8028; // ADC Interrupt Disable Register 342 AT91C_ADC_IMR : DWord absolute $FFFD802C; // ADC Interrupt Mask Register 343 AT91C_ADC_CDR0 : DWord absolute $FFFD8030; // ADC Channel Data Register 0 344 AT91C_ADC_CDR1 : DWord absolute $FFFD8034; // ADC Channel Data Register 1 345 AT91C_ADC_CDR2 : DWord absolute $FFFD8038; // ADC Channel Data Register 2 346 AT91C_ADC_CDR3 : DWord absolute $FFFD803C; // ADC Channel Data Register 3 347 AT91C_ADC_CDR4 : DWord absolute $FFFD8040; // ADC Channel Data Register 4 348 AT91C_ADC_CDR5 : DWord absolute $FFFD8044; // ADC Channel Data Register 5 349 AT91C_ADC_CDR6 : DWord absolute $FFFD8048; // ADC Channel Data Register 6 350 AT91C_ADC_CDR7 : DWord absolute $FFFD804C; // ADC Channel Data Register 7 351 // ========== Register definition for PDC_ADC peripheral ========== 352 AT91C_ADC_RPR : DWord absolute $FFFD8100; // Receive Pointer Register 353 AT91C_ADC_RCR : DWord absolute $FFFD8104; // Receive Counter Register 354 AT91C_ADC_TPR : DWord absolute $FFFD8108; // Transmit Pointer Register 355 AT91C_ADC_TCR : DWord absolute $FFFD810C; // Transmit Counter Register 356 AT91C_ADC_RNPR : DWord absolute $FFFD8110; // Receive Next Pointer Register 357 AT91C_ADC_RNCR : DWord absolute $FFFD8114; // Receive Next Counter Register 358 AT91C_ADC_TNPR : DWord absolute $FFFD8118; // Transmit Next Pointer Register 359 AT91C_ADC_TNCR : DWord absolute $FFFD811C; // Transmit Next Counter Register 360 AT91C_ADC_PTCR : DWord absolute $FFFD8120; // PDC Transfer Control Register 361 AT91C_ADC_PTSR : DWord absolute $FFFD8124; // PDC Transfer Status Register 362 363 364 procedure lowlevelinit(LowLewelValues:TAT91C_Low_Lewel_Settings); 365 366 var 367 Undefined_Handler, 368 SWI_Handler, 369 Prefetch_Handler, 370 Abort_Handler, 371 IRQ_Handler, 372 FIQ_Handler : pointer; 373 374 implementation 375 376 377 procedure AT91F_Default_FIQ_handler; assembler; nostackframe; public name 'AT91F_Default_FIQ_handler'; 378 asm 379 .Lloop: 380 b .Lloop 381 end; 382 383 384 procedure AT91F_Default_IRQ_handler; assembler; nostackframe; public name 'AT91F_Default_IRQ_handler'; 385 asm 386 .Lloop: 387 b .Lloop 388 end; 389 390 391 procedure AT91F_Spurious_handler; assembler; nostackframe; public name 'AT91F_Spurious_handler'; 392 asm 393 .Lloop: 394 b .Lloop 395 end; 396 397 398 { Basic hardware initialization 399 400 Note: see page 5 - 6 of Atmel's 401 "Getting Started with AT91SAM7X Microcontrollers" for details.} 402 procedure lowlevelinit(LowLewelValues:TAT91C_Low_Lewel_Settings); 403 var 404 i : Longint; 405 begin 406 { Set Flash Wait state (AT91C_MC_FMR = MC Flash Mode Register)} 407 AT91C_MC_FMR := ((AT91C_MC_FMCN) and (50*$10000)) or AT91C_MC_FWS_1FWS; 408 409 { Watchdog Disable (AT91C_WDTC_WDMR = Watchdog Mode Register)} 410 AT91C_WDTC_WDMR := AT91C_WDTC_WDDIS; 411 412 {Enable the Main Oscillator (AT91C_PMC_MOR = Main Oscillator Register)} 413 AT91C_PMC_MOR := (( AT91C_CKGR_OSCOUNT and ($0800) or AT91C_CKGR_MOSCEN )); 414 415 { Wait the startup time (until PMC Status register MOSCEN bit is set) 416 result: $FFFFFC68 bit 0 will set when main oscillator has stabilized} 417 while (AT91C_PMC_SR and AT91C_PMC_MOSCS)=0 do 418 ; 419 420 421 { PMC Clock Generator PLL Register setup } 422 AT91C_PMC_PLLR :=((AT91C_CKGR_OUT_0) or 423 (AT91C_CKGR_DIV and LowLewelValues.osc_div_factor) or 424 (AT91C_CKGR_PLLCOUNT and (40 shl 10)) or 425 (AT91C_CKGR_MUL and (LowLewelValues.osc_mul_factor shl 16))); 426 427 { Wait the startup time (until PMC Status register LOCK bit is set) 428 result: 0xFFFFFC68 bit 2 will set when PLL has locked } 429 while (AT91C_PMC_SR and AT91C_PMC_LOCK)=0 do 430 ; 431 432 433 { PMC Master Clock Register setup (AT91C_PMC_MCKR = Master Clock Register)} 434 AT91C_PMC_MCKR := AT91C_PMC_PRES_CLK_2; 435 436 { Wait the startup time (until PMC Status register MCKRDY bit is set) 437 result: $FFFFFC68 bit 3 will set when Master Clock has stabilized } 438 439 while (AT91C_PMC_SR and AT91C_PMC_MCKRDY)=0 do 440 ; 441 442 {(AT91C_PMC_MCKR = Master Clock Register) } 443 AT91C_PMC_MCKR := AT91C_PMC_MCKR or AT91C_PMC_CSS_PLL_CLK; 444 445 { Wait the startup time (until PMC Status register MCKRDY bit is set) 446 result: $FFFFFC68 bit 3 will set when Master Clock has stabilized } 447 while (AT91C_PMC_SR and AT91C_PMC_MCKRDY)=0 do 448 ; 449 450 { Set up the default interrupts handler vectors } 451 AT91C_AIC_SVR[0]:=AT91_REG(@AT91F_Default_FIQ_handler); 452 453 for i:=1 to 30 do 454 AT91C_AIC_SVR[i]:=AT91_REG(@AT91F_Default_IRQ_handler); 455 456 AT91C_AIC_SPU:=AT91_REG(@AT91F_Spurious_handler); 457 end; 458 459 460 procedure PASCALMAIN; external name 'PASCALMAIN'; 461 462 procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc'; 463 asm 464 .Lhalt: 465 b .Lhalt 466 end; 467 468 var 469 _data: record end; external name '_data'; 470 _edata: record end; external name '_edata'; 471 _etext: record end; external name '_etext'; 472 _bss_start: record end; external name '_bss_start'; 473 _bss_end: record end; external name '_bss_end'; 474 _stack_top: record end; external name '_stack_top'; 475 476 procedure _FPC_start; assembler; nostackframe; 477 label 478 _start; 479 asm 480 .init 481 .align 16 482 .globl _start 483 b _start 484 b .LUndefined_Addr // Undefined Instruction vector 485 b .LSWI_Addr // Software Interrupt vector 486 b .LPrefetch_Addr // Prefetch abort vector 487 b .LAbort_Addr // Data abort vector 488 nop // reserved 489 b .LIRQ_Addr // Interrupt Request (IRQ) vector 490 b .LFIQ_Addr // Fast interrupt request (FIQ) vector 491 492 .LUndefined_Addr: 493 ldr r0,.L1 494 ldr pc,[r0] 495 .LSWI_Addr: 496 ldr r0,.L2 497 ldr pc,[r0] 498 .LPrefetch_Addr: 499 ldr r0,.L3 500 ldr pc,[r0] 501 .LAbort_Addr: 502 ldr r0,.L4 503 ldr pc,[r0] 504 .LIRQ_Addr: 505 ldr r0,.L5 506 ldr pc,[r0] 507 .LFIQ_Addr: 508 ldr r0,.L5 509 ldr pc,[r0] 510 511 .L1: 512 .long Undefined_Handler 513 .L2: 514 .long SWI_Handler 515 .L3: 516 .long Prefetch_Handler 517 .L4: 518 .long Abort_Handler 519 .L5: 520 .long IRQ_Handler 521 .L6: 522 .long FIQ_Handler 523 524 _start: 525 (* 526 Set absolute stack top 527 528 stack is already set by bootloader 529 but if this point is entered by any 530 other means than reset, the stack pointer 531 needs to be set explicity 532 *) 533 ldr r0,.L_stack_top 534 535 (* 536 Setting up SP for the different CPU modes. 537 Change mode before setting each one 538 move back again to Supervisor mode 539 Each interrupt has its own link 540 register, stack pointer and program 541 counter The stack pointers must be 542 initialized for interrupts to be 543 used later. 544 *) 545 msr cpsr_c, #0xdb // switch to Undefined Instruction Mode 546 mov sp, r0 547 sub r0, r0, #0x10 548 549 msr cpsr_c, #0xd7 // switch to Abort Mode 550 mov sp, r0 551 sub r0, r0, #0x10 552 553 msr CPSR_c, #0xd1 // switch to FIQ Mode 554 mov sp, r0 555 sub r0, r0, #0x80 556 557 msr CPSR_c, #0xd2 // switch to IRQ Mode 558 mov sp, r0 559 sub r0, r0, #0x80 560 561 msr CPSR_c, #0xd3 // switch to Supervisor Mode 562 mov sp, r0 563 sub r0, r0, #0x80 564 565 msr CPSR_c, #0x1f // switch to System Mode, interrupts enabled 566 mov sp, r0 567 568 // for now, all handlers are set to a default one 569 ldr r1,.LDefaultHandlerAddr 570 ldr r0,.L1 571 str r1,[r0] 572 ldr r0,.L2 573 str r1,[r0] 574 ldr r0,.L3 575 str r1,[r0] 576 ldr r0,.L4 577 str r1,[r0] 578 ldr r0,.L5 579 str r1,[r0] 580 ldr r0,.L6 581 str r1,[r0] 582 583 // copy initialized data from flash to ram 584 ldr r1,.L_etext 585 ldr r2,.L_data 586 ldr r3,.L_edata 587.Lcopyloop: 588 cmp r2,r3 589 ldrls r0,[r1],#4 590 strls r0,[r2],#4 591 bls .Lcopyloop 592 593 // clear onboard ram 594 ldr r1,.L_bss_start 595 ldr r2,.L_bss_end 596 mov r0,#0 597.Lzeroloop: 598 cmp r1,r2 599 strls r0,[r1],#4 600 bls .Lzeroloop 601 602 bl PASCALMAIN 603 bl _FPC_haltproc 604.L_bss_start: 605 .long _bss_start 606.L_bss_end: 607 .long _bss_end 608.L_etext: 609 .long _etext 610.L_data: 611 .long _data 612.L_edata: 613 .long _edata 614.L_stack_top: 615 .long _stack_top 616.LDefaultHandlerAddr: 617 .long .LDefaultHandler 618 // default irq handler just returns 619.LDefaultHandler: 620 mov pc,r14 621 .text 622 end; 623 624end. 625 626end. 627 628