1unit stm32f407xx; 2interface 3{$PACKRECORDS 2} 4{$GOTO ON} 5{$MODESWITCH ADVANCEDRECORDS} 6// * 7// ****************************************************************************** 8// * @file stm32f407xx.h 9// * @author MCD Application Team 10// * @version V2.4.0 11// * @date 14-August-2015 12// CMSIS STM32F407xx Device Peripheral Access Layer Header File. 13// * 14// * This file contains: 15// * - Data structures and the address mapping for all peripherals 16// * - Peripheral's registers declarations and bits definition 17// * - Macros to access peripheral�s registers hardware 18// * 19// ****************************************************************************** 20// * @attention 21// * 22// * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 23// * 24// * Redistribution and use in source and binary forms, with or without modification, 25// * are permitted provided that the following conditions are met: 26// * 1. Redistributions of source code must retain the above copyright notice, 27// * this list of conditions and the following disclaimer. 28// * 2. Redistributions in binary form must reproduce the above copyright notice, 29// * this list of conditions and the following disclaimer in the documentation 30// * and/or other materials provided with the distribution. 31// * 3. Neither the name of STMicroelectronics nor the names of its contributors 32// * may be used to endorse or promote products derived from this software 33// * without specific prior written permission. 34// * 35// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 36// * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37// * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 38// * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 39// * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40// * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 41// * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 42// * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 43// * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44// * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45// * 46// ****************************************************************************** 47// Configuration of the Cortex-M4 Processor and Core Peripherals 48// STM32F4XX Interrupt Number Definition, according to the selected device 49// * in @ref Library_configuration_section 50 51type 52 TIRQn_Enum = ( 53 NonMaskableInt_IRQn = -14, // 2 Non Maskable Interrupt 54 MemoryManagement_IRQn = -12, // 4 Cortex-M4 Memory Management Interrupt 55 BusFault_IRQn = -11, // 5 Cortex-M4 Bus Fault Interrupt 56 UsageFault_IRQn = -10, // 6 Cortex-M4 Usage Fault Interrupt 57 SVCall_IRQn = -5, // 11 Cortex-M4 SV Call Interrupt 58 DebugMonitor_IRQn = -4, // 12 Cortex-M4 Debug Monitor Interrupt 59 PendSV_IRQn = -2, // 14 Cortex-M4 Pend SV Interrupt 60 SysTick_IRQn = -1, // 15 Cortex-M4 System Tick Interrupt 61 WWDG_IRQn = 0, // Window WatchDog Interrupt 62 PVD_IRQn = 1, // PVD through EXTI Line detection Interrupt 63 TAMP_STAMP_IRQn = 2, // Tamper and TimeStamp interrupts through the EXTI line 64 RTC_WKUP_IRQn = 3, // RTC Wakeup interrupt through the EXTI line 65 FLASH_IRQn = 4, // FLASH global Interrupt 66 RCC_IRQn = 5, // RCC global Interrupt 67 EXTI0_IRQn = 6, // EXTI Line0 Interrupt 68 EXTI1_IRQn = 7, // EXTI Line1 Interrupt 69 EXTI2_IRQn = 8, // EXTI Line2 Interrupt 70 EXTI3_IRQn = 9, // EXTI Line3 Interrupt 71 EXTI4_IRQn = 10, // EXTI Line4 Interrupt 72 DMA1_Stream0_IRQn = 11, // DMA1 Stream 0 global Interrupt 73 DMA1_Stream1_IRQn = 12, // DMA1 Stream 1 global Interrupt 74 DMA1_Stream2_IRQn = 13, // DMA1 Stream 2 global Interrupt 75 DMA1_Stream3_IRQn = 14, // DMA1 Stream 3 global Interrupt 76 DMA1_Stream4_IRQn = 15, // DMA1 Stream 4 global Interrupt 77 DMA1_Stream5_IRQn = 16, // DMA1 Stream 5 global Interrupt 78 DMA1_Stream6_IRQn = 17, // DMA1 Stream 6 global Interrupt 79 ADC_IRQn = 18, // ADC1, ADC2 and ADC3 global Interrupts 80 CAN1_TX_IRQn = 19, // CAN1 TX Interrupt 81 CAN1_RX0_IRQn = 20, // CAN1 RX0 Interrupt 82 CAN1_RX1_IRQn = 21, // CAN1 RX1 Interrupt 83 CAN1_SCE_IRQn = 22, // CAN1 SCE Interrupt 84 EXTI9_5_IRQn = 23, // External Line[9:5] Interrupts 85 TIM1_BRK_TIM9_IRQn = 24, // TIM1 Break interrupt and TIM9 global interrupt 86 TIM1_UP_TIM10_IRQn = 25, // TIM1 Update Interrupt and TIM10 global interrupt 87 TIM1_TRG_COM_TIM11_IRQn = 26, // TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt 88 TIM1_CC_IRQn = 27, // TIM1 Capture Compare Interrupt 89 TIM2_IRQn = 28, // TIM2 global Interrupt 90 TIM3_IRQn = 29, // TIM3 global Interrupt 91 TIM4_IRQn = 30, // TIM4 global Interrupt 92 I2C1_EV_IRQn = 31, // I2C1 Event Interrupt 93 I2C1_ER_IRQn = 32, // I2C1 Error Interrupt 94 I2C2_EV_IRQn = 33, // I2C2 Event Interrupt 95 I2C2_ER_IRQn = 34, // I2C2 Error Interrupt 96 SPI1_IRQn = 35, // SPI1 global Interrupt 97 SPI2_IRQn = 36, // SPI2 global Interrupt 98 USART1_IRQn = 37, // USART1 global Interrupt 99 USART2_IRQn = 38, // USART2 global Interrupt 100 USART3_IRQn = 39, // USART3 global Interrupt 101 EXTI15_10_IRQn = 40, // External Line[15:10] Interrupts 102 RTC_Alarm_IRQn = 41, // RTC Alarm (A and B) through EXTI Line Interrupt 103 OTG_FS_WKUP_IRQn = 42, // USB OTG FS Wakeup through EXTI line interrupt 104 TIM8_BRK_TIM12_IRQn = 43, // TIM8 Break Interrupt and TIM12 global interrupt 105 TIM8_UP_TIM13_IRQn = 44, // TIM8 Update Interrupt and TIM13 global interrupt 106 TIM8_TRG_COM_TIM14_IRQn = 45, // TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt 107 TIM8_CC_IRQn = 46, // TIM8 Capture Compare Interrupt 108 DMA1_Stream7_IRQn = 47, // DMA1 Stream7 Interrupt 109 FSMC_IRQn = 48, // FSMC global Interrupt 110 SDIO_IRQn = 49, // SDIO global Interrupt 111 TIM5_IRQn = 50, // TIM5 global Interrupt 112 SPI3_IRQn = 51, // SPI3 global Interrupt 113 UART4_IRQn = 52, // UART4 global Interrupt 114 UART5_IRQn = 53, // UART5 global Interrupt 115 TIM6_DAC_IRQn = 54, // TIM6 global and DAC1&2 underrun error interrupts 116 TIM7_IRQn = 55, // TIM7 global interrupt 117 DMA2_Stream0_IRQn = 56, // DMA2 Stream 0 global Interrupt 118 DMA2_Stream1_IRQn = 57, // DMA2 Stream 1 global Interrupt 119 DMA2_Stream2_IRQn = 58, // DMA2 Stream 2 global Interrupt 120 DMA2_Stream3_IRQn = 59, // DMA2 Stream 3 global Interrupt 121 DMA2_Stream4_IRQn = 60, // DMA2 Stream 4 global Interrupt 122 ETH_IRQn = 61, // Ethernet global Interrupt 123 ETH_WKUP_IRQn = 62, // Ethernet Wakeup through EXTI line Interrupt 124 CAN2_TX_IRQn = 63, // CAN2 TX Interrupt 125 CAN2_RX0_IRQn = 64, // CAN2 RX0 Interrupt 126 CAN2_RX1_IRQn = 65, // CAN2 RX1 Interrupt 127 CAN2_SCE_IRQn = 66, // CAN2 SCE Interrupt 128 OTG_FS_IRQn = 67, // USB OTG FS global Interrupt 129 DMA2_Stream5_IRQn = 68, // DMA2 Stream 5 global interrupt 130 DMA2_Stream6_IRQn = 69, // DMA2 Stream 6 global interrupt 131 DMA2_Stream7_IRQn = 70, // DMA2 Stream 7 global interrupt 132 USART6_IRQn = 71, // USART6 global interrupt 133 I2C3_EV_IRQn = 72, // I2C3 event interrupt 134 I2C3_ER_IRQn = 73, // I2C3 error interrupt 135 OTG_HS_EP1_OUT_IRQn = 74, // USB OTG HS End Point 1 Out global interrupt 136 OTG_HS_EP1_IN_IRQn = 75, // USB OTG HS End Point 1 In global interrupt 137 OTG_HS_WKUP_IRQn = 76, // USB OTG HS Wakeup through EXTI interrupt 138 OTG_HS_IRQn = 77, // USB OTG HS global interrupt 139 DCMI_IRQn = 78, // DCMI global interrupt 140 HASH_RNG_IRQn = 80, // Hash and RNG global interrupt 141 FPU_IRQn = 81 // FPU global interrupt 142 ); 143 144 TADC_Registers = record 145 SR : longword; // ADC status register 146 CR1 : longword; // ADC control register 1 147 CR2 : longword; // ADC control register 2 148 SMPR1 : longword; // ADC sample time register 1 149 SMPR2 : longword; // ADC sample time register 2 150 JOFR1 : longword; // ADC injected channel data offset register 1 151 JOFR2 : longword; // ADC injected channel data offset register 2 152 JOFR3 : longword; // ADC injected channel data offset register 3 153 JOFR4 : longword; // ADC injected channel data offset register 4 154 HTR : longword; // ADC watchdog higher threshold register 155 LTR : longword; // ADC watchdog lower threshold register 156 SQR1 : longword; // ADC regular sequence register 1 157 SQR2 : longword; // ADC regular sequence register 2 158 SQR3 : longword; // ADC regular sequence register 3 159 JSQR : longword; // ADC injected sequence register 160 JDR1 : longword; // ADC injected data register 1 161 JDR2 : longword; // ADC injected data register 2 162 JDR3 : longword; // ADC injected data register 3 163 JDR4 : longword; // ADC injected data register 4 164 DR : longword; // ADC regular data register 165 end; 166 167 TADC_COMMON_Registers = record 168 CSR : longword; // ADC Common status register 169 CCR : longword; // ADC common control register 170 CDR : longword; // ADC common regular data register for dual 171 end; 172 173 TCAN_TXMAILBOX_Registers = record 174 TIR : longword; // CAN TX mailbox identifier register 175 TDTR : longword; // CAN mailbox data length control and time stamp register 176 TDLR : longword; // CAN mailbox data low register 177 TDHR : longword; // CAN mailbox data high register 178 end; 179 180 TCAN_FIFOMAILBOX_Registers = record 181 RIR : longword; // CAN receive FIFO mailbox identifier register 182 RDTR : longword; // CAN receive FIFO mailbox data length control and time stamp register 183 RDLR : longword; // CAN receive FIFO mailbox data low register 184 RDHR : longword; // CAN receive FIFO mailbox data high register 185 end; 186 187 TCAN_FILTERREGISTER_Registers = record 188 FR1 : longword; // CAN Filter bank register 1 189 FR2 : longword; // CAN Filter bank register 1 190 end; 191 192 TCAN_Registers = record 193 MCR : longword; // CAN master control register 194 MSR : longword; // CAN master status register 195 TSR : longword; // CAN transmit status register 196 RF0R : longword; // CAN receive FIFO 0 register 197 RF1R : longword; // CAN receive FIFO 1 register 198 IER : longword; // CAN interrupt enable register 199 ESR : longword; // CAN error status register 200 BTR : longword; // CAN bit timing register 201 RESERVED0 : array[0..87] of longword; // Reserved, 0x020 - 0x17F 202 sTxMailBox : array[0..2] of TCAN_TXMAILBOX_Registers; // CAN Tx MailBox 203 sFIFOMailBox : array[0..1] of TCAN_FIFOMAILBOX_Registers; // CAN FIFO MailBox 204 RESERVED1 : array[0..11] of longword; // Reserved, 0x1D0 - 0x1FF 205 FMR : longword; // CAN filter master register 206 FM1R : longword; // CAN filter mode register 207 RESERVED2 : longword; // Reserved, 0x208 208 FS1R : longword; // CAN filter scale register 209 RESERVED3 : longword; // Reserved, 0x210 210 FFA1R : longword; // CAN filter FIFO assignment register 211 RESERVED4 : longword; // Reserved, 0x218 212 FA1R : longword; // CAN filter activation register 213 RESERVED5 : array[0..7] of longword; // Reserved, 0x220-0x23F 214 sFilterRegister : array[0..27] of TCAN_FILTERREGISTER_Registers; // CAN Filter Register 215 end; 216 217 TCRC_Registers = record 218 DR : longword; // CRC Data register 219 IDR : byte; // CRC Independent data register 220 RESERVED0 : byte; // Reserved, 0x05 221 RESERVED1 : word; // Reserved, 0x06 222 CR : longword; // CRC Control register 223 end; 224 225 TDAC_Registers = record 226 CR : longword; // DAC control register 227 SWTRIGR : longword; // DAC software trigger register 228 DHR12R1 : longword; // DAC channel1 12-bit right-aligned data holding register 229 DHR12L1 : longword; // DAC channel1 12-bit left aligned data holding register 230 DHR8R1 : longword; // DAC channel1 8-bit right aligned data holding register 231 DHR12R2 : longword; // DAC channel2 12-bit right aligned data holding register 232 DHR12L2 : longword; // DAC channel2 12-bit left aligned data holding register 233 DHR8R2 : longword; // DAC channel2 8-bit right-aligned data holding register 234 DHR12RD : longword; // Dual DAC 12-bit right-aligned data holding register 235 DHR12LD : longword; // DUAL DAC 12-bit left aligned data holding register 236 DHR8RD : longword; // DUAL DAC 8-bit right aligned data holding register 237 DOR1 : longword; // DAC channel1 data output register 238 DOR2 : longword; // DAC channel2 data output register 239 SR : longword; // DAC status register 240 end; 241 242 TDBGMCU_Registers = record 243 IDCODE : longword; // MCU device ID code 244 CR : longword; // Debug MCU configuration register 245 APB1FZ : longword; // Debug MCU APB1 freeze register 246 APB2FZ : longword; // Debug MCU APB2 freeze register 247 end; 248 249 TDCMI_Registers = record 250 CR : longword; // DCMI control register 1 251 SR : longword; // DCMI status register 252 RISR : longword; // DCMI raw interrupt status register 253 IER : longword; // DCMI interrupt enable register 254 MISR : longword; // DCMI masked interrupt status register 255 ICR : longword; // DCMI interrupt clear register 256 ESCR : longword; // DCMI embedded synchronization code register 257 ESUR : longword; // DCMI embedded synchronization unmask register 258 CWSTRTR : longword; // DCMI crop window start 259 CWSIZER : longword; // DCMI crop window size 260 DR : longword; // DCMI data register 261 end; 262 263 TDMA_STREAM_Registers = record 264 CR : longword; // DMA stream x configuration register 265 NDTR : longword; // DMA stream x number of data register 266 PAR : longword; // DMA stream x peripheral address register 267 M0AR : longword; // DMA stream x memory 0 address register 268 M1AR : longword; // DMA stream x memory 1 address register 269 FCR : longword; // DMA stream x FIFO control register 270 end; 271 272 TDMA_Registers = record 273 LISR : longword; // DMA low interrupt status register 274 HISR : longword; // DMA high interrupt status register 275 LIFCR : longword; // DMA low interrupt flag clear register 276 HIFCR : longword; // DMA high interrupt flag clear register 277 end; 278 279 TETH_Registers = record 280 MACCR : longword; 281 MACFFR : longword; 282 MACHTHR : longword; 283 MACHTLR : longword; 284 MACMIIAR : longword; 285 MACMIIDR : longword; 286 MACFCR : longword; 287 MACVLANTR : longword; // 8 288 RESERVED0 : array[0..1] of longword; 289 MACRWUFFR : longword; // 11 290 MACPMTCSR : longword; 291 RESERVED1 : array[0..1] of longword; 292 MACSR : longword; // 15 293 MACIMR : longword; 294 MACA0HR : longword; 295 MACA0LR : longword; 296 MACA1HR : longword; 297 MACA1LR : longword; 298 MACA2HR : longword; 299 MACA2LR : longword; 300 MACA3HR : longword; 301 MACA3LR : longword; // 24 302 RESERVED2 : array[0..39] of longword; 303 MMCCR : longword; // 65 304 MMCRIR : longword; 305 MMCTIR : longword; 306 MMCRIMR : longword; 307 MMCTIMR : longword; // 69 308 RESERVED3 : array[0..13] of longword; 309 MMCTGFSCCR : longword; // 84 310 MMCTGFMSCCR : longword; 311 RESERVED4 : array[0..4] of longword; 312 MMCTGFCR : longword; 313 RESERVED5 : array[0..9] of longword; 314 MMCRFCECR : longword; 315 MMCRFAECR : longword; 316 RESERVED6 : array[0..9] of longword; 317 MMCRGUFCR : longword; 318 RESERVED7 : array[0..333] of longword; 319 PTPTSCR : longword; 320 PTPSSIR : longword; 321 PTPTSHR : longword; 322 PTPTSLR : longword; 323 PTPTSHUR : longword; 324 PTPTSLUR : longword; 325 PTPTSAR : longword; 326 PTPTTHR : longword; 327 PTPTTLR : longword; 328 RESERVED8 : longword; 329 PTPTSSR : longword; 330 RESERVED9 : array[0..564] of longword; 331 DMABMR : longword; 332 DMATPDR : longword; 333 DMARPDR : longword; 334 DMARDLAR : longword; 335 DMATDLAR : longword; 336 DMASR : longword; 337 DMAOMR : longword; 338 DMAIER : longword; 339 DMAMFBOCR : longword; 340 DMARSWTR : longword; 341 RESERVED10 : array[0..7] of longword; 342 DMACHTDR : longword; 343 DMACHRDR : longword; 344 DMACHTBAR : longword; 345 DMACHRBAR : longword; 346 end; 347 348 TEXTI_Registers = record 349 IMR : longword; // EXTI Interrupt mask register 350 EMR : longword; // EXTI Event mask register 351 RTSR : longword; // EXTI Rising trigger selection register 352 FTSR : longword; // EXTI Falling trigger selection register 353 SWIER : longword; // EXTI Software interrupt event register 354 PR : longword; // EXTI Pending register 355 end; 356 357 TFLASH_Registers = record 358 ACR : longword; // FLASH access control register 359 KEYR : longword; // FLASH key register 360 OPTKEYR : longword; // FLASH option key register 361 SR : longword; // FLASH status register 362 CR : longword; // FLASH control register 363 OPTCR : longword; // FLASH option control register 364 OPTCR1 : longword; // FLASH option control register 1 365 end; 366 367 TFSMC_BANK1_Registers = record 368 BTCR : array[0..7] of longword; // NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 369 end; 370 371 TFSMC_BANK1E_Registers = record 372 BWTR : array[0..6] of longword; // NOR/PSRAM write timing registers 373 end; 374 375 TFSMC_BANK2_3_Registers = record 376 PCR2 : longword; // NAND Flash control register 2 377 SR2 : longword; // NAND Flash FIFO status and interrupt register 2 378 PMEM2 : longword; // NAND Flash Common memory space timing register 2 379 PATT2 : longword; // NAND Flash Attribute memory space timing register 2 380 RESERVED0 : longword; // Reserved, 0x70 381 ECCR2 : longword; // NAND Flash ECC result registers 2 382 RESERVED1 : longword; // Reserved, 0x78 383 RESERVED2 : longword; // Reserved, 0x7C 384 PCR3 : longword; // NAND Flash control register 3 385 SR3 : longword; // NAND Flash FIFO status and interrupt register 3 386 PMEM3 : longword; // NAND Flash Common memory space timing register 3 387 PATT3 : longword; // NAND Flash Attribute memory space timing register 3 388 RESERVED3 : longword; // Reserved, 0x90 389 ECCR3 : longword; // NAND Flash ECC result registers 3 390 end; 391 392 TFSMC_BANK4_Registers = record 393 PCR4 : longword; // PC Card control register 4 394 SR4 : longword; // PC Card FIFO status and interrupt register 4 395 PMEM4 : longword; // PC Card Common memory space timing register 4 396 PATT4 : longword; // PC Card Attribute memory space timing register 4 397 PIO4 : longword; // PC Card I/O space timing register 4 398 end; 399 400 TGPIO_Registers = record 401 MODER : longword; // GPIO port mode register 402 OTYPER : longword; // GPIO port output type register 403 OSPEEDR : longword; // GPIO port output speed register 404 PUPDR : longword; // GPIO port pull-up/pull-down register 405 IDR : longword; // GPIO port input data register 406 ODR : longword; // GPIO port output data register 407 BSRR : longword; // GPIO port bit set/reset register 408 LCKR : longword; // GPIO port configuration lock register 409 AFR : array[0..1] of longword; // GPIO alternate function registers 410 end; 411 412 TSYSCFG_Registers = record 413 MEMRMP : longword; // SYSCFG memory remap register 414 PMC : longword; // SYSCFG peripheral mode configuration register 415 EXTICR : array[0..3] of longword; // SYSCFG external interrupt configuration registers 416 RESERVED : array[0..1] of longword; // Reserved, 0x18-0x1C 417 CMPCR : longword; // SYSCFG Compensation cell control register 418 end; 419 420 TI2C_Registers = record 421 CR1 : longword; // I2C Control register 1 422 CR2 : longword; // I2C Control register 2 423 OAR1 : longword; // I2C Own address register 1 424 OAR2 : longword; // I2C Own address register 2 425 DR : longword; // I2C Data register 426 SR1 : longword; // I2C Status register 1 427 SR2 : longword; // I2C Status register 2 428 CCR : longword; // I2C Clock control register 429 TRISE : longword; // I2C TRISE register 430 FLTR : longword; // I2C FLTR register 431 end; 432 433 TIWDG_Registers = record 434 KR : longword; // IWDG Key register 435 PR : longword; // IWDG Prescaler register 436 RLR : longword; // IWDG Reload register 437 SR : longword; // IWDG Status register 438 end; 439 440 TPWR_Registers = record 441 CR : longword; // PWR power control register 442 CSR : longword; // PWR power control/status register 443 end; 444 445 TRCC_Registers = record 446 CR : longword; // RCC clock control register 447 PLLCFGR : longword; // RCC PLL configuration register 448 CFGR : longword; // RCC clock configuration register 449 CIR : longword; // RCC clock interrupt register 450 AHB1RSTR : longword; // RCC AHB1 peripheral reset register 451 AHB2RSTR : longword; // RCC AHB2 peripheral reset register 452 AHB3RSTR : longword; // RCC AHB3 peripheral reset register 453 RESERVED0 : longword; // Reserved, 0x1C 454 APB1RSTR : longword; // RCC APB1 peripheral reset register 455 APB2RSTR : longword; // RCC APB2 peripheral reset register 456 RESERVED1 : array[0..1] of longword; // Reserved, 0x28-0x2C 457 AHB1ENR : longword; // RCC AHB1 peripheral clock register 458 AHB2ENR : longword; // RCC AHB2 peripheral clock register 459 AHB3ENR : longword; // RCC AHB3 peripheral clock register 460 RESERVED2 : longword; // Reserved, 0x3C 461 APB1ENR : longword; // RCC APB1 peripheral clock enable register 462 APB2ENR : longword; // RCC APB2 peripheral clock enable register 463 RESERVED3 : array[0..1] of longword; // Reserved, 0x48-0x4C 464 AHB1LPENR : longword; // RCC AHB1 peripheral clock enable in low power mode register 465 AHB2LPENR : longword; // RCC AHB2 peripheral clock enable in low power mode register 466 AHB3LPENR : longword; // RCC AHB3 peripheral clock enable in low power mode register 467 RESERVED4 : longword; // Reserved, 0x5C 468 APB1LPENR : longword; // RCC APB1 peripheral clock enable in low power mode register 469 APB2LPENR : longword; // RCC APB2 peripheral clock enable in low power mode register 470 RESERVED5 : array[0..1] of longword; // Reserved, 0x68-0x6C 471 BDCR : longword; // RCC Backup domain control register 472 CSR : longword; // RCC clock control & status register 473 RESERVED6 : array[0..1] of longword; // Reserved, 0x78-0x7C 474 SSCGR : longword; // RCC spread spectrum clock generation register 475 PLLI2SCFGR : longword; // RCC PLLI2S configuration register 476 RESERVED7 : longword; // Reserved, 0x88 477 DCKCFGR : longWord; // RCC Dedicated Clocks Configuration Register 478 end; 479 480 TRTC_Registers = record 481 TR : longword; // RTC time register 482 DR : longword; // RTC date register 483 CR : longword; // RTC control register 484 ISR : longword; // RTC initialization and status register 485 PRER : longword; // RTC prescaler register 486 WUTR : longword; // RTC wakeup timer register 487 CALIBR : longword; // RTC calibration register 488 ALRMAR : longword; // RTC alarm A register 489 ALRMBR : longword; // RTC alarm B register 490 WPR : longword; // RTC write protection register 491 SSR : longword; // RTC sub second register 492 SHIFTR : longword; // RTC shift control register 493 TSTR : longword; // RTC time stamp time register 494 TSDR : longword; // RTC time stamp date register 495 TSSSR : longword; // RTC time-stamp sub second register 496 CALR : longword; // RTC calibration register 497 TAFCR : longword; // RTC tamper and alternate function configuration register 498 ALRMASSR : longword; // RTC alarm A sub second register 499 ALRMBSSR : longword; // RTC alarm B sub second register 500 RESERVED7 : longword; // Reserved, 0x4C 501 BKP0R : longword; // RTC backup register 1 502 BKP1R : longword; // RTC backup register 1 503 BKP2R : longword; // RTC backup register 2 504 BKP3R : longword; // RTC backup register 3 505 BKP4R : longword; // RTC backup register 4 506 BKP5R : longword; // RTC backup register 5 507 BKP6R : longword; // RTC backup register 6 508 BKP7R : longword; // RTC backup register 7 509 BKP8R : longword; // RTC backup register 8 510 BKP9R : longword; // RTC backup register 9 511 BKP10R : longword; // RTC backup register 10 512 BKP11R : longword; // RTC backup register 11 513 BKP12R : longword; // RTC backup register 12 514 BKP13R : longword; // RTC backup register 13 515 BKP14R : longword; // RTC backup register 14 516 BKP15R : longword; // RTC backup register 15 517 BKP16R : longword; // RTC backup register 16 518 BKP17R : longword; // RTC backup register 17 519 BKP18R : longword; // RTC backup register 18 520 BKP19R : longword; // RTC backup register 19 521 end; 522 523 TSDIO_Registers = record 524 POWER : longword; // SDIO power control register 525 CLKCR : longword; // SDI clock control register 526 ARG : longword; // SDIO argument register 527 CMD : longword; // SDIO command register 528 RESPCMD : longword; // SDIO command response register 529 RESP1 : longword; // SDIO response 1 register 530 RESP2 : longword; // SDIO response 2 register 531 RESP3 : longword; // SDIO response 3 register 532 RESP4 : longword; // SDIO response 4 register 533 DTIMER : longword; // SDIO data timer register 534 DLEN : longword; // SDIO data length register 535 DCTRL : longword; // SDIO data control register 536 DCOUNT : longword; // SDIO data counter register 537 STA : longword; // SDIO status register 538 ICR : longword; // SDIO interrupt clear register 539 MASK : longword; // SDIO mask register 540 RESERVED0 : array[0..1] of longword; // Reserved, 0x40-0x44 541 FIFOCNT : longword; // SDIO FIFO counter register 542 RESERVED1 : array[0..12] of longword; // Reserved, 0x4C-0x7C 543 FIFO : longword; // SDIO data FIFO register 544 end; 545 546 TSPI_Registers = record 547 CR1 : longword; // SPI control register 1 (not used in I2S mode) 548 CR2 : longword; // SPI control register 2 549 SR : longword; // SPI status register 550 DR : longword; // SPI data register 551 CRCPR : longword; // SPI CRC polynomial register (not used in I2S mode) 552 RXCRCR : longword; // SPI RX CRC register (not used in I2S mode) 553 TXCRCR : longword; // SPI TX CRC register (not used in I2S mode) 554 I2SCFGR : longword; // SPI_I2S configuration register 555 I2SPR : longword; // SPI_I2S prescaler register 556 end; 557 558 TTIM_Registers = record 559 CR1 : longword; // TIM control register 1 560 CR2 : longword; // TIM control register 2 561 SMCR : longword; // TIM slave mode control register 562 DIER : longword; // TIM DMA/interrupt enable register 563 SR : longword; // TIM status register 564 EGR : longword; // TIM event generation register 565 CCMR1 : longword; // TIM capture/compare mode register 1 566 CCMR2 : longword; // TIM capture/compare mode register 2 567 CCER : longword; // TIM capture/compare enable register 568 CNT : longword; // TIM counter register 569 PSC : longword; // TIM prescaler 570 ARR : longword; // TIM auto-reload register 571 RCR : longword; // TIM repetition counter register 572 CCR1 : longword; // TIM capture/compare register 1 573 CCR2 : longword; // TIM capture/compare register 2 574 CCR3 : longword; // TIM capture/compare register 3 575 CCR4 : longword; // TIM capture/compare register 4 576 BDTR : longword; // TIM break and dead-time register 577 DCR : longword; // TIM DMA control register 578 DMAR : longword; // TIM DMA address for full transfer 579 &OR : longword; // TIM option register 580 end; 581 582 TUSART_Registers = record 583 SR : longword; // USART Status register 584 DR : longword; // USART Data register 585 BRR : longword; // USART Baud rate register 586 CR1 : longword; // USART Control register 1 587 CR2 : longword; // USART Control register 2 588 CR3 : longword; // USART Control register 3 589 GTPR : longword; // USART Guard time and prescaler register 590 end; 591 592 TWWDG_Registers = record 593 CR : longword; // WWDG Control register 594 CFR : longword; // WWDG Configuration register 595 SR : longword; // WWDG Status register 596 end; 597 598 TRNG_Registers = record 599 CR : longword; // RNG control register 600 SR : longword; // RNG status register 601 DR : longword; // RNG data register 602 end; 603 604 TUSB_OTG_GLOBAL_Registers = record 605 GOTGCTL : longword; // USB_OTG Control and Status Register 000h 606 GOTGINT : longword; // USB_OTG Interrupt Register 004h 607 GAHBCFG : longword; // Core AHB Configuration Register 008h 608 GUSBCFG : longword; // Core USB Configuration Register 00Ch 609 GRSTCTL : longword; // Core Reset Register 010h 610 GINTSTS : longword; // Core Interrupt Register 014h 611 GINTMSK : longword; // Core Interrupt Mask Register 018h 612 GRXSTSR : longword; // Receive Sts Q Read Register 01Ch 613 GRXSTSP : longword; // Receive Sts Q Read & POP Register 020h 614 GRXFSIZ : longword; // Receive FIFO Size Register 024h 615 DIEPTXF0_HNPTXFSIZ : longword; // EP0 / Non Periodic Tx FIFO Size Register 028h 616 HNPTXSTS : longword; // Non Periodic Tx FIFO/Queue Sts reg 02Ch 617 RESERVED30 : array[0..1] of longword; // Reserved 030h 618 GCCFG : longword; // General Purpose IO Register 038h 619 CID : longword; // User ID Register 03Ch 620 RESERVED40 : array[0..47] of longword; // Reserved 040h-0FFh 621 HPTXFSIZ : longword; // Host Periodic Tx FIFO Size Reg 100h 622 DIEPTXF : array[0..14] of longword; // dev Periodic Transmit FIFO 623 end; 624 625 TUSB_OTG_DEVICE_Registers = record 626 DCFG : longword; // dev Configuration Register 800h 627 DCTL : longword; // dev Control Register 804h 628 DSTS : longword; // dev Status Register (RO) 808h 629 RESERVED0C : longword; // Reserved 80Ch 630 DIEPMSK : longword; // dev IN Endpoint Mask 810h 631 DOEPMSK : longword; // dev OUT Endpoint Mask 814h 632 DAINT : longword; // dev All Endpoints Itr Reg 818h 633 DAINTMSK : longword; // dev All Endpoints Itr Mask 81Ch 634 RESERVED20 : longword; // Reserved 820h 635 RESERVED9 : longword; // Reserved 824h 636 DVBUSDIS : longword; // dev VBUS discharge Register 828h 637 DVBUSPULSE : longword; // dev VBUS Pulse Register 82Ch 638 DTHRCTL : longword; // dev thr 830h 639 DIEPEMPMSK : longword; // dev empty msk 834h 640 DEACHINT : longword; // dedicated EP interrupt 838h 641 DEACHMSK : longword; // dedicated EP msk 83Ch 642 RESERVED40 : longword; // dedicated EP mask 840h 643 DINEP1MSK : longword; // dedicated EP mask 844h 644 RESERVED44 : array[0..14] of longword; // Reserved 844-87Ch 645 DOUTEP1MSK : longword; // dedicated EP msk 884h 646 end; 647 648 TUSB_OTG_INENDPOINT_Registers = record 649 DIEPCTL : longword; // dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h 650 RESERVED04 : longword; // Reserved 900h + (ep_num * 20h) + 04h 651 DIEPINT : longword; // dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h 652 RESERVED0C : longword; // Reserved 900h + (ep_num * 20h) + 0Ch 653 DIEPTSIZ : longword; // IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h 654 DIEPDMA : longword; // IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h 655 DTXFSTS : longword; // IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h 656 RESERVED18 : longword; // Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch 657 end; 658 659 TUSB_OTG_OUTENDPOINT_Registers = record 660 DOEPCTL : longword; // dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h 661 RESERVED04 : longword; // Reserved B00h + (ep_num * 20h) + 04h 662 DOEPINT : longword; // dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h 663 RESERVED0C : longword; // Reserved B00h + (ep_num * 20h) + 0Ch 664 DOEPTSIZ : longword; // dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h 665 DOEPDMA : longword; // dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h 666 RESERVED18 : array[0..1] of longword; // Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch 667 end; 668 669 TUSB_OTG_HOST_Registers = record 670 HCFG : longword; // Host Configuration Register 400h 671 HFIR : longword; // Host Frame Interval Register 404h 672 HFNUM : longword; // Host Frame Nbr/Frame Remaining 408h 673 RESERVED40C : longword; // Reserved 40Ch 674 HPTXSTS : longword; // Host Periodic Tx FIFO/ Queue Status 410h 675 HAINT : longword; // Host All Channels Interrupt Register 414h 676 HAINTMSK : longword; // Host All Channels Interrupt Mask 418h 677 end; 678 679 TUSB_OTG_HOSTCHANNEL_Registers = record 680 HCCHAR : longword; 681 HCSPLT : longword; 682 HCINT : longword; 683 HCINTMSK : longword; 684 HCTSIZ : longword; 685 HCDMA : longword; 686 RESERVED : array[0..1] of longword; 687 end; 688 689const 690 FLASH_BASE = $08000000; // FLASH(up to 1 MB) base address in the alias region 691 CCMDATARAM_BASE = $10000000; // CCM(core coupled memory) data RAM(64 KB) base address in the alias region 692 SRAM1_BASE = $20000000; // SRAM1(112 KB) base address in the alias region 693 SRAM2_BASE = $2001C000; // SRAM2(16 KB) base address in the alias region 694 PERIPH_BASE = $40000000; // Peripheral base address in the alias region 695 BKPSRAM_BASE = $40024000; // Backup SRAM(4 KB) base address in the alias region 696 FSMC_R_BASE = $A0000000; // FSMC registers base address 697 SRAM1_BB_BASE = $22000000; // SRAM1(112 KB) base address in the bit-band region 698 SRAM2_BB_BASE = $22380000; // SRAM2(16 KB) base address in the bit-band region 699 PERIPH_BB_BASE = $42000000; // Peripheral base address in the bit-band region 700 BKPSRAM_BB_BASE = $42480000; // Backup SRAM(4 KB) base address in the bit-band region 701 SRAM_BASE = $20000000; 702 SRAM_BB_BASE = $22000000; 703 APB1PERIPH_BASE = $40000000; 704 APB2PERIPH_BASE = PERIPH_BASE + $00010000; 705 AHB1PERIPH_BASE = PERIPH_BASE + $00020000; 706 AHB2PERIPH_BASE = PERIPH_BASE + $10000000; 707 TIM2_BASE = APB1PERIPH_BASE + $0000; 708 TIM3_BASE = APB1PERIPH_BASE + $0400; 709 TIM4_BASE = APB1PERIPH_BASE + $0800; 710 TIM5_BASE = APB1PERIPH_BASE + $0C00; 711 TIM6_BASE = APB1PERIPH_BASE + $1000; 712 TIM7_BASE = APB1PERIPH_BASE + $1400; 713 TIM12_BASE = APB1PERIPH_BASE + $1800; 714 TIM13_BASE = APB1PERIPH_BASE + $1C00; 715 TIM14_BASE = APB1PERIPH_BASE + $2000; 716 RTC_BASE = APB1PERIPH_BASE + $2800; 717 WWDG_BASE = APB1PERIPH_BASE + $2C00; 718 IWDG_BASE = APB1PERIPH_BASE + $3000; 719 I2S2ext_BASE = APB1PERIPH_BASE + $3400; 720 SPI2_BASE = APB1PERIPH_BASE + $3800; 721 SPI3_BASE = APB1PERIPH_BASE + $3C00; 722 I2S3ext_BASE = APB1PERIPH_BASE + $4000; 723 USART2_BASE = APB1PERIPH_BASE + $4400; 724 USART3_BASE = APB1PERIPH_BASE + $4800; 725 UART4_BASE = APB1PERIPH_BASE + $4C00; 726 UART5_BASE = APB1PERIPH_BASE + $5000; 727 I2C1_BASE = APB1PERIPH_BASE + $5400; 728 I2C2_BASE = APB1PERIPH_BASE + $5800; 729 I2C3_BASE = APB1PERIPH_BASE + $5C00; 730 CAN1_BASE = APB1PERIPH_BASE + $6400; 731 CAN2_BASE = APB1PERIPH_BASE + $6800; 732 PWR_BASE = APB1PERIPH_BASE + $7000; 733 DAC_BASE = APB1PERIPH_BASE + $7400; 734 TIM1_BASE = APB2PERIPH_BASE + $0000; 735 TIM8_BASE = APB2PERIPH_BASE + $0400; 736 USART1_BASE = APB2PERIPH_BASE + $1000; 737 USART6_BASE = APB2PERIPH_BASE + $1400; 738 ADC1_BASE = APB2PERIPH_BASE + $2000; 739 ADC2_BASE = APB2PERIPH_BASE + $2100; 740 ADC3_BASE = APB2PERIPH_BASE + $2200; 741 ADC_BASE = APB2PERIPH_BASE + $2300; 742 SDIO_BASE = APB2PERIPH_BASE + $2C00; 743 SPI1_BASE = APB2PERIPH_BASE + $3000; 744 SYSCFG_BASE = APB2PERIPH_BASE + $3800; 745 EXTI_BASE = APB2PERIPH_BASE + $3C00; 746 TIM9_BASE = APB2PERIPH_BASE + $4000; 747 TIM10_BASE = APB2PERIPH_BASE + $4400; 748 TIM11_BASE = APB2PERIPH_BASE + $4800; 749 GPIOA_BASE = AHB1PERIPH_BASE + $0000; 750 GPIOB_BASE = AHB1PERIPH_BASE + $0400; 751 GPIOC_BASE = AHB1PERIPH_BASE + $0800; 752 GPIOD_BASE = AHB1PERIPH_BASE + $0C00; 753 GPIOE_BASE = AHB1PERIPH_BASE + $1000; 754 GPIOF_BASE = AHB1PERIPH_BASE + $1400; 755 GPIOG_BASE = AHB1PERIPH_BASE + $1800; 756 GPIOH_BASE = AHB1PERIPH_BASE + $1C00; 757 GPIOI_BASE = AHB1PERIPH_BASE + $2000; 758 CRC_BASE = AHB1PERIPH_BASE + $3000; 759 RCC_BASE = AHB1PERIPH_BASE + $3800; 760 FLASH_R_BASE = AHB1PERIPH_BASE + $3C00; 761 DMA1_BASE = AHB1PERIPH_BASE + $6000; 762 DMA1_Stream0_BASE = DMA1_BASE + $010; 763 DMA1_Stream1_BASE = DMA1_BASE + $028; 764 DMA1_Stream2_BASE = DMA1_BASE + $040; 765 DMA1_Stream3_BASE = DMA1_BASE + $058; 766 DMA1_Stream4_BASE = DMA1_BASE + $070; 767 DMA1_Stream5_BASE = DMA1_BASE + $088; 768 DMA1_Stream6_BASE = DMA1_BASE + $0A0; 769 DMA1_Stream7_BASE = DMA1_BASE + $0B8; 770 DMA2_BASE = AHB1PERIPH_BASE + $6400; 771 DMA2_Stream0_BASE = DMA2_BASE + $010; 772 DMA2_Stream1_BASE = DMA2_BASE + $028; 773 DMA2_Stream2_BASE = DMA2_BASE + $040; 774 DMA2_Stream3_BASE = DMA2_BASE + $058; 775 DMA2_Stream4_BASE = DMA2_BASE + $070; 776 DMA2_Stream5_BASE = DMA2_BASE + $088; 777 DMA2_Stream6_BASE = DMA2_BASE + $0A0; 778 DMA2_Stream7_BASE = DMA2_BASE + $0B8; 779 ETH_BASE = AHB1PERIPH_BASE + $8000; 780 ETH_MAC_BASE = AHB1PERIPH_BASE + $8000; 781 ETH_MMC_BASE = ETH_BASE + $0100; 782 ETH_PTP_BASE = ETH_BASE + $0700; 783 ETH_DMA_BASE = ETH_BASE + $1000; 784 DCMI_BASE = AHB2PERIPH_BASE + $50000; 785 RNG_BASE = AHB2PERIPH_BASE + $60800; 786 FSMC_Bank1_R_BASE = FSMC_R_BASE + $0000; 787 FSMC_Bank1E_R_BASE = FSMC_R_BASE + $0104; 788 FSMC_Bank2_3_R_BASE = FSMC_R_BASE + $0060; 789 FSMC_Bank4_R_BASE = FSMC_R_BASE + $00A0; 790 DBGMCU_BASE = $E0042000; 791 USB_OTG_HS_PERIPH_BASE = $40040000; 792 USB_OTG_FS_PERIPH_BASE = $50000000; 793 USB_OTG_GLOBAL_BASE = $000; 794 USB_OTG_DEVICE_BASE = $800; 795 USB_OTG_IN_ENDPOINT_BASE = $900; 796 USB_OTG_OUT_ENDPOINT_BASE = $B00; 797 USB_OTG_HOST_BASE = $400; 798 USB_OTG_HOST_PORT_BASE = $440; 799 USB_OTG_HOST_CHANNEL_BASE = $500; 800 USB_OTG_PCGCCTL_BASE = $E00; 801 USB_OTG_FIFO_BASE = $1000; 802 803var 804 TIM2 : TTIM_Registers absolute TIM2_BASE; 805 TIM3 : TTIM_Registers absolute TIM3_BASE; 806 TIM4 : TTIM_Registers absolute TIM4_BASE; 807 TIM5 : TTIM_Registers absolute TIM5_BASE; 808 TIM6 : TTIM_Registers absolute TIM6_BASE; 809 TIM7 : TTIM_Registers absolute TIM7_BASE; 810 TIM12 : TTIM_Registers absolute TIM12_BASE; 811 TIM13 : TTIM_Registers absolute TIM13_BASE; 812 TIM14 : TTIM_Registers absolute TIM14_BASE; 813 RTC : TRTC_Registers absolute RTC_BASE; 814 WWDG : TWWDG_Registers absolute WWDG_BASE; 815 IWDG : TIWDG_Registers absolute IWDG_BASE; 816 I2S2ext : TSPI_Registers absolute I2S2ext_BASE; 817 SPI2 : TSPI_Registers absolute SPI2_BASE; 818 SPI3 : TSPI_Registers absolute SPI3_BASE; 819 I2S3ext : TSPI_Registers absolute I2S3ext_BASE; 820 USART2 : TUSART_Registers absolute USART2_BASE; 821 USART3 : TUSART_Registers absolute USART3_BASE; 822 UART4 : TUSART_Registers absolute UART4_BASE; 823 UART5 : TUSART_Registers absolute UART5_BASE; 824 I2C1 : TI2C_Registers absolute I2C1_BASE; 825 I2C2 : TI2C_Registers absolute I2C2_BASE; 826 I2C3 : TI2C_Registers absolute I2C3_BASE; 827 CAN1 : TCAN_Registers absolute CAN1_BASE; 828 CAN2 : TCAN_Registers absolute CAN2_BASE; 829 PWR : TPWR_Registers absolute PWR_BASE; 830 DAC : TDAC_Registers absolute DAC_BASE; 831 TIM1 : TTIM_Registers absolute TIM1_BASE; 832 TIM8 : TTIM_Registers absolute TIM8_BASE; 833 USART1 : TUSART_Registers absolute USART1_BASE; 834 USART6 : TUSART_Registers absolute USART6_BASE; 835 ADC : TADC_Common_Registers absolute ADC_BASE; 836 ADC1 : TADC_Registers absolute ADC1_BASE; 837 ADC2 : TADC_Registers absolute ADC2_BASE; 838 ADC3 : TADC_Registers absolute ADC3_BASE; 839 SDIO : TSDIO_Registers absolute SDIO_BASE; 840 SPI1 : TSPI_Registers absolute SPI1_BASE; 841 SYSCFG : TSYSCFG_Registers absolute SYSCFG_BASE; 842 EXTI : TEXTI_Registers absolute EXTI_BASE; 843 TIM9 : TTIM_Registers absolute TIM9_BASE; 844 TIM10 : TTIM_Registers absolute TIM10_BASE; 845 TIM11 : TTIM_Registers absolute TIM11_BASE; 846 GPIOA : TGPIO_Registers absolute GPIOA_BASE; 847 GPIOB : TGPIO_Registers absolute GPIOB_BASE; 848 GPIOC : TGPIO_Registers absolute GPIOC_BASE; 849 GPIOD : TGPIO_Registers absolute GPIOD_BASE; 850 GPIOE : TGPIO_Registers absolute GPIOE_BASE; 851 GPIOF : TGPIO_Registers absolute GPIOF_BASE; 852 GPIOG : TGPIO_Registers absolute GPIOG_BASE; 853 GPIOH : TGPIO_Registers absolute GPIOH_BASE; 854 GPIOI : TGPIO_Registers absolute GPIOI_BASE; 855 CRC : TCRC_Registers absolute CRC_BASE; 856 RCC : TRCC_Registers absolute RCC_BASE; 857 FLASH : TFLASH_Registers absolute FLASH_R_BASE; 858 DMA1 : TDMA_Registers absolute DMA1_BASE; 859 DMA1_Stream0 : TDMA_Stream_Registers absolute DMA1_Stream0_BASE; 860 DMA1_Stream1 : TDMA_Stream_Registers absolute DMA1_Stream1_BASE; 861 DMA1_Stream2 : TDMA_Stream_Registers absolute DMA1_Stream2_BASE; 862 DMA1_Stream3 : TDMA_Stream_Registers absolute DMA1_Stream3_BASE; 863 DMA1_Stream4 : TDMA_Stream_Registers absolute DMA1_Stream4_BASE; 864 DMA1_Stream5 : TDMA_Stream_Registers absolute DMA1_Stream5_BASE; 865 DMA1_Stream6 : TDMA_Stream_Registers absolute DMA1_Stream6_BASE; 866 DMA1_Stream7 : TDMA_Stream_Registers absolute DMA1_Stream7_BASE; 867 DMA2 : TDMA_Registers absolute DMA2_BASE; 868 DMA2_Stream0 : TDMA_Stream_Registers absolute DMA2_Stream0_BASE; 869 DMA2_Stream1 : TDMA_Stream_Registers absolute DMA2_Stream1_BASE; 870 DMA2_Stream2 : TDMA_Stream_Registers absolute DMA2_Stream2_BASE; 871 DMA2_Stream3 : TDMA_Stream_Registers absolute DMA2_Stream3_BASE; 872 DMA2_Stream4 : TDMA_Stream_Registers absolute DMA2_Stream4_BASE; 873 DMA2_Stream5 : TDMA_Stream_Registers absolute DMA2_Stream5_BASE; 874 DMA2_Stream6 : TDMA_Stream_Registers absolute DMA2_Stream6_BASE; 875 DMA2_Stream7 : TDMA_Stream_Registers absolute DMA2_Stream7_BASE; 876 ETH : TETH_Registers absolute ETH_BASE; 877 DCMI : TDCMI_Registers absolute DCMI_BASE; 878 RNG : TRNG_Registers absolute RNG_BASE; 879 FSMC_Bank1 : TFSMC_Bank1_Registers absolute FSMC_Bank1_R_BASE; 880 FSMC_Bank1E : TFSMC_Bank1E_Registers absolute FSMC_Bank1E_R_BASE; 881 FSMC_Bank2_3 : TFSMC_Bank2_3_Registers absolute FSMC_Bank2_3_R_BASE; 882 FSMC_Bank4 : TFSMC_Bank4_Registers absolute FSMC_Bank4_R_BASE; 883 DBGMCU : TDBGMCU_Registers absolute DBGMCU_BASE; 884 885implementation 886 887procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt'; 888procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt'; 889procedure BusFault_interrupt; external name 'BusFault_interrupt'; 890procedure UsageFault_interrupt; external name 'UsageFault_interrupt'; 891procedure SVCall_interrupt; external name 'SVCall_interrupt'; 892procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt'; 893procedure PendSV_interrupt; external name 'PendSV_interrupt'; 894procedure SysTick_interrupt; external name 'SysTick_interrupt'; 895procedure WWDG_interrupt; external name 'WWDG_interrupt'; 896procedure PVD_interrupt; external name 'PVD_interrupt'; 897procedure TAMP_STAMP_interrupt; external name 'TAMP_STAMP_interrupt'; 898procedure RTC_WKUP_interrupt; external name 'RTC_WKUP_interrupt'; 899procedure FLASH_interrupt; external name 'FLASH_interrupt'; 900procedure RCC_interrupt; external name 'RCC_interrupt'; 901procedure EXTI0_interrupt; external name 'EXTI0_interrupt'; 902procedure EXTI1_interrupt; external name 'EXTI1_interrupt'; 903procedure EXTI2_interrupt; external name 'EXTI2_interrupt'; 904procedure EXTI3_interrupt; external name 'EXTI3_interrupt'; 905procedure EXTI4_interrupt; external name 'EXTI4_interrupt'; 906procedure DMA1_Stream0_interrupt; external name 'DMA1_Stream0_interrupt'; 907procedure DMA1_Stream1_interrupt; external name 'DMA1_Stream1_interrupt'; 908procedure DMA1_Stream2_interrupt; external name 'DMA1_Stream2_interrupt'; 909procedure DMA1_Stream3_interrupt; external name 'DMA1_Stream3_interrupt'; 910procedure DMA1_Stream4_interrupt; external name 'DMA1_Stream4_interrupt'; 911procedure DMA1_Stream5_interrupt; external name 'DMA1_Stream5_interrupt'; 912procedure DMA1_Stream6_interrupt; external name 'DMA1_Stream6_interrupt'; 913procedure ADC_interrupt; external name 'ADC_interrupt'; 914procedure CAN1_TX_interrupt; external name 'CAN1_TX_interrupt'; 915procedure CAN1_RX0_interrupt; external name 'CAN1_RX0_interrupt'; 916procedure CAN1_RX1_interrupt; external name 'CAN1_RX1_interrupt'; 917procedure CAN1_SCE_interrupt; external name 'CAN1_SCE_interrupt'; 918procedure EXTI9_5_interrupt; external name 'EXTI9_5_interrupt'; 919procedure TIM1_BRK_TIM9_interrupt; external name 'TIM1_BRK_TIM9_interrupt'; 920procedure TIM1_UP_TIM10_interrupt; external name 'TIM1_UP_TIM10_interrupt'; 921procedure TIM1_TRG_COM_TIM11_interrupt; external name 'TIM1_TRG_COM_TIM11_interrupt'; 922procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt'; 923procedure TIM2_interrupt; external name 'TIM2_interrupt'; 924procedure TIM3_interrupt; external name 'TIM3_interrupt'; 925procedure TIM4_interrupt; external name 'TIM4_interrupt'; 926procedure I2C1_EV_interrupt; external name 'I2C1_EV_interrupt'; 927procedure I2C1_ER_interrupt; external name 'I2C1_ER_interrupt'; 928procedure I2C2_EV_interrupt; external name 'I2C2_EV_interrupt'; 929procedure I2C2_ER_interrupt; external name 'I2C2_ER_interrupt'; 930procedure SPI1_interrupt; external name 'SPI1_interrupt'; 931procedure SPI2_interrupt; external name 'SPI2_interrupt'; 932procedure USART1_interrupt; external name 'USART1_interrupt'; 933procedure USART2_interrupt; external name 'USART2_interrupt'; 934procedure USART3_interrupt; external name 'USART3_interrupt'; 935procedure EXTI15_10_interrupt; external name 'EXTI15_10_interrupt'; 936procedure RTC_Alarm_interrupt; external name 'RTC_Alarm_interrupt'; 937procedure OTG_FS_WKUP_interrupt; external name 'OTG_FS_WKUP_interrupt'; 938procedure TIM8_BRK_TIM12_interrupt; external name 'TIM8_BRK_TIM12_interrupt'; 939procedure TIM8_UP_TIM13_interrupt; external name 'TIM8_UP_TIM13_interrupt'; 940procedure TIM8_TRG_COM_TIM14_interrupt; external name 'TIM8_TRG_COM_TIM14_interrupt'; 941procedure TIM8_CC_interrupt; external name 'TIM8_CC_interrupt'; 942procedure DMA1_Stream7_interrupt; external name 'DMA1_Stream7_interrupt'; 943procedure FSMC_interrupt; external name 'FSMC_interrupt'; 944procedure SDIO_interrupt; external name 'SDIO_interrupt'; 945procedure TIM5_interrupt; external name 'TIM5_interrupt'; 946procedure SPI3_interrupt; external name 'SPI3_interrupt'; 947procedure UART4_interrupt; external name 'UART4_interrupt'; 948procedure UART5_interrupt; external name 'UART5_interrupt'; 949procedure TIM6_DAC_interrupt; external name 'TIM6_DAC_interrupt'; 950procedure TIM7_interrupt; external name 'TIM7_interrupt'; 951procedure DMA2_Stream0_interrupt; external name 'DMA2_Stream0_interrupt'; 952procedure DMA2_Stream1_interrupt; external name 'DMA2_Stream1_interrupt'; 953procedure DMA2_Stream2_interrupt; external name 'DMA2_Stream2_interrupt'; 954procedure DMA2_Stream3_interrupt; external name 'DMA2_Stream3_interrupt'; 955procedure DMA2_Stream4_interrupt; external name 'DMA2_Stream4_interrupt'; 956procedure ETH_interrupt; external name 'ETH_interrupt'; 957procedure ETH_WKUP_interrupt; external name 'ETH_WKUP_interrupt'; 958procedure CAN2_TX_interrupt; external name 'CAN2_TX_interrupt'; 959procedure CAN2_RX0_interrupt; external name 'CAN2_RX0_interrupt'; 960procedure CAN2_RX1_interrupt; external name 'CAN2_RX1_interrupt'; 961procedure CAN2_SCE_interrupt; external name 'CAN2_SCE_interrupt'; 962procedure OTG_FS_interrupt; external name 'OTG_FS_interrupt'; 963procedure DMA2_Stream5_interrupt; external name 'DMA2_Stream5_interrupt'; 964procedure DMA2_Stream6_interrupt; external name 'DMA2_Stream6_interrupt'; 965procedure DMA2_Stream7_interrupt; external name 'DMA2_Stream7_interrupt'; 966procedure USART6_interrupt; external name 'USART6_interrupt'; 967procedure I2C3_EV_interrupt; external name 'I2C3_EV_interrupt'; 968procedure I2C3_ER_interrupt; external name 'I2C3_ER_interrupt'; 969procedure OTG_HS_EP1_OUT_interrupt; external name 'OTG_HS_EP1_OUT_interrupt'; 970procedure OTG_HS_EP1_IN_interrupt; external name 'OTG_HS_EP1_IN_interrupt'; 971procedure OTG_HS_WKUP_interrupt; external name 'OTG_HS_WKUP_interrupt'; 972procedure OTG_HS_interrupt; external name 'OTG_HS_interrupt'; 973procedure DCMI_interrupt; external name 'DCMI_interrupt'; 974procedure HASH_RNG_interrupt; external name 'HASH_RNG_interrupt'; 975procedure FPU_interrupt; external name 'FPU_interrupt'; 976 977{$i cortexm4f_start.inc} 978 979procedure Vectors; assembler; nostackframe; 980label interrupt_vectors; 981asm 982 .section ".init.interrupt_vectors" 983 interrupt_vectors: 984 .long _stack_top 985 .long Startup 986 .long NonMaskableInt_interrupt 987 .long 0 988 .long MemoryManagement_interrupt 989 .long BusFault_interrupt 990 .long UsageFault_interrupt 991 .long 0 992 .long 0 993 .long 0 994 .long 0 995 .long SVCall_interrupt 996 .long DebugMonitor_interrupt 997 .long 0 998 .long PendSV_interrupt 999 .long SysTick_interrupt 1000 .long WWDG_interrupt 1001 .long PVD_interrupt 1002 .long TAMP_STAMP_interrupt 1003 .long RTC_WKUP_interrupt 1004 .long FLASH_interrupt 1005 .long RCC_interrupt 1006 .long EXTI0_interrupt 1007 .long EXTI1_interrupt 1008 .long EXTI2_interrupt 1009 .long EXTI3_interrupt 1010 .long EXTI4_interrupt 1011 .long DMA1_Stream0_interrupt 1012 .long DMA1_Stream1_interrupt 1013 .long DMA1_Stream2_interrupt 1014 .long DMA1_Stream3_interrupt 1015 .long DMA1_Stream4_interrupt 1016 .long DMA1_Stream5_interrupt 1017 .long DMA1_Stream6_interrupt 1018 .long ADC_interrupt 1019 .long CAN1_TX_interrupt 1020 .long CAN1_RX0_interrupt 1021 .long CAN1_RX1_interrupt 1022 .long CAN1_SCE_interrupt 1023 .long EXTI9_5_interrupt 1024 .long TIM1_BRK_TIM9_interrupt 1025 .long TIM1_UP_TIM10_interrupt 1026 .long TIM1_TRG_COM_TIM11_interrupt 1027 .long TIM1_CC_interrupt 1028 .long TIM2_interrupt 1029 .long TIM3_interrupt 1030 .long TIM4_interrupt 1031 .long I2C1_EV_interrupt 1032 .long I2C1_ER_interrupt 1033 .long I2C2_EV_interrupt 1034 .long I2C2_ER_interrupt 1035 .long SPI1_interrupt 1036 .long SPI2_interrupt 1037 .long USART1_interrupt 1038 .long USART2_interrupt 1039 .long USART3_interrupt 1040 .long EXTI15_10_interrupt 1041 .long RTC_Alarm_interrupt 1042 .long OTG_FS_WKUP_interrupt 1043 .long TIM8_BRK_TIM12_interrupt 1044 .long TIM8_UP_TIM13_interrupt 1045 .long TIM8_TRG_COM_TIM14_interrupt 1046 .long TIM8_CC_interrupt 1047 .long DMA1_Stream7_interrupt 1048 .long FSMC_interrupt 1049 .long SDIO_interrupt 1050 .long TIM5_interrupt 1051 .long SPI3_interrupt 1052 .long UART4_interrupt 1053 .long UART5_interrupt 1054 .long TIM6_DAC_interrupt 1055 .long TIM7_interrupt 1056 .long DMA2_Stream0_interrupt 1057 .long DMA2_Stream1_interrupt 1058 .long DMA2_Stream2_interrupt 1059 .long DMA2_Stream3_interrupt 1060 .long DMA2_Stream4_interrupt 1061 .long ETH_interrupt 1062 .long ETH_WKUP_interrupt 1063 .long CAN2_TX_interrupt 1064 .long CAN2_RX0_interrupt 1065 .long CAN2_RX1_interrupt 1066 .long CAN2_SCE_interrupt 1067 .long OTG_FS_interrupt 1068 .long DMA2_Stream5_interrupt 1069 .long DMA2_Stream6_interrupt 1070 .long DMA2_Stream7_interrupt 1071 .long USART6_interrupt 1072 .long I2C3_EV_interrupt 1073 .long I2C3_ER_interrupt 1074 .long OTG_HS_EP1_OUT_interrupt 1075 .long OTG_HS_EP1_IN_interrupt 1076 .long OTG_HS_WKUP_interrupt 1077 .long OTG_HS_interrupt 1078 .long DCMI_interrupt 1079 .long 0 1080 .long HASH_RNG_interrupt 1081 .long FPU_interrupt 1082 .weak NonMaskableInt_interrupt 1083 .weak MemoryManagement_interrupt 1084 .weak BusFault_interrupt 1085 .weak UsageFault_interrupt 1086 .weak SVCall_interrupt 1087 .weak DebugMonitor_interrupt 1088 .weak PendSV_interrupt 1089 .weak SysTick_interrupt 1090 .weak WWDG_interrupt 1091 .weak PVD_interrupt 1092 .weak TAMP_STAMP_interrupt 1093 .weak RTC_WKUP_interrupt 1094 .weak FLASH_interrupt 1095 .weak RCC_interrupt 1096 .weak EXTI0_interrupt 1097 .weak EXTI1_interrupt 1098 .weak EXTI2_interrupt 1099 .weak EXTI3_interrupt 1100 .weak EXTI4_interrupt 1101 .weak DMA1_Stream0_interrupt 1102 .weak DMA1_Stream1_interrupt 1103 .weak DMA1_Stream2_interrupt 1104 .weak DMA1_Stream3_interrupt 1105 .weak DMA1_Stream4_interrupt 1106 .weak DMA1_Stream5_interrupt 1107 .weak DMA1_Stream6_interrupt 1108 .weak ADC_interrupt 1109 .weak CAN1_TX_interrupt 1110 .weak CAN1_RX0_interrupt 1111 .weak CAN1_RX1_interrupt 1112 .weak CAN1_SCE_interrupt 1113 .weak EXTI9_5_interrupt 1114 .weak TIM1_BRK_TIM9_interrupt 1115 .weak TIM1_UP_TIM10_interrupt 1116 .weak TIM1_TRG_COM_TIM11_interrupt 1117 .weak TIM1_CC_interrupt 1118 .weak TIM2_interrupt 1119 .weak TIM3_interrupt 1120 .weak TIM4_interrupt 1121 .weak I2C1_EV_interrupt 1122 .weak I2C1_ER_interrupt 1123 .weak I2C2_EV_interrupt 1124 .weak I2C2_ER_interrupt 1125 .weak SPI1_interrupt 1126 .weak SPI2_interrupt 1127 .weak USART1_interrupt 1128 .weak USART2_interrupt 1129 .weak USART3_interrupt 1130 .weak EXTI15_10_interrupt 1131 .weak RTC_Alarm_interrupt 1132 .weak OTG_FS_WKUP_interrupt 1133 .weak TIM8_BRK_TIM12_interrupt 1134 .weak TIM8_UP_TIM13_interrupt 1135 .weak TIM8_TRG_COM_TIM14_interrupt 1136 .weak TIM8_CC_interrupt 1137 .weak DMA1_Stream7_interrupt 1138 .weak FSMC_interrupt 1139 .weak SDIO_interrupt 1140 .weak TIM5_interrupt 1141 .weak SPI3_interrupt 1142 .weak UART4_interrupt 1143 .weak UART5_interrupt 1144 .weak TIM6_DAC_interrupt 1145 .weak TIM7_interrupt 1146 .weak DMA2_Stream0_interrupt 1147 .weak DMA2_Stream1_interrupt 1148 .weak DMA2_Stream2_interrupt 1149 .weak DMA2_Stream3_interrupt 1150 .weak DMA2_Stream4_interrupt 1151 .weak ETH_interrupt 1152 .weak ETH_WKUP_interrupt 1153 .weak CAN2_TX_interrupt 1154 .weak CAN2_RX0_interrupt 1155 .weak CAN2_RX1_interrupt 1156 .weak CAN2_SCE_interrupt 1157 .weak OTG_FS_interrupt 1158 .weak DMA2_Stream5_interrupt 1159 .weak DMA2_Stream6_interrupt 1160 .weak DMA2_Stream7_interrupt 1161 .weak USART6_interrupt 1162 .weak I2C3_EV_interrupt 1163 .weak I2C3_ER_interrupt 1164 .weak OTG_HS_EP1_OUT_interrupt 1165 .weak OTG_HS_EP1_IN_interrupt 1166 .weak OTG_HS_WKUP_interrupt 1167 .weak OTG_HS_interrupt 1168 .weak DCMI_interrupt 1169 .weak HASH_RNG_interrupt 1170 .weak FPU_interrupt 1171 .set NonMaskableInt_interrupt, HaltProc 1172 .set MemoryManagement_interrupt, HaltProc 1173 .set BusFault_interrupt, HaltProc 1174 .set UsageFault_interrupt, HaltProc 1175 .set SVCall_interrupt, HaltProc 1176 .set DebugMonitor_interrupt, HaltProc 1177 .set PendSV_interrupt, HaltProc 1178 .set SysTick_interrupt, HaltProc 1179 .set WWDG_interrupt, HaltProc 1180 .set PVD_interrupt, HaltProc 1181 .set TAMP_STAMP_interrupt, HaltProc 1182 .set RTC_WKUP_interrupt, HaltProc 1183 .set FLASH_interrupt, HaltProc 1184 .set RCC_interrupt, HaltProc 1185 .set EXTI0_interrupt, HaltProc 1186 .set EXTI1_interrupt, HaltProc 1187 .set EXTI2_interrupt, HaltProc 1188 .set EXTI3_interrupt, HaltProc 1189 .set EXTI4_interrupt, HaltProc 1190 .set DMA1_Stream0_interrupt, HaltProc 1191 .set DMA1_Stream1_interrupt, HaltProc 1192 .set DMA1_Stream2_interrupt, HaltProc 1193 .set DMA1_Stream3_interrupt, HaltProc 1194 .set DMA1_Stream4_interrupt, HaltProc 1195 .set DMA1_Stream5_interrupt, HaltProc 1196 .set DMA1_Stream6_interrupt, HaltProc 1197 .set ADC_interrupt, HaltProc 1198 .set CAN1_TX_interrupt, HaltProc 1199 .set CAN1_RX0_interrupt, HaltProc 1200 .set CAN1_RX1_interrupt, HaltProc 1201 .set CAN1_SCE_interrupt, HaltProc 1202 .set EXTI9_5_interrupt, HaltProc 1203 .set TIM1_BRK_TIM9_interrupt, HaltProc 1204 .set TIM1_UP_TIM10_interrupt, HaltProc 1205 .set TIM1_TRG_COM_TIM11_interrupt, HaltProc 1206 .set TIM1_CC_interrupt, HaltProc 1207 .set TIM2_interrupt, HaltProc 1208 .set TIM3_interrupt, HaltProc 1209 .set TIM4_interrupt, HaltProc 1210 .set I2C1_EV_interrupt, HaltProc 1211 .set I2C1_ER_interrupt, HaltProc 1212 .set I2C2_EV_interrupt, HaltProc 1213 .set I2C2_ER_interrupt, HaltProc 1214 .set SPI1_interrupt, HaltProc 1215 .set SPI2_interrupt, HaltProc 1216 .set USART1_interrupt, HaltProc 1217 .set USART2_interrupt, HaltProc 1218 .set USART3_interrupt, HaltProc 1219 .set EXTI15_10_interrupt, HaltProc 1220 .set RTC_Alarm_interrupt, HaltProc 1221 .set OTG_FS_WKUP_interrupt, HaltProc 1222 .set TIM8_BRK_TIM12_interrupt, HaltProc 1223 .set TIM8_UP_TIM13_interrupt, HaltProc 1224 .set TIM8_TRG_COM_TIM14_interrupt, HaltProc 1225 .set TIM8_CC_interrupt, HaltProc 1226 .set DMA1_Stream7_interrupt, HaltProc 1227 .set FSMC_interrupt, HaltProc 1228 .set SDIO_interrupt, HaltProc 1229 .set TIM5_interrupt, HaltProc 1230 .set SPI3_interrupt, HaltProc 1231 .set UART4_interrupt, HaltProc 1232 .set UART5_interrupt, HaltProc 1233 .set TIM6_DAC_interrupt, HaltProc 1234 .set TIM7_interrupt, HaltProc 1235 .set DMA2_Stream0_interrupt, HaltProc 1236 .set DMA2_Stream1_interrupt, HaltProc 1237 .set DMA2_Stream2_interrupt, HaltProc 1238 .set DMA2_Stream3_interrupt, HaltProc 1239 .set DMA2_Stream4_interrupt, HaltProc 1240 .set ETH_interrupt, HaltProc 1241 .set ETH_WKUP_interrupt, HaltProc 1242 .set CAN2_TX_interrupt, HaltProc 1243 .set CAN2_RX0_interrupt, HaltProc 1244 .set CAN2_RX1_interrupt, HaltProc 1245 .set CAN2_SCE_interrupt, HaltProc 1246 .set OTG_FS_interrupt, HaltProc 1247 .set DMA2_Stream5_interrupt, HaltProc 1248 .set DMA2_Stream6_interrupt, HaltProc 1249 .set DMA2_Stream7_interrupt, HaltProc 1250 .set USART6_interrupt, HaltProc 1251 .set I2C3_EV_interrupt, HaltProc 1252 .set I2C3_ER_interrupt, HaltProc 1253 .set OTG_HS_EP1_OUT_interrupt, HaltProc 1254 .set OTG_HS_EP1_IN_interrupt, HaltProc 1255 .set OTG_HS_WKUP_interrupt, HaltProc 1256 .set OTG_HS_interrupt, HaltProc 1257 .set DCMI_interrupt, HaltProc 1258 .set HASH_RNG_interrupt, HaltProc 1259 .set FPU_interrupt, HaltProc 1260 .text 1261end; 1262end. 1263