1;; Machine description for DEC Alpha for GNU C compiler 2;; Copyright (C) 1992-2020 Free Software Foundation, Inc. 3;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22 23;; Uses of UNSPEC in this file: 24 25(define_c_enum "unspec" [ 26 UNSPEC_XFLT_COMPARE 27 UNSPEC_ARG_HOME 28 UNSPEC_LDGP1 29 UNSPEC_INSXH 30 UNSPEC_MSKXH 31 UNSPEC_CVTQL 32 UNSPEC_CVTLQ 33 UNSPEC_LDGP2 34 UNSPEC_LITERAL 35 UNSPEC_LITUSE 36 UNSPEC_SIBCALL 37 UNSPEC_SYMBOL 38 39 ;; TLS Support 40 UNSPEC_TLSGD_CALL 41 UNSPEC_TLSLDM_CALL 42 UNSPEC_TLSGD 43 UNSPEC_TLSLDM 44 UNSPEC_DTPREL 45 UNSPEC_TPREL 46 UNSPEC_TP 47 48 ;; Builtins 49 UNSPEC_CMPBGE 50 UNSPEC_ZAP 51 UNSPEC_AMASK 52 UNSPEC_IMPLVER 53 UNSPEC_PERR 54 UNSPEC_COPYSIGN 55 56 ;; Atomic operations 57 UNSPEC_MB 58 UNSPEC_ATOMIC 59 UNSPEC_CMPXCHG 60 UNSPEC_XCHG 61]) 62 63;; UNSPEC_VOLATILE: 64 65(define_c_enum "unspecv" [ 66 UNSPECV_IMB 67 UNSPECV_BLOCKAGE 68 UNSPECV_SETJMPR ; builtin_setjmp_receiver 69 UNSPECV_LONGJMP ; builtin_longjmp 70 UNSPECV_TRAPB 71 UNSPECV_PSPL ; prologue_stack_probe_loop 72 UNSPECV_REALIGN 73 UNSPECV_EHR ; exception_receiver 74 UNSPECV_MCOUNT 75 UNSPECV_FORCE_MOV 76 UNSPECV_LDGP1 77 UNSPECV_PLDGP2 ; prologue ldgp 78 UNSPECV_SET_TP 79 UNSPECV_RPCC 80 UNSPECV_SETJMPR_ER ; builtin_setjmp_receiver fragment 81 UNSPECV_LL ; load-locked 82 UNSPECV_SC ; store-conditional 83 UNSPECV_CMPXCHG 84]) 85 86;; On non-BWX targets, CQImode must be handled the similarly to HImode 87;; when generating reloads. 88(define_mode_iterator RELOAD12 [QI HI CQI]) 89(define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")]) 90 91;; Other mode iterators 92(define_mode_iterator IMODE [QI HI SI DI]) 93(define_mode_iterator I12MODE [QI HI]) 94(define_mode_iterator I124MODE [QI HI SI]) 95(define_mode_iterator I24MODE [HI SI]) 96(define_mode_iterator I248MODE [HI SI DI]) 97(define_mode_iterator I48MODE [SI DI]) 98 99(define_mode_attr DWI [(SI "DI") (DI "TI")]) 100(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q") 101 (V8QI "b8") (V4HI "w4") 102 (SF "%,") (DF "%-")]) 103(define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")]) 104 105(define_code_iterator any_maxmin [smax smin umax umin]) 106 107(define_code_attr maxmin [(smax "maxs") (smin "mins") 108 (umax "maxu") (umin "minu")]) 109 110;; Where necessary, the suffixes _le and _be are used to distinguish between 111;; little-endian and big-endian patterns. 112;; 113;; Note that the Unicos/Mk assembler does not support the following 114;; opcodes: mov, fmov, nop, fnop, unop. 115 116;; Processor type -- this attribute must exactly match the processor_type 117;; enumeration in alpha.h. 118 119(define_attr "tune" "ev4,ev5,ev6" 120 (const (symbol_ref "((enum attr_tune) alpha_tune)"))) 121 122;; Define an insn type attribute. This is used in function unit delay 123;; computations, among other purposes. For the most part, we use the names 124;; defined in the EV4 documentation, but add a few that we have to know about 125;; separately. 126 127(define_attr "type" 128 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov, 129 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c, 130 multi,none" 131 (const_string "iadd")) 132 133;; Describe a user's asm statement. 134(define_asm_attributes 135 [(set_attr "type" "multi")]) 136 137;; Define the operand size an insn operates on. Used primarily by mul 138;; and div operations that have size dependent timings. 139 140(define_attr "opsize" "si,di,udi" 141 (const_string "di")) 142 143;; The TRAP attribute marks instructions that may generate traps 144;; (which are imprecise and may need a trapb if software completion 145;; is desired). 146 147(define_attr "trap" "no,yes" 148 (const_string "no")) 149 150;; The ROUND_SUFFIX attribute marks which instructions require a 151;; rounding-mode suffix. The value NONE indicates no suffix, 152;; the value NORMAL indicates a suffix controlled by alpha_fprm. 153 154(define_attr "round_suffix" "none,normal,c" 155 (const_string "none")) 156 157;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix: 158;; NONE no suffix 159;; SU accepts only /su (cmpt et al) 160;; SUI accepts only /sui (cvtqt and cvtqs) 161;; V_SV accepts /v and /sv (cvtql only) 162;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) 163;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) 164;; 165;; The actual suffix emitted is controlled by alpha_fptm. 166 167(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" 168 (const_string "none")) 169 170;; The length of an instruction sequence in bytes. 171 172(define_attr "length" "" 173 (const_int 4)) 174 175;; The USEGP attribute marks instructions that have relocations that use 176;; the GP. 177 178(define_attr "usegp" "no,yes" 179 (cond [(eq_attr "type" "ldsym,jsr") 180 (const_string "yes") 181 (eq_attr "type" "ild,fld,ist,fst") 182 (symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))") 183 ] 184 (const_string "no"))) 185 186;; The CANNOT_COPY attribute marks instructions with relocations that 187;; cannot easily be duplicated. This includes insns with gpdisp relocs 188;; since they have to stay in 1-1 correspondence with one another. This 189;; also includes jsr insns, since they must stay in correspondence with 190;; the immediately following gpdisp instructions. 191 192(define_attr "cannot_copy" "false,true" 193 (const_string "false")) 194 195;; Used to control the "enabled" attribute on a per-instruction basis. 196;; For convenience, conflate ABI issues re loading of addresses with 197;; an "isa". 198(define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er" 199 (const_string "base")) 200 201(define_attr "enabled" "" 202 (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX") 203 (eq_attr "isa" "max") (symbol_ref "TARGET_MAX") 204 (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX") 205 (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX") 206 (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS") 207 (eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS") 208 (eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS") 209 ] 210 (const_int 1))) 211 212;; Include scheduling descriptions. 213 214(include "ev4.md") 215(include "ev5.md") 216(include "ev6.md") 217 218 219;; Operand and operator predicates and constraints 220 221(include "predicates.md") 222(include "constraints.md") 223 224 225;; First define the arithmetic insns. Note that the 32-bit forms also 226;; sign-extend. 227 228;; Handle 32-64 bit extension from memory to a floating point register 229;; specially, since this occurs frequently in int->double conversions. 230;; 231;; Note that while we must retain the =f case in the insn for reload's 232;; benefit, it should be eliminated after reload, so we should never emit 233;; code for that case. But we don't reject the possibility. 234 235(define_expand "extendsidi2" 236 [(set (match_operand:DI 0 "register_operand") 237 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) 238 239(define_insn "*cvtlq" 240 [(set (match_operand:DI 0 "register_operand" "=f") 241 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")] 242 UNSPEC_CVTLQ))] 243 "" 244 "cvtlq %1,%0" 245 [(set_attr "type" "fadd")]) 246 247(define_insn "*extendsidi2_1" 248 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f") 249 (sign_extend:DI 250 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] 251 "" 252 "@ 253 addl $31,%1,%0 254 ldl %0,%1 255 lds %0,%1\;cvtlq %0,%0" 256 [(set_attr "type" "iadd,ild,fld") 257 (set_attr "length" "*,*,8")]) 258 259(define_split 260 [(set (match_operand:DI 0 "hard_fp_register_operand") 261 (sign_extend:DI (match_operand:SI 1 "memory_operand")))] 262 "reload_completed" 263 [(set (match_dup 2) (match_dup 1)) 264 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] 265{ 266 operands[1] = adjust_address (operands[1], SFmode, 0); 267 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0])); 268}) 269 270;; Optimize sign-extension of SImode loads. This shows up in the wake of 271;; reload when converting fp->int. 272 273(define_peephole2 274 [(set (match_operand:SI 0 "hard_int_register_operand") 275 (match_operand:SI 1 "memory_operand")) 276 (set (match_operand:DI 2 "hard_int_register_operand") 277 (sign_extend:DI (match_dup 0)))] 278 "true_regnum (operands[0]) == true_regnum (operands[2]) 279 || peep2_reg_dead_p (2, operands[0])" 280 [(set (match_dup 2) 281 (sign_extend:DI (match_dup 1)))]) 282 283(define_insn "addsi3" 284 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 285 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 286 (match_operand:SI 2 "add_operand" "rI,O,K,L")))] 287 "" 288 "@ 289 addl %r1,%2,%0 290 subl %r1,%n2,%0 291 lda %0,%2(%r1) 292 ldah %0,%h2(%r1)") 293 294(define_split 295 [(set (match_operand:SI 0 "register_operand") 296 (plus:SI (match_operand:SI 1 "register_operand") 297 (match_operand:SI 2 "const_int_operand")))] 298 "! add_operand (operands[2], SImode)" 299 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 300 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 301{ 302 HOST_WIDE_INT val = INTVAL (operands[2]); 303 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 304 HOST_WIDE_INT rest = val - low; 305 306 operands[3] = GEN_INT (rest); 307 operands[4] = GEN_INT (low); 308}) 309 310(define_insn "*addsi_se" 311 [(set (match_operand:DI 0 "register_operand" "=r,r") 312 (sign_extend:DI 313 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 314 (match_operand:SI 2 "sext_add_operand" "rI,O"))))] 315 "" 316 "@ 317 addl %r1,%2,%0 318 subl %r1,%n2,%0") 319 320(define_insn "*addsi_se2" 321 [(set (match_operand:DI 0 "register_operand" "=r,r") 322 (sign_extend:DI 323 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 324 (match_operand:DI 2 "sext_add_operand" "rI,O")) 325 0)))] 326 "" 327 "@ 328 addl %r1,%2,%0 329 subl %r1,%n2,%0") 330 331(define_split 332 [(set (match_operand:DI 0 "register_operand") 333 (sign_extend:DI 334 (plus:SI (match_operand:SI 1 "reg_not_elim_operand") 335 (match_operand:SI 2 "const_int_operand")))) 336 (clobber (match_operand:SI 3 "reg_not_elim_operand"))] 337 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 338 && INTVAL (operands[2]) % 4 == 0" 339 [(set (match_dup 3) (match_dup 4)) 340 (set (match_dup 0) (sign_extend:DI (plus:SI (ashift:SI (match_dup 3) 341 (match_dup 5)) 342 (match_dup 1))))] 343{ 344 HOST_WIDE_INT val = INTVAL (operands[2]) / 4; 345 int mult = 4; 346 347 if (val % 2 == 0) 348 val /= 2, mult = 8; 349 350 operands[4] = GEN_INT (val); 351 operands[5] = GEN_INT (exact_log2 (mult)); 352}) 353 354(define_split 355 [(set (match_operand:DI 0 "register_operand") 356 (sign_extend:DI 357 (plus:SI (match_operator:SI 1 "comparison_operator" 358 [(match_operand 2) 359 (match_operand 3)]) 360 (match_operand:SI 4 "add_operand")))) 361 (clobber (match_operand:DI 5 "register_operand"))] 362 "" 363 [(set (match_dup 5) (match_dup 6)) 364 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] 365{ 366 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 367 operands[2], operands[3]); 368 operands[7] = gen_lowpart (SImode, operands[5]); 369}) 370 371(define_expand "adddi3" 372 [(set (match_operand:DI 0 "register_operand") 373 (plus:DI (match_operand:DI 1 "register_operand") 374 (match_operand:DI 2 "add_operand")))]) 375 376(define_insn "*adddi_er_lo16_dtp" 377 [(set (match_operand:DI 0 "register_operand" "=r") 378 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 379 (match_operand:DI 2 "dtp16_symbolic_operand")))] 380 "HAVE_AS_TLS" 381 "lda %0,%2(%1)\t\t!dtprel") 382 383(define_insn "*adddi_er_hi32_dtp" 384 [(set (match_operand:DI 0 "register_operand" "=r") 385 (plus:DI (match_operand:DI 1 "register_operand" "r") 386 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))] 387 "HAVE_AS_TLS" 388 "ldah %0,%2(%1)\t\t!dtprelhi") 389 390(define_insn "*adddi_er_lo32_dtp" 391 [(set (match_operand:DI 0 "register_operand" "=r") 392 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 393 (match_operand:DI 2 "dtp32_symbolic_operand")))] 394 "HAVE_AS_TLS" 395 "lda %0,%2(%1)\t\t!dtprello") 396 397(define_insn "*adddi_er_lo16_tp" 398 [(set (match_operand:DI 0 "register_operand" "=r") 399 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 400 (match_operand:DI 2 "tp16_symbolic_operand")))] 401 "HAVE_AS_TLS" 402 "lda %0,%2(%1)\t\t!tprel") 403 404(define_insn "*adddi_er_hi32_tp" 405 [(set (match_operand:DI 0 "register_operand" "=r") 406 (plus:DI (match_operand:DI 1 "register_operand" "r") 407 (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))] 408 "HAVE_AS_TLS" 409 "ldah %0,%2(%1)\t\t!tprelhi") 410 411(define_insn "*adddi_er_lo32_tp" 412 [(set (match_operand:DI 0 "register_operand" "=r") 413 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 414 (match_operand:DI 2 "tp32_symbolic_operand")))] 415 "HAVE_AS_TLS" 416 "lda %0,%2(%1)\t\t!tprello") 417 418(define_insn "*adddi_er_high_l" 419 [(set (match_operand:DI 0 "register_operand" "=r") 420 (plus:DI (match_operand:DI 1 "register_operand" "r") 421 (high:DI (match_operand:DI 2 "local_symbolic_operand"))))] 422 "TARGET_EXPLICIT_RELOCS && reload_completed" 423 "ldah %0,%2(%1)\t\t!gprelhigh" 424 [(set_attr "usegp" "yes")]) 425 426(define_split 427 [(set (match_operand:DI 0 "register_operand") 428 (high:DI (match_operand:DI 1 "local_symbolic_operand")))] 429 "TARGET_EXPLICIT_RELOCS && reload_completed" 430 [(set (match_dup 0) 431 (plus:DI (match_dup 2) (high:DI (match_dup 1))))] 432 "operands[2] = pic_offset_table_rtx;") 433 434;; We used to expend quite a lot of effort choosing addq/subq/lda. 435;; With complications like 436;; 437;; The NT stack unwind code can't handle a subq to adjust the stack 438;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3, 439;; the exception handling code will loop if a subq is used and an 440;; exception occurs. 441;; 442;; The 19980616 change to emit prologues as RTL also confused some 443;; versions of GDB, which also interprets prologues. This has been 444;; fixed as of GDB 4.18, but it does not harm to unconditionally 445;; use lda here. 446;; 447;; and the fact that the three insns schedule exactly the same, it's 448;; just not worth the effort. 449 450(define_insn "*adddi_internal" 451 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 452 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r") 453 (match_operand:DI 2 "add_operand" "r,K,L")))] 454 "" 455 "@ 456 addq %1,%2,%0 457 lda %0,%2(%1) 458 ldah %0,%h2(%1)") 459 460;; ??? Allow large constants when basing off the frame pointer or some 461;; virtual register that may eliminate to the frame pointer. This is 462;; done because register elimination offsets will change the hi/lo split, 463;; and if we split before reload, we will require additional instructions. 464 465(define_insn "*adddi_fp_hack" 466 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 467 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r") 468 (match_operand:DI 2 "const_int_operand" "K,L,n")))] 469 "NONSTRICT_REG_OK_FP_BASE_P (operands[1]) 470 && INTVAL (operands[2]) >= 0 471 /* This is the largest constant an lda+ldah pair can add, minus 472 an upper bound on the displacement between SP and AP during 473 register elimination. See INITIAL_ELIMINATION_OFFSET. */ 474 && INTVAL (operands[2]) 475 < (0x7fff8000 476 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD 477 - ALPHA_ROUND(crtl->outgoing_args_size) 478 - (ALPHA_ROUND (get_frame_size () 479 + max_reg_num () * UNITS_PER_WORD 480 + crtl->args.pretend_args_size) 481 - crtl->args.pretend_args_size))" 482 "@ 483 lda %0,%2(%1) 484 ldah %0,%h2(%1) 485 #") 486 487;; Don't do this if we are adjusting SP since we don't want to do it 488;; in two steps. Don't split FP sources for the reason listed above. 489(define_split 490 [(set (match_operand:DI 0 "register_operand") 491 (plus:DI (match_operand:DI 1 "register_operand") 492 (match_operand:DI 2 "const_int_operand")))] 493 "! add_operand (operands[2], DImode) 494 && operands[0] != stack_pointer_rtx 495 && operands[1] != frame_pointer_rtx 496 && operands[1] != arg_pointer_rtx" 497 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 498 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 499{ 500 HOST_WIDE_INT val = INTVAL (operands[2]); 501 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 502 HOST_WIDE_INT rest = val - low; 503 rtx rest_rtx = GEN_INT (rest); 504 505 operands[4] = GEN_INT (low); 506 if (satisfies_constraint_L (rest_rtx)) 507 operands[3] = rest_rtx; 508 else if (can_create_pseudo_p ()) 509 { 510 operands[3] = gen_reg_rtx (DImode); 511 emit_move_insn (operands[3], operands[2]); 512 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 513 DONE; 514 } 515 else 516 FAIL; 517}) 518 519(define_insn "*sadd<modesuffix>" 520 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 521 (plus:I48MODE 522 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r") 523 (match_operand:I48MODE 2 "const23_operand" "I,I")) 524 (match_operand:I48MODE 3 "sext_add_operand" "rI,O")))] 525 "" 526 "@ 527 s%P2add<modesuffix> %1,%3,%0 528 s%P2sub<modesuffix> %1,%n3,%0") 529 530(define_insn "*saddl_se" 531 [(set (match_operand:DI 0 "register_operand" "=r,r") 532 (sign_extend:DI 533 (plus:SI 534 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") 535 (match_operand:SI 2 "const23_operand" "I,I")) 536 (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 537 "" 538 "@ 539 s%P2addl %1,%3,%0 540 s%P2subl %1,%n3,%0") 541 542(define_split 543 [(set (match_operand:DI 0 "register_operand") 544 (sign_extend:DI 545 (plus:SI (ashift:SI (match_operator:SI 1 "comparison_operator" 546 [(match_operand 2) 547 (match_operand 3)]) 548 (match_operand:SI 4 "const23_operand")) 549 (match_operand:SI 5 "sext_add_operand")))) 550 (clobber (match_operand:DI 6 "reg_not_elim_operand"))] 551 "" 552 [(set (match_dup 6) (match_dup 7)) 553 (set (match_dup 0) 554 (sign_extend:DI (plus:SI (ashift:SI (match_dup 8) (match_dup 4)) 555 (match_dup 5))))] 556{ 557 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 558 operands[2], operands[3]); 559 operands[8] = gen_lowpart (SImode, operands[6]); 560}) 561 562(define_insn "addv<mode>3" 563 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 564 (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ") 565 (match_operand:I48MODE 2 "sext_add_operand" "rI,O"))) 566 (trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1)) 567 (sign_extend:<DWI> (match_dup 2))) 568 (sign_extend:<DWI> (plus:I48MODE (match_dup 1) 569 (match_dup 2)))) 570 (const_int 0))] 571 "" 572 "@ 573 add<modesuffix>v %r1,%2,%0 574 sub<modesuffix>v %r1,%n2,%0") 575 576(define_insn "neg<mode>2" 577 [(set (match_operand:I48MODE 0 "register_operand" "=r") 578 (neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))] 579 "" 580 "sub<modesuffix> $31,%1,%0") 581 582(define_insn "*negsi_se" 583 [(set (match_operand:DI 0 "register_operand" "=r") 584 (sign_extend:DI (neg:SI 585 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] 586 "" 587 "subl $31,%1,%0") 588 589(define_insn "negv<mode>2" 590 [(set (match_operand:I48MODE 0 "register_operand" "=r") 591 (neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r"))) 592 (trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1))) 593 (sign_extend:<DWI> (neg:I48MODE (match_dup 1)))) 594 (const_int 0))] 595 "" 596 "sub<modesuffix>v $31,%1,%0") 597 598(define_insn "sub<mode>3" 599 [(set (match_operand:I48MODE 0 "register_operand" "=r") 600 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 601 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 602 "" 603 "sub<modesuffix> %r1,%2,%0") 604 605(define_insn "*subsi_se" 606 [(set (match_operand:DI 0 "register_operand" "=r") 607 (sign_extend:DI 608 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 609 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 610 "" 611 "subl %r1,%2,%0") 612 613(define_insn "*subsi_se2" 614 [(set (match_operand:DI 0 "register_operand" "=r") 615 (sign_extend:DI 616 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 617 (match_operand:DI 2 "reg_or_8bit_operand" "rI")) 618 0)))] 619 "" 620 "subl %r1,%2,%0") 621 622(define_insn "*ssub<modesuffix>" 623 [(set (match_operand:I48MODE 0 "register_operand" "=r") 624 (minus:I48MODE 625 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r") 626 (match_operand:I48MODE 2 "const23_operand" "I")) 627 (match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))] 628 "" 629 "s%P2sub<modesuffix> %1,%3,%0") 630 631(define_insn "*ssubl_se" 632 [(set (match_operand:DI 0 "register_operand" "=r") 633 (sign_extend:DI 634 (minus:SI 635 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r") 636 (match_operand:SI 2 "const23_operand" "I")) 637 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 638 "" 639 "s%P2subl %1,%3,%0") 640 641(define_insn "subv<mode>3" 642 [(set (match_operand:I48MODE 0 "register_operand" "=r") 643 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 644 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 645 (trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1)) 646 (sign_extend:<DWI> (match_dup 2))) 647 (sign_extend:<DWI> (minus:I48MODE (match_dup 1) 648 (match_dup 2)))) 649 (const_int 0))] 650 "" 651 "sub<modesuffix>v %r1,%2,%0") 652 653(define_insn "mul<mode>3" 654 [(set (match_operand:I48MODE 0 "register_operand" "=r") 655 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 656 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 657 "" 658 "mul<modesuffix> %r1,%2,%0" 659 [(set_attr "type" "imul") 660 (set_attr "opsize" "<mode>")]) 661 662(define_insn "*mulsi_se" 663 [(set (match_operand:DI 0 "register_operand" "=r") 664 (sign_extend:DI 665 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 666 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 667 "" 668 "mull %r1,%2,%0" 669 [(set_attr "type" "imul") 670 (set_attr "opsize" "si")]) 671 672(define_insn "mulv<mode>3" 673 [(set (match_operand:I48MODE 0 "register_operand" "=r") 674 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 675 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 676 (trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1)) 677 (sign_extend:<DWI> (match_dup 2))) 678 (sign_extend:<DWI> (mult:I48MODE (match_dup 1) 679 (match_dup 2)))) 680 (const_int 0))] 681 "" 682 "mul<modesuffix>v %r1,%2,%0" 683 [(set_attr "type" "imul") 684 (set_attr "opsize" "<mode>")]) 685 686(define_expand "umuldi3_highpart" 687 [(set (match_operand:DI 0 "register_operand") 688 (truncate:DI 689 (lshiftrt:TI 690 (mult:TI (zero_extend:TI 691 (match_operand:DI 1 "register_operand")) 692 (match_operand:DI 2 "reg_or_8bit_operand")) 693 (const_int 64))))] 694 "" 695{ 696 if (REG_P (operands[2])) 697 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); 698}) 699 700(define_insn "*umuldi3_highpart_reg" 701 [(set (match_operand:DI 0 "register_operand" "=r") 702 (truncate:DI 703 (lshiftrt:TI 704 (mult:TI (zero_extend:TI 705 (match_operand:DI 1 "register_operand" "r")) 706 (zero_extend:TI 707 (match_operand:DI 2 "register_operand" "r"))) 708 (const_int 64))))] 709 "" 710 "umulh %1,%2,%0" 711 [(set_attr "type" "imul") 712 (set_attr "opsize" "udi")]) 713 714(define_insn "*umuldi3_highpart_const" 715 [(set (match_operand:DI 0 "register_operand" "=r") 716 (truncate:DI 717 (lshiftrt:TI 718 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 719 (match_operand:TI 2 "cint8_operand" "I")) 720 (const_int 64))))] 721 "" 722 "umulh %1,%2,%0" 723 [(set_attr "type" "imul") 724 (set_attr "opsize" "udi")]) 725 726(define_expand "umulditi3" 727 [(set (match_operand:TI 0 "register_operand") 728 (mult:TI 729 (zero_extend:TI (match_operand:DI 1 "reg_no_subreg_operand")) 730 (zero_extend:TI (match_operand:DI 2 "reg_no_subreg_operand"))))] 731 "" 732{ 733 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode); 734 emit_insn (gen_muldi3 (l, operands[1], operands[2])); 735 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2])); 736 emit_move_insn (gen_lowpart (DImode, operands[0]), l); 737 emit_move_insn (gen_highpart (DImode, operands[0]), h); 738 DONE; 739}) 740 741;; The divide and remainder operations take their inputs from r24 and 742;; r25, put their output in r27, and clobber r23 and r28 on all systems. 743;; 744;; ??? Force sign-extension here because some versions of OSF/1 and 745;; Interix/NT don't do the right thing if the inputs are not properly 746;; sign-extended. But Linux, for instance, does not have this 747;; problem. Is it worth the complication here to eliminate the sign 748;; extension? 749 750(define_code_iterator any_divmod [div mod udiv umod]) 751 752(define_expand "<code>si3" 753 [(set (match_dup 3) 754 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"))) 755 (set (match_dup 4) 756 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand"))) 757 (parallel [(set (match_dup 5) 758 (sign_extend:DI 759 (any_divmod:SI (match_dup 3) (match_dup 4)))) 760 (clobber (reg:DI 23)) 761 (clobber (reg:DI 28))]) 762 (set (match_operand:SI 0 "nonimmediate_operand") 763 (subreg:SI (match_dup 5) 0))] 764 "TARGET_ABI_OSF" 765{ 766 operands[3] = gen_reg_rtx (DImode); 767 operands[4] = gen_reg_rtx (DImode); 768 operands[5] = gen_reg_rtx (DImode); 769}) 770 771(define_expand "<code>di3" 772 [(parallel [(set (match_operand:DI 0 "register_operand") 773 (any_divmod:DI 774 (match_operand:DI 1 "register_operand") 775 (match_operand:DI 2 "register_operand"))) 776 (clobber (reg:DI 23)) 777 (clobber (reg:DI 28))])] 778 "TARGET_ABI_OSF") 779 780;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as 781;; expanded by the assembler. 782 783(define_insn_and_split "*divmodsi_internal_er" 784 [(set (match_operand:DI 0 "register_operand" "=c") 785 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 786 [(match_operand:DI 1 "register_operand" "a") 787 (match_operand:DI 2 "register_operand" "b")]))) 788 (clobber (reg:DI 23)) 789 (clobber (reg:DI 28))] 790 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 791 "#" 792 "&& reload_completed" 793 [(parallel [(set (match_dup 0) 794 (sign_extend:DI (match_dup 3))) 795 (use (match_dup 0)) 796 (use (match_dup 4)) 797 (clobber (reg:DI 23)) 798 (clobber (reg:DI 28))])] 799{ 800 const char *str; 801 switch (GET_CODE (operands[3])) 802 { 803 case DIV: 804 str = "__divl"; 805 break; 806 case UDIV: 807 str = "__divlu"; 808 break; 809 case MOD: 810 str = "__reml"; 811 break; 812 case UMOD: 813 str = "__remlu"; 814 break; 815 default: 816 gcc_unreachable (); 817 } 818 operands[4] = GEN_INT (alpha_next_sequence_number++); 819 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 820 gen_rtx_SYMBOL_REF (DImode, str), 821 operands[4])); 822} 823 [(set_attr "type" "jsr") 824 (set_attr "length" "8")]) 825 826(define_insn "*divmodsi_internal_er_1" 827 [(set (match_operand:DI 0 "register_operand" "=c") 828 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 829 [(match_operand:DI 1 "register_operand" "a") 830 (match_operand:DI 2 "register_operand" "b")]))) 831 (use (match_operand:DI 4 "register_operand" "c")) 832 (use (match_operand 5 "const_int_operand")) 833 (clobber (reg:DI 23)) 834 (clobber (reg:DI 28))] 835 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 836 "jsr $23,($27),__%E3%j5" 837 [(set_attr "type" "jsr") 838 (set_attr "length" "4")]) 839 840(define_insn "*divmodsi_internal" 841 [(set (match_operand:DI 0 "register_operand" "=c") 842 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 843 [(match_operand:DI 1 "register_operand" "a") 844 (match_operand:DI 2 "register_operand" "b")]))) 845 (clobber (reg:DI 23)) 846 (clobber (reg:DI 28))] 847 "TARGET_ABI_OSF" 848 "%E3 %1,%2,%0" 849 [(set_attr "type" "jsr") 850 (set_attr "length" "8")]) 851 852(define_insn_and_split "*divmoddi_internal_er" 853 [(set (match_operand:DI 0 "register_operand" "=c") 854 (match_operator:DI 3 "divmod_operator" 855 [(match_operand:DI 1 "register_operand" "a") 856 (match_operand:DI 2 "register_operand" "b")])) 857 (clobber (reg:DI 23)) 858 (clobber (reg:DI 28))] 859 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 860 "#" 861 "&& reload_completed" 862 [(parallel [(set (match_dup 0) (match_dup 3)) 863 (use (match_dup 0)) 864 (use (match_dup 4)) 865 (clobber (reg:DI 23)) 866 (clobber (reg:DI 28))])] 867{ 868 const char *str; 869 switch (GET_CODE (operands[3])) 870 { 871 case DIV: 872 str = "__divq"; 873 break; 874 case UDIV: 875 str = "__divqu"; 876 break; 877 case MOD: 878 str = "__remq"; 879 break; 880 case UMOD: 881 str = "__remqu"; 882 break; 883 default: 884 gcc_unreachable (); 885 } 886 operands[4] = GEN_INT (alpha_next_sequence_number++); 887 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 888 gen_rtx_SYMBOL_REF (DImode, str), 889 operands[4])); 890} 891 [(set_attr "type" "jsr") 892 (set_attr "length" "8")]) 893 894(define_insn "*divmoddi_internal_er_1" 895 [(set (match_operand:DI 0 "register_operand" "=c") 896 (match_operator:DI 3 "divmod_operator" 897 [(match_operand:DI 1 "register_operand" "a") 898 (match_operand:DI 2 "register_operand" "b")])) 899 (use (match_operand:DI 4 "register_operand" "c")) 900 (use (match_operand 5 "const_int_operand")) 901 (clobber (reg:DI 23)) 902 (clobber (reg:DI 28))] 903 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 904 "jsr $23,($27),__%E3%j5" 905 [(set_attr "type" "jsr") 906 (set_attr "length" "4")]) 907 908(define_insn "*divmoddi_internal" 909 [(set (match_operand:DI 0 "register_operand" "=c") 910 (match_operator:DI 3 "divmod_operator" 911 [(match_operand:DI 1 "register_operand" "a") 912 (match_operand:DI 2 "register_operand" "b")])) 913 (clobber (reg:DI 23)) 914 (clobber (reg:DI 28))] 915 "TARGET_ABI_OSF" 916 "%E3 %1,%2,%0" 917 [(set_attr "type" "jsr") 918 (set_attr "length" "8")]) 919 920;; Next are the basic logical operations. We only expose the DImode operations 921;; to the rtl expanders, but SImode versions exist for combine as well as for 922;; the atomic operation splitters. 923 924(define_insn "*andsi_internal" 925 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 926 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 927 (match_operand:SI 2 "and_operand" "rI,N,M")))] 928 "" 929 "@ 930 and %r1,%2,%0 931 bic %r1,%N2,%0 932 zapnot %r1,%m2,%0" 933 [(set_attr "type" "ilog,ilog,shift")]) 934 935(define_insn "anddi3" 936 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 937 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 938 (match_operand:DI 2 "and_operand" "rI,N,M")))] 939 "" 940 "@ 941 and %r1,%2,%0 942 bic %r1,%N2,%0 943 zapnot %r1,%m2,%0" 944 [(set_attr "type" "ilog,ilog,shift")]) 945 946;; There are times when we can split an AND into two AND insns. This occurs 947;; when we can first clear any bytes and then clear anything else. For 948;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". 949;; Only do this when running on 64-bit host since the computations are 950;; too messy otherwise. 951 952(define_split 953 [(set (match_operand:DI 0 "register_operand") 954 (and:DI (match_operand:DI 1 "register_operand") 955 (match_operand:DI 2 "const_int_operand")))] 956 "! and_operand (operands[2], DImode)" 957 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) 958 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] 959{ 960 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); 961 unsigned HOST_WIDE_INT mask2 = mask1; 962 int i; 963 964 /* For each byte that isn't all zeros, make it all ones. */ 965 for (i = 0; i < 64; i += 8) 966 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) 967 mask1 |= (HOST_WIDE_INT) 0xff << i; 968 969 /* Now turn on any bits we've just turned off. */ 970 mask2 |= ~ mask1; 971 972 operands[3] = GEN_INT (mask1); 973 operands[4] = GEN_INT (mask2); 974}) 975 976(define_insn "zero_extendqi<mode>2" 977 [(set (match_operand:I248MODE 0 "register_operand" "=r,r") 978 (zero_extend:I248MODE 979 (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] 980 "" 981 "@ 982 and %1,0xff,%0 983 ldbu %0,%1" 984 [(set_attr "type" "ilog,ild") 985 (set_attr "isa" "*,bwx")]) 986 987(define_insn "zero_extendhi<mode>2" 988 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 989 (zero_extend:I48MODE 990 (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))] 991 "" 992 "@ 993 zapnot %1,3,%0 994 ldwu %0,%1" 995 [(set_attr "type" "shift,ild") 996 (set_attr "isa" "*,bwx")]) 997 998(define_insn "zero_extendsidi2" 999 [(set (match_operand:DI 0 "register_operand" "=r") 1000 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 1001 "" 1002 "zapnot %1,15,%0" 1003 [(set_attr "type" "shift")]) 1004 1005(define_insn "andnot<mode>3" 1006 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1007 (and:I48MODE 1008 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1009 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1010 "" 1011 "bic %r2,%1,%0" 1012 [(set_attr "type" "ilog")]) 1013 1014(define_insn "*iorsi_internal" 1015 [(set (match_operand:SI 0 "register_operand" "=r,r") 1016 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1017 (match_operand:SI 2 "or_operand" "rI,N")))] 1018 "" 1019 "@ 1020 bis %r1,%2,%0 1021 ornot %r1,%N2,%0" 1022 [(set_attr "type" "ilog")]) 1023 1024(define_insn "iordi3" 1025 [(set (match_operand:DI 0 "register_operand" "=r,r") 1026 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1027 (match_operand:DI 2 "or_operand" "rI,N")))] 1028 "" 1029 "@ 1030 bis %r1,%2,%0 1031 ornot %r1,%N2,%0" 1032 [(set_attr "type" "ilog")]) 1033 1034(define_insn "*one_cmplsi_internal" 1035 [(set (match_operand:SI 0 "register_operand" "=r") 1036 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] 1037 "" 1038 "ornot $31,%1,%0" 1039 [(set_attr "type" "ilog")]) 1040 1041(define_insn "one_cmpldi2" 1042 [(set (match_operand:DI 0 "register_operand" "=r") 1043 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 1044 "" 1045 "ornot $31,%1,%0" 1046 [(set_attr "type" "ilog")]) 1047 1048(define_insn "*iornot<mode>3" 1049 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1050 (ior:I48MODE 1051 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1052 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1053 "" 1054 "ornot %r2,%1,%0" 1055 [(set_attr "type" "ilog")]) 1056 1057(define_insn "*xorsi_internal" 1058 [(set (match_operand:SI 0 "register_operand" "=r,r") 1059 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1060 (match_operand:SI 2 "or_operand" "rI,N")))] 1061 "" 1062 "@ 1063 xor %r1,%2,%0 1064 eqv %r1,%N2,%0" 1065 [(set_attr "type" "ilog")]) 1066 1067(define_insn "xordi3" 1068 [(set (match_operand:DI 0 "register_operand" "=r,r") 1069 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1070 (match_operand:DI 2 "or_operand" "rI,N")))] 1071 "" 1072 "@ 1073 xor %r1,%2,%0 1074 eqv %r1,%N2,%0" 1075 [(set_attr "type" "ilog")]) 1076 1077(define_insn "*xornot<mode>3" 1078 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1079 (not:I48MODE (xor:I48MODE 1080 (match_operand:I48MODE 1 "register_operand" "%rJ") 1081 (match_operand:I48MODE 2 "register_operand" "rI"))))] 1082 "" 1083 "eqv %r1,%2,%0" 1084 [(set_attr "type" "ilog")]) 1085 1086;; Handle FFS and related insns iff we support CIX. 1087 1088(define_expand "ffsdi2" 1089 [(set (match_dup 2) 1090 (ctz:DI (match_operand:DI 1 "register_operand"))) 1091 (set (match_dup 3) 1092 (plus:DI (match_dup 2) (const_int 1))) 1093 (set (match_operand:DI 0 "register_operand") 1094 (if_then_else:DI (eq (match_dup 1) (const_int 0)) 1095 (const_int 0) (match_dup 3)))] 1096 "TARGET_CIX" 1097{ 1098 operands[2] = gen_reg_rtx (DImode); 1099 operands[3] = gen_reg_rtx (DImode); 1100}) 1101 1102(define_insn "clzdi2" 1103 [(set (match_operand:DI 0 "register_operand" "=r") 1104 (clz:DI (match_operand:DI 1 "register_operand" "r")))] 1105 "TARGET_CIX" 1106 "ctlz %1,%0" 1107 [(set_attr "type" "mvi")]) 1108 1109(define_insn "ctzdi2" 1110 [(set (match_operand:DI 0 "register_operand" "=r") 1111 (ctz:DI (match_operand:DI 1 "register_operand" "r")))] 1112 "TARGET_CIX" 1113 "cttz %1,%0" 1114 [(set_attr "type" "mvi")]) 1115 1116(define_insn "popcountdi2" 1117 [(set (match_operand:DI 0 "register_operand" "=r") 1118 (popcount:DI (match_operand:DI 1 "register_operand" "r")))] 1119 "TARGET_CIX" 1120 "ctpop %1,%0" 1121 [(set_attr "type" "mvi")]) 1122 1123(define_expand "bswapsi2" 1124 [(set (match_operand:SI 0 "register_operand") 1125 (bswap:SI (match_operand:SI 1 "register_operand")))] 1126 "!optimize_size" 1127{ 1128 rtx t0, t1; 1129 1130 t0 = gen_reg_rtx (DImode); 1131 t1 = gen_reg_rtx (DImode); 1132 1133 emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7))); 1134 emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]), 1135 GEN_INT (24))); 1136 emit_insn (gen_iordi3 (t1, t0, t1)); 1137 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1138 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5))); 1139 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa))); 1140 emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0), 1141 gen_lowpart (SImode, t1))); 1142 DONE; 1143}) 1144 1145(define_expand "bswapdi2" 1146 [(set (match_operand:DI 0 "register_operand") 1147 (bswap:DI (match_operand:DI 1 "register_operand")))] 1148 "!optimize_size" 1149{ 1150 rtx t0, t1; 1151 1152 t0 = gen_reg_rtx (DImode); 1153 t1 = gen_reg_rtx (DImode); 1154 1155 /* This method of shifting and masking is not specific to Alpha, but 1156 is only profitable on Alpha because of our handy byte zap insn. */ 1157 1158 emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32))); 1159 emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32))); 1160 emit_insn (gen_iordi3 (t1, t0, t1)); 1161 1162 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1163 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16))); 1164 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc))); 1165 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33))); 1166 emit_insn (gen_iordi3 (t1, t0, t1)); 1167 1168 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8))); 1169 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8))); 1170 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa))); 1171 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55))); 1172 emit_insn (gen_iordi3 (operands[0], t0, t1)); 1173 DONE; 1174}) 1175 1176;; Next come the shifts and the various extract and insert operations. 1177 1178(define_insn "ashldi3" 1179 [(set (match_operand:DI 0 "register_operand" "=r,r") 1180 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 1181 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))] 1182 "" 1183{ 1184 switch (which_alternative) 1185 { 1186 case 0: 1187 if (operands[2] == const1_rtx) 1188 return "addq %r1,%r1,%0"; 1189 else 1190 return "s%P2addq %r1,0,%0"; 1191 case 1: 1192 return "sll %r1,%2,%0"; 1193 default: 1194 gcc_unreachable (); 1195 } 1196} 1197 [(set_attr "type" "iadd,shift")]) 1198 1199(define_insn "ashlsi3" 1200 [(set (match_operand:SI 0 "register_operand" "=r") 1201 (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 1202 (match_operand:SI 2 "const123_operand" "P")))] 1203 "" 1204{ 1205 if (operands[2] == const1_rtx) 1206 return "addl %r1,%r1,%0"; 1207 else 1208 return "s%P2addl %r1,0,%0"; 1209} 1210 [(set_attr "type" "iadd")]) 1211 1212(define_insn "*ashlsi_se" 1213 [(set (match_operand:DI 0 "register_operand" "=r") 1214 (sign_extend:DI 1215 (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 1216 (match_operand:SI 2 "const123_operand" "P"))))] 1217 "" 1218{ 1219 if (operands[2] == const1_rtx) 1220 return "addl %r1,%r1,%0"; 1221 else 1222 return "s%P2addl %r1,0,%0"; 1223} 1224 [(set_attr "type" "iadd")]) 1225 1226(define_insn "lshrdi3" 1227 [(set (match_operand:DI 0 "register_operand" "=r") 1228 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1229 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1230 "" 1231 "srl %r1,%2,%0" 1232 [(set_attr "type" "shift")]) 1233 1234(define_insn "ashrdi3" 1235 [(set (match_operand:DI 0 "register_operand" "=r") 1236 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1237 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1238 "" 1239 "sra %r1,%2,%0" 1240 [(set_attr "type" "shift")]) 1241 1242(define_insn "extendqi<mode>2" 1243 [(set (match_operand:I24MODE 0 "register_operand" "=r") 1244 (sign_extend:I24MODE 1245 (match_operand:QI 1 "register_operand" "r")))] 1246 "TARGET_BWX" 1247 "sextb %1,%0" 1248 [(set_attr "type" "shift")]) 1249 1250(define_expand "extendqidi2" 1251 [(set (match_operand:DI 0 "register_operand") 1252 (sign_extend:DI (match_operand:QI 1 "general_operand")))] 1253 "" 1254{ 1255 if (TARGET_BWX) 1256 operands[1] = force_reg (QImode, operands[1]); 1257 else 1258 { 1259 rtx x, t1, t2, i56; 1260 1261 if (unaligned_memory_operand (operands[1], QImode)) 1262 { 1263 x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0)); 1264 alpha_set_memflags (x, operands[1]); 1265 emit_insn (x); 1266 DONE; 1267 } 1268 1269 t1 = gen_reg_rtx (DImode); 1270 t2 = gen_reg_rtx (DImode); 1271 i56 = GEN_INT (56); 1272 1273 x = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1274 emit_move_insn (t1, x); 1275 emit_insn (gen_ashldi3 (t2, t1, i56)); 1276 emit_insn (gen_ashrdi3 (operands[0], t2, i56)); 1277 DONE; 1278 } 1279}) 1280 1281(define_insn "*extendqidi2_bwx" 1282 [(set (match_operand:DI 0 "register_operand" "=r") 1283 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))] 1284 "TARGET_BWX" 1285 "sextb %1,%0" 1286 [(set_attr "type" "shift")]) 1287 1288(define_insn "extendhisi2" 1289 [(set (match_operand:SI 0 "register_operand" "=r") 1290 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] 1291 "TARGET_BWX" 1292 "sextw %1,%0" 1293 [(set_attr "type" "shift")]) 1294 1295(define_expand "extendhidi2" 1296 [(set (match_operand:DI 0 "register_operand") 1297 (sign_extend:DI (match_operand:HI 1 "general_operand")))] 1298 "" 1299{ 1300 if (TARGET_BWX) 1301 operands[1] = force_reg (HImode, operands[1]); 1302 else 1303 { 1304 rtx x, t1, t2, i48; 1305 1306 if (unaligned_memory_operand (operands[1], HImode)) 1307 { 1308 x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0)); 1309 alpha_set_memflags (x, operands[1]); 1310 emit_insn (x); 1311 DONE; 1312 } 1313 1314 t1 = gen_reg_rtx (DImode); 1315 t2 = gen_reg_rtx (DImode); 1316 i48 = GEN_INT (48); 1317 1318 x = gen_lowpart (DImode, force_reg (HImode, operands[1])); 1319 emit_move_insn (t1, x); 1320 emit_insn (gen_ashldi3 (t2, t1, i48)); 1321 emit_insn (gen_ashrdi3 (operands[0], t2, i48)); 1322 DONE; 1323 } 1324}) 1325 1326(define_insn "*extendhidi2_bwx" 1327 [(set (match_operand:DI 0 "register_operand" "=r") 1328 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))] 1329 "TARGET_BWX" 1330 "sextw %1,%0" 1331 [(set_attr "type" "shift")]) 1332 1333;; Here's how we sign extend an unaligned byte and halfword. Doing this 1334;; as a pattern saves one instruction. The code is similar to that for 1335;; the unaligned loads (see below). 1336;; 1337;; Operand 1 is the address, operand 0 is the result. 1338 1339(define_expand "unaligned_extendqidi" 1340 [(set (match_dup 3) 1341 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1342 (set (match_dup 4) 1343 (ashift:DI (match_dup 3) 1344 (minus:DI (const_int 64) 1345 (ashift:DI 1346 (and:DI (match_dup 2) (const_int 7)) 1347 (const_int 3))))) 1348 (set (match_operand:QI 0 "register_operand") 1349 (ashiftrt:DI (match_dup 4) (const_int 56)))] 1350 "" 1351{ 1352 operands[0] = gen_lowpart (DImode, operands[0]); 1353 operands[2] = get_unaligned_offset (operands[1], 1); 1354 operands[3] = gen_reg_rtx (DImode); 1355 operands[4] = gen_reg_rtx (DImode); 1356}) 1357 1358(define_expand "unaligned_extendhidi" 1359 [(set (match_dup 3) 1360 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1361 (set (match_dup 4) 1362 (ashift:DI (match_dup 3) 1363 (minus:DI (const_int 64) 1364 (ashift:DI 1365 (and:DI (match_dup 2) (const_int 7)) 1366 (const_int 3))))) 1367 (set (match_operand:HI 0 "register_operand") 1368 (ashiftrt:DI (match_dup 4) (const_int 48)))] 1369 "" 1370{ 1371 operands[0] = gen_lowpart (DImode, operands[0]); 1372 operands[2] = get_unaligned_offset (operands[1], 2); 1373 operands[3] = gen_reg_rtx (DImode); 1374 operands[4] = gen_reg_rtx (DImode); 1375}) 1376 1377(define_insn "*extxl_const" 1378 [(set (match_operand:DI 0 "register_operand" "=r") 1379 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1380 (match_operand:DI 2 "mode_width_operand" "n") 1381 (match_operand:DI 3 "mul8_operand" "I")))] 1382 "" 1383 "ext%M2l %r1,%s3,%0" 1384 [(set_attr "type" "shift")]) 1385 1386(define_insn "extxl" 1387 [(set (match_operand:DI 0 "register_operand" "=r") 1388 (zero_extract:DI 1389 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1390 (match_operand:DI 2 "mode_width_operand" "n") 1391 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1392 (const_int 3))))] 1393 "" 1394 "ext%M2l %r1,%3,%0" 1395 [(set_attr "type" "shift")]) 1396 1397;; Combine has some strange notion of preserving existing undefined behavior 1398;; in shifts larger than a word size. So capture these patterns that it 1399;; should have turned into zero_extracts. 1400 1401(define_insn "*extxl_1" 1402 [(set (match_operand:DI 0 "register_operand" "=r") 1403 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1404 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1405 (const_int 3))) 1406 (match_operand:DI 3 "mode_mask_operand" "n")))] 1407 "" 1408 "ext%U3l %1,%2,%0" 1409 [(set_attr "type" "shift")]) 1410 1411(define_insn "*extql_2" 1412 [(set (match_operand:DI 0 "register_operand" "=r") 1413 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1414 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1415 (const_int 3))))] 1416 "" 1417 "extql %1,%2,%0" 1418 [(set_attr "type" "shift")]) 1419 1420(define_insn "extqh" 1421 [(set (match_operand:DI 0 "register_operand" "=r") 1422 (ashift:DI 1423 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1424 (minus:DI (const_int 64) 1425 (ashift:DI 1426 (and:DI 1427 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1428 (const_int 7)) 1429 (const_int 3)))))] 1430 "" 1431 "extqh %r1,%2,%0" 1432 [(set_attr "type" "shift")]) 1433 1434(define_insn "extwh" 1435 [(set (match_operand:DI 0 "register_operand" "=r") 1436 (ashift:DI 1437 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1438 (const_int 65535)) 1439 (minus:DI (const_int 64) 1440 (ashift:DI 1441 (and:DI 1442 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1443 (const_int 7)) 1444 (const_int 3)))))] 1445 "" 1446 "extwh %r1,%2,%0" 1447 [(set_attr "type" "shift")]) 1448 1449(define_insn "extlh" 1450 [(set (match_operand:DI 0 "register_operand" "=r") 1451 (ashift:DI 1452 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1453 (const_int 2147483647)) 1454 (minus:DI (const_int 64) 1455 (ashift:DI 1456 (and:DI 1457 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1458 (const_int 7)) 1459 (const_int 3)))))] 1460 "" 1461 "extlh %r1,%2,%0" 1462 [(set_attr "type" "shift")]) 1463 1464;; This converts an extXl into an extXh with an appropriate adjustment 1465;; to the address calculation. 1466 1467;;(define_split 1468;; [(set (match_operand:DI 0 "register_operand") 1469;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand") 1470;; (match_operand:DI 2 "mode_width_operand") 1471;; (ashift:DI (match_operand:DI 3) 1472;; (const_int 3))) 1473;; (match_operand:DI 4 "const_int_operand"))) 1474;; (clobber (match_operand:DI 5 "register_operand"))] 1475;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" 1476;; [(set (match_dup 5) (match_dup 6)) 1477;; (set (match_dup 0) 1478;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) 1479;; (ashift:DI (plus:DI (match_dup 5) 1480;; (match_dup 7)) 1481;; (const_int 3))) 1482;; (match_dup 4)))] 1483;; " 1484;;{ 1485;; operands[6] = plus_constant (DImode, operands[3], 1486;; INTVAL (operands[2]) / BITS_PER_UNIT); 1487;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); 1488;;}") 1489 1490(define_insn "ins<modesuffix>l_const" 1491 [(set (match_operand:DI 0 "register_operand" "=r") 1492 (ashift:DI (zero_extend:DI 1493 (match_operand:I124MODE 1 "register_operand" "r")) 1494 (match_operand:DI 2 "mul8_operand" "I")))] 1495 "" 1496 "ins<modesuffix>l %1,%s2,%0" 1497 [(set_attr "type" "shift")]) 1498 1499(define_insn "ins<modesuffix>l" 1500 [(set (match_operand:DI 0 "register_operand" "=r") 1501 (ashift:DI (zero_extend:DI 1502 (match_operand:I124MODE 1 "register_operand" "r")) 1503 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1504 (const_int 3))))] 1505 "" 1506 "ins<modesuffix>l %1,%2,%0" 1507 [(set_attr "type" "shift")]) 1508 1509(define_insn "insql" 1510 [(set (match_operand:DI 0 "register_operand" "=r") 1511 (ashift:DI (match_operand:DI 1 "register_operand" "r") 1512 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1513 (const_int 3))))] 1514 "" 1515 "insql %1,%2,%0" 1516 [(set_attr "type" "shift")]) 1517 1518;; Combine has this sometimes habit of moving the and outside of the 1519;; shift, making life more interesting. 1520 1521(define_insn "*insxl" 1522 [(set (match_operand:DI 0 "register_operand" "=r") 1523 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") 1524 (match_operand:DI 2 "mul8_operand" "I")) 1525 (match_operand:DI 3 "const_int_operand" "i")))] 1526 "((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1527 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1528 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1529 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1530 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1531 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))" 1532{ 1533 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1534 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1535 return "insbl %1,%s2,%0"; 1536 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1537 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1538 return "inswl %1,%s2,%0"; 1539 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1540 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1541 return "insll %1,%s2,%0"; 1542 1543 gcc_unreachable (); 1544} 1545 [(set_attr "type" "shift")]) 1546 1547;; We do not include the insXh insns because they are complex to express 1548;; and it does not appear that we would ever want to generate them. 1549;; 1550;; Since we need them for block moves, though, cop out and use unspec. 1551 1552(define_insn "insxh" 1553 [(set (match_operand:DI 0 "register_operand" "=r") 1554 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1555 (match_operand:DI 2 "mode_width_operand" "n") 1556 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1557 UNSPEC_INSXH))] 1558 "" 1559 "ins%M2h %1,%3,%0" 1560 [(set_attr "type" "shift")]) 1561 1562(define_insn "mskxl" 1563 [(set (match_operand:DI 0 "register_operand" "=r") 1564 (and:DI (not:DI (ashift:DI 1565 (match_operand:DI 2 "mode_mask_operand" "n") 1566 (ashift:DI 1567 (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1568 (const_int 3)))) 1569 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 1570 "" 1571 "msk%U2l %r1,%3,%0" 1572 [(set_attr "type" "shift")]) 1573 1574;; We do not include the mskXh insns because it does not appear we would 1575;; ever generate one. 1576;; 1577;; Again, we do for block moves and we use unspec again. 1578 1579(define_insn "mskxh" 1580 [(set (match_operand:DI 0 "register_operand" "=r") 1581 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1582 (match_operand:DI 2 "mode_width_operand" "n") 1583 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1584 UNSPEC_MSKXH))] 1585 "" 1586 "msk%M2h %1,%3,%0" 1587 [(set_attr "type" "shift")]) 1588 1589;; Prefer AND + NE over LSHIFTRT + AND. 1590 1591(define_insn_and_split "*ze_and_ne" 1592 [(set (match_operand:DI 0 "register_operand" "=r") 1593 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1594 (const_int 1) 1595 (match_operand 2 "const_int_operand" "I")))] 1596 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1597 "#" 1598 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1599 [(set (match_dup 0) 1600 (and:DI (match_dup 1) (match_dup 3))) 1601 (set (match_dup 0) 1602 (ne:DI (match_dup 0) (const_int 0)))] 1603 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));") 1604 1605;; Floating-point operations. All the double-precision insns can extend 1606;; from single, so indicate that. The exception are the ones that simply 1607;; play with the sign bits; it's not clear what to do there. 1608 1609(define_mode_iterator FMODE [SF DF]) 1610 1611(define_mode_attr opmode [(SF "si") (DF "di")]) 1612 1613(define_insn "abs<mode>2" 1614 [(set (match_operand:FMODE 0 "register_operand" "=f") 1615 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1616 "TARGET_FP" 1617 "cpys $f31,%R1,%0" 1618 [(set_attr "type" "fcpys")]) 1619 1620(define_insn "*nabs<mode>2" 1621 [(set (match_operand:FMODE 0 "register_operand" "=f") 1622 (neg:FMODE 1623 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))] 1624 "TARGET_FP" 1625 "cpysn $f31,%R1,%0" 1626 [(set_attr "type" "fadd")]) 1627 1628(define_expand "abstf2" 1629 [(parallel [(set (match_operand:TF 0 "register_operand") 1630 (abs:TF (match_operand:TF 1 "reg_or_0_operand"))) 1631 (use (match_dup 2))])] 1632 "TARGET_HAS_XFLOATING_LIBS" 1633 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1634 1635(define_insn_and_split "*abstf_internal" 1636 [(set (match_operand:TF 0 "register_operand" "=r") 1637 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1638 (use (match_operand:DI 2 "register_operand" "r"))] 1639 "TARGET_HAS_XFLOATING_LIBS" 1640 "#" 1641 "&& reload_completed" 1642 [(const_int 0)] 1643 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") 1644 1645(define_insn "neg<mode>2" 1646 [(set (match_operand:FMODE 0 "register_operand" "=f") 1647 (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1648 "TARGET_FP" 1649 "cpysn %R1,%R1,%0" 1650 [(set_attr "type" "fadd")]) 1651 1652(define_expand "negtf2" 1653 [(parallel [(set (match_operand:TF 0 "register_operand") 1654 (neg:TF (match_operand:TF 1 "reg_or_0_operand"))) 1655 (use (match_dup 2))])] 1656 "TARGET_HAS_XFLOATING_LIBS" 1657 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1658 1659(define_insn_and_split "*negtf_internal" 1660 [(set (match_operand:TF 0 "register_operand" "=r") 1661 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1662 (use (match_operand:DI 2 "register_operand" "r"))] 1663 "TARGET_HAS_XFLOATING_LIBS" 1664 "#" 1665 "&& reload_completed" 1666 [(const_int 0)] 1667 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") 1668 1669(define_insn "copysign<mode>3" 1670 [(set (match_operand:FMODE 0 "register_operand" "=f") 1671 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1672 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1673 UNSPEC_COPYSIGN))] 1674 "TARGET_FP" 1675 "cpys %R2,%R1,%0" 1676 [(set_attr "type" "fadd")]) 1677 1678(define_insn "*ncopysign<mode>3" 1679 [(set (match_operand:FMODE 0 "register_operand" "=f") 1680 (neg:FMODE 1681 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1682 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1683 UNSPEC_COPYSIGN)))] 1684 "TARGET_FP" 1685 "cpysn %R2,%R1,%0" 1686 [(set_attr "type" "fadd")]) 1687 1688(define_insn "add<mode>3" 1689 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1690 (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1691 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1692 "TARGET_FP" 1693 "add<modesuffix>%/ %R1,%R2,%0" 1694 [(set_attr "type" "fadd") 1695 (set_attr "trap" "yes") 1696 (set_attr "round_suffix" "normal") 1697 (set_attr "trap_suffix" "u_su_sui") 1698 (set (attr "enabled") 1699 (cond [(eq_attr "alternative" "0") 1700 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1701 ] 1702 (symbol_ref "true")))]) 1703 1704(define_insn "*adddf_ext1" 1705 [(set (match_operand:DF 0 "register_operand" "=f") 1706 (plus:DF (float_extend:DF 1707 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1708 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1709 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1710 "add%-%/ %R1,%R2,%0" 1711 [(set_attr "type" "fadd") 1712 (set_attr "trap" "yes") 1713 (set_attr "round_suffix" "normal") 1714 (set_attr "trap_suffix" "u_su_sui")]) 1715 1716(define_insn "*adddf_ext2" 1717 [(set (match_operand:DF 0 "register_operand" "=f") 1718 (plus:DF (float_extend:DF 1719 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1720 (float_extend:DF 1721 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1722 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1723 "add%-%/ %R1,%R2,%0" 1724 [(set_attr "type" "fadd") 1725 (set_attr "trap" "yes") 1726 (set_attr "round_suffix" "normal") 1727 (set_attr "trap_suffix" "u_su_sui")]) 1728 1729(define_expand "addtf3" 1730 [(use (match_operand:TF 0 "register_operand")) 1731 (use (match_operand:TF 1 "general_operand")) 1732 (use (match_operand:TF 2 "general_operand"))] 1733 "TARGET_HAS_XFLOATING_LIBS" 1734 "alpha_emit_xfloating_arith (PLUS, operands); DONE;") 1735 1736(define_insn "sub<mode>3" 1737 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1738 (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1739 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1740 "TARGET_FP" 1741 "sub<modesuffix>%/ %R1,%R2,%0" 1742 [(set_attr "type" "fadd") 1743 (set_attr "trap" "yes") 1744 (set_attr "round_suffix" "normal") 1745 (set_attr "trap_suffix" "u_su_sui") 1746 (set (attr "enabled") 1747 (cond [(eq_attr "alternative" "0") 1748 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1749 ] 1750 (symbol_ref "true")))]) 1751 1752(define_insn "*subdf_ext1" 1753 [(set (match_operand:DF 0 "register_operand" "=f") 1754 (minus:DF (float_extend:DF 1755 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1756 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1757 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1758 "sub%-%/ %R1,%R2,%0" 1759 [(set_attr "type" "fadd") 1760 (set_attr "trap" "yes") 1761 (set_attr "round_suffix" "normal") 1762 (set_attr "trap_suffix" "u_su_sui")]) 1763 1764(define_insn "*subdf_ext2" 1765 [(set (match_operand:DF 0 "register_operand" "=f") 1766 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1767 (float_extend:DF 1768 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1769 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1770 "sub%-%/ %R1,%R2,%0" 1771 [(set_attr "type" "fadd") 1772 (set_attr "trap" "yes") 1773 (set_attr "round_suffix" "normal") 1774 (set_attr "trap_suffix" "u_su_sui")]) 1775 1776(define_insn "*subdf_ext3" 1777 [(set (match_operand:DF 0 "register_operand" "=f") 1778 (minus:DF (float_extend:DF 1779 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1780 (float_extend:DF 1781 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1782 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1783 "sub%-%/ %R1,%R2,%0" 1784 [(set_attr "type" "fadd") 1785 (set_attr "trap" "yes") 1786 (set_attr "round_suffix" "normal") 1787 (set_attr "trap_suffix" "u_su_sui")]) 1788 1789(define_expand "subtf3" 1790 [(use (match_operand:TF 0 "register_operand")) 1791 (use (match_operand:TF 1 "general_operand")) 1792 (use (match_operand:TF 2 "general_operand"))] 1793 "TARGET_HAS_XFLOATING_LIBS" 1794 "alpha_emit_xfloating_arith (MINUS, operands); DONE;") 1795 1796(define_insn "mul<mode>3" 1797 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1798 (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1799 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1800 "TARGET_FP" 1801 "mul<modesuffix>%/ %R1,%R2,%0" 1802 [(set_attr "type" "fmul") 1803 (set_attr "trap" "yes") 1804 (set_attr "round_suffix" "normal") 1805 (set_attr "trap_suffix" "u_su_sui") 1806 (set (attr "enabled") 1807 (cond [(eq_attr "alternative" "0") 1808 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1809 ] 1810 (symbol_ref "true")))]) 1811 1812(define_insn "*muldf_ext1" 1813 [(set (match_operand:DF 0 "register_operand" "=f") 1814 (mult:DF (float_extend:DF 1815 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1816 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1817 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1818 "mul%-%/ %R1,%R2,%0" 1819 [(set_attr "type" "fmul") 1820 (set_attr "trap" "yes") 1821 (set_attr "round_suffix" "normal") 1822 (set_attr "trap_suffix" "u_su_sui")]) 1823 1824(define_insn "*muldf_ext2" 1825 [(set (match_operand:DF 0 "register_operand" "=f") 1826 (mult:DF (float_extend:DF 1827 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1828 (float_extend:DF 1829 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1830 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1831 "mul%-%/ %R1,%R2,%0" 1832 [(set_attr "type" "fmul") 1833 (set_attr "trap" "yes") 1834 (set_attr "round_suffix" "normal") 1835 (set_attr "trap_suffix" "u_su_sui")]) 1836 1837(define_expand "multf3" 1838 [(use (match_operand:TF 0 "register_operand")) 1839 (use (match_operand:TF 1 "general_operand")) 1840 (use (match_operand:TF 2 "general_operand"))] 1841 "TARGET_HAS_XFLOATING_LIBS" 1842 "alpha_emit_xfloating_arith (MULT, operands); DONE;") 1843 1844(define_insn "div<mode>3" 1845 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1846 (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1847 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1848 "TARGET_FP" 1849 "div<modesuffix>%/ %R1,%R2,%0" 1850 [(set_attr "type" "fdiv") 1851 (set_attr "opsize" "<opmode>") 1852 (set_attr "trap" "yes") 1853 (set_attr "round_suffix" "normal") 1854 (set_attr "trap_suffix" "u_su_sui") 1855 (set (attr "enabled") 1856 (cond [(eq_attr "alternative" "0") 1857 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1858 ] 1859 (symbol_ref "true")))]) 1860 1861(define_insn "*divdf_ext1" 1862 [(set (match_operand:DF 0 "register_operand" "=f") 1863 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) 1864 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1865 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1866 "div%-%/ %R1,%R2,%0" 1867 [(set_attr "type" "fdiv") 1868 (set_attr "trap" "yes") 1869 (set_attr "round_suffix" "normal") 1870 (set_attr "trap_suffix" "u_su_sui")]) 1871 1872(define_insn "*divdf_ext2" 1873 [(set (match_operand:DF 0 "register_operand" "=f") 1874 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1875 (float_extend:DF 1876 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1877 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1878 "div%-%/ %R1,%R2,%0" 1879 [(set_attr "type" "fdiv") 1880 (set_attr "trap" "yes") 1881 (set_attr "round_suffix" "normal") 1882 (set_attr "trap_suffix" "u_su_sui")]) 1883 1884(define_insn "*divdf_ext3" 1885 [(set (match_operand:DF 0 "register_operand" "=f") 1886 (div:DF (float_extend:DF 1887 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1888 (float_extend:DF 1889 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1890 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1891 "div%-%/ %R1,%R2,%0" 1892 [(set_attr "type" "fdiv") 1893 (set_attr "trap" "yes") 1894 (set_attr "round_suffix" "normal") 1895 (set_attr "trap_suffix" "u_su_sui")]) 1896 1897(define_expand "divtf3" 1898 [(use (match_operand:TF 0 "register_operand")) 1899 (use (match_operand:TF 1 "general_operand")) 1900 (use (match_operand:TF 2 "general_operand"))] 1901 "TARGET_HAS_XFLOATING_LIBS" 1902 "alpha_emit_xfloating_arith (DIV, operands); DONE;") 1903 1904(define_insn "sqrt<mode>2" 1905 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1906 (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")))] 1907 "TARGET_FP && TARGET_FIX" 1908 "sqrt<modesuffix>%/ %R1,%0" 1909 [(set_attr "type" "fsqrt") 1910 (set_attr "opsize" "<opmode>") 1911 (set_attr "trap" "yes") 1912 (set_attr "round_suffix" "normal") 1913 (set_attr "trap_suffix" "u_su_sui") 1914 (set (attr "enabled") 1915 (cond [(eq_attr "alternative" "0") 1916 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1917 ] 1918 (symbol_ref "true")))]) 1919 1920;; Define conversion operators between DFmode and SImode, using the cvtql 1921;; instruction. To allow combine et al to do useful things, we keep the 1922;; operation as a unit until after reload, at which point we split the 1923;; instructions. 1924;; 1925;; Note that we (attempt to) only consider this optimization when the 1926;; ultimate destination is memory. If we will be doing further integer 1927;; processing, it is cheaper to do the truncation in the int regs. 1928 1929(define_insn "*cvtql" 1930 [(set (match_operand:SF 0 "register_operand" "=f") 1931 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")] 1932 UNSPEC_CVTQL))] 1933 "TARGET_FP" 1934 "cvtql%/ %R1,%0" 1935 [(set_attr "type" "fadd") 1936 (set_attr "trap" "yes") 1937 (set_attr "trap_suffix" "v_sv")]) 1938 1939(define_insn_and_split "*fix_truncdfsi_ieee" 1940 [(set (match_operand:SI 0 "memory_operand" "=m") 1941 (subreg:SI 1942 (match_operator:DI 4 "fix_operator" 1943 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1944 (clobber (match_scratch:DI 2 "=&f")) 1945 (clobber (match_scratch:SF 3 "=&f"))] 1946 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1947 "#" 1948 "&& reload_completed" 1949 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)])) 1950 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1951 (set (match_dup 5) (match_dup 3))] 1952{ 1953 operands[5] = adjust_address (operands[0], SFmode, 0); 1954} 1955 [(set_attr "type" "fadd") 1956 (set_attr "trap" "yes")]) 1957 1958(define_insn_and_split "*fix_truncdfsi_internal" 1959 [(set (match_operand:SI 0 "memory_operand" "=m") 1960 (subreg:SI 1961 (match_operator:DI 3 "fix_operator" 1962 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1963 (clobber (match_scratch:DI 2 "=f"))] 1964 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1965 "#" 1966 "&& reload_completed" 1967 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)])) 1968 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1969 (set (match_dup 5) (match_dup 4))] 1970{ 1971 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 1972 operands[5] = adjust_address (operands[0], SFmode, 0); 1973} 1974 [(set_attr "type" "fadd") 1975 (set_attr "trap" "yes")]) 1976 1977(define_insn "*fix_truncdfdi2" 1978 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 1979 (match_operator:DI 2 "fix_operator" 1980 [(match_operand:DF 1 "reg_or_0_operand" "fG,fG")]))] 1981 "TARGET_FP" 1982 "cvt%-q%/ %R1,%0" 1983 [(set_attr "type" "fadd") 1984 (set_attr "trap" "yes") 1985 (set_attr "round_suffix" "c") 1986 (set_attr "trap_suffix" "v_sv_svi") 1987 (set (attr "enabled") 1988 (cond [(eq_attr "alternative" "0") 1989 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1990 ] 1991 (symbol_ref "true")))]) 1992 1993(define_expand "fix_truncdfdi2" 1994 [(set (match_operand:DI 0 "reg_no_subreg_operand") 1995 (fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 1996 "TARGET_FP") 1997 1998(define_expand "fixuns_truncdfdi2" 1999 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2000 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2001 "TARGET_FP") 2002 2003;; Likewise between SFmode and SImode. 2004 2005(define_insn_and_split "*fix_truncsfsi_ieee" 2006 [(set (match_operand:SI 0 "memory_operand" "=m") 2007 (subreg:SI 2008 (match_operator:DI 4 "fix_operator" 2009 [(float_extend:DF 2010 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2011 (clobber (match_scratch:DI 2 "=&f")) 2012 (clobber (match_scratch:SF 3 "=&f"))] 2013 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2014 "#" 2015 "&& reload_completed" 2016 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))])) 2017 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2018 (set (match_dup 5) (match_dup 3))] 2019 "operands[5] = adjust_address (operands[0], SFmode, 0);" 2020 [(set_attr "type" "fadd") 2021 (set_attr "trap" "yes")]) 2022 2023(define_insn_and_split "*fix_truncsfsi_internal" 2024 [(set (match_operand:SI 0 "memory_operand" "=m") 2025 (subreg:SI 2026 (match_operator:DI 3 "fix_operator" 2027 [(float_extend:DF 2028 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2029 (clobber (match_scratch:DI 2 "=f"))] 2030 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2031 "#" 2032 "&& reload_completed" 2033 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))])) 2034 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2035 (set (match_dup 5) (match_dup 4))] 2036{ 2037 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2038 operands[5] = adjust_address (operands[0], SFmode, 0); 2039} 2040 [(set_attr "type" "fadd") 2041 (set_attr "trap" "yes")]) 2042 2043(define_insn "*fix_truncsfdi2" 2044 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 2045 (match_operator:DI 2 "fix_operator" 2046 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,fG"))]))] 2047 "TARGET_FP" 2048 "cvt%-q%/ %R1,%0" 2049 [(set_attr "type" "fadd") 2050 (set_attr "trap" "yes") 2051 (set_attr "round_suffix" "c") 2052 (set_attr "trap_suffix" "v_sv_svi") 2053 (set (attr "enabled") 2054 (cond [(eq_attr "alternative" "0") 2055 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2056 ] 2057 (symbol_ref "true")))]) 2058 2059(define_expand "fix_truncsfdi2" 2060 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2061 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2062 "TARGET_FP") 2063 2064(define_expand "fixuns_truncsfdi2" 2065 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2066 (unsigned_fix:DI 2067 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2068 "TARGET_FP") 2069 2070(define_expand "fix_trunctfdi2" 2071 [(use (match_operand:DI 0 "register_operand")) 2072 (use (match_operand:TF 1 "general_operand"))] 2073 "TARGET_HAS_XFLOATING_LIBS" 2074 "alpha_emit_xfloating_cvt (FIX, operands); DONE;") 2075 2076(define_expand "fixuns_trunctfdi2" 2077 [(use (match_operand:DI 0 "register_operand")) 2078 (use (match_operand:TF 1 "general_operand"))] 2079 "TARGET_HAS_XFLOATING_LIBS" 2080 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;") 2081 2082(define_insn "floatdisf2" 2083 [(set (match_operand:SF 0 "register_operand" "=f,&f") 2084 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2085 "TARGET_FP" 2086 "cvtq%,%/ %1,%0" 2087 [(set_attr "type" "fadd") 2088 (set_attr "trap" "yes") 2089 (set_attr "round_suffix" "normal") 2090 (set_attr "trap_suffix" "sui") 2091 (set (attr "enabled") 2092 (cond [(eq_attr "alternative" "0") 2093 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2094 ] 2095 (symbol_ref "true")))]) 2096 2097(define_insn_and_split "*floatsisf2_ieee" 2098 [(set (match_operand:SF 0 "register_operand" "=&f") 2099 (float:SF (match_operand:SI 1 "memory_operand" "m"))) 2100 (clobber (match_scratch:DI 2 "=&f")) 2101 (clobber (match_scratch:SF 3 "=&f"))] 2102 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2103 "#" 2104 "&& reload_completed" 2105 [(set (match_dup 3) (match_dup 1)) 2106 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2107 (set (match_dup 0) (float:SF (match_dup 2)))] 2108 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2109 2110(define_insn_and_split "*floatsisf2" 2111 [(set (match_operand:SF 0 "register_operand" "=f") 2112 (float:SF (match_operand:SI 1 "memory_operand" "m")))] 2113 "TARGET_FP" 2114 "#" 2115 "&& reload_completed" 2116 [(set (match_dup 0) (match_dup 1)) 2117 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ)) 2118 (set (match_dup 0) (float:SF (match_dup 2)))] 2119{ 2120 operands[1] = adjust_address (operands[1], SFmode, 0); 2121 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2122}) 2123 2124(define_insn "floatdidf2" 2125 [(set (match_operand:DF 0 "register_operand" "=f,&f") 2126 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2127 "TARGET_FP" 2128 "cvtq%-%/ %1,%0" 2129 [(set_attr "type" "fadd") 2130 (set_attr "trap" "yes") 2131 (set_attr "round_suffix" "normal") 2132 (set_attr "trap_suffix" "sui") 2133 (set (attr "enabled") 2134 (cond [(eq_attr "alternative" "0") 2135 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2136 ] 2137 (symbol_ref "true")))]) 2138 2139(define_insn_and_split "*floatsidf2_ieee" 2140 [(set (match_operand:DF 0 "register_operand" "=&f") 2141 (float:DF (match_operand:SI 1 "memory_operand" "m"))) 2142 (clobber (match_scratch:DI 2 "=&f")) 2143 (clobber (match_scratch:SF 3 "=&f"))] 2144 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2145 "#" 2146 "&& reload_completed" 2147 [(set (match_dup 3) (match_dup 1)) 2148 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2149 (set (match_dup 0) (float:DF (match_dup 2)))] 2150 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2151 2152(define_insn_and_split "*floatsidf2" 2153 [(set (match_operand:DF 0 "register_operand" "=f") 2154 (float:DF (match_operand:SI 1 "memory_operand" "m")))] 2155 "TARGET_FP" 2156 "#" 2157 "&& reload_completed" 2158 [(set (match_dup 3) (match_dup 1)) 2159 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2160 (set (match_dup 0) (float:DF (match_dup 2)))] 2161{ 2162 operands[1] = adjust_address (operands[1], SFmode, 0); 2163 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2164 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0])); 2165}) 2166 2167(define_expand "floatditf2" 2168 [(use (match_operand:TF 0 "register_operand")) 2169 (use (match_operand:DI 1 "general_operand"))] 2170 "TARGET_HAS_XFLOATING_LIBS" 2171 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;") 2172 2173(define_expand "floatunsdisf2" 2174 [(use (match_operand:SF 0 "register_operand")) 2175 (use (match_operand:DI 1 "register_operand"))] 2176 "TARGET_FP" 2177 "alpha_emit_floatuns (operands); DONE;") 2178 2179(define_expand "floatunsdidf2" 2180 [(use (match_operand:DF 0 "register_operand")) 2181 (use (match_operand:DI 1 "register_operand"))] 2182 "TARGET_FP" 2183 "alpha_emit_floatuns (operands); DONE;") 2184 2185(define_expand "floatunsditf2" 2186 [(use (match_operand:TF 0 "register_operand")) 2187 (use (match_operand:DI 1 "general_operand"))] 2188 "TARGET_HAS_XFLOATING_LIBS" 2189 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;") 2190 2191(define_expand "extendsfdf2" 2192 [(set (match_operand:DF 0 "register_operand") 2193 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))] 2194 "TARGET_FP" 2195{ 2196 if (alpha_fptm >= ALPHA_FPTM_SU) 2197 operands[1] = force_reg (SFmode, operands[1]); 2198}) 2199 2200;; The Unicos/Mk assembler doesn't support cvtst, but we've already 2201;; asserted that alpha_fptm == ALPHA_FPTM_N. 2202 2203(define_insn "*extendsfdf2_ieee" 2204 [(set (match_operand:DF 0 "register_operand" "=&f") 2205 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 2206 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2207 "cvtsts %1,%0" 2208 [(set_attr "type" "fadd") 2209 (set_attr "trap" "yes")]) 2210 2211(define_insn "*extendsfdf2_internal" 2212 [(set (match_operand:DF 0 "register_operand" "=f,f,m") 2213 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))] 2214 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2215 "@ 2216 cpys %1,%1,%0 2217 ld%, %0,%1 2218 st%- %1,%0" 2219 [(set_attr "type" "fcpys,fld,fst")]) 2220 2221;; Use register_operand for operand 1 to prevent compress_float_constant 2222;; from doing something silly. When optimizing we'll put things back 2223;; together anyway. 2224(define_expand "extendsftf2" 2225 [(use (match_operand:TF 0 "register_operand")) 2226 (use (match_operand:SF 1 "register_operand"))] 2227 "TARGET_HAS_XFLOATING_LIBS" 2228{ 2229 rtx tmp = gen_reg_rtx (DFmode); 2230 emit_insn (gen_extendsfdf2 (tmp, operands[1])); 2231 emit_insn (gen_extenddftf2 (operands[0], tmp)); 2232 DONE; 2233}) 2234 2235(define_expand "extenddftf2" 2236 [(use (match_operand:TF 0 "register_operand")) 2237 (use (match_operand:DF 1 "register_operand"))] 2238 "TARGET_HAS_XFLOATING_LIBS" 2239 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;") 2240 2241(define_insn "truncdfsf2" 2242 [(set (match_operand:SF 0 "register_operand" "=f,&f") 2243 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG,fG")))] 2244 "TARGET_FP" 2245 "cvt%-%,%/ %R1,%0" 2246 [(set_attr "type" "fadd") 2247 (set_attr "trap" "yes") 2248 (set_attr "round_suffix" "normal") 2249 (set_attr "trap_suffix" "u_su_sui") 2250 (set (attr "enabled") 2251 (cond [(eq_attr "alternative" "0") 2252 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2253 ] 2254 (symbol_ref "true")))]) 2255 2256(define_expand "trunctfdf2" 2257 [(use (match_operand:DF 0 "register_operand")) 2258 (use (match_operand:TF 1 "general_operand"))] 2259 "TARGET_HAS_XFLOATING_LIBS" 2260 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;") 2261 2262(define_expand "trunctfsf2" 2263 [(use (match_operand:SF 0 "register_operand")) 2264 (use (match_operand:TF 1 "general_operand"))] 2265 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS" 2266{ 2267 rtx tmpf, sticky, arg, lo, hi; 2268 2269 tmpf = gen_reg_rtx (DFmode); 2270 sticky = gen_reg_rtx (DImode); 2271 arg = copy_to_mode_reg (TFmode, operands[1]); 2272 lo = gen_lowpart (DImode, arg); 2273 hi = gen_highpart (DImode, arg); 2274 2275 /* Convert the low word of the TFmode value into a sticky rounding bit, 2276 then or it into the low bit of the high word. This leaves the sticky 2277 bit at bit 48 of the fraction, which is representable in DFmode, 2278 which prevents rounding error in the final conversion to SFmode. */ 2279 2280 emit_insn (gen_rtx_SET (sticky, gen_rtx_NE (DImode, lo, const0_rtx))); 2281 emit_insn (gen_iordi3 (hi, hi, sticky)); 2282 emit_insn (gen_trunctfdf2 (tmpf, arg)); 2283 emit_insn (gen_truncdfsf2 (operands[0], tmpf)); 2284 DONE; 2285}) 2286 2287;; Next are all the integer comparisons, and conditional moves and branches 2288;; and some of the related define_expand's and define_split's. 2289 2290(define_insn "*setcc_internal" 2291 [(set (match_operand 0 "register_operand" "=r") 2292 (match_operator 1 "alpha_comparison_operator" 2293 [(match_operand:DI 2 "register_operand" "r") 2294 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] 2295 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2296 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2297 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2298 "cmp%C1 %2,%3,%0" 2299 [(set_attr "type" "icmp")]) 2300 2301;; Yes, we can technically support reg_or_8bit_operand in operand 2, 2302;; but that's non-canonical rtl and allowing that causes inefficiencies 2303;; from cse on. 2304(define_insn "*setcc_swapped_internal" 2305 [(set (match_operand 0 "register_operand" "=r") 2306 (match_operator 1 "alpha_swapped_comparison_operator" 2307 [(match_operand:DI 2 "register_operand" "r") 2308 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))] 2309 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2310 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2311 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2312 "cmp%c1 %r3,%2,%0" 2313 [(set_attr "type" "icmp")]) 2314 2315;; Use match_operator rather than ne directly so that we can match 2316;; multiple integer modes. 2317(define_insn "*setne_internal" 2318 [(set (match_operand 0 "register_operand" "=r") 2319 (match_operator 1 "signed_comparison_operator" 2320 [(match_operand:DI 2 "register_operand" "r") 2321 (const_int 0)]))] 2322 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2323 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2324 && GET_CODE (operands[1]) == NE 2325 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2326 "cmpult $31,%2,%0" 2327 [(set_attr "type" "icmp")]) 2328 2329;; The mode folding trick can't be used with const_int operands, since 2330;; reload needs to know the proper mode. 2331;; 2332;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand 2333;; in order to create more pairs of constants. As long as we're allowing 2334;; two constants at the same time, and will have to reload one of them... 2335 2336(define_insn "*mov<mode>cc_internal" 2337 [(set (match_operand:IMODE 0 "register_operand" "=r,r,r,r") 2338 (if_then_else:IMODE 2339 (match_operator 2 "signed_comparison_operator" 2340 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 2341 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 2342 (match_operand:IMODE 1 "add_operand" "rI,0,rI,0") 2343 (match_operand:IMODE 5 "add_operand" "0,rI,0,rI")))] 2344 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)" 2345 "@ 2346 cmov%C2 %r3,%1,%0 2347 cmov%D2 %r3,%5,%0 2348 cmov%c2 %r4,%1,%0 2349 cmov%d2 %r4,%5,%0" 2350 [(set_attr "type" "icmov")]) 2351 2352(define_insn "*mov<mode>cc_lbc" 2353 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2354 (if_then_else:IMODE 2355 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2356 (const_int 1) 2357 (const_int 0)) 2358 (const_int 0)) 2359 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2360 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2361 "" 2362 "@ 2363 cmovlbc %r2,%1,%0 2364 cmovlbs %r2,%3,%0" 2365 [(set_attr "type" "icmov")]) 2366 2367(define_insn "*mov<mode>cc_lbs" 2368 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2369 (if_then_else:IMODE 2370 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2371 (const_int 1) 2372 (const_int 0)) 2373 (const_int 0)) 2374 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2375 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2376 "" 2377 "@ 2378 cmovlbs %r2,%1,%0 2379 cmovlbc %r2,%3,%0" 2380 [(set_attr "type" "icmov")]) 2381 2382;; For ABS, we have two choices, depending on whether the input and output 2383;; registers are the same or not. 2384(define_expand "absdi2" 2385 [(set (match_operand:DI 0 "register_operand") 2386 (abs:DI (match_operand:DI 1 "register_operand")))] 2387 "" 2388{ 2389 if (rtx_equal_p (operands[0], operands[1])) 2390 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); 2391 else 2392 emit_insn (gen_absdi2_diff (operands[0], operands[1])); 2393 DONE; 2394}) 2395 2396(define_expand "absdi2_same" 2397 [(set (match_operand:DI 1 "register_operand") 2398 (neg:DI (match_operand:DI 0 "register_operand"))) 2399 (set (match_dup 0) 2400 (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2401 (match_dup 0) 2402 (match_dup 1)))]) 2403 2404(define_expand "absdi2_diff" 2405 [(set (match_operand:DI 0 "register_operand") 2406 (neg:DI (match_operand:DI 1 "register_operand"))) 2407 (set (match_dup 0) 2408 (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2409 (match_dup 0) 2410 (match_dup 1)))]) 2411 2412(define_split 2413 [(set (match_operand:DI 0 "register_operand") 2414 (abs:DI (match_dup 0))) 2415 (clobber (match_operand:DI 1 "register_operand"))] 2416 "" 2417 [(set (match_dup 1) (neg:DI (match_dup 0))) 2418 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2419 (match_dup 0) (match_dup 1)))]) 2420 2421(define_split 2422 [(set (match_operand:DI 0 "register_operand") 2423 (abs:DI (match_operand:DI 1 "register_operand")))] 2424 "! rtx_equal_p (operands[0], operands[1])" 2425 [(set (match_dup 0) (neg:DI (match_dup 1))) 2426 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2427 (match_dup 0) (match_dup 1)))]) 2428 2429(define_split 2430 [(set (match_operand:DI 0 "register_operand") 2431 (neg:DI (abs:DI (match_dup 0)))) 2432 (clobber (match_operand:DI 1 "register_operand"))] 2433 "" 2434 [(set (match_dup 1) (neg:DI (match_dup 0))) 2435 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) 2436 (match_dup 0) (match_dup 1)))]) 2437 2438(define_split 2439 [(set (match_operand:DI 0 "register_operand") 2440 (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))] 2441 "! rtx_equal_p (operands[0], operands[1])" 2442 [(set (match_dup 0) (neg:DI (match_dup 1))) 2443 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) 2444 (match_dup 0) (match_dup 1)))]) 2445 2446(define_insn "<code><mode>3" 2447 [(set (match_operand:I12MODE 0 "register_operand" "=r") 2448 (any_maxmin:I12MODE 2449 (match_operand:I12MODE 1 "reg_or_0_operand" "%rJ") 2450 (match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))] 2451 "TARGET_MAX" 2452 "<maxmin><vecmodesuffix> %r1,%2,%0" 2453 [(set_attr "type" "mvi")]) 2454 2455(define_expand "smaxdi3" 2456 [(set (match_dup 3) 2457 (le:DI (match_operand:DI 1 "reg_or_0_operand") 2458 (match_operand:DI 2 "reg_or_8bit_operand"))) 2459 (set (match_operand:DI 0 "register_operand") 2460 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2461 (match_dup 1) (match_dup 2)))] 2462 "" 2463 "operands[3] = gen_reg_rtx (DImode);") 2464 2465(define_split 2466 [(set (match_operand:DI 0 "register_operand") 2467 (smax:DI (match_operand:DI 1 "reg_or_0_operand") 2468 (match_operand:DI 2 "reg_or_8bit_operand"))) 2469 (clobber (match_operand:DI 3 "register_operand"))] 2470 "operands[2] != const0_rtx" 2471 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) 2472 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2473 (match_dup 1) (match_dup 2)))]) 2474 2475(define_insn "*smax_const0" 2476 [(set (match_operand:DI 0 "register_operand" "=r") 2477 (smax:DI (match_operand:DI 1 "register_operand" "0") 2478 (const_int 0)))] 2479 "" 2480 "cmovlt %0,0,%0" 2481 [(set_attr "type" "icmov")]) 2482 2483(define_expand "smindi3" 2484 [(set (match_dup 3) 2485 (lt:DI (match_operand:DI 1 "reg_or_0_operand") 2486 (match_operand:DI 2 "reg_or_8bit_operand"))) 2487 (set (match_operand:DI 0 "register_operand") 2488 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2489 (match_dup 1) (match_dup 2)))] 2490 "" 2491 "operands[3] = gen_reg_rtx (DImode);") 2492 2493(define_split 2494 [(set (match_operand:DI 0 "register_operand") 2495 (smin:DI (match_operand:DI 1 "reg_or_0_operand") 2496 (match_operand:DI 2 "reg_or_8bit_operand"))) 2497 (clobber (match_operand:DI 3 "register_operand"))] 2498 "operands[2] != const0_rtx" 2499 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) 2500 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2501 (match_dup 1) (match_dup 2)))]) 2502 2503(define_insn "*smin_const0" 2504 [(set (match_operand:DI 0 "register_operand" "=r") 2505 (smin:DI (match_operand:DI 1 "register_operand" "0") 2506 (const_int 0)))] 2507 "" 2508 "cmovgt %0,0,%0" 2509 [(set_attr "type" "icmov")]) 2510 2511(define_expand "umaxdi3" 2512 [(set (match_dup 3) 2513 (leu:DI (match_operand:DI 1 "reg_or_0_operand") 2514 (match_operand:DI 2 "reg_or_8bit_operand"))) 2515 (set (match_operand:DI 0 "register_operand") 2516 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2517 (match_dup 1) (match_dup 2)))] 2518 "" 2519 "operands[3] = gen_reg_rtx (DImode);") 2520 2521(define_split 2522 [(set (match_operand:DI 0 "register_operand") 2523 (umax:DI (match_operand:DI 1 "reg_or_0_operand") 2524 (match_operand:DI 2 "reg_or_8bit_operand"))) 2525 (clobber (match_operand:DI 3 "register_operand"))] 2526 "operands[2] != const0_rtx" 2527 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) 2528 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2529 (match_dup 1) (match_dup 2)))]) 2530 2531(define_expand "umindi3" 2532 [(set (match_dup 3) 2533 (ltu:DI (match_operand:DI 1 "reg_or_0_operand") 2534 (match_operand:DI 2 "reg_or_8bit_operand"))) 2535 (set (match_operand:DI 0 "register_operand") 2536 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2537 (match_dup 1) (match_dup 2)))] 2538 "" 2539 "operands[3] = gen_reg_rtx (DImode);") 2540 2541(define_split 2542 [(set (match_operand:DI 0 "register_operand") 2543 (umin:DI (match_operand:DI 1 "reg_or_0_operand") 2544 (match_operand:DI 2 "reg_or_8bit_operand"))) 2545 (clobber (match_operand:DI 3 "register_operand"))] 2546 "operands[2] != const0_rtx" 2547 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) 2548 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2549 (match_dup 1) (match_dup 2)))]) 2550 2551(define_insn "*bcc_normal" 2552 [(set (pc) 2553 (if_then_else 2554 (match_operator 1 "signed_comparison_operator" 2555 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 2556 (const_int 0)]) 2557 (label_ref (match_operand 0)) 2558 (pc)))] 2559 "" 2560 "b%C1 %r2,%0" 2561 [(set_attr "type" "ibr")]) 2562 2563(define_insn "*bcc_reverse" 2564 [(set (pc) 2565 (if_then_else 2566 (match_operator 1 "signed_comparison_operator" 2567 [(match_operand:DI 2 "register_operand" "r") 2568 (const_int 0)]) 2569 2570 (pc) 2571 (label_ref (match_operand 0))))] 2572 "" 2573 "b%c1 %2,%0" 2574 [(set_attr "type" "ibr")]) 2575 2576(define_insn "*blbs_normal" 2577 [(set (pc) 2578 (if_then_else 2579 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2580 (const_int 1) 2581 (const_int 0)) 2582 (const_int 0)) 2583 (label_ref (match_operand 0)) 2584 (pc)))] 2585 "" 2586 "blbs %r1,%0" 2587 [(set_attr "type" "ibr")]) 2588 2589(define_insn "*blbc_normal" 2590 [(set (pc) 2591 (if_then_else 2592 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2593 (const_int 1) 2594 (const_int 0)) 2595 (const_int 0)) 2596 (label_ref (match_operand 0)) 2597 (pc)))] 2598 "" 2599 "blbc %r1,%0" 2600 [(set_attr "type" "ibr")]) 2601 2602(define_split 2603 [(parallel 2604 [(set (pc) 2605 (if_then_else 2606 (match_operator 1 "comparison_operator" 2607 [(zero_extract:DI (match_operand:DI 2 "register_operand") 2608 (const_int 1) 2609 (match_operand:DI 3 "const_int_operand")) 2610 (const_int 0)]) 2611 (label_ref (match_operand 0)) 2612 (pc))) 2613 (clobber (match_operand:DI 4 "register_operand"))])] 2614 "INTVAL (operands[3]) != 0" 2615 [(set (match_dup 4) 2616 (lshiftrt:DI (match_dup 2) (match_dup 3))) 2617 (set (pc) 2618 (if_then_else (match_op_dup 1 2619 [(zero_extract:DI (match_dup 4) 2620 (const_int 1) 2621 (const_int 0)) 2622 (const_int 0)]) 2623 (label_ref (match_dup 0)) 2624 (pc)))] 2625 ) 2626 2627;; The following are the corresponding floating-point insns. Recall 2628;; we need to have variants that expand the arguments from SFmode 2629;; to DFmode. 2630 2631(define_insn "*cmpdf_internal" 2632 [(set (match_operand:DF 0 "register_operand" "=f,&f") 2633 (match_operator:DF 1 "alpha_fp_comparison_operator" 2634 [(match_operand:DF 2 "reg_or_0_operand" "fG,fG") 2635 (match_operand:DF 3 "reg_or_0_operand" "fG,fG")]))] 2636 "TARGET_FP" 2637 "cmp%-%C1%/ %R2,%R3,%0" 2638 [(set_attr "type" "fadd") 2639 (set_attr "trap" "yes") 2640 (set_attr "trap_suffix" "su") 2641 (set (attr "enabled") 2642 (cond [(eq_attr "alternative" "0") 2643 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2644 ] 2645 (symbol_ref "true")))]) 2646 2647(define_insn "*cmpdf_ext1" 2648 [(set (match_operand:DF 0 "register_operand" "=f") 2649 (match_operator:DF 1 "alpha_fp_comparison_operator" 2650 [(float_extend:DF 2651 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2652 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2653 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2654 "cmp%-%C1%/ %R2,%R3,%0" 2655 [(set_attr "type" "fadd") 2656 (set_attr "trap" "yes") 2657 (set_attr "trap_suffix" "su")]) 2658 2659(define_insn "*cmpdf_ext2" 2660 [(set (match_operand:DF 0 "register_operand" "=f") 2661 (match_operator:DF 1 "alpha_fp_comparison_operator" 2662 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2663 (float_extend:DF 2664 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2665 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2666 "cmp%-%C1%/ %R2,%R3,%0" 2667 [(set_attr "type" "fadd") 2668 (set_attr "trap" "yes") 2669 (set_attr "trap_suffix" "su")]) 2670 2671(define_insn "*cmpdf_ext3" 2672 [(set (match_operand:DF 0 "register_operand" "=f") 2673 (match_operator:DF 1 "alpha_fp_comparison_operator" 2674 [(float_extend:DF 2675 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2676 (float_extend:DF 2677 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2678 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2679 "cmp%-%C1%/ %R2,%R3,%0" 2680 [(set_attr "type" "fadd") 2681 (set_attr "trap" "yes") 2682 (set_attr "trap_suffix" "su")]) 2683 2684(define_insn "*mov<mode>cc_internal" 2685 [(set (match_operand:FMODE 0 "register_operand" "=f,f") 2686 (if_then_else:FMODE 2687 (match_operator 3 "signed_comparison_operator" 2688 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2689 (match_operand:DF 2 "const0_operand" "G,G")]) 2690 (match_operand:FMODE 1 "reg_or_0_operand" "fG,0") 2691 (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))] 2692 "TARGET_FP" 2693 "@ 2694 fcmov%C3 %R4,%R1,%0 2695 fcmov%D3 %R4,%R5,%0" 2696 [(set_attr "type" "fcmov")]) 2697 2698(define_insn "*movdfcc_ext1" 2699 [(set (match_operand:DF 0 "register_operand" "=f,f") 2700 (if_then_else:DF 2701 (match_operator 3 "signed_comparison_operator" 2702 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2703 (match_operand:DF 2 "const0_operand" "G,G")]) 2704 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2705 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2706 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2707 "@ 2708 fcmov%C3 %R4,%R1,%0 2709 fcmov%D3 %R4,%R5,%0" 2710 [(set_attr "type" "fcmov")]) 2711 2712(define_insn "*movdfcc_ext2" 2713 [(set (match_operand:DF 0 "register_operand" "=f,f") 2714 (if_then_else:DF 2715 (match_operator 3 "signed_comparison_operator" 2716 [(float_extend:DF 2717 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2718 (match_operand:DF 2 "const0_operand" "G,G")]) 2719 (match_operand:DF 1 "reg_or_0_operand" "fG,0") 2720 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2721 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2722 "@ 2723 fcmov%C3 %R4,%R1,%0 2724 fcmov%D3 %R4,%R5,%0" 2725 [(set_attr "type" "fcmov")]) 2726 2727(define_insn "*movdfcc_ext3" 2728 [(set (match_operand:SF 0 "register_operand" "=f,f") 2729 (if_then_else:SF 2730 (match_operator 3 "signed_comparison_operator" 2731 [(float_extend:DF 2732 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2733 (match_operand:DF 2 "const0_operand" "G,G")]) 2734 (match_operand:SF 1 "reg_or_0_operand" "fG,0") 2735 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] 2736 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2737 "@ 2738 fcmov%C3 %R4,%R1,%0 2739 fcmov%D3 %R4,%R5,%0" 2740 [(set_attr "type" "fcmov")]) 2741 2742(define_insn "*movdfcc_ext4" 2743 [(set (match_operand:DF 0 "register_operand" "=f,f") 2744 (if_then_else:DF 2745 (match_operator 3 "signed_comparison_operator" 2746 [(float_extend:DF 2747 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2748 (match_operand:DF 2 "const0_operand" "G,G")]) 2749 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2750 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2751 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2752 "@ 2753 fcmov%C3 %R4,%R1,%0 2754 fcmov%D3 %R4,%R5,%0" 2755 [(set_attr "type" "fcmov")]) 2756 2757(define_expand "smaxdf3" 2758 [(set (match_dup 3) 2759 (le:DF (match_operand:DF 1 "reg_or_0_operand") 2760 (match_operand:DF 2 "reg_or_0_operand"))) 2761 (set (match_operand:DF 0 "register_operand") 2762 (if_then_else:DF (eq (match_dup 3) (match_dup 4)) 2763 (match_dup 1) (match_dup 2)))] 2764 "TARGET_FP" 2765{ 2766 operands[3] = gen_reg_rtx (DFmode); 2767 operands[4] = CONST0_RTX (DFmode); 2768}) 2769 2770(define_expand "smindf3" 2771 [(set (match_dup 3) 2772 (lt:DF (match_operand:DF 1 "reg_or_0_operand") 2773 (match_operand:DF 2 "reg_or_0_operand"))) 2774 (set (match_operand:DF 0 "register_operand") 2775 (if_then_else:DF (ne (match_dup 3) (match_dup 4)) 2776 (match_dup 1) (match_dup 2)))] 2777 "TARGET_FP" 2778{ 2779 operands[3] = gen_reg_rtx (DFmode); 2780 operands[4] = CONST0_RTX (DFmode); 2781}) 2782 2783(define_expand "smaxsf3" 2784 [(set (match_dup 3) 2785 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2786 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2787 (set (match_operand:SF 0 "register_operand") 2788 (if_then_else:SF (eq (match_dup 3) (match_dup 4)) 2789 (match_dup 1) (match_dup 2)))] 2790 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2791{ 2792 operands[3] = gen_reg_rtx (DFmode); 2793 operands[4] = CONST0_RTX (DFmode); 2794}) 2795 2796(define_expand "sminsf3" 2797 [(set (match_dup 3) 2798 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2799 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2800 (set (match_operand:SF 0 "register_operand") 2801 (if_then_else:SF (ne (match_dup 3) (match_dup 4)) 2802 (match_dup 1) (match_dup 2)))] 2803 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2804{ 2805 operands[3] = gen_reg_rtx (DFmode); 2806 operands[4] = CONST0_RTX (DFmode); 2807}) 2808 2809(define_insn "*fbcc_normal" 2810 [(set (pc) 2811 (if_then_else 2812 (match_operator 1 "signed_comparison_operator" 2813 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2814 (match_operand:DF 3 "const0_operand" "G")]) 2815 (label_ref (match_operand 0)) 2816 (pc)))] 2817 "TARGET_FP" 2818 "fb%C1 %R2,%0" 2819 [(set_attr "type" "fbr")]) 2820 2821(define_insn "*fbcc_ext_normal" 2822 [(set (pc) 2823 (if_then_else 2824 (match_operator 1 "signed_comparison_operator" 2825 [(float_extend:DF 2826 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2827 (match_operand:DF 3 "const0_operand" "G")]) 2828 (label_ref (match_operand 0)) 2829 (pc)))] 2830 "TARGET_FP" 2831 "fb%C1 %R2,%0" 2832 [(set_attr "type" "fbr")]) 2833 2834;; These are the main define_expand's used to make conditional branches 2835;; and compares. 2836 2837(define_expand "cbranchdf4" 2838 [(use (match_operator 0 "alpha_cbranch_operator" 2839 [(match_operand:DF 1 "reg_or_0_operand") 2840 (match_operand:DF 2 "reg_or_0_operand")])) 2841 (use (match_operand 3))] 2842 "TARGET_FP" 2843 "alpha_emit_conditional_branch (operands, DFmode); DONE;") 2844 2845(define_expand "cbranchtf4" 2846 [(use (match_operator 0 "alpha_cbranch_operator" 2847 [(match_operand:TF 1 "general_operand") 2848 (match_operand:TF 2 "general_operand")])) 2849 (use (match_operand 3))] 2850 "TARGET_HAS_XFLOATING_LIBS" 2851 "alpha_emit_conditional_branch (operands, TFmode); DONE;") 2852 2853(define_expand "cbranchdi4" 2854 [(use (match_operator 0 "alpha_cbranch_operator" 2855 [(match_operand:DI 1 "general_operand") 2856 (match_operand:DI 2 "general_operand")])) 2857 (use (match_operand 3))] 2858 "" 2859 "alpha_emit_conditional_branch (operands, DImode); DONE;") 2860 2861(define_expand "cstoredf4" 2862 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2863 [(match_operand:DF 2 "reg_or_0_operand") 2864 (match_operand:DF 3 "reg_or_0_operand")])) 2865 (clobber (match_operand:DI 0 "register_operand"))] 2866 "TARGET_FP" 2867{ 2868 if (alpha_emit_setcc (operands, DFmode)) 2869 DONE; 2870 else 2871 FAIL; 2872}) 2873 2874(define_expand "cstoretf4" 2875 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2876 [(match_operand:TF 2 "general_operand") 2877 (match_operand:TF 3 "general_operand")])) 2878 (clobber (match_operand:DI 0 "register_operand"))] 2879 "TARGET_HAS_XFLOATING_LIBS" 2880{ 2881 if (alpha_emit_setcc (operands, TFmode)) 2882 DONE; 2883 else 2884 FAIL; 2885}) 2886 2887(define_expand "cstoredi4" 2888 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2889 [(match_operand:DI 2 "general_operand") 2890 (match_operand:DI 3 "general_operand")])) 2891 (clobber (match_operand:DI 0 "register_operand"))] 2892 "" 2893{ 2894 if (alpha_emit_setcc (operands, DImode)) 2895 DONE; 2896 else 2897 FAIL; 2898}) 2899 2900;; These are the main define_expand's used to make conditional moves. 2901 2902(define_expand "mov<mode>cc" 2903 [(set (match_operand:I48MODE 0 "register_operand") 2904 (if_then_else:I48MODE 2905 (match_operand 1 "comparison_operator") 2906 (match_operand:I48MODE 2 "reg_or_8bit_operand") 2907 (match_operand:I48MODE 3 "reg_or_8bit_operand")))] 2908 "" 2909{ 2910 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2911 if (operands[1] == 0) 2912 FAIL; 2913}) 2914 2915(define_expand "mov<mode>cc" 2916 [(set (match_operand:FMODE 0 "register_operand") 2917 (if_then_else:FMODE 2918 (match_operand 1 "comparison_operator") 2919 (match_operand:FMODE 2 "reg_or_8bit_operand") 2920 (match_operand:FMODE 3 "reg_or_8bit_operand")))] 2921 "" 2922{ 2923 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2924 if (operands[1] == 0) 2925 FAIL; 2926}) 2927 2928;; These define_split definitions are used in cases when comparisons have 2929;; not be stated in the correct way and we need to reverse the second 2930;; comparison. For example, x >= 7 has to be done as x < 6 with the 2931;; comparison that tests the result being reversed. We have one define_split 2932;; for each use of a comparison. They do not match valid insns and need 2933;; not generate valid insns. 2934;; 2935;; We can also handle equality comparisons (and inequality comparisons in 2936;; cases where the resulting add cannot overflow) by doing an add followed by 2937;; a comparison with zero. This is faster since the addition takes one 2938;; less cycle than a compare when feeding into a conditional move. 2939;; For this case, we also have an SImode pattern since we can merge the add 2940;; and sign extend and the order doesn't matter. 2941;; 2942;; We do not do this for floating-point, since it isn't clear how the "wrong" 2943;; operation could have been generated. 2944 2945(define_split 2946 [(set (match_operand:DI 0 "register_operand") 2947 (if_then_else:DI 2948 (match_operator 1 "comparison_operator" 2949 [(match_operand:DI 2 "reg_or_0_operand") 2950 (match_operand:DI 3 "reg_or_cint_operand")]) 2951 (match_operand:DI 4 "reg_or_cint_operand") 2952 (match_operand:DI 5 "reg_or_cint_operand"))) 2953 (clobber (match_operand:DI 6 "register_operand"))] 2954 "operands[3] != const0_rtx" 2955 [(set (match_dup 6) (match_dup 7)) 2956 (set (match_dup 0) 2957 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 2958{ 2959 enum rtx_code code = GET_CODE (operands[1]); 2960 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 2961 2962 /* If we are comparing for equality with a constant and that constant 2963 appears in the arm when the register equals the constant, use the 2964 register since that is more likely to match (and to produce better code 2965 if both would). */ 2966 2967 if (code == EQ && CONST_INT_P (operands[3]) 2968 && rtx_equal_p (operands[4], operands[3])) 2969 operands[4] = operands[2]; 2970 2971 else if (code == NE && CONST_INT_P (operands[3]) 2972 && rtx_equal_p (operands[5], operands[3])) 2973 operands[5] = operands[2]; 2974 2975 if (code == NE || code == EQ 2976 || (extended_count (operands[2], DImode, unsignedp) >= 1 2977 && extended_count (operands[3], DImode, unsignedp) >= 1)) 2978 { 2979 if (CONST_INT_P (operands[3])) 2980 operands[7] = gen_rtx_PLUS (DImode, operands[2], 2981 GEN_INT (- INTVAL (operands[3]))); 2982 else 2983 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]); 2984 2985 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx); 2986 } 2987 2988 else if (code == EQ || code == LE || code == LT 2989 || code == LEU || code == LTU) 2990 { 2991 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]); 2992 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx); 2993 } 2994 else 2995 { 2996 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode, 2997 operands[2], operands[3]); 2998 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx); 2999 } 3000}) 3001 3002(define_split 3003 [(set (match_operand:DI 0 "register_operand") 3004 (if_then_else:DI 3005 (match_operator 1 "comparison_operator" 3006 [(match_operand:SI 2 "reg_or_0_operand") 3007 (match_operand:SI 3 "reg_or_cint_operand")]) 3008 (match_operand:DI 4 "reg_or_8bit_operand") 3009 (match_operand:DI 5 "reg_or_8bit_operand"))) 3010 (clobber (match_operand:DI 6 "register_operand"))] 3011 "operands[3] != const0_rtx 3012 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 3013 [(set (match_dup 6) (match_dup 7)) 3014 (set (match_dup 0) 3015 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3016{ 3017 enum rtx_code code = GET_CODE (operands[1]); 3018 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3019 rtx tem; 3020 3021 if ((code != NE && code != EQ 3022 && ! (extended_count (operands[2], DImode, unsignedp) >= 1 3023 && extended_count (operands[3], DImode, unsignedp) >= 1))) 3024 FAIL; 3025 3026 if (CONST_INT_P (operands[3])) 3027 tem = gen_rtx_PLUS (SImode, operands[2], 3028 GEN_INT (- INTVAL (operands[3]))); 3029 else 3030 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); 3031 3032 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem); 3033 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode, 3034 operands[6], const0_rtx); 3035}) 3036 3037;; Prefer to use cmp and arithmetic when possible instead of a cmove. 3038 3039(define_split 3040 [(set (match_operand 0 "register_operand") 3041 (if_then_else (match_operator 1 "signed_comparison_operator" 3042 [(match_operand:DI 2 "reg_or_0_operand") 3043 (const_int 0)]) 3044 (match_operand 3 "const_int_operand") 3045 (match_operand 4 "const_int_operand")))] 3046 "" 3047 [(const_int 0)] 3048{ 3049 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0], 3050 operands[2], operands[3], operands[4])) 3051 DONE; 3052 else 3053 FAIL; 3054}) 3055 3056;; ??? Why combine is allowed to create such non-canonical rtl, I don't know. 3057;; Oh well, we match it in movcc, so it must be partially our fault. 3058(define_split 3059 [(set (match_operand 0 "register_operand") 3060 (if_then_else (match_operator 1 "signed_comparison_operator" 3061 [(const_int 0) 3062 (match_operand:DI 2 "reg_or_0_operand")]) 3063 (match_operand 3 "const_int_operand") 3064 (match_operand 4 "const_int_operand")))] 3065 "" 3066 [(const_int 0)] 3067{ 3068 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])), 3069 operands[0], operands[2], operands[3], 3070 operands[4])) 3071 DONE; 3072 else 3073 FAIL; 3074}) 3075 3076(define_insn_and_split "*cmp_sadd_di" 3077 [(set (match_operand:DI 0 "register_operand" "=r") 3078 (plus:DI (if_then_else:DI 3079 (match_operator 1 "alpha_zero_comparison_operator" 3080 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3081 (const_int 0)]) 3082 (match_operand:DI 3 "const48_operand" "I") 3083 (const_int 0)) 3084 (match_operand:DI 4 "sext_add_operand" "rIO"))) 3085 (clobber (match_scratch:DI 5 "=r"))] 3086 "" 3087 "#" 3088 "" 3089 [(set (match_dup 5) 3090 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3091 (set (match_dup 0) 3092 (plus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3093 (match_dup 4)))] 3094{ 3095 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3096 if (can_create_pseudo_p ()) 3097 operands[5] = gen_reg_rtx (DImode); 3098 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3099 operands[5] = operands[0]; 3100}) 3101 3102(define_insn_and_split "*cmp_sadd_si" 3103 [(set (match_operand:SI 0 "register_operand" "=r") 3104 (plus:SI (if_then_else:SI 3105 (match_operator 1 "alpha_zero_comparison_operator" 3106 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3107 (const_int 0)]) 3108 (match_operand:SI 3 "const48_operand" "I") 3109 (const_int 0)) 3110 (match_operand:SI 4 "sext_add_operand" "rIO"))) 3111 (clobber (match_scratch:DI 5 "=r"))] 3112 "" 3113 "#" 3114 "" 3115 [(set (match_dup 5) 3116 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3117 (set (match_dup 0) 3118 (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3119 (match_dup 4)))] 3120{ 3121 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3122 if (can_create_pseudo_p ()) 3123 operands[5] = gen_reg_rtx (DImode); 3124 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3125 operands[5] = gen_lowpart (DImode, operands[0]); 3126 3127 operands[6] = gen_lowpart (SImode, operands[5]); 3128}) 3129 3130(define_insn_and_split "*cmp_sadd_sidi" 3131 [(set (match_operand:DI 0 "register_operand" "=r") 3132 (sign_extend:DI 3133 (plus:SI (if_then_else:SI 3134 (match_operator 1 "alpha_zero_comparison_operator" 3135 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3136 (const_int 0)]) 3137 (match_operand:SI 3 "const48_operand" "I") 3138 (const_int 0)) 3139 (match_operand:SI 4 "sext_add_operand" "rIO")))) 3140 (clobber (match_scratch:DI 5 "=r"))] 3141 "" 3142 "#" 3143 "" 3144 [(set (match_dup 5) 3145 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3146 (set (match_dup 0) 3147 (sign_extend:DI (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3148 (match_dup 4))))] 3149{ 3150 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3151 if (can_create_pseudo_p ()) 3152 operands[5] = gen_reg_rtx (DImode); 3153 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3154 operands[5] = operands[0]; 3155 3156 operands[6] = gen_lowpart (SImode, operands[5]); 3157}) 3158 3159(define_insn_and_split "*cmp_ssub_di" 3160 [(set (match_operand:DI 0 "register_operand" "=r") 3161 (minus:DI (if_then_else:DI 3162 (match_operator 1 "alpha_zero_comparison_operator" 3163 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3164 (const_int 0)]) 3165 (match_operand:DI 3 "const48_operand" "I") 3166 (const_int 0)) 3167 (match_operand:DI 4 "reg_or_8bit_operand" "rI"))) 3168 (clobber (match_scratch:DI 5 "=r"))] 3169 "" 3170 "#" 3171 "" 3172 [(set (match_dup 5) 3173 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3174 (set (match_dup 0) 3175 (minus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3176 (match_dup 4)))] 3177{ 3178 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3179 if (can_create_pseudo_p ()) 3180 operands[5] = gen_reg_rtx (DImode); 3181 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3182 operands[5] = operands[0]; 3183}) 3184 3185(define_insn_and_split "*cmp_ssub_si" 3186 [(set (match_operand:SI 0 "register_operand" "=r") 3187 (minus:SI (if_then_else:SI 3188 (match_operator 1 "alpha_zero_comparison_operator" 3189 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3190 (const_int 0)]) 3191 (match_operand:SI 3 "const48_operand" "I") 3192 (const_int 0)) 3193 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))) 3194 (clobber (match_scratch:DI 5 "=r"))] 3195 "" 3196 "#" 3197 "" 3198 [(set (match_dup 5) 3199 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3200 (set (match_dup 0) 3201 (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3202 (match_dup 4)))] 3203{ 3204 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3205 if (can_create_pseudo_p ()) 3206 operands[5] = gen_reg_rtx (DImode); 3207 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3208 operands[5] = gen_lowpart (DImode, operands[0]); 3209 3210 operands[6] = gen_lowpart (SImode, operands[5]); 3211}) 3212 3213(define_insn_and_split "*cmp_ssub_sidi" 3214 [(set (match_operand:DI 0 "register_operand" "=r") 3215 (sign_extend:DI 3216 (minus:SI (if_then_else:SI 3217 (match_operator 1 "alpha_zero_comparison_operator" 3218 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3219 (const_int 0)]) 3220 (match_operand:SI 3 "const48_operand" "I") 3221 (const_int 0)) 3222 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))) 3223 (clobber (match_scratch:DI 5 "=r"))] 3224 "" 3225 "#" 3226 "" 3227 [(set (match_dup 5) 3228 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3229 (set (match_dup 0) 3230 (sign_extend:DI (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3231 (match_dup 4))))] 3232{ 3233 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3234 if (can_create_pseudo_p ()) 3235 operands[5] = gen_reg_rtx (DImode); 3236 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3237 operands[5] = operands[0]; 3238 3239 operands[6] = gen_lowpart (SImode, operands[5]); 3240}) 3241 3242;; Here are the CALL and unconditional branch insns. Calls on NT and OSF 3243;; work differently, so we have different patterns for each. 3244 3245(define_expand "call" 3246 [(use (match_operand:DI 0)) 3247 (use (match_operand 1)) 3248 (use (match_operand 2)) 3249 (use (match_operand 3))] 3250 "" 3251{ 3252 if (TARGET_ABI_OPEN_VMS) 3253 emit_call_insn (gen_call_vms (operands[0], operands[2])); 3254 else 3255 emit_call_insn (gen_call_osf (operands[0], operands[1])); 3256 DONE; 3257}) 3258 3259(define_expand "sibcall" 3260 [(parallel [(call (mem:DI (match_operand 0)) 3261 (match_operand 1)) 3262 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3263 "TARGET_ABI_OSF" 3264{ 3265 gcc_assert (MEM_P (operands[0])); 3266 operands[0] = XEXP (operands[0], 0); 3267}) 3268 3269(define_expand "call_osf" 3270 [(parallel [(call (mem:DI (match_operand 0)) 3271 (match_operand 1)) 3272 (use (reg:DI 29)) 3273 (clobber (reg:DI 26))])] 3274 "" 3275{ 3276 gcc_assert (MEM_P (operands[0])); 3277 3278 operands[0] = XEXP (operands[0], 0); 3279 if (! call_operand (operands[0], Pmode)) 3280 operands[0] = copy_to_mode_reg (Pmode, operands[0]); 3281}) 3282 3283;; 3284;; call openvms/alpha 3285;; op 0: symbol ref for called function 3286;; op 1: next_arg_reg (argument information value for R25) 3287;; 3288(define_expand "call_vms" 3289 [(parallel [(call (mem:DI (match_operand 0)) 3290 (match_operand 1)) 3291 (use (match_dup 2)) 3292 (use (reg:DI 25)) 3293 (use (reg:DI 26)) 3294 (clobber (reg:DI 27))])] 3295 "" 3296{ 3297 gcc_assert (MEM_P (operands[0])); 3298 3299 operands[0] = XEXP (operands[0], 0); 3300 3301 /* Always load AI with argument information, then handle symbolic and 3302 indirect call differently. Load RA and set operands[2] to PV in 3303 both cases. */ 3304 3305 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); 3306 if (GET_CODE (operands[0]) == SYMBOL_REF) 3307 { 3308 operands[2] = const0_rtx; 3309 } 3310 else 3311 { 3312 emit_move_insn (gen_rtx_REG (Pmode, 26), 3313 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3314 operands[0], 8))); 3315 operands[2] = operands[0]; 3316 } 3317}) 3318 3319(define_expand "call_value" 3320 [(use (match_operand 0)) 3321 (use (match_operand:DI 1)) 3322 (use (match_operand 2)) 3323 (use (match_operand 3)) 3324 (use (match_operand 4))] 3325 "" 3326{ 3327 if (TARGET_ABI_OPEN_VMS) 3328 emit_call_insn (gen_call_value_vms (operands[0], operands[1], 3329 operands[3])); 3330 else 3331 emit_call_insn (gen_call_value_osf (operands[0], operands[1], 3332 operands[2])); 3333 DONE; 3334}) 3335 3336(define_expand "sibcall_value" 3337 [(parallel [(set (match_operand 0) 3338 (call (mem:DI (match_operand 1)) 3339 (match_operand 2))) 3340 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3341 "TARGET_ABI_OSF" 3342{ 3343 gcc_assert (MEM_P (operands[1])); 3344 operands[1] = XEXP (operands[1], 0); 3345}) 3346 3347(define_expand "call_value_osf" 3348 [(parallel [(set (match_operand 0) 3349 (call (mem:DI (match_operand 1)) 3350 (match_operand 2))) 3351 (use (reg:DI 29)) 3352 (clobber (reg:DI 26))])] 3353 "" 3354{ 3355 gcc_assert (MEM_P (operands[1])); 3356 3357 operands[1] = XEXP (operands[1], 0); 3358 if (! call_operand (operands[1], Pmode)) 3359 operands[1] = copy_to_mode_reg (Pmode, operands[1]); 3360}) 3361 3362(define_expand "call_value_vms" 3363 [(parallel [(set (match_operand 0) 3364 (call (mem:DI (match_operand:DI 1)) 3365 (match_operand 2))) 3366 (use (match_dup 3)) 3367 (use (reg:DI 25)) 3368 (use (reg:DI 26)) 3369 (clobber (reg:DI 27))])] 3370 "" 3371{ 3372 gcc_assert (MEM_P (operands[1])); 3373 3374 operands[1] = XEXP (operands[1], 0); 3375 3376 /* Always load AI with argument information, then handle symbolic and 3377 indirect call differently. Load RA and set operands[3] to PV in 3378 both cases. */ 3379 3380 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); 3381 if (GET_CODE (operands[1]) == SYMBOL_REF) 3382 { 3383 operands[3] = const0_rtx; 3384 } 3385 else 3386 { 3387 emit_move_insn (gen_rtx_REG (Pmode, 26), 3388 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3389 operands[1], 8))); 3390 operands[3] = operands[1]; 3391 } 3392}) 3393 3394(define_insn "*call_osf_1_er_noreturn" 3395 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3396 (match_operand 1)) 3397 (use (reg:DI 29)) 3398 (clobber (reg:DI 26))] 3399 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3400 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3401 "@ 3402 jsr $26,($27),0 3403 bsr $26,%0\t\t!samegp 3404 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#" 3405 [(set_attr "type" "jsr") 3406 (set_attr "length" "*,*,8")]) 3407 3408(define_insn "*call_osf_1_er" 3409 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3410 (match_operand 1)) 3411 (use (reg:DI 29)) 3412 (clobber (reg:DI 26))] 3413 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3414 "@ 3415 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 3416 bsr $26,%0\t\t!samegp 3417 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 3418 [(set_attr "type" "jsr") 3419 (set_attr "length" "12,*,16")]) 3420 3421;; We must use peep2 instead of a split because we need accurate life 3422;; information for $gp. Consider the case of { bar(); while (1); }. 3423(define_peephole2 3424 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3425 (match_operand 1)) 3426 (use (reg:DI 29)) 3427 (clobber (reg:DI 26))])] 3428 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3429 && ! samegp_function_operand (operands[0], Pmode) 3430 && (peep2_regno_dead_p (1, 29) 3431 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3432 [(parallel [(call (mem:DI (match_dup 2)) 3433 (match_dup 1)) 3434 (use (reg:DI 29)) 3435 (use (match_dup 0)) 3436 (use (match_dup 3)) 3437 (clobber (reg:DI 26))])] 3438{ 3439 if (CONSTANT_P (operands[0])) 3440 { 3441 operands[2] = gen_rtx_REG (Pmode, 27); 3442 operands[3] = GEN_INT (alpha_next_sequence_number++); 3443 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3444 operands[0], operands[3])); 3445 } 3446 else 3447 { 3448 operands[2] = operands[0]; 3449 operands[0] = const0_rtx; 3450 operands[3] = const0_rtx; 3451 } 3452}) 3453 3454(define_peephole2 3455 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3456 (match_operand 1)) 3457 (use (reg:DI 29)) 3458 (clobber (reg:DI 26))])] 3459 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3460 && ! samegp_function_operand (operands[0], Pmode) 3461 && ! (peep2_regno_dead_p (1, 29) 3462 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3463 [(parallel [(call (mem:DI (match_dup 2)) 3464 (match_dup 1)) 3465 (set (match_dup 5) 3466 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1)) 3467 (use (match_dup 0)) 3468 (use (match_dup 4)) 3469 (clobber (reg:DI 26))]) 3470 (set (match_dup 5) 3471 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))] 3472{ 3473 if (CONSTANT_P (operands[0])) 3474 { 3475 operands[2] = gen_rtx_REG (Pmode, 27); 3476 operands[4] = GEN_INT (alpha_next_sequence_number++); 3477 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3478 operands[0], operands[4])); 3479 } 3480 else 3481 { 3482 operands[2] = operands[0]; 3483 operands[0] = const0_rtx; 3484 operands[4] = const0_rtx; 3485 } 3486 operands[3] = GEN_INT (alpha_next_sequence_number++); 3487 operands[5] = pic_offset_table_rtx; 3488}) 3489 3490(define_insn "*call_osf_2_er_nogp" 3491 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3492 (match_operand 1)) 3493 (use (reg:DI 29)) 3494 (use (match_operand 2)) 3495 (use (match_operand 3 "const_int_operand")) 3496 (clobber (reg:DI 26))] 3497 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3498 "jsr $26,(%0),%2%J3" 3499 [(set_attr "type" "jsr")]) 3500 3501(define_insn "*call_osf_2_er" 3502 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3503 (match_operand 1)) 3504 (set (reg:DI 29) 3505 (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")] 3506 UNSPEC_LDGP1)) 3507 (use (match_operand 2)) 3508 (use (match_operand 3 "const_int_operand")) 3509 (clobber (reg:DI 26))] 3510 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3511 "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4" 3512 [(set_attr "type" "jsr") 3513 (set_attr "cannot_copy" "true") 3514 (set_attr "length" "8")]) 3515 3516(define_insn "*call_osf_1_noreturn" 3517 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3518 (match_operand 1)) 3519 (use (reg:DI 29)) 3520 (clobber (reg:DI 26))] 3521 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3522 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3523 "@ 3524 jsr $26,($27),0 3525 bsr $26,$%0..ng 3526 jsr $26,%0" 3527 [(set_attr "type" "jsr") 3528 (set_attr "length" "*,*,8")]) 3529 3530(define_insn "*call_osf_1" 3531 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3532 (match_operand 1)) 3533 (use (reg:DI 29)) 3534 (clobber (reg:DI 26))] 3535 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3536 "@ 3537 jsr $26,($27),0\;ldgp $29,0($26) 3538 bsr $26,$%0..ng 3539 jsr $26,%0\;ldgp $29,0($26)" 3540 [(set_attr "type" "jsr") 3541 (set_attr "length" "12,*,16")]) 3542 3543(define_insn "*sibcall_osf_1_er" 3544 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3545 (match_operand 1)) 3546 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3547 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3548 "@ 3549 br $31,%0\t\t!samegp 3550 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#" 3551 [(set_attr "type" "jsr") 3552 (set_attr "length" "*,8")]) 3553 3554;; Note that the DEC assembler expands "jmp foo" with $at, which 3555;; doesn't do what we want. 3556(define_insn "*sibcall_osf_1" 3557 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3558 (match_operand 1)) 3559 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3560 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3561 "@ 3562 br $31,$%0..ng 3563 lda $27,%0\;jmp $31,($27),%0" 3564 [(set_attr "type" "jsr") 3565 (set_attr "length" "*,8")]) 3566 3567; GAS relies on the order and position of instructions output below in order 3568; to generate relocs for VMS link to potentially optimize the call. 3569; Please do not molest. 3570(define_insn "*call_vms_1" 3571 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) 3572 (match_operand 1)) 3573 (use (match_operand:DI 2 "nonmemory_operand" "r,n")) 3574 (use (reg:DI 25)) 3575 (use (reg:DI 26)) 3576 (clobber (reg:DI 27))] 3577 "TARGET_ABI_OPEN_VMS" 3578{ 3579 switch (which_alternative) 3580 { 3581 case 0: 3582 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)"; 3583 case 1: 3584 operands [2] = alpha_use_linkage (operands [0], true, false); 3585 operands [3] = alpha_use_linkage (operands [0], false, false); 3586 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"; 3587 default: 3588 gcc_unreachable (); 3589 } 3590} 3591 [(set_attr "type" "jsr") 3592 (set_attr "length" "12,16")]) 3593 3594;; Call subroutine returning any type. 3595 3596(define_expand "untyped_call" 3597 [(parallel [(call (match_operand 0) 3598 (const_int 0)) 3599 (match_operand 1) 3600 (match_operand 2)])] 3601 "" 3602{ 3603 int i; 3604 3605 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 3606 3607 for (i = 0; i < XVECLEN (operands[2], 0); i++) 3608 { 3609 rtx set = XVECEXP (operands[2], 0, i); 3610 emit_move_insn (SET_DEST (set), SET_SRC (set)); 3611 } 3612 3613 /* The optimizer does not know that the call sets the function value 3614 registers we stored in the result block. We avoid problems by 3615 claiming that all hard registers are used and clobbered at this 3616 point. */ 3617 emit_insn (gen_blockage ()); 3618 3619 DONE; 3620}) 3621 3622;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 3623;; all of memory. This blocks insns from being moved across this point. 3624 3625(define_insn "blockage" 3626 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 3627 "" 3628 "" 3629 [(set_attr "length" "0") 3630 (set_attr "type" "none")]) 3631 3632(define_insn "jump" 3633 [(set (pc) 3634 (label_ref (match_operand 0)))] 3635 "" 3636 "br $31,%l0" 3637 [(set_attr "type" "ibr")]) 3638 3639(define_expand "return" 3640 [(return)] 3641 "direct_return ()") 3642 3643(define_insn "*return_internal" 3644 [(return)] 3645 "reload_completed" 3646 "ret $31,($26),1" 3647 [(set_attr "type" "ibr")]) 3648 3649(define_insn "indirect_jump" 3650 [(set (pc) (match_operand:DI 0 "register_operand" "r"))] 3651 "" 3652 "jmp $31,(%0),0" 3653 [(set_attr "type" "ibr")]) 3654 3655(define_expand "tablejump" 3656 [(parallel [(set (pc) 3657 (match_operand 0 "register_operand")) 3658 (use (label_ref:DI (match_operand 1)))])] 3659 "" 3660{ 3661 if (TARGET_ABI_OSF) 3662 { 3663 rtx dest = gen_reg_rtx (DImode); 3664 emit_insn (gen_extendsidi2 (dest, operands[0])); 3665 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest)); 3666 operands[0] = dest; 3667 } 3668}) 3669 3670(define_insn "*tablejump_internal" 3671 [(set (pc) 3672 (match_operand:DI 0 "register_operand" "r")) 3673 (use (label_ref (match_operand 1)))] 3674 "" 3675 "jmp $31,(%0),0" 3676 [(set_attr "type" "ibr")]) 3677 3678;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't 3679;; want to have to include pal.h in our .s file. 3680(define_insn "imb" 3681 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)] 3682 "" 3683 "call_pal 0x86" 3684 [(set_attr "type" "callpal")]) 3685 3686(define_expand "clear_cache" 3687 [(match_operand:DI 0) ; region start 3688 (match_operand:DI 1)] ; region end 3689 "" 3690{ 3691 emit_insn (gen_imb ()); 3692 DONE; 3693}) 3694 3695;; BUGCHK is documented common to OSF/1 and VMS PALcode. 3696(define_insn "trap" 3697 [(trap_if (const_int 1) (const_int 0)) 3698 (use (reg:DI 29))] 3699 "" 3700 "call_pal 0x81" 3701 [(set_attr "type" "callpal")]) 3702 3703;; For userland, we load the thread pointer from the TCB. 3704;; For the kernel, we load the per-cpu private value. 3705 3706(define_insn "get_thread_pointerdi" 3707 [(set (match_operand:DI 0 "register_operand" "=v") 3708 (unspec:DI [(const_int 0)] UNSPEC_TP))] 3709 "TARGET_ABI_OSF" 3710{ 3711 if (TARGET_TLS_KERNEL) 3712 return "call_pal 0x32"; 3713 else 3714 return "call_pal 0x9e"; 3715} 3716 [(set_attr "type" "callpal")]) 3717 3718;; For completeness, and possibly a __builtin function, here's how to 3719;; set the thread pointer. Since we don't describe enough of this 3720;; quantity for CSE, we have to use a volatile unspec, and then there's 3721;; not much point in creating an R16_REG register class. 3722 3723(define_expand "set_thread_pointerdi" 3724 [(set (reg:DI 16) (match_operand:DI 0 "input_operand")) 3725 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3726 "TARGET_ABI_OSF") 3727 3728(define_insn "*set_tp" 3729 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3730 "TARGET_ABI_OSF" 3731{ 3732 if (TARGET_TLS_KERNEL) 3733 return "call_pal 0x31"; 3734 else 3735 return "call_pal 0x9f"; 3736} 3737 [(set_attr "type" "callpal")]) 3738 3739;; Special builtins for establishing and reverting VMS condition handlers. 3740 3741(define_expand "builtin_establish_vms_condition_handler" 3742 [(set (reg:DI 0) (match_operand:DI 0 "register_operand")) 3743 (use (match_operand:DI 1 "address_operand"))] 3744 "TARGET_ABI_OPEN_VMS" 3745{ 3746 alpha_expand_builtin_establish_vms_condition_handler (operands[0], 3747 operands[1]); 3748}) 3749 3750(define_expand "builtin_revert_vms_condition_handler" 3751 [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))] 3752 "TARGET_ABI_OPEN_VMS" 3753 "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);") 3754 3755;; Finally, we have the basic data motion insns. The byte and word insns 3756;; are done via define_expand. Start with the floating-point insns, since 3757;; they are simpler. 3758 3759(define_expand "movsf" 3760 [(set (match_operand:SF 0 "nonimmediate_operand") 3761 (match_operand:SF 1 "general_operand"))] 3762 "" 3763{ 3764 if (MEM_P (operands[0]) 3765 && ! reg_or_0_operand (operands[1], SFmode)) 3766 operands[1] = force_reg (SFmode, operands[1]); 3767}) 3768 3769(define_insn "*movsf" 3770 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3771 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3772 "register_operand (operands[0], SFmode) 3773 || reg_or_0_operand (operands[1], SFmode)" 3774 "@ 3775 cpys %R1,%R1,%0 3776 ld%, %0,%1 3777 bis $31,%r1,%0 3778 ldl %0,%1 3779 st%, %R1,%0 3780 stl %r1,%0 3781 itofs %1,%0 3782 ftois %1,%0" 3783 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3784 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3785 3786(define_expand "movdf" 3787 [(set (match_operand:DF 0 "nonimmediate_operand") 3788 (match_operand:DF 1 "general_operand"))] 3789 "" 3790{ 3791 if (MEM_P (operands[0]) 3792 && ! reg_or_0_operand (operands[1], DFmode)) 3793 operands[1] = force_reg (DFmode, operands[1]); 3794}) 3795 3796(define_insn "*movdf" 3797 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3798 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3799 "register_operand (operands[0], DFmode) 3800 || reg_or_0_operand (operands[1], DFmode)" 3801 "@ 3802 cpys %R1,%R1,%0 3803 ld%- %0,%1 3804 bis $31,%r1,%0 3805 ldq %0,%1 3806 st%- %R1,%0 3807 stq %r1,%0 3808 itoft %1,%0 3809 ftoit %1,%0" 3810 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3811 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3812 3813;; Subregs suck for register allocation. Pretend we can move TFmode 3814;; data between general registers until after reload. 3815;; ??? Is this still true now that we have the lower-subreg pass? 3816 3817(define_expand "movtf" 3818 [(set (match_operand:TF 0 "nonimmediate_operand") 3819 (match_operand:TF 1 "general_operand"))] 3820 "" 3821{ 3822 if (MEM_P (operands[0]) 3823 && ! reg_or_0_operand (operands[1], TFmode)) 3824 operands[1] = force_reg (TFmode, operands[1]); 3825}) 3826 3827(define_insn_and_split "*movtf_internal" 3828 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") 3829 (match_operand:TF 1 "input_operand" "roG,rG"))] 3830 "register_operand (operands[0], TFmode) 3831 || reg_or_0_operand (operands[1], TFmode)" 3832 "#" 3833 "reload_completed" 3834 [(set (match_dup 0) (match_dup 2)) 3835 (set (match_dup 1) (match_dup 3))] 3836 "alpha_split_tmode_pair (operands, TFmode, true);") 3837 3838;; We do two major things here: handle mem->mem and construct long 3839;; constants. 3840 3841(define_expand "movsi" 3842 [(set (match_operand:SI 0 "nonimmediate_operand") 3843 (match_operand:SI 1 "general_operand"))] 3844 "" 3845{ 3846 if (alpha_expand_mov (SImode, operands)) 3847 DONE; 3848}) 3849 3850(define_insn "*movsi" 3851 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r") 3852 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))] 3853 "register_operand (operands[0], SImode) 3854 || reg_or_0_operand (operands[1], SImode)" 3855 "@ 3856 bis $31,%r1,%0 3857 lda %0,%1($31) 3858 ldah %0,%h1($31) 3859 # 3860 ldl %0,%1 3861 stl %r1,%0 3862 lda %0,%1" 3863 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym") 3864 (set_attr "isa" "*,*,*,*,*,*,vms")]) 3865 3866;; Split a load of a large constant into the appropriate two-insn 3867;; sequence. 3868 3869(define_split 3870 [(set (match_operand:SI 0 "register_operand") 3871 (match_operand:SI 1 "non_add_const_operand"))] 3872 "" 3873 [(const_int 0)] 3874{ 3875 if (alpha_split_const_mov (SImode, operands)) 3876 DONE; 3877 else 3878 FAIL; 3879}) 3880 3881(define_insn "*movdi_er_low_l" 3882 [(set (match_operand:DI 0 "register_operand" "=r") 3883 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 3884 (match_operand:DI 2 "local_symbolic_operand")))] 3885 "TARGET_EXPLICIT_RELOCS" 3886{ 3887 if (true_regnum (operands[1]) == 29) 3888 return "lda %0,%2(%1)\t\t!gprel"; 3889 else 3890 return "lda %0,%2(%1)\t\t!gprellow"; 3891} 3892 [(set_attr "usegp" "yes")]) 3893 3894(define_split 3895 [(set (match_operand:DI 0 "register_operand") 3896 (match_operand:DI 1 "small_symbolic_operand"))] 3897 "TARGET_EXPLICIT_RELOCS && reload_completed" 3898 [(set (match_dup 0) 3899 (lo_sum:DI (match_dup 2) (match_dup 1)))] 3900 "operands[2] = pic_offset_table_rtx;") 3901 3902(define_split 3903 [(set (match_operand:DI 0 "register_operand") 3904 (match_operand:DI 1 "local_symbolic_operand"))] 3905 "TARGET_EXPLICIT_RELOCS && reload_completed" 3906 [(set (match_dup 0) 3907 (plus:DI (match_dup 2) (high:DI (match_dup 1)))) 3908 (set (match_dup 0) 3909 (lo_sum:DI (match_dup 0) (match_dup 1)))] 3910 "operands[2] = pic_offset_table_rtx;") 3911 3912(define_split 3913 [(match_operand 0 "some_small_symbolic_operand")] 3914 "" 3915 [(match_dup 0)] 3916 "operands[0] = split_small_symbolic_operand (operands[0]);") 3917 3918;; Accepts any symbolic, not just global, since function calls that 3919;; don't go via bsr still use !literal in hopes of linker relaxation. 3920(define_insn "movdi_er_high_g" 3921 [(set (match_operand:DI 0 "register_operand" "=r") 3922 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3923 (match_operand:DI 2 "symbolic_operand") 3924 (match_operand 3 "const_int_operand")] 3925 UNSPEC_LITERAL))] 3926 "TARGET_EXPLICIT_RELOCS" 3927{ 3928 if (INTVAL (operands[3]) == 0) 3929 return "ldq %0,%2(%1)\t\t!literal"; 3930 else 3931 return "ldq %0,%2(%1)\t\t!literal!%3"; 3932} 3933 [(set_attr "type" "ldsym")]) 3934 3935(define_split 3936 [(set (match_operand:DI 0 "register_operand") 3937 (match_operand:DI 1 "global_symbolic_operand"))] 3938 "TARGET_EXPLICIT_RELOCS && reload_completed" 3939 [(set (match_dup 0) 3940 (unspec:DI [(match_dup 2) 3941 (match_dup 1) 3942 (const_int 0)] UNSPEC_LITERAL))] 3943 "operands[2] = pic_offset_table_rtx;") 3944 3945(define_insn "movdi_er_tlsgd" 3946 [(set (match_operand:DI 0 "register_operand" "=r") 3947 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3948 (match_operand:DI 2 "symbolic_operand") 3949 (match_operand 3 "const_int_operand")] 3950 UNSPEC_TLSGD))] 3951 "HAVE_AS_TLS" 3952{ 3953 if (INTVAL (operands[3]) == 0) 3954 return "lda %0,%2(%1)\t\t!tlsgd"; 3955 else 3956 return "lda %0,%2(%1)\t\t!tlsgd!%3"; 3957}) 3958 3959(define_insn "movdi_er_tlsldm" 3960 [(set (match_operand:DI 0 "register_operand" "=r") 3961 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3962 (match_operand 2 "const_int_operand")] 3963 UNSPEC_TLSLDM))] 3964 "HAVE_AS_TLS" 3965{ 3966 if (INTVAL (operands[2]) == 0) 3967 return "lda %0,%&(%1)\t\t!tlsldm"; 3968 else 3969 return "lda %0,%&(%1)\t\t!tlsldm!%2"; 3970}) 3971 3972(define_insn "*movdi_er_gotdtp" 3973 [(set (match_operand:DI 0 "register_operand" "=r") 3974 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3975 (match_operand:DI 2 "symbolic_operand")] 3976 UNSPEC_DTPREL))] 3977 "HAVE_AS_TLS" 3978 "ldq %0,%2(%1)\t\t!gotdtprel" 3979 [(set_attr "type" "ild") 3980 (set_attr "usegp" "yes")]) 3981 3982(define_split 3983 [(set (match_operand:DI 0 "register_operand") 3984 (match_operand:DI 1 "gotdtp_symbolic_operand"))] 3985 "HAVE_AS_TLS && reload_completed" 3986 [(set (match_dup 0) 3987 (unspec:DI [(match_dup 2) 3988 (match_dup 1)] UNSPEC_DTPREL))] 3989{ 3990 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 3991 operands[2] = pic_offset_table_rtx; 3992}) 3993 3994(define_insn "*movdi_er_gottp" 3995 [(set (match_operand:DI 0 "register_operand" "=r") 3996 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3997 (match_operand:DI 2 "symbolic_operand")] 3998 UNSPEC_TPREL))] 3999 "HAVE_AS_TLS" 4000 "ldq %0,%2(%1)\t\t!gottprel" 4001 [(set_attr "type" "ild") 4002 (set_attr "usegp" "yes")]) 4003 4004(define_split 4005 [(set (match_operand:DI 0 "register_operand") 4006 (match_operand:DI 1 "gottp_symbolic_operand"))] 4007 "HAVE_AS_TLS && reload_completed" 4008 [(set (match_dup 0) 4009 (unspec:DI [(match_dup 2) 4010 (match_dup 1)] UNSPEC_TPREL))] 4011{ 4012 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4013 operands[2] = pic_offset_table_rtx; 4014}) 4015 4016(define_insn "*movdi" 4017 [(set (match_operand:DI 0 "nonimmediate_operand" 4018 "=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f") 4019 (match_operand:DI 1 "input_operand" 4020 "rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))] 4021 "register_operand (operands[0], DImode) 4022 || reg_or_0_operand (operands[1], DImode)" 4023 "@ 4024 mov %r1,%0 4025 lda %0,%1($31) 4026 ldah %0,%h1($31) 4027 # 4028 # 4029 # 4030 lda %0,%1 4031 ldq%A1 %0,%1 4032 stq%A0 %r1,%0 4033 fmov %R1,%0 4034 ldt %0,%1 4035 stt %R1,%0 4036 ftoit %1,%0 4037 itoft %1,%0" 4038 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") 4039 (set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix") 4040 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")]) 4041 4042;; VMS needs to set up "vms_base_regno" for unwinding. This move 4043;; often appears dead to the life analysis code, at which point we 4044;; die for emitting dead prologue instructions. Force this live. 4045 4046(define_insn "force_movdi" 4047 [(set (match_operand:DI 0 "register_operand" "=r") 4048 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")] 4049 UNSPECV_FORCE_MOV))] 4050 "" 4051 "mov %1,%0" 4052 [(set_attr "type" "ilog")]) 4053 4054;; We do three major things here: handle mem->mem, put 64-bit constants in 4055;; memory, and construct long 32-bit constants. 4056 4057(define_expand "movdi" 4058 [(set (match_operand:DI 0 "nonimmediate_operand") 4059 (match_operand:DI 1 "general_operand"))] 4060 "" 4061{ 4062 if (alpha_expand_mov (DImode, operands)) 4063 DONE; 4064}) 4065 4066;; Split a load of a large constant into the appropriate two-insn 4067;; sequence. 4068 4069(define_split 4070 [(set (match_operand:DI 0 "register_operand") 4071 (match_operand:DI 1 "non_add_const_operand"))] 4072 "" 4073 [(const_int 0)] 4074{ 4075 if (alpha_split_const_mov (DImode, operands)) 4076 DONE; 4077 else 4078 FAIL; 4079}) 4080 4081;; We need to prevent reload from splitting TImode moves, because it 4082;; might decide to overwrite a pointer with the value it points to. 4083;; In that case we have to do the loads in the appropriate order so 4084;; that the pointer is not destroyed too early. 4085 4086(define_insn_and_split "*movti_internal" 4087 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o") 4088 (match_operand:TI 1 "input_operand" "roJ,rJ"))] 4089 "(register_operand (operands[0], TImode) 4090 /* Prevent rematerialization of constants. */ 4091 && ! CONSTANT_P (operands[1])) 4092 || reg_or_0_operand (operands[1], TImode)" 4093 "#" 4094 "reload_completed" 4095 [(set (match_dup 0) (match_dup 2)) 4096 (set (match_dup 1) (match_dup 3))] 4097 "alpha_split_tmode_pair (operands, TImode, true);") 4098 4099(define_expand "movti" 4100 [(set (match_operand:TI 0 "nonimmediate_operand") 4101 (match_operand:TI 1 "general_operand"))] 4102 "" 4103{ 4104 if (MEM_P (operands[0]) 4105 && ! reg_or_0_operand (operands[1], TImode)) 4106 operands[1] = force_reg (TImode, operands[1]); 4107 4108 if (operands[1] == const0_rtx) 4109 ; 4110 /* We must put 64-bit constants in memory. We could keep the 4111 32-bit constants in TImode and rely on the splitter, but 4112 this doesn't seem to be worth the pain. */ 4113 else if (CONST_SCALAR_INT_P (operands[1])) 4114 { 4115 rtx in[2], out[2], target; 4116 4117 gcc_assert (can_create_pseudo_p ()); 4118 4119 split_double (operands[1], &in[0], &in[1]); 4120 4121 if (in[0] == const0_rtx) 4122 out[0] = const0_rtx; 4123 else 4124 { 4125 out[0] = gen_reg_rtx (DImode); 4126 emit_insn (gen_movdi (out[0], in[0])); 4127 } 4128 4129 if (in[1] == const0_rtx) 4130 out[1] = const0_rtx; 4131 else 4132 { 4133 out[1] = gen_reg_rtx (DImode); 4134 emit_insn (gen_movdi (out[1], in[1])); 4135 } 4136 4137 if (!REG_P (operands[0])) 4138 target = gen_reg_rtx (TImode); 4139 else 4140 target = operands[0]; 4141 4142 emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0])); 4143 emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1])); 4144 4145 if (target != operands[0]) 4146 emit_insn (gen_rtx_SET (operands[0], target)); 4147 4148 DONE; 4149 } 4150}) 4151 4152;; These are the partial-word cases. 4153;; 4154;; First we have the code to load an aligned word. Operand 0 is the register 4155;; in which to place the result. It's mode is QImode or HImode. Operand 1 4156;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the 4157;; number of bits within the word that the value is. Operand 3 is an SImode 4158;; scratch register. If operand 0 is a hard register, operand 3 may be the 4159;; same register. It is allowed to conflict with operand 1 as well. 4160 4161(define_expand "aligned_loadqi" 4162 [(set (match_operand:SI 3 "register_operand") 4163 (match_operand:SI 1 "memory_operand")) 4164 (set (match_operand:DI 0 "register_operand") 4165 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4166 (const_int 8) 4167 (match_operand:DI 2 "const_int_operand")))]) 4168 4169(define_expand "aligned_loadhi" 4170 [(set (match_operand:SI 3 "register_operand") 4171 (match_operand:SI 1 "memory_operand")) 4172 (set (match_operand:DI 0 "register_operand") 4173 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4174 (const_int 16) 4175 (match_operand:DI 2 "const_int_operand")))]) 4176 4177;; Similar for unaligned loads, where we use the sequence from the 4178;; Alpha Architecture manual. We have to distinguish between little-endian 4179;; and big-endian systems as the sequences are different. 4180;; 4181;; Operand 1 is the address. Operands 2 and 3 are temporaries, where 4182;; operand 3 can overlap the input and output registers. 4183 4184(define_expand "unaligned_loadqi" 4185 [(set (match_operand:DI 2 "register_operand") 4186 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4187 (const_int -8)))) 4188 (set (match_operand:DI 3 "register_operand") 4189 (match_dup 1)) 4190 (set (match_operand:DI 0 "register_operand") 4191 (zero_extract:DI (match_dup 2) 4192 (const_int 8) 4193 (ashift:DI (match_dup 3) (const_int 3))))]) 4194 4195(define_expand "unaligned_loadhi" 4196 [(set (match_operand:DI 2 "register_operand") 4197 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4198 (const_int -8)))) 4199 (set (match_operand:DI 3 "register_operand") 4200 (match_dup 1)) 4201 (set (match_operand:DI 0 "register_operand") 4202 (zero_extract:DI (match_dup 2) 4203 (const_int 16) 4204 (ashift:DI (match_dup 3) (const_int 3))))]) 4205 4206;; Storing an aligned byte or word requires two temporaries. Operand 0 is the 4207;; aligned SImode MEM. Operand 1 is the register containing the 4208;; byte or word to store. Operand 2 is the number of bits within the word that 4209;; the value should be placed. Operands 3 and 4 are SImode temporaries. 4210 4211(define_expand "aligned_store" 4212 [(set (match_operand:SI 3 "register_operand") 4213 (match_operand:SI 0 "memory_operand")) 4214 (set (subreg:DI (match_dup 3) 0) 4215 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) 4216 (set (subreg:DI (match_operand:SI 4 "register_operand") 0) 4217 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand")) 4218 (match_operand:DI 2 "const_int_operand"))) 4219 (set (subreg:DI (match_dup 4) 0) 4220 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) 4221 (set (match_dup 0) (match_dup 4))] 4222 "" 4223{ 4224 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) 4225 << INTVAL (operands[2]))); 4226}) 4227 4228;; For the unaligned byte and halfword cases, we use code similar to that 4229;; in the ;; Architecture book, but reordered to lower the number of registers 4230;; required. Operand 0 is the address. Operand 1 is the data to store. 4231;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may 4232;; be the same temporary, if desired. If the address is in a register, 4233;; operand 2 can be that register. 4234 4235(define_expand "@unaligned_store<mode>" 4236 [(set (match_operand:DI 3 "register_operand") 4237 (mem:DI (and:DI (match_operand:DI 0 "address_operand") 4238 (const_int -8)))) 4239 (set (match_operand:DI 2 "register_operand") 4240 (match_dup 0)) 4241 (set (match_dup 3) 4242 (and:DI (not:DI (ashift:DI (match_dup 5) 4243 (ashift:DI (match_dup 2) (const_int 3)))) 4244 (match_dup 3))) 4245 (set (match_operand:DI 4 "register_operand") 4246 (ashift:DI (zero_extend:DI 4247 (match_operand:I12MODE 1 "register_operand")) 4248 (ashift:DI (match_dup 2) (const_int 3)))) 4249 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 4250 (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 4251 (match_dup 4))] 4252 "" 4253 "operands[5] = GEN_INT (GET_MODE_MASK (<MODE>mode));") 4254 4255;; Here are the define_expand's for QI and HI moves that use the above 4256;; patterns. We have the normal sets, plus the ones that need scratch 4257;; registers for reload. 4258 4259(define_expand "mov<mode>" 4260 [(set (match_operand:I12MODE 0 "nonimmediate_operand") 4261 (match_operand:I12MODE 1 "general_operand"))] 4262 "" 4263{ 4264 if (TARGET_BWX 4265 ? alpha_expand_mov (<MODE>mode, operands) 4266 : alpha_expand_mov_nobwx (<MODE>mode, operands)) 4267 DONE; 4268}) 4269 4270(define_insn "*movqi" 4271 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") 4272 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))] 4273 "register_operand (operands[0], QImode) 4274 || reg_or_0_operand (operands[1], QImode)" 4275 "@ 4276 bis $31,%r1,%0 4277 lda %0,%L1($31) 4278 ldbu %0,%1 4279 stb %r1,%0" 4280 [(set_attr "type" "ilog,iadd,ild,ist") 4281 (set_attr "isa" "*,*,bwx,bwx")]) 4282 4283(define_insn "*movhi" 4284 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") 4285 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))] 4286 "register_operand (operands[0], HImode) 4287 || reg_or_0_operand (operands[1], HImode)" 4288 "@ 4289 bis $31,%r1,%0 4290 lda %0,%L1($31) 4291 ldwu %0,%1 4292 stw %r1,%0" 4293 [(set_attr "type" "ilog,iadd,ild,ist") 4294 (set_attr "isa" "*,*,bwx,bwx")]) 4295 4296;; We need to hook into the extra support that we have for HImode 4297;; reloads when BWX insns are not available. 4298(define_expand "movcqi" 4299 [(set (match_operand:CQI 0 "nonimmediate_operand") 4300 (match_operand:CQI 1 "general_operand"))] 4301 "!TARGET_BWX" 4302{ 4303 if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT) 4304 ; 4305 else if (!any_memory_operand (operands[0], CQImode)) 4306 { 4307 if (!any_memory_operand (operands[1], CQImode)) 4308 { 4309 emit_move_insn (gen_lowpart (HImode, operands[0]), 4310 gen_lowpart (HImode, operands[1])); 4311 DONE; 4312 } 4313 if (aligned_memory_operand (operands[1], CQImode)) 4314 { 4315 bool done; 4316 do_aligned1: 4317 operands[1] = gen_lowpart (HImode, operands[1]); 4318 do_aligned2: 4319 operands[0] = gen_lowpart (HImode, operands[0]); 4320 done = alpha_expand_mov_nobwx (HImode, operands); 4321 gcc_assert (done); 4322 DONE; 4323 } 4324 } 4325 else if (aligned_memory_operand (operands[0], CQImode)) 4326 { 4327 if (MEM_P (operands[1])) 4328 { 4329 rtx x = gen_reg_rtx (HImode); 4330 emit_move_insn (gen_lowpart (CQImode, x), operands[1]); 4331 operands[1] = x; 4332 goto do_aligned2; 4333 } 4334 goto do_aligned1; 4335 } 4336 4337 gcc_assert (!reload_in_progress); 4338 emit_move_complex_parts (operands[0], operands[1]); 4339 DONE; 4340}) 4341 4342;; Here are the versions for reload. 4343;; 4344;; The aligned input case is recognized early in alpha_secondary_reload 4345;; in order to avoid allocating an unnecessary scratch register. 4346;; 4347;; Note that in the unaligned cases we know that the operand must not be 4348;; a pseudo-register because stack slots are always aligned references. 4349 4350(define_expand "reload_in<mode>" 4351 [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r") 4352 (match_operand:RELOAD12 1 "any_memory_operand" "m") 4353 (match_operand:TI 2 "register_operand" "=&r")])] 4354 "!TARGET_BWX" 4355{ 4356 rtx scratch, seq, addr; 4357 unsigned regno = REGNO (operands[2]); 4358 4359 /* It is possible that one of the registers we got for operands[2] 4360 might coincide with that of operands[0] (which is why we made 4361 it TImode). Pick the other one to use as our scratch. */ 4362 if (regno == REGNO (operands[0])) 4363 regno++; 4364 scratch = gen_rtx_REG (DImode, regno); 4365 4366 addr = get_unaligned_address (operands[1]); 4367 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 4368 seq = gen_unaligned_load<reloadmode> (operands[0], addr, 4369 scratch, operands[0]); 4370 alpha_set_memflags (seq, operands[1]); 4371 4372 emit_insn (seq); 4373 DONE; 4374}) 4375 4376(define_expand "reload_out<mode>" 4377 [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m") 4378 (match_operand:RELOAD12 1 "register_operand" "r") 4379 (match_operand:TI 2 "register_operand" "=&r")])] 4380 "!TARGET_BWX" 4381{ 4382 unsigned regno = REGNO (operands[2]); 4383 4384 if (<MODE>mode == CQImode) 4385 { 4386 operands[0] = gen_lowpart (HImode, operands[0]); 4387 operands[1] = gen_lowpart (HImode, operands[1]); 4388 } 4389 4390 if (aligned_memory_operand (operands[0], <MODE>mode)) 4391 { 4392 emit_insn (gen_reload_out<reloadmode>_aligned 4393 (operands[0], operands[1], 4394 gen_rtx_REG (SImode, regno), 4395 gen_rtx_REG (SImode, regno + 1))); 4396 } 4397 else 4398 { 4399 rtx addr = get_unaligned_address (operands[0]); 4400 rtx scratch1 = gen_rtx_REG (DImode, regno); 4401 rtx scratch2 = gen_rtx_REG (DImode, regno + 1); 4402 rtx scratch3 = scratch1; 4403 rtx seq; 4404 4405 if (REG_P (addr)) 4406 scratch1 = addr; 4407 4408 seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1, 4409 scratch2, scratch3); 4410 alpha_set_memflags (seq, operands[0]); 4411 emit_insn (seq); 4412 } 4413 DONE; 4414}) 4415 4416;; Helpers for the above. The way reload is structured, we can't 4417;; always get a proper address for a stack slot during reload_foo 4418;; expansion, so we must delay our address manipulations until after. 4419 4420(define_insn_and_split "@reload_in<mode>_aligned" 4421 [(set (match_operand:I12MODE 0 "register_operand" "=r") 4422 (match_operand:I12MODE 1 "memory_operand" "m"))] 4423 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4424 "#" 4425 "!TARGET_BWX && reload_completed" 4426 [(const_int 0)] 4427{ 4428 rtx aligned_mem, bitnum; 4429 get_aligned_mem (operands[1], &aligned_mem, &bitnum); 4430 emit_insn (gen_aligned_load<reloadmode> 4431 (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum, 4432 gen_rtx_REG (SImode, REGNO (operands[0])))); 4433 DONE; 4434}) 4435 4436(define_insn_and_split "reload_out<mode>_aligned" 4437 [(set (match_operand:I12MODE 0 "memory_operand" "=m") 4438 (match_operand:I12MODE 1 "register_operand" "r")) 4439 (clobber (match_operand:SI 2 "register_operand" "=&r")) 4440 (clobber (match_operand:SI 3 "register_operand" "=&r"))] 4441 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4442 "#" 4443 "!TARGET_BWX && reload_completed" 4444 [(const_int 0)] 4445{ 4446 rtx aligned_mem, bitnum; 4447 get_aligned_mem (operands[0], &aligned_mem, &bitnum); 4448 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 4449 operands[2], operands[3])); 4450 DONE; 4451}) 4452 4453;; Vector operations 4454 4455(define_mode_iterator VEC [V8QI V4HI V2SI]) 4456(define_mode_iterator VEC12 [V8QI V4HI]) 4457 4458(define_expand "mov<mode>" 4459 [(set (match_operand:VEC 0 "nonimmediate_operand") 4460 (match_operand:VEC 1 "general_operand"))] 4461 "" 4462{ 4463 if (alpha_expand_mov (<MODE>mode, operands)) 4464 DONE; 4465}) 4466 4467(define_split 4468 [(set (match_operand:VEC 0 "register_operand") 4469 (match_operand:VEC 1 "non_zero_const_operand"))] 4470 "" 4471 [(const_int 0)] 4472{ 4473 if (alpha_split_const_mov (<MODE>mode, operands)) 4474 DONE; 4475 else 4476 FAIL; 4477}) 4478 4479 4480(define_expand "movmisalign<mode>" 4481 [(set (match_operand:VEC 0 "nonimmediate_operand") 4482 (match_operand:VEC 1 "general_operand"))] 4483 "" 4484{ 4485 alpha_expand_movmisalign (<MODE>mode, operands); 4486 DONE; 4487}) 4488 4489(define_insn "*mov<mode>_fix" 4490 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f") 4491 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))] 4492 "register_operand (operands[0], <MODE>mode) 4493 || reg_or_0_operand (operands[1], <MODE>mode)" 4494 "@ 4495 bis $31,%r1,%0 4496 # 4497 ldq %0,%1 4498 stq %r1,%0 4499 cpys %R1,%R1,%0 4500 ldt %0,%1 4501 stt %R1,%0 4502 ftoit %1,%0 4503 itoft %1,%0" 4504 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof") 4505 (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")]) 4506 4507(define_insn "<code><mode>3" 4508 [(set (match_operand:VEC12 0 "register_operand" "=r") 4509 (any_maxmin:VEC12 4510 (match_operand:VEC12 1 "reg_or_0_operand" "rW") 4511 (match_operand:VEC12 2 "reg_or_0_operand" "rW")))] 4512 "TARGET_MAX" 4513 "<maxmin><modesuffix> %r1,%r2,%0" 4514 [(set_attr "type" "mvi")]) 4515 4516(define_insn "one_cmpl<mode>2" 4517 [(set (match_operand:VEC 0 "register_operand" "=r") 4518 (not:VEC (match_operand:VEC 1 "register_operand" "r")))] 4519 "" 4520 "ornot $31,%1,%0" 4521 [(set_attr "type" "ilog")]) 4522 4523(define_insn "and<mode>3" 4524 [(set (match_operand:VEC 0 "register_operand" "=r") 4525 (and:VEC (match_operand:VEC 1 "register_operand" "r") 4526 (match_operand:VEC 2 "register_operand" "r")))] 4527 "" 4528 "and %1,%2,%0" 4529 [(set_attr "type" "ilog")]) 4530 4531(define_insn "*andnot<mode>3" 4532 [(set (match_operand:VEC 0 "register_operand" "=r") 4533 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r")) 4534 (match_operand:VEC 2 "register_operand" "r")))] 4535 "" 4536 "bic %2,%1,%0" 4537 [(set_attr "type" "ilog")]) 4538 4539(define_insn "ior<mode>3" 4540 [(set (match_operand:VEC 0 "register_operand" "=r") 4541 (ior:VEC (match_operand:VEC 1 "register_operand" "r") 4542 (match_operand:VEC 2 "register_operand" "r")))] 4543 "" 4544 "bis %1,%2,%0" 4545 [(set_attr "type" "ilog")]) 4546 4547(define_insn "*iornot<mode>3" 4548 [(set (match_operand:VEC 0 "register_operand" "=r") 4549 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r")) 4550 (match_operand:VEC 2 "register_operand" "r")))] 4551 "" 4552 "ornot %2,%1,%0" 4553 [(set_attr "type" "ilog")]) 4554 4555(define_insn "xor<mode>3" 4556 [(set (match_operand:VEC 0 "register_operand" "=r") 4557 (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4558 (match_operand:VEC 2 "register_operand" "r")))] 4559 "" 4560 "xor %1,%2,%0" 4561 [(set_attr "type" "ilog")]) 4562 4563(define_insn "*xornot<mode>3" 4564 [(set (match_operand:VEC 0 "register_operand" "=r") 4565 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4566 (match_operand:VEC 2 "register_operand" "r"))))] 4567 "" 4568 "eqv %1,%2,%0" 4569 [(set_attr "type" "ilog")]) 4570 4571(define_expand "vec_shl_<mode>" 4572 [(set (match_operand:VEC 0 "register_operand") 4573 (ashift:DI (match_operand:VEC 1 "register_operand") 4574 (match_operand:DI 2 "reg_or_6bit_operand")))] 4575 "" 4576{ 4577 operands[0] = gen_lowpart (DImode, operands[0]); 4578 operands[1] = gen_lowpart (DImode, operands[1]); 4579}) 4580 4581(define_expand "vec_shr_<mode>" 4582 [(set (match_operand:VEC 0 "register_operand") 4583 (lshiftrt:DI (match_operand:VEC 1 "register_operand") 4584 (match_operand:DI 2 "reg_or_6bit_operand")))] 4585 "" 4586{ 4587 operands[0] = gen_lowpart (DImode, operands[0]); 4588 operands[1] = gen_lowpart (DImode, operands[1]); 4589}) 4590 4591;; Bit field extract patterns which use ext[wlq][lh] 4592 4593(define_expand "extvmisaligndi" 4594 [(set (match_operand:DI 0 "register_operand") 4595 (sign_extract:DI (match_operand:BLK 1 "memory_operand") 4596 (match_operand:DI 2 "const_int_operand") 4597 (match_operand:DI 3 "const_int_operand")))] 4598 "" 4599{ 4600 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4601 if (INTVAL (operands[3]) % 8 != 0 4602 || (INTVAL (operands[2]) != 16 4603 && INTVAL (operands[2]) != 32 4604 && INTVAL (operands[2]) != 64)) 4605 FAIL; 4606 4607 alpha_expand_unaligned_load (operands[0], operands[1], 4608 INTVAL (operands[2]) / 8, 4609 INTVAL (operands[3]) / 8, 1); 4610 DONE; 4611}) 4612 4613(define_expand "extzvdi" 4614 [(set (match_operand:DI 0 "register_operand") 4615 (zero_extract:DI (match_operand:DI 1 "register_operand") 4616 (match_operand:DI 2 "const_int_operand") 4617 (match_operand:DI 3 "const_int_operand")))] 4618 "" 4619{ 4620 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4621 if (INTVAL (operands[3]) % 8 != 0 4622 || (INTVAL (operands[2]) != 8 4623 && INTVAL (operands[2]) != 16 4624 && INTVAL (operands[2]) != 32 4625 && INTVAL (operands[2]) != 64)) 4626 FAIL; 4627}) 4628 4629(define_expand "extzvmisaligndi" 4630 [(set (match_operand:DI 0 "register_operand") 4631 (zero_extract:DI (match_operand:BLK 1 "memory_operand") 4632 (match_operand:DI 2 "const_int_operand") 4633 (match_operand:DI 3 "const_int_operand")))] 4634 "" 4635{ 4636 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. 4637 We fail 8-bit fields, falling back on a simple byte load. */ 4638 if (INTVAL (operands[3]) % 8 != 0 4639 || (INTVAL (operands[2]) != 16 4640 && INTVAL (operands[2]) != 32 4641 && INTVAL (operands[2]) != 64)) 4642 FAIL; 4643 4644 alpha_expand_unaligned_load (operands[0], operands[1], 4645 INTVAL (operands[2]) / 8, 4646 INTVAL (operands[3]) / 8, 0); 4647 DONE; 4648}) 4649 4650(define_expand "insvmisaligndi" 4651 [(set (zero_extract:DI (match_operand:BLK 0 "memory_operand") 4652 (match_operand:DI 1 "const_int_operand") 4653 (match_operand:DI 2 "const_int_operand")) 4654 (match_operand:DI 3 "register_operand"))] 4655 "" 4656{ 4657 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4658 if (INTVAL (operands[2]) % 8 != 0 4659 || (INTVAL (operands[1]) != 16 4660 && INTVAL (operands[1]) != 32 4661 && INTVAL (operands[1]) != 64)) 4662 FAIL; 4663 4664 alpha_expand_unaligned_store (operands[0], operands[3], 4665 INTVAL (operands[1]) / 8, 4666 INTVAL (operands[2]) / 8); 4667 DONE; 4668}) 4669 4670;; Block move/clear, see alpha.c for more details. 4671;; Argument 0 is the destination 4672;; Argument 1 is the source 4673;; Argument 2 is the length 4674;; Argument 3 is the alignment 4675 4676(define_expand "cpymemqi" 4677 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4678 (match_operand:BLK 1 "memory_operand")) 4679 (use (match_operand:DI 2 "immediate_operand")) 4680 (use (match_operand:DI 3 "immediate_operand"))])] 4681 "" 4682{ 4683 if (alpha_expand_block_move (operands)) 4684 DONE; 4685 else 4686 FAIL; 4687}) 4688 4689(define_expand "cpymemdi" 4690 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4691 (match_operand:BLK 1 "memory_operand")) 4692 (use (match_operand:DI 2 "immediate_operand")) 4693 (use (match_operand:DI 3 "immediate_operand")) 4694 (use (match_dup 4)) 4695 (clobber (reg:DI 25)) 4696 (clobber (reg:DI 16)) 4697 (clobber (reg:DI 17)) 4698 (clobber (reg:DI 18)) 4699 (clobber (reg:DI 19)) 4700 (clobber (reg:DI 20)) 4701 (clobber (reg:DI 26)) 4702 (clobber (reg:DI 27))])] 4703 "TARGET_ABI_OPEN_VMS" 4704 "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");") 4705 4706(define_insn "*cpymemdi_1" 4707 [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4708 (match_operand:BLK 1 "memory_operand" "m,m")) 4709 (use (match_operand:DI 2 "nonmemory_operand" "r,i")) 4710 (use (match_operand:DI 3 "immediate_operand")) 4711 (use (match_operand:DI 4 "call_operand" "i,i")) 4712 (clobber (reg:DI 25)) 4713 (clobber (reg:DI 16)) 4714 (clobber (reg:DI 17)) 4715 (clobber (reg:DI 18)) 4716 (clobber (reg:DI 19)) 4717 (clobber (reg:DI 20)) 4718 (clobber (reg:DI 26)) 4719 (clobber (reg:DI 27))] 4720 "TARGET_ABI_OPEN_VMS" 4721{ 4722 operands [5] = alpha_use_linkage (operands [4], false, true); 4723 switch (which_alternative) 4724 { 4725 case 0: 4726 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4727 case 1: 4728 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4729 default: 4730 gcc_unreachable (); 4731 } 4732} 4733 [(set_attr "type" "multi") 4734 (set_attr "length" "28")]) 4735 4736(define_expand "setmemqi" 4737 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4738 (match_operand 2 "const_int_operand")) 4739 (use (match_operand:DI 1 "immediate_operand")) 4740 (use (match_operand:DI 3 "immediate_operand"))])] 4741 "" 4742{ 4743 /* If value to set is not zero, use the library routine. */ 4744 if (operands[2] != const0_rtx) 4745 FAIL; 4746 4747 if (alpha_expand_block_clear (operands)) 4748 DONE; 4749 else 4750 FAIL; 4751}) 4752 4753(define_expand "setmemdi" 4754 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4755 (match_operand 2 "const_int_operand")) 4756 (use (match_operand:DI 1 "immediate_operand")) 4757 (use (match_operand:DI 3 "immediate_operand")) 4758 (use (match_dup 4)) 4759 (clobber (reg:DI 25)) 4760 (clobber (reg:DI 16)) 4761 (clobber (reg:DI 17)) 4762 (clobber (reg:DI 26)) 4763 (clobber (reg:DI 27))])] 4764 "TARGET_ABI_OPEN_VMS" 4765{ 4766 /* If value to set is not zero, use the library routine. */ 4767 if (operands[2] != const0_rtx) 4768 FAIL; 4769 4770 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO"); 4771}) 4772 4773(define_insn "*clrmemdi_1" 4774 [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4775 (const_int 0)) 4776 (use (match_operand:DI 1 "nonmemory_operand" "r,i")) 4777 (use (match_operand:DI 2 "immediate_operand")) 4778 (use (match_operand:DI 3 "call_operand" "i,i")) 4779 (clobber (reg:DI 25)) 4780 (clobber (reg:DI 16)) 4781 (clobber (reg:DI 17)) 4782 (clobber (reg:DI 26)) 4783 (clobber (reg:DI 27))] 4784 "TARGET_ABI_OPEN_VMS" 4785{ 4786 operands [4] = alpha_use_linkage (operands [3], false, true); 4787 switch (which_alternative) 4788 { 4789 case 0: 4790 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4791 case 1: 4792 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4793 default: 4794 gcc_unreachable (); 4795 } 4796} 4797 [(set_attr "type" "multi") 4798 (set_attr "length" "24")]) 4799 4800 4801;; Subroutine of stack space allocation. Perform a stack probe. 4802(define_expand "stack_probe_internal" 4803 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))] 4804 "" 4805{ 4806 operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx, 4807 INTVAL (operands[0]))); 4808 MEM_VOLATILE_P (operands[1]) = 1; 4809 4810 operands[0] = const0_rtx; 4811}) 4812 4813;; This is how we allocate stack space. If we are allocating a 4814;; constant amount of space and we know it is less than 4096 4815;; bytes, we need do nothing. 4816;; 4817;; If it is more than 4096 bytes, we need to probe the stack 4818;; periodically. 4819(define_expand "allocate_stack" 4820 [(set (reg:DI 30) 4821 (plus:DI (reg:DI 30) 4822 (match_operand:DI 1 "reg_or_cint_operand"))) 4823 (set (match_operand:DI 0 "register_operand" "=r") 4824 (match_dup 2))] 4825 "" 4826{ 4827 if (CONST_INT_P (operands[1]) 4828 && INTVAL (operands[1]) < 32768) 4829 { 4830 if (INTVAL (operands[1]) >= 4096) 4831 { 4832 /* We do this the same way as in the prologue and generate explicit 4833 probes. Then we update the stack by the constant. */ 4834 4835 int probed = 4096; 4836 4837 emit_insn (gen_stack_probe_internal (GEN_INT (- probed))); 4838 while (probed + 8192 < INTVAL (operands[1])) 4839 emit_insn (gen_stack_probe_internal 4840 (GEN_INT (- (probed += 8192)))); 4841 4842 if (probed + 4096 < INTVAL (operands[1])) 4843 emit_insn (gen_stack_probe_internal 4844 (GEN_INT (- INTVAL(operands[1])))); 4845 } 4846 4847 operands[1] = GEN_INT (- INTVAL (operands[1])); 4848 operands[2] = virtual_stack_dynamic_rtx; 4849 } 4850 else 4851 { 4852 rtx_code_label *out_label = 0; 4853 rtx_code_label *loop_label = gen_label_rtx (); 4854 rtx want = gen_reg_rtx (Pmode); 4855 rtx tmp = gen_reg_rtx (Pmode); 4856 rtx memref, test; 4857 4858 emit_insn (gen_subdi3 (want, stack_pointer_rtx, 4859 force_reg (Pmode, operands[1]))); 4860 4861 if (!CONST_INT_P (operands[1])) 4862 { 4863 rtx limit = GEN_INT (4096); 4864 out_label = gen_label_rtx (); 4865 test = gen_rtx_LTU (VOIDmode, operands[1], limit); 4866 emit_jump_insn 4867 (gen_cbranchdi4 (test, operands[1], limit, out_label)); 4868 } 4869 4870 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); 4871 emit_label (loop_label); 4872 memref = gen_rtx_MEM (DImode, tmp); 4873 MEM_VOLATILE_P (memref) = 1; 4874 emit_move_insn (memref, const0_rtx); 4875 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); 4876 test = gen_rtx_GTU (VOIDmode, tmp, want); 4877 emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label)); 4878 4879 memref = gen_rtx_MEM (DImode, want); 4880 MEM_VOLATILE_P (memref) = 1; 4881 emit_move_insn (memref, const0_rtx); 4882 4883 if (out_label) 4884 emit_label (out_label); 4885 4886 emit_move_insn (stack_pointer_rtx, want); 4887 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 4888 DONE; 4889 } 4890}) 4891 4892;; This is used by alpha_expand_prolog to do the same thing as above, 4893;; except we cannot at that time generate new basic blocks, so we hide 4894;; the loop in this one insn. 4895 4896(define_insn "prologue_stack_probe_loop" 4897 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") 4898 (match_operand:DI 1 "register_operand" "r")] 4899 UNSPECV_PSPL)] 4900 "" 4901{ 4902 operands[2] = gen_label_rtx (); 4903 (*targetm.asm_out.internal_label) (asm_out_file, "L", 4904 CODE_LABEL_NUMBER (operands[2])); 4905 4906 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2"; 4907} 4908 [(set_attr "length" "16") 4909 (set_attr "type" "multi")]) 4910 4911(define_expand "prologue" 4912 [(const_int 0)] 4913 "" 4914{ 4915 alpha_expand_prologue (); 4916 DONE; 4917}) 4918 4919;; These take care of emitting the ldgp insn in the prologue. This will be 4920;; an lda/ldah pair and we want to align them properly. So we have two 4921;; unspec_volatile insns, the first of which emits the ldgp assembler macro 4922;; and the second of which emits nothing. However, both are marked as type 4923;; IADD (the default) so the alignment code in alpha.c does the right thing 4924;; with them. 4925 4926(define_expand "prologue_ldgp" 4927 [(set (match_dup 0) 4928 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 4929 (set (match_dup 0) 4930 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))] 4931 "" 4932{ 4933 operands[0] = pic_offset_table_rtx; 4934 operands[1] = gen_rtx_REG (Pmode, 27); 4935 operands[2] = (TARGET_EXPLICIT_RELOCS 4936 ? GEN_INT (alpha_next_sequence_number++) 4937 : const0_rtx); 4938}) 4939 4940(define_insn "*ldgp_er_1" 4941 [(set (match_operand:DI 0 "register_operand" "=r") 4942 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4943 (match_operand 2 "const_int_operand")] 4944 UNSPECV_LDGP1))] 4945 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4946 "ldah %0,0(%1)\t\t!gpdisp!%2" 4947 [(set_attr "cannot_copy" "true")]) 4948 4949(define_insn "*ldgp_er_2" 4950 [(set (match_operand:DI 0 "register_operand" "=r") 4951 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4952 (match_operand 2 "const_int_operand")] 4953 UNSPEC_LDGP2))] 4954 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4955 "lda %0,0(%1)\t\t!gpdisp!%2" 4956 [(set_attr "cannot_copy" "true")]) 4957 4958(define_insn "*prologue_ldgp_er_2" 4959 [(set (match_operand:DI 0 "register_operand" "=r") 4960 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4961 (match_operand 2 "const_int_operand")] 4962 UNSPECV_PLDGP2))] 4963 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4964 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:" 4965 [(set_attr "cannot_copy" "true")]) 4966 4967(define_insn "*prologue_ldgp_1" 4968 [(set (match_operand:DI 0 "register_operand" "=r") 4969 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4970 (match_operand 2 "const_int_operand")] 4971 UNSPECV_LDGP1))] 4972 "" 4973 "ldgp %0,0(%1)\n$%~..ng:" 4974 [(set_attr "cannot_copy" "true")]) 4975 4976(define_insn "*prologue_ldgp_2" 4977 [(set (match_operand:DI 0 "register_operand" "=r") 4978 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4979 (match_operand 2 "const_int_operand")] 4980 UNSPECV_PLDGP2))] 4981 "" 4982 ) 4983 4984;; The _mcount profiling hook has special calling conventions, and 4985;; does not clobber all the registers that a normal call would. So 4986;; hide the fact this is a call at all. 4987 4988(define_insn "prologue_mcount" 4989 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)] 4990 "" 4991{ 4992 if (TARGET_EXPLICIT_RELOCS) 4993 /* Note that we cannot use a lituse_jsr reloc, since _mcount 4994 cannot be called via the PLT. */ 4995 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount"; 4996 else 4997 return "lda $28,_mcount\;jsr $28,($28),_mcount"; 4998} 4999 [(set_attr "type" "multi") 5000 (set_attr "length" "8")]) 5001 5002(define_insn "init_fp" 5003 [(set (match_operand:DI 0 "register_operand" "=r") 5004 (match_operand:DI 1 "register_operand" "r")) 5005 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))] 5006 "" 5007 "bis $31,%1,%0") 5008 5009(define_expand "epilogue" 5010 [(return)] 5011 "" 5012 "alpha_expand_epilogue ();") 5013 5014(define_expand "sibcall_epilogue" 5015 [(return)] 5016 "TARGET_ABI_OSF" 5017{ 5018 alpha_expand_epilogue (); 5019 DONE; 5020}) 5021 5022(define_expand "builtin_longjmp" 5023 [(use (match_operand:DI 0 "register_operand" "r"))] 5024 "TARGET_ABI_OSF" 5025{ 5026 /* The elements of the buffer are, in order: */ 5027 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 5028 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 8)); 5029 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 16)); 5030 rtx pv = gen_rtx_REG (Pmode, 27); 5031 5032 /* This bit is the same as expand_builtin_longjmp. */ 5033 emit_move_insn (hard_frame_pointer_rtx, fp); 5034 emit_move_insn (pv, lab); 5035 emit_stack_restore (SAVE_NONLOCAL, stack); 5036 emit_use (hard_frame_pointer_rtx); 5037 emit_use (stack_pointer_rtx); 5038 5039 /* Load the label we are jumping through into $27 so that we know 5040 where to look for it when we get back to setjmp's function for 5041 restoring the gp. */ 5042 emit_jump_insn (gen_builtin_longjmp_internal (pv)); 5043 emit_barrier (); 5044 DONE; 5045}) 5046 5047;; This is effectively a copy of indirect_jump, but constrained such 5048;; that register renaming cannot foil our cunning plan with $27. 5049(define_insn "builtin_longjmp_internal" 5050 [(set (pc) 5051 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 5052 UNSPECV_LONGJMP))] 5053 "" 5054 "jmp $31,(%0),0" 5055 [(set_attr "type" "ibr")]) 5056 5057(define_expand "builtin_setjmp_receiver" 5058 [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)] 5059 "TARGET_ABI_OSF") 5060 5061(define_insn_and_split "*builtin_setjmp_receiver_1" 5062 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)] 5063 "TARGET_ABI_OSF" 5064{ 5065 if (TARGET_EXPLICIT_RELOCS) 5066 return "#"; 5067 else 5068 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"; 5069} 5070 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5071 [(set (match_dup 1) 5072 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1)) 5073 (set (match_dup 1) 5074 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))] 5075{ 5076 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0)) 5077 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]), 5078 UNSPECV_SETJMPR_ER)); 5079 operands[1] = pic_offset_table_rtx; 5080 operands[2] = gen_rtx_REG (Pmode, 27); 5081 operands[3] = GEN_INT (alpha_next_sequence_number++); 5082} 5083 [(set_attr "length" "12") 5084 (set_attr "type" "multi")]) 5085 5086(define_insn "*builtin_setjmp_receiver_er_sl_1" 5087 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)] 5088 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS" 5089 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:") 5090 5091;; When flag_reorder_blocks_and_partition is in effect, compiler puts 5092;; exception landing pads in a cold section. To prevent inter-section offset 5093;; calculation, a jump to original landing pad is emitted in the place of the 5094;; original landing pad. Since landing pad is moved, RA-relative GP 5095;; calculation in the prologue of landing pad breaks. To solve this problem, 5096;; we use alternative GP load approach. 5097 5098(define_expand "exception_receiver" 5099 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)] 5100 "TARGET_ABI_OSF" 5101{ 5102 if (flag_reorder_blocks_and_partition) 5103 operands[0] = copy_rtx (alpha_gp_save_rtx ()); 5104 else 5105 operands[0] = const0_rtx; 5106}) 5107 5108(define_insn "*exception_receiver_2" 5109 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)] 5110 "TARGET_ABI_OSF && flag_reorder_blocks_and_partition" 5111 "ldq $29,%0" 5112 [(set_attr "type" "ild")]) 5113 5114(define_insn_and_split "*exception_receiver_1" 5115 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)] 5116 "TARGET_ABI_OSF" 5117{ 5118 if (TARGET_EXPLICIT_RELOCS) 5119 return "#"; 5120 else 5121 return "ldgp $29,0($26)"; 5122} 5123 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5124 [(set (match_dup 0) 5125 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 5126 (set (match_dup 0) 5127 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))] 5128{ 5129 operands[0] = pic_offset_table_rtx; 5130 operands[1] = gen_rtx_REG (Pmode, 26); 5131 operands[2] = GEN_INT (alpha_next_sequence_number++); 5132} 5133 [(set_attr "length" "8") 5134 (set_attr "type" "multi")]) 5135 5136(define_expand "nonlocal_goto_receiver" 5137 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5138 (set (reg:DI 27) (mem:DI (reg:DI 29))) 5139 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5140 (use (reg:DI 27))] 5141 "TARGET_ABI_OPEN_VMS") 5142 5143(define_insn "arg_home" 5144 [(unspec [(const_int 0)] UNSPEC_ARG_HOME) 5145 (use (reg:DI 1)) 5146 (use (reg:DI 25)) 5147 (use (reg:DI 16)) 5148 (use (reg:DI 17)) 5149 (use (reg:DI 18)) 5150 (use (reg:DI 19)) 5151 (use (reg:DI 20)) 5152 (use (reg:DI 21)) 5153 (use (reg:DI 48)) 5154 (use (reg:DI 49)) 5155 (use (reg:DI 50)) 5156 (use (reg:DI 51)) 5157 (use (reg:DI 52)) 5158 (use (reg:DI 53)) 5159 (clobber (mem:BLK (const_int 0))) 5160 (clobber (reg:DI 24)) 5161 (clobber (reg:DI 25)) 5162 (clobber (reg:DI 0))] 5163 "TARGET_ABI_OPEN_VMS" 5164 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS" 5165 [(set_attr "length" "16") 5166 (set_attr "type" "multi")]) 5167 5168;; Prefetch data. 5169;; 5170;; On EV4, these instructions are nops -- no load occurs. 5171;; 5172;; On EV5, these instructions act as a normal load, and thus can trap 5173;; if the address is invalid. The OS may (or may not) handle this in 5174;; the entMM fault handler and suppress the fault. If so, then this 5175;; has the effect of a read prefetch instruction. 5176;; 5177;; On EV6, these become official prefetch instructions. 5178 5179(define_insn "prefetch" 5180 [(prefetch (match_operand:DI 0 "address_operand" "p") 5181 (match_operand:DI 1 "const_int_operand" "n") 5182 (match_operand:DI 2 "const_int_operand" "n"))] 5183 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6" 5184{ 5185 /* Interpret "no temporal locality" as this data should be evicted once 5186 it is used. The "evict next" alternatives load the data into the cache 5187 and leave the LRU eviction counter pointing to that block. */ 5188 static const char * const alt[2][2] = { 5189 { 5190 "ldq $31,%a0", /* read, evict next */ 5191 "ldl $31,%a0", /* read, evict last */ 5192 }, 5193 { 5194 "ldt $f31,%a0", /* write, evict next */ 5195 "lds $f31,%a0", /* write, evict last */ 5196 } 5197 }; 5198 5199 bool write = INTVAL (operands[1]) != 0; 5200 bool lru = INTVAL (operands[2]) != 0; 5201 5202 return alt[write][lru]; 5203} 5204 [(set_attr "type" "ild")]) 5205 5206;; Close the trap shadow of preceding instructions. This is generated 5207;; by alpha_reorg. 5208 5209(define_insn "trapb" 5210 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)] 5211 "" 5212 "trapb" 5213 [(set_attr "type" "misc")]) 5214 5215;; No-op instructions used by machine-dependent reorg to preserve 5216;; alignment for instruction issue. 5217;; The Unicos/Mk assembler does not support these opcodes. 5218 5219(define_insn "nop" 5220 [(const_int 0)] 5221 "" 5222 "bis $31,$31,$31" 5223 [(set_attr "type" "ilog")]) 5224 5225(define_insn "fnop" 5226 [(const_int 1)] 5227 "TARGET_FP" 5228 "cpys $f31,$f31,$f31" 5229 [(set_attr "type" "fcpys")]) 5230 5231(define_insn "unop" 5232 [(const_int 2)] 5233 "" 5234 "ldq_u $31,0($30)") 5235 5236(define_insn "realign" 5237 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 5238 UNSPECV_REALIGN)] 5239 "" 5240 ".align %0 #realign") 5241 5242;; Instructions to be emitted from __builtins. 5243 5244(define_insn "builtin_cmpbge" 5245 [(set (match_operand:DI 0 "register_operand" "=r") 5246 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ") 5247 (match_operand:DI 2 "reg_or_8bit_operand" "rI")] 5248 UNSPEC_CMPBGE))] 5249 "" 5250 "cmpbge %r1,%2,%0" 5251 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't 5252 ;; actually differentiate between ILOG and ICMP in the schedule. 5253 [(set_attr "type" "icmp")]) 5254 5255(define_expand "extbl" 5256 [(match_operand:DI 0 "register_operand") 5257 (match_operand:DI 1 "reg_or_0_operand") 5258 (match_operand:DI 2 "reg_or_8bit_operand")] 5259 "" 5260{ 5261 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2])); 5262 DONE; 5263}) 5264 5265(define_expand "extwl" 5266 [(match_operand:DI 0 "register_operand") 5267 (match_operand:DI 1 "reg_or_0_operand") 5268 (match_operand:DI 2 "reg_or_8bit_operand")] 5269 "" 5270{ 5271 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2])); 5272 DONE; 5273}) 5274 5275(define_expand "extll" 5276 [(match_operand:DI 0 "register_operand") 5277 (match_operand:DI 1 "reg_or_0_operand") 5278 (match_operand:DI 2 "reg_or_8bit_operand")] 5279 "" 5280{ 5281 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2])); 5282 DONE; 5283}) 5284 5285(define_expand "extql" 5286 [(match_operand:DI 0 "register_operand") 5287 (match_operand:DI 1 "reg_or_0_operand") 5288 (match_operand:DI 2 "reg_or_8bit_operand")] 5289 "" 5290{ 5291 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2])); 5292 DONE; 5293}) 5294 5295(define_expand "builtin_insbl" 5296 [(match_operand:DI 0 "register_operand") 5297 (match_operand:DI 1 "register_operand") 5298 (match_operand:DI 2 "reg_or_8bit_operand")] 5299 "" 5300{ 5301 operands[1] = gen_lowpart (QImode, operands[1]); 5302 emit_insn (gen_insbl (operands[0], operands[1], operands[2])); 5303 DONE; 5304}) 5305 5306(define_expand "builtin_inswl" 5307 [(match_operand:DI 0 "register_operand") 5308 (match_operand:DI 1 "register_operand") 5309 (match_operand:DI 2 "reg_or_8bit_operand")] 5310 "" 5311{ 5312 operands[1] = gen_lowpart (HImode, operands[1]); 5313 emit_insn (gen_inswl (operands[0], operands[1], operands[2])); 5314 DONE; 5315}) 5316 5317(define_expand "builtin_insll" 5318 [(match_operand:DI 0 "register_operand") 5319 (match_operand:DI 1 "register_operand") 5320 (match_operand:DI 2 "reg_or_8bit_operand")] 5321 "" 5322{ 5323 operands[1] = gen_lowpart (SImode, operands[1]); 5324 emit_insn (gen_insll (operands[0], operands[1], operands[2])); 5325 DONE; 5326}) 5327 5328(define_expand "inswh" 5329 [(match_operand:DI 0 "register_operand") 5330 (match_operand:DI 1 "register_operand") 5331 (match_operand:DI 2 "reg_or_8bit_operand")] 5332 "" 5333{ 5334 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5335 DONE; 5336}) 5337 5338(define_expand "inslh" 5339 [(match_operand:DI 0 "register_operand") 5340 (match_operand:DI 1 "register_operand") 5341 (match_operand:DI 2 "reg_or_8bit_operand")] 5342 "" 5343{ 5344 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5345 DONE; 5346}) 5347 5348(define_expand "insqh" 5349 [(match_operand:DI 0 "register_operand") 5350 (match_operand:DI 1 "register_operand") 5351 (match_operand:DI 2 "reg_or_8bit_operand")] 5352 "" 5353{ 5354 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5355 DONE; 5356}) 5357 5358(define_expand "mskbl" 5359 [(match_operand:DI 0 "register_operand") 5360 (match_operand:DI 1 "reg_or_0_operand") 5361 (match_operand:DI 2 "reg_or_8bit_operand")] 5362 "" 5363{ 5364 rtx mask = GEN_INT (0xff); 5365 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5366 DONE; 5367}) 5368 5369(define_expand "mskwl" 5370 [(match_operand:DI 0 "register_operand") 5371 (match_operand:DI 1 "reg_or_0_operand") 5372 (match_operand:DI 2 "reg_or_8bit_operand")] 5373 "" 5374{ 5375 rtx mask = GEN_INT (0xffff); 5376 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5377 DONE; 5378}) 5379 5380(define_expand "mskll" 5381 [(match_operand:DI 0 "register_operand") 5382 (match_operand:DI 1 "reg_or_0_operand") 5383 (match_operand:DI 2 "reg_or_8bit_operand")] 5384 "" 5385{ 5386 rtx mask = gen_int_mode (0xffffffff, DImode); 5387 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5388 DONE; 5389}) 5390 5391(define_expand "mskql" 5392 [(match_operand:DI 0 "register_operand") 5393 (match_operand:DI 1 "reg_or_0_operand") 5394 (match_operand:DI 2 "reg_or_8bit_operand")] 5395 "" 5396{ 5397 rtx mask = constm1_rtx; 5398 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5399 DONE; 5400}) 5401 5402(define_expand "mskwh" 5403 [(match_operand:DI 0 "register_operand") 5404 (match_operand:DI 1 "register_operand") 5405 (match_operand:DI 2 "reg_or_8bit_operand")] 5406 "" 5407{ 5408 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5409 DONE; 5410}) 5411 5412(define_expand "msklh" 5413 [(match_operand:DI 0 "register_operand") 5414 (match_operand:DI 1 "register_operand") 5415 (match_operand:DI 2 "reg_or_8bit_operand")] 5416 "" 5417{ 5418 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5419 DONE; 5420}) 5421 5422(define_expand "mskqh" 5423 [(match_operand:DI 0 "register_operand") 5424 (match_operand:DI 1 "register_operand") 5425 (match_operand:DI 2 "reg_or_8bit_operand")] 5426 "" 5427{ 5428 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5429 DONE; 5430}) 5431 5432(define_expand "builtin_zap" 5433 [(set (match_operand:DI 0 "register_operand") 5434 (and:DI (unspec:DI 5435 [(match_operand:DI 2 "reg_or_cint_operand")] 5436 UNSPEC_ZAP) 5437 (match_operand:DI 1 "reg_or_cint_operand")))] 5438 "" 5439{ 5440 if (CONST_INT_P (operands[2])) 5441 { 5442 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5443 5444 if (mask == const0_rtx) 5445 { 5446 emit_move_insn (operands[0], const0_rtx); 5447 DONE; 5448 } 5449 if (mask == constm1_rtx) 5450 { 5451 emit_move_insn (operands[0], operands[1]); 5452 DONE; 5453 } 5454 5455 operands[1] = force_reg (DImode, operands[1]); 5456 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5457 DONE; 5458 } 5459 5460 operands[1] = force_reg (DImode, operands[1]); 5461 operands[2] = gen_lowpart (QImode, operands[2]); 5462}) 5463 5464(define_insn "*builtin_zap_1" 5465 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 5466 (and:DI (unspec:DI 5467 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")] 5468 UNSPEC_ZAP) 5469 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))] 5470 "" 5471 "@ 5472 # 5473 # 5474 bis $31,$31,%0 5475 zap %r1,%2,%0" 5476 [(set_attr "type" "shift,shift,ilog,shift")]) 5477 5478(define_split 5479 [(set (match_operand:DI 0 "register_operand") 5480 (and:DI (unspec:DI 5481 [(match_operand:QI 2 "const_int_operand")] 5482 UNSPEC_ZAP) 5483 (match_operand:DI 1 "const_int_operand")))] 5484 "" 5485 [(const_int 0)] 5486{ 5487 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5488 5489 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode); 5490 emit_move_insn (operands[0], operands[1]); 5491 DONE; 5492}) 5493 5494(define_split 5495 [(set (match_operand:DI 0 "register_operand") 5496 (and:DI (unspec:DI 5497 [(match_operand:QI 2 "const_int_operand")] 5498 UNSPEC_ZAP) 5499 (match_operand:DI 1 "register_operand")))] 5500 "" 5501 [(set (match_dup 0) 5502 (and:DI (match_dup 1) (match_dup 2)))] 5503{ 5504 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2])); 5505 if (operands[2] == const0_rtx) 5506 { 5507 emit_move_insn (operands[0], const0_rtx); 5508 DONE; 5509 } 5510 if (operands[2] == constm1_rtx) 5511 { 5512 emit_move_insn (operands[0], operands[1]); 5513 DONE; 5514 } 5515}) 5516 5517(define_expand "builtin_zapnot" 5518 [(set (match_operand:DI 0 "register_operand") 5519 (and:DI (unspec:DI 5520 [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))] 5521 UNSPEC_ZAP) 5522 (match_operand:DI 1 "reg_or_cint_operand")))] 5523 "" 5524{ 5525 if (CONST_INT_P (operands[2])) 5526 { 5527 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2])); 5528 5529 if (mask == const0_rtx) 5530 { 5531 emit_move_insn (operands[0], const0_rtx); 5532 DONE; 5533 } 5534 if (mask == constm1_rtx) 5535 { 5536 emit_move_insn (operands[0], operands[1]); 5537 DONE; 5538 } 5539 5540 operands[1] = force_reg (DImode, operands[1]); 5541 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5542 DONE; 5543 } 5544 5545 operands[1] = force_reg (DImode, operands[1]); 5546 operands[2] = gen_lowpart (QImode, operands[2]); 5547}) 5548 5549(define_insn "*builtin_zapnot_1" 5550 [(set (match_operand:DI 0 "register_operand" "=r") 5551 (and:DI (unspec:DI 5552 [(not:QI (match_operand:QI 2 "register_operand" "r"))] 5553 UNSPEC_ZAP) 5554 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 5555 "" 5556 "zapnot %r1,%2,%0" 5557 [(set_attr "type" "shift")]) 5558 5559(define_insn "builtin_amask" 5560 [(set (match_operand:DI 0 "register_operand" "=r") 5561 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")] 5562 UNSPEC_AMASK))] 5563 "" 5564 "amask %1,%0" 5565 [(set_attr "type" "ilog")]) 5566 5567(define_insn "builtin_implver" 5568 [(set (match_operand:DI 0 "register_operand" "=r") 5569 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))] 5570 "" 5571 "implver %0" 5572 [(set_attr "type" "ilog")]) 5573 5574(define_insn "builtin_rpcc" 5575 [(set (match_operand:DI 0 "register_operand" "=r") 5576 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))] 5577 "" 5578 "rpcc %0" 5579 [(set_attr "type" "ilog")]) 5580 5581(define_expand "builtin_minub8" 5582 [(match_operand:DI 0 "register_operand") 5583 (match_operand:DI 1 "reg_or_0_operand") 5584 (match_operand:DI 2 "reg_or_0_operand")] 5585 "TARGET_MAX" 5586{ 5587 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], 5588 operands[1], operands[2]); 5589 DONE; 5590}) 5591 5592(define_expand "builtin_minsb8" 5593 [(match_operand:DI 0 "register_operand") 5594 (match_operand:DI 1 "reg_or_0_operand") 5595 (match_operand:DI 2 "reg_or_0_operand")] 5596 "TARGET_MAX" 5597{ 5598 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], 5599 operands[1], operands[2]); 5600 DONE; 5601}) 5602 5603(define_expand "builtin_minuw4" 5604 [(match_operand:DI 0 "register_operand") 5605 (match_operand:DI 1 "reg_or_0_operand") 5606 (match_operand:DI 2 "reg_or_0_operand")] 5607 "TARGET_MAX" 5608{ 5609 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], 5610 operands[1], operands[2]); 5611 DONE; 5612}) 5613 5614(define_expand "builtin_minsw4" 5615 [(match_operand:DI 0 "register_operand") 5616 (match_operand:DI 1 "reg_or_0_operand") 5617 (match_operand:DI 2 "reg_or_0_operand")] 5618 "TARGET_MAX" 5619{ 5620 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], 5621 operands[1], operands[2]); 5622 DONE; 5623}) 5624 5625(define_expand "builtin_maxub8" 5626 [(match_operand:DI 0 "register_operand") 5627 (match_operand:DI 1 "reg_or_0_operand") 5628 (match_operand:DI 2 "reg_or_0_operand")] 5629 "TARGET_MAX" 5630{ 5631 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], 5632 operands[1], operands[2]); 5633 DONE; 5634}) 5635 5636(define_expand "builtin_maxsb8" 5637 [(match_operand:DI 0 "register_operand") 5638 (match_operand:DI 1 "reg_or_0_operand") 5639 (match_operand:DI 2 "reg_or_0_operand")] 5640 "TARGET_MAX" 5641{ 5642 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], 5643 operands[1], operands[2]); 5644 DONE; 5645}) 5646 5647(define_expand "builtin_maxuw4" 5648 [(match_operand:DI 0 "register_operand") 5649 (match_operand:DI 1 "reg_or_0_operand") 5650 (match_operand:DI 2 "reg_or_0_operand")] 5651 "TARGET_MAX" 5652{ 5653 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], 5654 operands[1], operands[2]); 5655 DONE; 5656}) 5657 5658(define_expand "builtin_maxsw4" 5659 [(match_operand:DI 0 "register_operand") 5660 (match_operand:DI 1 "reg_or_0_operand") 5661 (match_operand:DI 2 "reg_or_0_operand")] 5662 "TARGET_MAX" 5663{ 5664 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], 5665 operands[1], operands[2]); 5666 DONE; 5667}) 5668 5669(define_insn "builtin_perr" 5670 [(set (match_operand:DI 0 "register_operand" "=r") 5671 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ") 5672 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")] 5673 UNSPEC_PERR))] 5674 "TARGET_MAX" 5675 "perr %r1,%r2,%0" 5676 [(set_attr "type" "mvi")]) 5677 5678(define_expand "builtin_pklb" 5679 [(set (match_operand:DI 0 "register_operand") 5680 (vec_concat:V8QI 5681 (vec_concat:V4QI 5682 (truncate:V2QI (match_operand:DI 1 "register_operand")) 5683 (match_dup 2)) 5684 (match_dup 3)))] 5685 "TARGET_MAX" 5686{ 5687 operands[0] = gen_lowpart (V8QImode, operands[0]); 5688 operands[1] = gen_lowpart (V2SImode, operands[1]); 5689 operands[2] = CONST0_RTX (V2QImode); 5690 operands[3] = CONST0_RTX (V4QImode); 5691}) 5692 5693(define_insn "*pklb" 5694 [(set (match_operand:V8QI 0 "register_operand" "=r") 5695 (vec_concat:V8QI 5696 (vec_concat:V4QI 5697 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) 5698 (match_operand:V2QI 2 "const0_operand")) 5699 (match_operand:V4QI 3 "const0_operand")))] 5700 "TARGET_MAX" 5701 "pklb %r1,%0" 5702 [(set_attr "type" "mvi")]) 5703 5704(define_expand "builtin_pkwb" 5705 [(set (match_operand:DI 0 "register_operand") 5706 (vec_concat:V8QI 5707 (truncate:V4QI (match_operand:DI 1 "register_operand")) 5708 (match_dup 2)))] 5709 "TARGET_MAX" 5710{ 5711 operands[0] = gen_lowpart (V8QImode, operands[0]); 5712 operands[1] = gen_lowpart (V4HImode, operands[1]); 5713 operands[2] = CONST0_RTX (V4QImode); 5714}) 5715 5716(define_insn "*pkwb" 5717 [(set (match_operand:V8QI 0 "register_operand" "=r") 5718 (vec_concat:V8QI 5719 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) 5720 (match_operand:V4QI 2 "const0_operand")))] 5721 "TARGET_MAX" 5722 "pkwb %r1,%0" 5723 [(set_attr "type" "mvi")]) 5724 5725(define_expand "builtin_unpkbl" 5726 [(set (match_operand:DI 0 "register_operand") 5727 (zero_extend:V2SI 5728 (vec_select:V2QI (match_operand:DI 1 "register_operand") 5729 (parallel [(const_int 0) (const_int 1)]))))] 5730 "TARGET_MAX" 5731{ 5732 operands[0] = gen_lowpart (V2SImode, operands[0]); 5733 operands[1] = gen_lowpart (V8QImode, operands[1]); 5734}) 5735 5736(define_insn "*unpkbl" 5737 [(set (match_operand:V2SI 0 "register_operand" "=r") 5738 (zero_extend:V2SI 5739 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5740 (parallel [(const_int 0) (const_int 1)]))))] 5741 "TARGET_MAX" 5742 "unpkbl %r1,%0" 5743 [(set_attr "type" "mvi")]) 5744 5745(define_expand "builtin_unpkbw" 5746 [(set (match_operand:DI 0 "register_operand") 5747 (zero_extend:V4HI 5748 (vec_select:V4QI (match_operand:DI 1 "register_operand") 5749 (parallel [(const_int 0) 5750 (const_int 1) 5751 (const_int 2) 5752 (const_int 3)]))))] 5753 "TARGET_MAX" 5754{ 5755 operands[0] = gen_lowpart (V4HImode, operands[0]); 5756 operands[1] = gen_lowpart (V8QImode, operands[1]); 5757}) 5758 5759(define_insn "*unpkbw" 5760 [(set (match_operand:V4HI 0 "register_operand" "=r") 5761 (zero_extend:V4HI 5762 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5763 (parallel [(const_int 0) 5764 (const_int 1) 5765 (const_int 2) 5766 (const_int 3)]))))] 5767 "TARGET_MAX" 5768 "unpkbw %r1,%0" 5769 [(set_attr "type" "mvi")]) 5770 5771(include "sync.md") 5772 5773;; The call patterns are at the end of the file because their 5774;; wildcard operand0 interferes with nice recognition. 5775 5776(define_insn "*call_value_osf_1_er_noreturn" 5777 [(set (match_operand 0) 5778 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5779 (match_operand 2))) 5780 (use (reg:DI 29)) 5781 (clobber (reg:DI 26))] 5782 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5783 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5784 "@ 5785 jsr $26,($27),0 5786 bsr $26,%1\t\t!samegp 5787 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#" 5788 [(set_attr "type" "jsr") 5789 (set_attr "length" "*,*,8")]) 5790 5791(define_insn "*call_value_osf_1_er" 5792 [(set (match_operand 0) 5793 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5794 (match_operand 2))) 5795 (use (reg:DI 29)) 5796 (clobber (reg:DI 26))] 5797 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5798 "@ 5799 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 5800 bsr $26,%1\t\t!samegp 5801 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5802 [(set_attr "type" "jsr") 5803 (set_attr "length" "12,*,16")]) 5804 5805;; We must use peep2 instead of a split because we need accurate life 5806;; information for $gp. Consider the case of { bar(); while (1); }. 5807(define_peephole2 5808 [(parallel [(set (match_operand 0) 5809 (call (mem:DI (match_operand:DI 1 "call_operand")) 5810 (match_operand 2))) 5811 (use (reg:DI 29)) 5812 (clobber (reg:DI 26))])] 5813 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5814 && ! samegp_function_operand (operands[1], Pmode) 5815 && (peep2_regno_dead_p (1, 29) 5816 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5817 [(parallel [(set (match_dup 0) 5818 (call (mem:DI (match_dup 3)) 5819 (match_dup 2))) 5820 (use (reg:DI 29)) 5821 (use (match_dup 1)) 5822 (use (match_dup 4)) 5823 (clobber (reg:DI 26))])] 5824{ 5825 if (CONSTANT_P (operands[1])) 5826 { 5827 operands[3] = gen_rtx_REG (Pmode, 27); 5828 operands[4] = GEN_INT (alpha_next_sequence_number++); 5829 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5830 operands[1], operands[4])); 5831 } 5832 else 5833 { 5834 operands[3] = operands[1]; 5835 operands[1] = const0_rtx; 5836 operands[4] = const0_rtx; 5837 } 5838}) 5839 5840(define_peephole2 5841 [(parallel [(set (match_operand 0) 5842 (call (mem:DI (match_operand:DI 1 "call_operand")) 5843 (match_operand 2))) 5844 (use (reg:DI 29)) 5845 (clobber (reg:DI 26))])] 5846 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5847 && ! samegp_function_operand (operands[1], Pmode) 5848 && ! (peep2_regno_dead_p (1, 29) 5849 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5850 [(parallel [(set (match_dup 0) 5851 (call (mem:DI (match_dup 3)) 5852 (match_dup 2))) 5853 (set (match_dup 6) 5854 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1)) 5855 (use (match_dup 1)) 5856 (use (match_dup 5)) 5857 (clobber (reg:DI 26))]) 5858 (set (match_dup 6) 5859 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))] 5860{ 5861 if (CONSTANT_P (operands[1])) 5862 { 5863 operands[3] = gen_rtx_REG (Pmode, 27); 5864 operands[5] = GEN_INT (alpha_next_sequence_number++); 5865 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5866 operands[1], operands[5])); 5867 } 5868 else 5869 { 5870 operands[3] = operands[1]; 5871 operands[1] = const0_rtx; 5872 operands[5] = const0_rtx; 5873 } 5874 operands[4] = GEN_INT (alpha_next_sequence_number++); 5875 operands[6] = pic_offset_table_rtx; 5876}) 5877 5878(define_insn "*call_value_osf_2_er_nogp" 5879 [(set (match_operand 0) 5880 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5881 (match_operand 2))) 5882 (use (reg:DI 29)) 5883 (use (match_operand 3)) 5884 (use (match_operand 4)) 5885 (clobber (reg:DI 26))] 5886 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5887 "jsr $26,(%1),%3%J4" 5888 [(set_attr "type" "jsr")]) 5889 5890(define_insn "*call_value_osf_2_er" 5891 [(set (match_operand 0) 5892 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5893 (match_operand 2))) 5894 (set (reg:DI 29) 5895 (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")] 5896 UNSPEC_LDGP1)) 5897 (use (match_operand 3)) 5898 (use (match_operand 4)) 5899 (clobber (reg:DI 26))] 5900 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5901 "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5" 5902 [(set_attr "type" "jsr") 5903 (set_attr "cannot_copy" "true") 5904 (set_attr "length" "8")]) 5905 5906(define_insn "*call_value_osf_1_noreturn" 5907 [(set (match_operand 0) 5908 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5909 (match_operand 2))) 5910 (use (reg:DI 29)) 5911 (clobber (reg:DI 26))] 5912 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5913 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5914 "@ 5915 jsr $26,($27),0 5916 bsr $26,$%1..ng 5917 jsr $26,%1" 5918 [(set_attr "type" "jsr") 5919 (set_attr "length" "*,*,8")]) 5920 5921(define_int_iterator TLS_CALL 5922 [UNSPEC_TLSGD_CALL 5923 UNSPEC_TLSLDM_CALL]) 5924 5925(define_int_attr tls 5926 [(UNSPEC_TLSGD_CALL "tlsgd") 5927 (UNSPEC_TLSLDM_CALL "tlsldm")]) 5928 5929(define_insn "call_value_osf_<tls>" 5930 [(set (match_operand 0) 5931 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5932 (const_int 0))) 5933 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5934 (use (reg:DI 29)) 5935 (clobber (reg:DI 26))] 5936 "HAVE_AS_TLS" 5937 "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5938 [(set_attr "type" "jsr") 5939 (set_attr "length" "16")]) 5940 5941;; We must use peep2 instead of a split because we need accurate life 5942;; information for $gp. 5943(define_peephole2 5944 [(parallel 5945 [(set (match_operand 0) 5946 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5947 (const_int 0))) 5948 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5949 (use (reg:DI 29)) 5950 (clobber (reg:DI 26))])] 5951 "HAVE_AS_TLS && reload_completed 5952 && peep2_regno_dead_p (1, 29)" 5953 [(set (match_dup 3) 5954 (unspec:DI [(match_dup 5) 5955 (match_dup 1) 5956 (match_dup 2)] UNSPEC_LITERAL)) 5957 (parallel [(set (match_dup 0) 5958 (call (mem:DI (match_dup 3)) 5959 (const_int 0))) 5960 (use (match_dup 5)) 5961 (use (match_dup 1)) 5962 (use (unspec [(match_dup 2)] TLS_CALL)) 5963 (clobber (reg:DI 26))]) 5964 (set (match_dup 5) 5965 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 5966{ 5967 operands[3] = gen_rtx_REG (Pmode, 27); 5968 operands[4] = GEN_INT (alpha_next_sequence_number++); 5969 operands[5] = pic_offset_table_rtx; 5970}) 5971 5972(define_peephole2 5973 [(parallel 5974 [(set (match_operand 0) 5975 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5976 (const_int 0))) 5977 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5978 (use (reg:DI 29)) 5979 (clobber (reg:DI 26))])] 5980 "HAVE_AS_TLS && reload_completed 5981 && !peep2_regno_dead_p (1, 29)" 5982 [(set (match_dup 3) 5983 (unspec:DI [(match_dup 5) 5984 (match_dup 1) 5985 (match_dup 2)] UNSPEC_LITERAL)) 5986 (parallel [(set (match_dup 0) 5987 (call (mem:DI (match_dup 3)) 5988 (const_int 0))) 5989 (set (match_dup 5) 5990 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) 5991 (use (match_dup 1)) 5992 (use (unspec [(match_dup 2)] TLS_CALL)) 5993 (clobber (reg:DI 26))]) 5994 (set (match_dup 5) 5995 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 5996{ 5997 operands[3] = gen_rtx_REG (Pmode, 27); 5998 operands[4] = GEN_INT (alpha_next_sequence_number++); 5999 operands[5] = pic_offset_table_rtx; 6000}) 6001 6002(define_insn "*call_value_osf_1" 6003 [(set (match_operand 0) 6004 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 6005 (match_operand 2))) 6006 (use (reg:DI 29)) 6007 (clobber (reg:DI 26))] 6008 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6009 "@ 6010 jsr $26,($27),0\;ldgp $29,0($26) 6011 bsr $26,$%1..ng 6012 jsr $26,%1\;ldgp $29,0($26)" 6013 [(set_attr "type" "jsr") 6014 (set_attr "length" "12,*,16")]) 6015 6016(define_insn "*sibcall_value_osf_1_er" 6017 [(set (match_operand 0) 6018 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6019 (match_operand 2))) 6020 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6021 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6022 "@ 6023 br $31,%1\t\t!samegp 6024 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#" 6025 [(set_attr "type" "jsr") 6026 (set_attr "length" "*,8")]) 6027 6028(define_insn "*sibcall_value_osf_1" 6029 [(set (match_operand 0) 6030 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6031 (match_operand 2))) 6032 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6033 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6034 "@ 6035 br $31,$%1..ng 6036 lda $27,%1\;jmp $31,($27),%1" 6037 [(set_attr "type" "jsr") 6038 (set_attr "length" "*,8")]) 6039 6040; GAS relies on the order and position of instructions output below in order 6041; to generate relocs for VMS link to potentially optimize the call. 6042; Please do not molest. 6043(define_insn "*call_value_vms_1" 6044 [(set (match_operand 0) 6045 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) 6046 (match_operand 2))) 6047 (use (match_operand:DI 3 "nonmemory_operand" "r,n")) 6048 (use (reg:DI 25)) 6049 (use (reg:DI 26)) 6050 (clobber (reg:DI 27))] 6051 "TARGET_ABI_OPEN_VMS" 6052{ 6053 switch (which_alternative) 6054 { 6055 case 0: 6056 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)"; 6057 case 1: 6058 operands [3] = alpha_use_linkage (operands [1], true, false); 6059 operands [4] = alpha_use_linkage (operands [1], false, false); 6060 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"; 6061 default: 6062 gcc_unreachable (); 6063 } 6064} 6065 [(set_attr "type" "jsr") 6066 (set_attr "length" "12,16")]) 6067