1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */ 2 /* { dg-options "-O -msve-vector-bits=256 -mlittle-endian --save-temps" } */ 3 4 typedef char vnx16qi __attribute__((vector_size(32))); 5 typedef struct { vnx16qi a[3]; } vnx48qi; 6 7 typedef short vnx8hi __attribute__((vector_size(32))); 8 typedef struct { vnx8hi a[3]; } vnx24hi; 9 10 typedef int vnx4si __attribute__((vector_size(32))); 11 typedef struct { vnx4si a[3]; } vnx12si; 12 13 typedef long vnx2di __attribute__((vector_size(32))); 14 typedef struct { vnx2di a[3]; } vnx6di; 15 16 typedef float vnx4sf __attribute__((vector_size(32))); 17 typedef struct { vnx4sf a[3]; } vnx12sf; 18 19 typedef double vnx2df __attribute__((vector_size(32))); 20 typedef struct { vnx2df a[3]; } vnx6df; 21 22 #define TEST_TYPE(TYPE, REG1, REG2) \ 23 void \ 24 f_##TYPE (TYPE *a) \ 25 { \ 26 register TYPE x asm (#REG1) = a[0]; \ 27 asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ 28 register TYPE y asm (#REG2) = x; \ 29 asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ 30 : "=&w" (x) : "0" (x), "w" (y)); \ 31 a[1] = x; \ 32 } 33 34 TEST_TYPE (vnx48qi, z0, z3) 35 TEST_TYPE (vnx24hi, z6, z2) 36 TEST_TYPE (vnx12si, z12, z15) 37 TEST_TYPE (vnx6di, z16, z13) 38 TEST_TYPE (vnx12sf, z20, z23) 39 TEST_TYPE (vnx6df, z26, z29) 40 41 /* { dg-final { scan-assembler {\tldr\tz0, \[x0\]\n} } } */ 42 /* { dg-final { scan-assembler {\tldr\tz1, \[x0, #1, mul vl\]\n} } } */ 43 /* { dg-final { scan-assembler {\tldr\tz2, \[x0, #2, mul vl\]\n} } } */ 44 /* { dg-final { scan-assembler { test vnx48qi 1 z0\n} } } */ 45 /* { dg-final { scan-assembler {\tmov\tz3.d, z0.d\n} } } */ 46 /* { dg-final { scan-assembler {\tmov\tz4.d, z1.d\n} } } */ 47 /* { dg-final { scan-assembler {\tmov\tz5.d, z2.d\n} } } */ 48 /* { dg-final { scan-assembler { test vnx48qi 2 z0, z0, z3\n} } } */ 49 /* { dg-final { scan-assembler {\tstr\tz0, \[x0, #3, mul vl\]\n} } } */ 50 /* { dg-final { scan-assembler {\tstr\tz1, \[x0, #4, mul vl\]\n} } } */ 51 /* { dg-final { scan-assembler {\tstr\tz2, \[x0, #5, mul vl\]\n} } } */ 52 53 /* { dg-final { scan-assembler {\tldr\tz6, \[x0\]\n} } } */ 54 /* { dg-final { scan-assembler {\tldr\tz7, \[x0, #1, mul vl\]\n} } } */ 55 /* { dg-final { scan-assembler {\tldr\tz8, \[x0, #2, mul vl\]\n} } } */ 56 /* { dg-final { scan-assembler { test vnx24hi 1 z6\n} } } */ 57 /* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ 58 /* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ 59 /* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ 60 /* { dg-final { scan-assembler { test vnx24hi 2 z6, z6, z2\n} } } */ 61 /* { dg-final { scan-assembler {\tstr\tz6, \[x0, #3, mul vl\]\n} } } */ 62 /* { dg-final { scan-assembler {\tstr\tz7, \[x0, #4, mul vl\]\n} } } */ 63 /* { dg-final { scan-assembler {\tstr\tz8, \[x0, #5, mul vl\]\n} } } */ 64 65 /* { dg-final { scan-assembler {\tldr\tz12, \[x0\]\n} } } */ 66 /* { dg-final { scan-assembler {\tldr\tz13, \[x0, #1, mul vl\]\n} } } */ 67 /* { dg-final { scan-assembler {\tldr\tz14, \[x0, #2, mul vl\]\n} } } */ 68 /* { dg-final { scan-assembler { test vnx12si 1 z12\n} } } */ 69 /* { dg-final { scan-assembler {\tmov\tz15.d, z12.d\n} } } */ 70 /* { dg-final { scan-assembler {\tmov\tz16.d, z13.d\n} } } */ 71 /* { dg-final { scan-assembler {\tmov\tz17.d, z14.d\n} } } */ 72 /* { dg-final { scan-assembler { test vnx12si 2 z12, z12, z15\n} } } */ 73 /* { dg-final { scan-assembler {\tstr\tz12, \[x0, #3, mul vl\]\n} } } */ 74 /* { dg-final { scan-assembler {\tstr\tz13, \[x0, #4, mul vl\]\n} } } */ 75 /* { dg-final { scan-assembler {\tstr\tz14, \[x0, #5, mul vl\]\n} } } */ 76 77 /* { dg-final { scan-assembler {\tldr\tz16, \[x0\]\n} } } */ 78 /* { dg-final { scan-assembler {\tldr\tz17, \[x0, #1, mul vl\]\n} } } */ 79 /* { dg-final { scan-assembler {\tldr\tz18, \[x0, #2, mul vl\]\n} } } */ 80 /* { dg-final { scan-assembler { test vnx6di 1 z16\n} } } */ 81 /* { dg-final { scan-assembler {\tmov\tz13.d, z16.d\n} } } */ 82 /* { dg-final { scan-assembler {\tmov\tz14.d, z17.d\n} } } */ 83 /* { dg-final { scan-assembler {\tmov\tz15.d, z18.d\n} } } */ 84 /* { dg-final { scan-assembler { test vnx6di 2 z16, z16, z13\n} } } */ 85 /* { dg-final { scan-assembler {\tstr\tz16, \[x0, #3, mul vl\]\n} } } */ 86 /* { dg-final { scan-assembler {\tstr\tz17, \[x0, #4, mul vl\]\n} } } */ 87 /* { dg-final { scan-assembler {\tstr\tz18, \[x0, #5, mul vl\]\n} } } */ 88 89 /* { dg-final { scan-assembler {\tldr\tz20, \[x0\]\n} } } */ 90 /* { dg-final { scan-assembler {\tldr\tz21, \[x0, #1, mul vl\]\n} } } */ 91 /* { dg-final { scan-assembler {\tldr\tz22, \[x0, #2, mul vl\]\n} } } */ 92 /* { dg-final { scan-assembler { test vnx12sf 1 z20\n} } } */ 93 /* { dg-final { scan-assembler {\tmov\tz23.d, z20.d\n} } } */ 94 /* { dg-final { scan-assembler {\tmov\tz24.d, z21.d\n} } } */ 95 /* { dg-final { scan-assembler {\tmov\tz25.d, z22.d\n} } } */ 96 /* { dg-final { scan-assembler { test vnx12sf 2 z20, z20, z23\n} } } */ 97 /* { dg-final { scan-assembler {\tstr\tz20, \[x0, #3, mul vl\]\n} } } */ 98 /* { dg-final { scan-assembler {\tstr\tz21, \[x0, #4, mul vl\]\n} } } */ 99 /* { dg-final { scan-assembler {\tstr\tz22, \[x0, #5, mul vl\]\n} } } */ 100 101 /* { dg-final { scan-assembler {\tldr\tz26, \[x0\]\n} } } */ 102 /* { dg-final { scan-assembler {\tldr\tz27, \[x0, #1, mul vl\]\n} } } */ 103 /* { dg-final { scan-assembler {\tldr\tz28, \[x0, #2, mul vl\]\n} } } */ 104 /* { dg-final { scan-assembler { test vnx6df 1 z26\n} } } */ 105 /* { dg-final { scan-assembler {\tmov\tz29.d, z26.d\n} } } */ 106 /* { dg-final { scan-assembler {\tmov\tz30.d, z27.d\n} } } */ 107 /* { dg-final { scan-assembler {\tmov\tz31.d, z28.d\n} } } */ 108 /* { dg-final { scan-assembler { test vnx6df 2 z26, z26, z29\n} } } */ 109 /* { dg-final { scan-assembler {\tstr\tz26, \[x0, #3, mul vl\]\n} } } */ 110 /* { dg-final { scan-assembler {\tstr\tz27, \[x0, #4, mul vl\]\n} } } */ 111 /* { dg-final { scan-assembler {\tstr\tz28, \[x0, #5, mul vl\]\n} } } */ 112