1 /* Definitions of target machine for GNU compiler, for IBM S/390 2 Copyright (C) 1999-2021 Free Software Foundation, Inc. 3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4 Ulrich Weigand (uweigand@de.ibm.com). 5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com) 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it under 10 the terms of the GNU General Public License as published by the Free 11 Software Foundation; either version 3, or (at your option) any later 12 version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15 WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #ifndef _S390_H 24 #define _S390_H 25 26 /* Optional architectural facilities supported by the processor. */ 27 28 enum processor_flags 29 { 30 PF_IEEE_FLOAT = 1, 31 PF_ZARCH = 2, 32 PF_LONG_DISPLACEMENT = 4, 33 PF_EXTIMM = 8, 34 PF_DFP = 16, 35 PF_Z10 = 32, 36 PF_Z196 = 64, 37 PF_ZEC12 = 128, 38 PF_TX = 256, 39 PF_Z13 = 512, 40 PF_VX = 1024, 41 PF_Z14 = 2048, 42 PF_VXE = 4096, 43 PF_VXE2 = 8192, 44 PF_Z15 = 16384, 45 PF_NNPA = 32768, 46 PF_ARCH14 = 65536 47 }; 48 49 /* This is necessary to avoid a warning about comparing different enum 50 types. */ 51 #define s390_tune_attr ((enum attr_cpu)(s390_tune > PROCESSOR_8561_Z15 ? PROCESSOR_8561_Z15 : s390_tune )) 52 53 /* These flags indicate that the generated code should run on a cpu 54 providing the respective hardware facility regardless of the 55 current cpu mode (ESA or z/Architecture). */ 56 57 #define TARGET_CPU_IEEE_FLOAT \ 58 (s390_arch_flags & PF_IEEE_FLOAT) 59 #define TARGET_CPU_IEEE_FLOAT_P(opts) \ 60 (opts->x_s390_arch_flags & PF_IEEE_FLOAT) 61 #define TARGET_CPU_LONG_DISPLACEMENT \ 62 (s390_arch_flags & PF_LONG_DISPLACEMENT) 63 #define TARGET_CPU_LONG_DISPLACEMENT_P(opts) \ 64 (opts->x_s390_arch_flags & PF_LONG_DISPLACEMENT) 65 #define TARGET_CPU_EXTIMM \ 66 (s390_arch_flags & PF_EXTIMM) 67 #define TARGET_CPU_EXTIMM_P(opts) \ 68 (opts->x_s390_arch_flags & PF_EXTIMM) 69 #define TARGET_CPU_DFP \ 70 (s390_arch_flags & PF_DFP) 71 #define TARGET_CPU_DFP_P(opts) \ 72 (opts->x_s390_arch_flags & PF_DFP) 73 #define TARGET_CPU_Z10 \ 74 (s390_arch_flags & PF_Z10) 75 #define TARGET_CPU_Z10_P(opts) \ 76 (opts->x_s390_arch_flags & PF_Z10) 77 #define TARGET_CPU_Z196 \ 78 (s390_arch_flags & PF_Z196) 79 #define TARGET_CPU_Z196_P(opts) \ 80 (opts->x_s390_arch_flags & PF_Z196) 81 #define TARGET_CPU_ZEC12 \ 82 (s390_arch_flags & PF_ZEC12) 83 #define TARGET_CPU_ZEC12_P(opts) \ 84 (opts->x_s390_arch_flags & PF_ZEC12) 85 #define TARGET_CPU_HTM \ 86 (s390_arch_flags & PF_TX) 87 #define TARGET_CPU_HTM_P(opts) \ 88 (opts->x_s390_arch_flags & PF_TX) 89 #define TARGET_CPU_Z13 \ 90 (s390_arch_flags & PF_Z13) 91 #define TARGET_CPU_Z13_P(opts) \ 92 (opts->x_s390_arch_flags & PF_Z13) 93 #define TARGET_CPU_VX \ 94 (s390_arch_flags & PF_VX) 95 #define TARGET_CPU_VX_P(opts) \ 96 (opts->x_s390_arch_flags & PF_VX) 97 #define TARGET_CPU_Z14 \ 98 (s390_arch_flags & PF_Z14) 99 #define TARGET_CPU_Z14_P(opts) \ 100 (opts->x_s390_arch_flags & PF_Z14) 101 #define TARGET_CPU_VXE \ 102 (s390_arch_flags & PF_VXE) 103 #define TARGET_CPU_VXE_P(opts) \ 104 (opts->x_s390_arch_flags & PF_VXE) 105 #define TARGET_CPU_Z15 \ 106 (s390_arch_flags & PF_Z15) 107 #define TARGET_CPU_Z15_P(opts) \ 108 (opts->x_s390_arch_flags & PF_Z15) 109 #define TARGET_CPU_VXE2 \ 110 (s390_arch_flags & PF_VXE2) 111 #define TARGET_CPU_VXE2_P(opts) \ 112 (opts->x_s390_arch_flags & PF_VXE2) 113 #define TARGET_CPU_ARCH14 \ 114 (s390_arch_flags & PF_ARCH14) 115 #define TARGET_CPU_ARCH14_P(opts) \ 116 (opts->x_s390_arch_flags & PF_ARCH14) 117 #define TARGET_CPU_NNPA \ 118 (s390_arch_flags & PF_NNPA) 119 #define TARGET_CPU_NNPA_P(opts) \ 120 (opts->x_s390_arch_flags & PF_NNPA) 121 122 #define TARGET_HARD_FLOAT_P(opts) (!TARGET_SOFT_FLOAT_P(opts)) 123 124 /* These flags indicate that the generated code should run on a cpu 125 providing the respective hardware facility when run in 126 z/Architecture mode. */ 127 128 #define TARGET_LONG_DISPLACEMENT \ 129 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) 130 #define TARGET_LONG_DISPLACEMENT_P(opts) \ 131 (TARGET_ZARCH_P (opts->x_target_flags) \ 132 && TARGET_CPU_LONG_DISPLACEMENT_P (opts)) 133 #define TARGET_EXTIMM \ 134 (TARGET_ZARCH && TARGET_CPU_EXTIMM) 135 #define TARGET_EXTIMM_P(opts) \ 136 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_EXTIMM_P (opts)) 137 #define TARGET_DFP \ 138 (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) 139 #define TARGET_DFP_P(opts) \ 140 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_DFP_P (opts) \ 141 && TARGET_HARD_FLOAT_P (opts->x_target_flags)) 142 #define TARGET_Z10 \ 143 (TARGET_ZARCH && TARGET_CPU_Z10) 144 #define TARGET_Z10_P(opts) \ 145 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z10_P (opts)) 146 #define TARGET_Z196 \ 147 (TARGET_ZARCH && TARGET_CPU_Z196) 148 #define TARGET_Z196_P(opts) \ 149 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z196_P (opts)) 150 #define TARGET_ZEC12 \ 151 (TARGET_ZARCH && TARGET_CPU_ZEC12) 152 #define TARGET_ZEC12_P(opts) \ 153 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ZEC12_P (opts)) 154 #define TARGET_HTM (TARGET_OPT_HTM) 155 #define TARGET_HTM_P(opts) (TARGET_OPT_HTM_P (opts->x_target_flags)) 156 #define TARGET_Z13 \ 157 (TARGET_ZARCH && TARGET_CPU_Z13) 158 #define TARGET_Z13_P(opts) \ 159 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z13_P (opts)) 160 #define TARGET_VX \ 161 (TARGET_ZARCH && TARGET_CPU_VX && TARGET_OPT_VX && TARGET_HARD_FLOAT) 162 #define TARGET_VX_P(opts) \ 163 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_VX_P (opts) \ 164 && TARGET_OPT_VX_P (opts->x_target_flags) \ 165 && TARGET_HARD_FLOAT_P (opts->x_target_flags)) 166 #define TARGET_Z14 (TARGET_ZARCH && TARGET_CPU_Z14) 167 #define TARGET_Z14_P(opts) \ 168 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z14_P (opts)) 169 #define TARGET_VXE \ 170 (TARGET_VX && TARGET_CPU_VXE) 171 #define TARGET_VXE_P(opts) \ 172 (TARGET_VX_P (opts) && TARGET_CPU_VXE_P (opts)) 173 #define TARGET_Z15 (TARGET_ZARCH && TARGET_CPU_Z15) 174 #define TARGET_Z15_P(opts) \ 175 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z15_P (opts)) 176 #define TARGET_VXE2 \ 177 (TARGET_VX && TARGET_CPU_VXE2) 178 #define TARGET_VXE2_P(opts) \ 179 (TARGET_VX_P (opts) && TARGET_CPU_VXE2_P (opts)) 180 #define TARGET_ARCH14 (TARGET_ZARCH && TARGET_CPU_ARCH14) 181 #define TARGET_ARCH14_P(opts) \ 182 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ARCH14_P (opts)) 183 #define TARGET_NNPA \ 184 (TARGET_ZARCH && TARGET_CPU_NNPA) 185 #define TARGET_NNPA_P(opts) \ 186 (TARGET_ZARCH_P (opts) && TARGET_CPU_NNPA_P (opts)) 187 188 #if defined(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13) 189 #define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS TARGET_Z13 190 #elif defined(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS) 191 #define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS TARGET_Z14 192 #else 193 #define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS 0 194 #endif 195 196 /* Evaluate to true if it is ok to emit a non-signaling vector 197 comparison. */ 198 #define TARGET_NONSIGNALING_VECTOR_COMPARE_OK \ 199 (TARGET_VX && !TARGET_VXE && (flag_finite_math_only || !flag_trapping_math)) 200 201 #ifdef HAVE_AS_MACHINE_MACHINEMODE 202 #define S390_USE_TARGET_ATTRIBUTE 1 203 #else 204 #define S390_USE_TARGET_ATTRIBUTE 0 205 #endif 206 207 #ifdef HAVE_AS_ARCHITECTURE_MODIFIERS 208 #define S390_USE_ARCHITECTURE_MODIFIERS 1 209 #else 210 #define S390_USE_ARCHITECTURE_MODIFIERS 0 211 #endif 212 213 #if S390_USE_TARGET_ATTRIBUTE 214 /* For switching between functions with different target attributes. */ 215 #define SWITCHABLE_TARGET 1 216 #endif 217 218 #define TARGET_SUPPORTS_WIDE_INT 1 219 220 /* Use the ABI introduced with IBM z13: 221 - pass vector arguments <= 16 bytes in VRs 222 - align *all* vector types to 8 bytes */ 223 #define TARGET_VX_ABI TARGET_VX 224 225 #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) 226 227 /* Issue a write prefetch for the +4 cache line. */ 228 #define TARGET_SETMEM_PREFETCH_DISTANCE 1024 229 230 /* Expand to a C expressions evaluating to true if a setmem to VAL of 231 length LEN should be emitted using prefetch instructions. */ 232 #define TARGET_SETMEM_PFD(VAL,LEN) \ 233 (TARGET_Z10 \ 234 && (s390_tune < PROCESSOR_2964_Z13 || (VAL) != const0_rtx) \ 235 && (!CONST_INT_P (LEN) || INTVAL ((LEN)) > TARGET_SETMEM_PREFETCH_DISTANCE)) 236 237 /* Run-time target specification. */ 238 239 /* Defaults for option flags defined only on some subtargets. */ 240 #ifndef TARGET_TPF_PROFILING 241 #define TARGET_TPF_PROFILING 0 242 #endif 243 244 /* This will be overridden by OS headers. */ 245 #define TARGET_TPF 0 246 247 /* Target CPU builtins. */ 248 #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile) 249 250 /* Target hooks for D language. */ 251 #define TARGET_D_CPU_VERSIONS s390_d_target_versions 252 #define TARGET_D_REGISTER_CPU_TARGET_INFO s390_d_register_target_info 253 254 #ifdef DEFAULT_TARGET_64BIT 255 #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP \ 256 | MASK_OPT_HTM | MASK_OPT_VX) 257 #else 258 #define TARGET_DEFAULT 0 259 #endif 260 261 /* Support for configure-time defaults. 262 The order here is important so that -march doesn't squash the 263 tune values. */ 264 #define OPTION_DEFAULT_SPECS \ 265 { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ 266 { "tune", "%{!mtune=*:%{!march=*:-mtune=%(VALUE)}}" }, \ 267 { "arch", "%{!march=*:-march=%(VALUE)}" } 268 269 #ifdef __s390__ 270 extern const char *s390_host_detect_local_cpu (int argc, const char **argv); 271 # define EXTRA_SPEC_FUNCTIONS \ 272 { "local_cpu_detect", s390_host_detect_local_cpu }, 273 274 #define MARCH_MTUNE_NATIVE_SPECS \ 275 "%{mtune=native:%<mtune=native %:local_cpu_detect(tune)} " \ 276 "%{march=native:%<march=native" \ 277 " %:local_cpu_detect(arch %{mesa|mzarch:mesa_mzarch})}" 278 #else 279 # define MARCH_MTUNE_NATIVE_SPECS "" 280 #endif 281 282 #ifdef DEFAULT_TARGET_64BIT 283 #define S390_TARGET_BITS_STRING "64" 284 #else 285 #define S390_TARGET_BITS_STRING "31" 286 #endif 287 288 /* Defaulting rules. */ 289 #define DRIVER_SELF_SPECS \ 290 MARCH_MTUNE_NATIVE_SPECS, \ 291 "%{!m31:%{!m64:-m" S390_TARGET_BITS_STRING "}}", \ 292 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ 293 "%{!march=*:-march=z900}" 294 295 /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ 296 #define S390_TDC_POSITIVE_ZERO (1 << 11) 297 #define S390_TDC_NEGATIVE_ZERO (1 << 10) 298 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) 299 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) 300 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) 301 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) 302 #define S390_TDC_POSITIVE_INFINITY (1 << 5) 303 #define S390_TDC_NEGATIVE_INFINITY (1 << 4) 304 #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) 305 #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) 306 #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) 307 #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) 308 309 /* The following values are different for DFP. */ 310 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) 311 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) 312 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) 313 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) 314 315 /* For signbit, the BFP-DFP-difference makes no difference. */ 316 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ 317 | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ 318 | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ 319 | S390_TDC_NEGATIVE_INFINITY \ 320 | S390_TDC_NEGATIVE_QUIET_NAN \ 321 | S390_TDC_NEGATIVE_SIGNALING_NAN ) 322 323 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ 324 | S390_TDC_NEGATIVE_INFINITY ) 325 326 /* Target machine storage layout. */ 327 328 /* Everything is big-endian. */ 329 #define BITS_BIG_ENDIAN 1 330 #define BYTES_BIG_ENDIAN 1 331 #define WORDS_BIG_ENDIAN 1 332 333 #define STACK_SIZE_MODE (Pmode) 334 335 #ifndef IN_LIBGCC2 336 337 /* Width of a word, in units (bytes). */ 338 #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) 339 340 /* Width of a pointer. To be used instead of UNITS_PER_WORD in 341 ABI-relevant contexts. This always matches 342 GET_MODE_SIZE (Pmode). */ 343 #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) 344 #define MIN_UNITS_PER_WORD 4 345 #define MAX_BITS_PER_WORD 64 346 #else 347 348 /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether 349 the library should export TImode functions or not. Thus, we have 350 to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ 351 #ifdef __s390x__ 352 #define UNITS_PER_WORD 8 353 #else 354 #define UNITS_PER_WORD 4 355 #endif 356 #endif 357 358 /* Width of a pointer, in bits. */ 359 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) 360 361 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 362 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) 363 364 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 365 #define STACK_BOUNDARY 64 366 367 /* Allocation boundary (in *bits*) for the code of a function. */ 368 #define FUNCTION_BOUNDARY 64 369 370 /* There is no point aligning anything to a rounder boundary than this. */ 371 #define BIGGEST_ALIGNMENT 64 372 373 /* Alignment of field after `int : 0' in a structure. */ 374 #define EMPTY_FIELD_BOUNDARY 32 375 376 /* Alignment on even addresses for LARL instruction. */ 377 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) 378 379 /* Alignment is not required by the hardware. */ 380 #define STRICT_ALIGNMENT 0 381 382 /* Mode of stack savearea. 383 FUNCTION is VOIDmode because calling convention maintains SP. 384 BLOCK needs Pmode for SP. 385 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 386 #define STACK_SAVEAREA_MODE(LEVEL) \ 387 ((LEVEL) == SAVE_FUNCTION ? VOIDmode \ 388 : (LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) 389 390 391 /* Type layout. */ 392 393 /* Sizes in bits of the source language data types. */ 394 #define SHORT_TYPE_SIZE 16 395 #define INT_TYPE_SIZE 32 396 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) 397 #define LONG_LONG_TYPE_SIZE 64 398 #define FLOAT_TYPE_SIZE 32 399 #define DOUBLE_TYPE_SIZE 64 400 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) 401 402 /* Work around target_flags dependency in ada/targtyps.c. */ 403 #define WIDEST_HARDWARE_FP_SIZE 64 404 405 /* We use "unsigned char" as default. */ 406 #define DEFAULT_SIGNED_CHAR 0 407 408 409 /* Register usage. */ 410 411 /* We have 16 general purpose registers (registers 0-15), 412 and 16 floating point registers (registers 16-31). 413 (On non-IEEE machines, we have only 4 fp registers.) 414 415 Amongst the general purpose registers, some are used 416 for specific purposes: 417 GPR 11: Hard frame pointer (if needed) 418 GPR 12: Global offset table pointer (if needed) 419 GPR 13: Literal pool base register 420 GPR 14: Return address register 421 GPR 15: Stack pointer 422 423 Registers 32-35 are 'fake' hard registers that do not 424 correspond to actual hardware: 425 Reg 32: Argument pointer 426 Reg 33: Condition code 427 Reg 34: Frame pointer 428 Reg 35: Return address pointer 429 430 Registers 36 and 37 are mapped to access registers 431 0 and 1, used to implement thread-local storage. 432 433 Reg 38-53: Vector registers v16-v31 */ 434 435 #define FIRST_PSEUDO_REGISTER 54 436 437 /* Standard register usage. */ 438 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) 439 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) 440 #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) 441 #define CC_REGNO_P(N) ((N) == 33) 442 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) 443 #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) 444 #define VECTOR_NOFP_REGNO_P(N) ((N) >= 38 && (N) <= 53) 445 #define VECTOR_REGNO_P(N) (FP_REGNO_P (N) || VECTOR_NOFP_REGNO_P (N)) 446 447 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 448 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) 449 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 450 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 451 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) 452 #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) 453 #define VECTOR_NOFP_REG_P(X) (REG_P (X) && VECTOR_NOFP_REGNO_P (REGNO (X))) 454 #define VECTOR_REG_P(X) (REG_P (X) && VECTOR_REGNO_P (REGNO (X))) 455 456 /* Set up fixed registers and calling convention: 457 458 GPRs 0-5 are always call-clobbered, 459 GPRs 6-15 are always call-saved. 460 GPR 12 is fixed if used as GOT pointer. 461 GPR 13 is always fixed (as literal pool pointer). 462 GPR 14 is always fixed on S/390 machines (as return address). 463 GPR 15 is always fixed (as stack pointer). 464 The 'fake' hard registers are call-clobbered and fixed. 465 The access registers are call-saved and fixed. 466 467 On 31-bit, FPRs 18-19 are call-clobbered; 468 on 64-bit, FPRs 24-31 are call-clobbered. 469 The remaining FPRs are call-saved. 470 471 All non-FP vector registers are call-clobbered v16-v31. */ 472 473 #define FIXED_REGISTERS \ 474 { 0, 0, 0, 0, \ 475 0, 0, 0, 0, \ 476 0, 0, 0, 0, \ 477 0, 1, 1, 1, \ 478 0, 0, 0, 0, \ 479 0, 0, 0, 0, \ 480 0, 0, 0, 0, \ 481 0, 0, 0, 0, \ 482 1, 1, 1, 1, \ 483 1, 1, \ 484 0, 0, 0, 0, \ 485 0, 0, 0, 0, \ 486 0, 0, 0, 0, \ 487 0, 0, 0, 0 } 488 489 #define CALL_REALLY_USED_REGISTERS \ 490 { 1, 1, 1, 1, /* r0 - r15 */ \ 491 1, 1, 0, 0, \ 492 0, 0, 0, 0, \ 493 0, 0, 0, 0, \ 494 1, 1, 1, 1, /* f0 (16) - f15 (31) */ \ 495 1, 1, 1, 1, \ 496 1, 1, 1, 1, \ 497 1, 1, 1, 1, \ 498 1, 1, 1, 1, /* arg, cc, fp, ret addr */ \ 499 0, 0, /* a0 (36), a1 (37) */ \ 500 1, 1, 1, 1, /* v16 (38) - v23 (45) */ \ 501 1, 1, 1, 1, \ 502 1, 1, 1, 1, /* v24 (46) - v31 (53) */ \ 503 1, 1, 1, 1 } 504 505 /* Preferred register allocation order. */ 506 #define REG_ALLOC_ORDER \ 507 { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ 508 16, 17, 18, 19, 20, 21, 22, 23, \ 509 24, 25, 26, 27, 28, 29, 30, 31, \ 510 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, \ 511 15, 32, 33, 34, 35, 36, 37 } 512 513 514 #define HARD_REGNO_RENAME_OK(FROM, TO) \ 515 s390_hard_regno_rename_ok ((FROM), (TO)) 516 517 /* Maximum number of registers to represent a value of mode MODE 518 in a register of class CLASS. */ 519 #define CLASS_MAX_NREGS(CLASS, MODE) \ 520 s390_class_max_nregs ((CLASS), (MODE)) 521 522 /* We can reverse a CC mode safely if we know whether it comes from a 523 floating point compare or not. With the vector modes it is encoded 524 as part of the mode. 525 FIXME: It might make sense to do this for other cc modes as well. */ 526 #define REVERSIBLE_CC_MODE(MODE) \ 527 ((MODE) == CCVIALLmode || (MODE) == CCVIANYmode \ 528 || (MODE) == CCVFALLmode || (MODE) == CCVFANYmode) 529 530 /* Given a condition code and a mode, return the inverse condition. */ 531 #define REVERSE_CONDITION(CODE, MODE) s390_reverse_condition (MODE, CODE) 532 533 534 /* Register classes. */ 535 536 /* We use the following register classes: 537 GENERAL_REGS All general purpose registers 538 ADDR_REGS All general purpose registers except %r0 539 (These registers can be used in address generation) 540 FP_REGS All floating point registers 541 CC_REGS The condition code register 542 ACCESS_REGS The access registers 543 544 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS 545 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS 546 GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS 547 ADDR_CC_REGS Union of ADDR_REGS and CC_REGS 548 549 NO_REGS No registers 550 ALL_REGS All registers 551 552 Note that the 'fake' frame pointer and argument pointer registers 553 are included amongst the address registers here. */ 554 555 enum reg_class 556 { 557 NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, 558 ADDR_CC_REGS, GENERAL_CC_REGS, 559 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, 560 VEC_REGS, ADDR_VEC_REGS, GENERAL_VEC_REGS, 561 ALL_REGS, LIM_REG_CLASSES 562 }; 563 #define N_REG_CLASSES (int) LIM_REG_CLASSES 564 565 #define REG_CLASS_NAMES \ 566 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ 567 "ADDR_CC_REGS", "GENERAL_CC_REGS", \ 568 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", \ 569 "VEC_REGS", "ADDR_VEC_REGS", "GENERAL_VEC_REGS", \ 570 "ALL_REGS" } 571 572 /* Class -> register mapping. */ 573 #define REG_CLASS_CONTENTS \ 574 { \ 575 { 0x00000000, 0x00000000 }, /* NO_REGS */ \ 576 { 0x00000000, 0x00000002 }, /* CC_REGS */ \ 577 { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ 578 { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ 579 { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ 580 { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ 581 { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ 582 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ 583 { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ 584 { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ 585 { 0xffff0000, 0x003fffc0 }, /* VEC_REGS */ \ 586 { 0xfffffffe, 0x003fffcd }, /* ADDR_VEC_REGS */ \ 587 { 0xffffffff, 0x003fffcd }, /* GENERAL_VEC_REGS */ \ 588 { 0xffffffff, 0x003fffff }, /* ALL_REGS */ \ 589 } 590 591 /* In some case register allocation order is not enough for IRA to 592 generate a good code. The following macro (if defined) increases 593 cost of REGNO for a pseudo approximately by pseudo usage frequency 594 multiplied by the macro value. 595 596 We avoid usage of BASE_REGNUM by nonzero macro value because the 597 reload can decide not to use the hard register because some 598 constant was forced to be in memory. */ 599 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ 600 ((regno) != BASE_REGNUM ? 0.0 : 0.5) 601 602 /* Register -> class mapping. */ 603 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; 604 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 605 606 /* ADDR_REGS can be used as base or index register. */ 607 #define INDEX_REG_CLASS ADDR_REGS 608 #define BASE_REG_CLASS ADDR_REGS 609 610 /* Check whether REGNO is a hard register of the suitable class 611 or a pseudo register currently allocated to one such. */ 612 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 613 (((REGNO) < FIRST_PSEUDO_REGISTER \ 614 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ 615 || ADDR_REGNO_P (reg_renumber[REGNO])) 616 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 617 618 619 /* Stack layout and calling conventions. */ 620 621 /* Our stack grows from higher to lower addresses. However, local variables 622 are accessed by positive offsets, and function arguments are stored at 623 increasing addresses. */ 624 #define STACK_GROWS_DOWNWARD 1 625 #define FRAME_GROWS_DOWNWARD 1 626 /* #undef ARGS_GROW_DOWNWARD */ 627 628 /* The basic stack layout looks like this: the stack pointer points 629 to the register save area for called functions. Above that area 630 is the location to place outgoing arguments. Above those follow 631 dynamic allocations (alloca), and finally the local variables. */ 632 633 /* Offset from stack-pointer to first location of outgoing args. */ 634 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) 635 636 /* Offset from the stack pointer register to an item dynamically 637 allocated on the stack, e.g., by `alloca'. */ 638 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 639 (STACK_POINTER_OFFSET + crtl->outgoing_args_size) 640 641 /* Offset of first parameter from the argument pointer register value. 642 We have a fake argument pointer register that points directly to 643 the argument area. */ 644 #define FIRST_PARM_OFFSET(FNDECL) 0 645 646 /* Defining this macro makes __builtin_frame_address(0) and 647 __builtin_return_address(0) work with -fomit-frame-pointer. */ 648 #define INITIAL_FRAME_ADDRESS_RTX \ 649 (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) 650 651 /* The return address of the current frame is retrieved 652 from the initial value of register RETURN_REGNUM. 653 For frames farther back, we use the stack slot where 654 the corresponding RETURN_REGNUM register was saved. */ 655 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ 656 (TARGET_PACKED_STACK ? \ 657 plus_constant (Pmode, (FRAME), \ 658 STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) 659 660 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of 661 builtin_frame_address. Otherwise arg pointer - 662 STACK_POINTER_OFFSET would be returned for 663 __builtin_frame_address(0) what might result in an address pointing 664 somewhere into the middle of the local variables since the packed 665 stack layout generally does not need all the bytes in the register 666 save area. */ 667 #define FRAME_ADDR_RTX(FRAME) \ 668 DYNAMIC_CHAIN_ADDRESS ((FRAME)) 669 670 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 671 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) 672 673 /* In 31-bit mode, we need to mask off the high bit of return addresses. */ 674 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) 675 676 677 /* Exception handling. */ 678 679 /* Describe calling conventions for DWARF-2 exception handling. */ 680 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) 681 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET 682 #define DWARF_FRAME_RETURN_COLUMN 14 683 684 /* Describe how we implement __builtin_eh_return. */ 685 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) 686 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) 687 688 /* Select a format to encode pointers in exception handling data. */ 689 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 690 (flag_pic \ 691 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 692 : DW_EH_PE_absptr) 693 694 /* Register save slot alignment. */ 695 #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) 696 697 /* Let the assembler generate debug line info. */ 698 #define DWARF2_ASM_LINE_DEBUG_INFO 1 699 700 /* Define the dwarf register mapping. 701 v16-v31 -> 68-83 702 rX -> X otherwise */ 703 #define DBX_REGISTER_NUMBER(regno) \ 704 (((regno) >= 38 && (regno) <= 53) ? (regno) + 30 : (regno)) 705 706 /* Frame registers. */ 707 708 #define STACK_POINTER_REGNUM 15 709 #define FRAME_POINTER_REGNUM 34 710 #define HARD_FRAME_POINTER_REGNUM 11 711 #define ARG_POINTER_REGNUM 32 712 #define RETURN_ADDRESS_POINTER_REGNUM 35 713 714 /* The static chain must be call-clobbered, but not used for 715 function argument passing. As register 1 is clobbered by 716 the trampoline code, we only have one option. */ 717 #define STATIC_CHAIN_REGNUM 0 718 719 /* Number of hardware registers that go into the DWARF-2 unwind info. 720 To avoid ABI incompatibility, this number must not change even as 721 'fake' hard registers are added or removed. */ 722 #define DWARF_FRAME_REGISTERS 34 723 724 725 /* Frame pointer and argument pointer elimination. */ 726 727 #define ELIMINABLE_REGS \ 728 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 729 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 730 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 731 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 732 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 733 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 734 { BASE_REGNUM, BASE_REGNUM }} 735 736 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 737 (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) 738 739 740 /* Stack arguments. */ 741 742 /* We need current_function_outgoing_args to be valid. */ 743 #define ACCUMULATE_OUTGOING_ARGS 1 744 745 746 /* Register arguments. */ 747 748 typedef struct s390_arg_structure 749 { 750 int gprs; /* gpr so far */ 751 int fprs; /* fpr so far */ 752 int vrs; /* vr so far */ 753 } 754 CUMULATIVE_ARGS; 755 756 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ 757 ((CUM).gprs=0, (CUM).fprs=0, (CUM).vrs=0) 758 759 #define FIRST_VEC_ARG_REGNO 46 760 #define LAST_VEC_ARG_REGNO 53 761 762 /* Arguments can be placed in general registers 2 to 6, or in floating 763 point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 764 bit. */ 765 #define FUNCTION_ARG_REGNO_P(N) \ 766 (((N) >=2 && (N) < 7) || (N) == 16 || (N) == 17 \ 767 || (TARGET_64BIT && ((N) == 18 || (N) == 19)) \ 768 || (TARGET_VX && ((N) >= FIRST_VEC_ARG_REGNO && (N) <= LAST_VEC_ARG_REGNO))) 769 770 771 /* Only gpr 2, fpr 0, and v24 are ever used as return registers. */ 772 #define FUNCTION_VALUE_REGNO_P(N) \ 773 ((N) == 2 || (N) == 16 \ 774 || (TARGET_VX && (N) == FIRST_VEC_ARG_REGNO)) 775 776 777 /* Function entry and exit. */ 778 779 /* When returning from a function, the stack pointer does not matter. */ 780 #define EXIT_IGNORE_STACK 1 781 782 783 /* Profiling. */ 784 785 #define FUNCTION_PROFILER(FILE, LABELNO) \ 786 s390_function_profiler ((FILE), ((LABELNO))) 787 788 #define PROFILE_BEFORE_PROLOGUE 1 789 790 #define NO_PROFILE_COUNTERS 1 791 792 793 /* Trampolines for nested functions. */ 794 795 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) 796 #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD 797 798 /* Addressing modes, and classification of registers for them. */ 799 800 /* Recognize any constant value that is a valid address. */ 801 #define CONSTANT_ADDRESS_P(X) 0 802 803 /* Maximum number of registers that can appear in a valid memory address. */ 804 #define MAX_REGS_PER_ADDRESS 2 805 806 /* This definition replaces the formerly used 'm' constraint with a 807 different constraint letter in order to avoid changing semantics of 808 the 'm' constraint when accepting new address formats in 809 TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here 810 must not be used in insn definitions or inline assemblies. */ 811 #define TARGET_MEM_CONSTRAINT 'e' 812 813 /* Try a machine-dependent way of reloading an illegitimate address 814 operand. If we find one, push the reload and jump to WIN. This 815 macro is used in only one place: `find_reloads_address' in reload.c. */ 816 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ 817 do { \ 818 rtx new_rtx = legitimize_reload_address ((AD), (MODE), \ 819 (OPNUM), (int)(TYPE)); \ 820 if (new_rtx) \ 821 { \ 822 (AD) = new_rtx; \ 823 goto WIN; \ 824 } \ 825 } while (0) 826 827 /* Helper macro for s390.c and s390.md to check for symbolic constants. */ 828 #define SYMBOLIC_CONST(X) \ 829 (GET_CODE (X) == SYMBOL_REF \ 830 || GET_CODE (X) == LABEL_REF \ 831 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 832 833 #define TLS_SYMBOLIC_CONST(X) \ 834 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ 835 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) 836 837 838 /* Condition codes. */ 839 840 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 841 return the mode to be used for the comparison. */ 842 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) 843 844 /* Relative costs of operations. */ 845 846 /* A C expression for the cost of a branch instruction. A value of 1 847 is the default; other values are interpreted relative to that. */ 848 #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost 849 850 /* Nonzero if access to memory by bytes is slow and undesirable. */ 851 #define SLOW_BYTE_ACCESS 1 852 853 /* An integer expression for the size in bits of the largest integer machine 854 mode that should actually be used. We allow pairs of registers. */ 855 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 856 857 /* The maximum number of bytes that a single instruction can move quickly 858 between memory and registers or between two memory locations. */ 859 #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) 860 #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) 861 #define MAX_MOVE_MAX 16 862 863 /* Don't perform CSE on function addresses. */ 864 #define NO_FUNCTION_CSE 1 865 866 /* This value is used in tree-sra to decide whether it might benefical 867 to split a struct move into several word-size moves. For S/390 868 only small values make sense here since struct moves are relatively 869 cheap thanks to mvc so the small default value chosen for archs 870 with memmove patterns should be ok. But this value is multiplied 871 in tree-sra with UNITS_PER_WORD to make a decision so we adjust it 872 here to compensate for that factor since mvc costs exactly the same 873 on 31 and 64 bit. */ 874 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) 875 876 877 /* Sections. */ 878 879 /* Output before read-only data. */ 880 #define TEXT_SECTION_ASM_OP ".text" 881 882 /* Output before writable (initialized) data. */ 883 #define DATA_SECTION_ASM_OP ".data" 884 885 /* Output before writable (uninitialized) data. */ 886 #define BSS_SECTION_ASM_OP ".bss" 887 888 /* S/390 constant pool breaks the devices in crtstuff.c to control section 889 in where code resides. We have to write it as asm code. */ 890 #ifndef __s390x__ 891 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 892 asm (SECTION_OP "\n\ 893 bras\t%r2,1f\n\ 894 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ 895 1: l\t%r3,0(%r2)\n\ 896 bas\t%r14,0(%r3,%r2)\n\ 897 .previous"); 898 #endif 899 900 901 /* Position independent code. */ 902 903 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) 904 905 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 906 907 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 908 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 909 #endif 910 911 912 /* Assembler file format. */ 913 914 /* Character to start a comment. */ 915 #define ASM_COMMENT_START "#" 916 917 /* Declare an uninitialized external linkage data object. */ 918 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 919 asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) 920 921 /* Globalizing directive for a label. */ 922 #define GLOBAL_ASM_OP ".globl " 923 924 /* Advance the location counter to a multiple of 2**LOG bytes. */ 925 #define ASM_OUTPUT_ALIGN(FILE, LOG) \ 926 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) 927 928 /* Advance the location counter by SIZE bytes. */ 929 #define ASM_OUTPUT_SKIP(FILE, SIZE) \ 930 fprintf ((FILE), "\t.set\t.,.+" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 931 932 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ 933 #define LOCAL_LABEL_PREFIX "." 934 935 #define LABEL_ALIGN(LABEL) \ 936 s390_label_align ((LABEL)) 937 938 /* How to refer to registers in assembler output. This sequence is 939 indexed by compiler's hard-register-number (see above). */ 940 #define REGISTER_NAMES \ 941 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ 942 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ 943 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ 944 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ 945 "%ap", "%cc", "%fp", "%rp", "%a0", "%a1", \ 946 "%v16", "%v18", "%v20", "%v22", "%v17", "%v19", "%v21", "%v23", \ 947 "%v24", "%v26", "%v28", "%v30", "%v25", "%v27", "%v29", "%v31" \ 948 } 949 950 #define ADDITIONAL_REGISTER_NAMES \ 951 { { "v0", 16 }, { "v2", 17 }, { "v4", 18 }, { "v6", 19 }, \ 952 { "v1", 20 }, { "v3", 21 }, { "v5", 22 }, { "v7", 23 }, \ 953 { "v8", 24 }, { "v10", 25 }, { "v12", 26 }, { "v14", 27 }, \ 954 { "v9", 28 }, { "v11", 29 }, { "v13", 30 }, { "v15", 31 } }; 955 956 /* Print operand X (an rtx) in assembler syntax to file FILE. */ 957 #define PRINT_OPERAND(FILE, X, CODE) print_operand ((FILE), (X), (CODE)) 958 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address ((FILE), (ADDR)) 959 960 /* Output an element of a case-vector that is absolute. */ 961 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 962 do { \ 963 char buf[32]; \ 964 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ 965 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 966 assemble_name ((FILE), buf); \ 967 fputc ('\n', (FILE)); \ 968 } while (0) 969 970 /* Output an element of a case-vector that is relative. */ 971 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 972 do { \ 973 char buf[32]; \ 974 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ 975 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 976 assemble_name ((FILE), buf); \ 977 fputc ('-', (FILE)); \ 978 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ 979 assemble_name ((FILE), buf); \ 980 fputc ('\n', (FILE)); \ 981 } while (0) 982 983 /* Mark the return register as used by the epilogue so that we can 984 use it in unadorned (return) and (simple_return) instructions. */ 985 #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_REGNUM) 986 987 #undef ASM_OUTPUT_FUNCTION_LABEL 988 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 989 s390_asm_output_function_label ((FILE), (NAME), (DECL)) 990 991 #if S390_USE_TARGET_ATTRIBUTE 992 /* Hook to output .machine and .machinemode at start of function. */ 993 #undef ASM_OUTPUT_FUNCTION_PREFIX 994 #define ASM_OUTPUT_FUNCTION_PREFIX s390_asm_output_function_prefix 995 996 /* Hook to output .machine and .machinemode at end of function. */ 997 #undef ASM_DECLARE_FUNCTION_SIZE 998 #define ASM_DECLARE_FUNCTION_SIZE s390_asm_declare_function_size 999 #endif 1000 1001 /* Miscellaneous parameters. */ 1002 1003 /* Specify the machine mode that this machine uses for the index in the 1004 tablejump instruction. */ 1005 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) 1006 1007 /* Specify the machine mode that pointers have. 1008 After generation of rtl, the compiler makes no further distinction 1009 between pointers and any other objects of this machine mode. */ 1010 #define Pmode (TARGET_64BIT ? DImode : SImode) 1011 1012 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ 1013 #define POINTERS_EXTEND_UNSIGNED -1 1014 1015 /* A function address in a call instruction is a byte address (for 1016 indexing purposes) so give the MEM rtx a byte's mode. */ 1017 #define FUNCTION_MODE QImode 1018 1019 /* Specify the value which is used when clz operand is zero. */ 1020 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) 1021 1022 /* Machine-specific symbol_ref flags. */ 1023 #define SYMBOL_FLAG_ALIGN_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT 1024 #define SYMBOL_FLAG_ALIGN_MASK \ 1025 ((SYMBOL_FLAG_MACH_DEP << 0) | (SYMBOL_FLAG_MACH_DEP << 1)) 1026 1027 #define SYMBOL_FLAG_SET_ALIGN(X, A) \ 1028 (SYMBOL_REF_FLAGS (X) = (SYMBOL_REF_FLAGS (X) & ~SYMBOL_FLAG_ALIGN_MASK) \ 1029 | (A << SYMBOL_FLAG_ALIGN_SHIFT)) 1030 1031 #define SYMBOL_FLAG_GET_ALIGN(X) \ 1032 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN_MASK) >> SYMBOL_FLAG_ALIGN_SHIFT) 1033 1034 /* Helpers to access symbol_ref flags. They are used in 1035 check_symref_alignment() and larl_operand to detect if the 1036 available alignment matches the required one. We do not use 1037 a positive check like _ALIGN2 because in that case we would have 1038 to annotate every symbol_ref. However, we only want to touch 1039 the symbol_refs that can be misaligned and assume that the others 1040 are correctly aligned. Hence, if a symbol_ref does not have 1041 a _NOTALIGN flag it is supposed to be correctly aligned. */ 1042 #define SYMBOL_FLAG_SET_NOTALIGN2(X) SYMBOL_FLAG_SET_ALIGN((X), 1) 1043 #define SYMBOL_FLAG_SET_NOTALIGN4(X) SYMBOL_FLAG_SET_ALIGN((X), 2) 1044 #define SYMBOL_FLAG_SET_NOTALIGN8(X) SYMBOL_FLAG_SET_ALIGN((X), 3) 1045 1046 #define SYMBOL_FLAG_NOTALIGN2_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 1) 1047 #define SYMBOL_FLAG_NOTALIGN4_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 2 \ 1048 || SYMBOL_FLAG_GET_ALIGN(X) == 1) 1049 #define SYMBOL_FLAG_NOTALIGN8_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 3 \ 1050 || SYMBOL_FLAG_GET_ALIGN(X) == 2 \ 1051 || SYMBOL_FLAG_GET_ALIGN(X) == 1) 1052 1053 /* Check whether integer displacement is in range for a short displacement. */ 1054 #define SHORT_DISP_IN_RANGE(d) ((d) >= 0 && (d) <= 4095) 1055 1056 /* Check whether integer displacement is in range. */ 1057 #define DISP_IN_RANGE(d) \ 1058 (TARGET_LONG_DISPLACEMENT \ 1059 ? ((d) >= -524288 && (d) <= 524287) \ 1060 : SHORT_DISP_IN_RANGE(d)) 1061 1062 /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ 1063 #define READ_CAN_USE_WRITE_PREFETCH 1 1064 1065 extern const int processor_flags_table[]; 1066 1067 struct s390_processor 1068 { 1069 /* The preferred name to be used in user visible output. */ 1070 const char *const name; 1071 /* CPU name as it should be passed to Binutils via .machine */ 1072 const char *const binutils_name; 1073 const enum processor_type processor; 1074 const struct processor_costs *cost; 1075 int arch_level; 1076 }; 1077 1078 extern const struct s390_processor processor_table[]; 1079 1080 /* The truth element value for vector comparisons. Our instructions 1081 always generate -1 in that case. */ 1082 #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) 1083 1084 /* Target pragma. */ 1085 1086 /* resolve_overloaded_builtin cannot be defined the normal way since 1087 it is defined in code which technically belongs to the 1088 front-end. */ 1089 #define REGISTER_TARGET_PRAGMAS() \ 1090 do { \ 1091 s390_register_target_pragmas (); \ 1092 } while (0) 1093 1094 #ifndef USED_FOR_TARGET 1095 /* The following structure is embedded in the machine 1096 specific part of struct function. */ 1097 1098 struct GTY (()) s390_frame_layout 1099 { 1100 /* Offset within stack frame. */ 1101 HOST_WIDE_INT gprs_offset; 1102 HOST_WIDE_INT f0_offset; 1103 HOST_WIDE_INT f4_offset; 1104 HOST_WIDE_INT f8_offset; 1105 HOST_WIDE_INT backchain_offset; 1106 1107 /* Number of first and last gpr where slots in the register 1108 save area are reserved for. */ 1109 int first_save_gpr_slot; 1110 int last_save_gpr_slot; 1111 1112 /* Location (FP register number) where GPRs (r0-r15) should 1113 be saved to. 1114 0 - does not need to be saved at all 1115 -1 - stack slot */ 1116 #define SAVE_SLOT_NONE 0 1117 #define SAVE_SLOT_STACK -1 1118 signed char gpr_save_slots[16]; 1119 1120 /* Number of first and last gpr to be saved, restored. */ 1121 int first_save_gpr; 1122 int first_restore_gpr; 1123 int last_save_gpr; 1124 int last_restore_gpr; 1125 1126 /* Bits standing for floating point registers. Set, if the 1127 respective register has to be saved. Starting with reg 16 (f0) 1128 at the rightmost bit. 1129 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1130 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0 1131 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */ 1132 unsigned int fpr_bitmap; 1133 1134 /* Number of floating point registers f8-f15 which must be saved. */ 1135 int high_fprs; 1136 1137 /* Set if return address needs to be saved. 1138 This flag is set by s390_return_addr_rtx if it could not use 1139 the initial value of r14 and therefore depends on r14 saved 1140 to the stack. */ 1141 bool save_return_addr_p; 1142 1143 /* Size of stack frame. */ 1144 HOST_WIDE_INT frame_size; 1145 }; 1146 1147 1148 /* Define the structure for the machine field in struct function. */ 1149 1150 struct GTY(()) machine_function 1151 { 1152 struct s390_frame_layout frame_layout; 1153 1154 /* Literal pool base register. */ 1155 rtx base_reg; 1156 1157 bool has_landing_pad_p; 1158 1159 /* True if the current function may contain a tbegin clobbering 1160 FPRs. */ 1161 bool tbegin_p; 1162 1163 /* For -fsplit-stack support: A stack local which holds a pointer to 1164 the stack arguments for a function with a variable number of 1165 arguments. This is set at the start of the function and is used 1166 to initialize the overflow_arg_area field of the va_list 1167 structure. */ 1168 rtx split_stack_varargs_pointer; 1169 1170 enum indirect_branch indirect_branch_jump; 1171 enum indirect_branch indirect_branch_call; 1172 1173 enum indirect_branch function_return_mem; 1174 enum indirect_branch function_return_reg; 1175 }; 1176 #endif 1177 1178 #define TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION \ 1179 (cfun->machine->function_return_reg != indirect_branch_keep \ 1180 || cfun->machine->function_return_mem != indirect_branch_keep) 1181 1182 #define TARGET_INDIRECT_BRANCH_NOBP_RET \ 1183 ((cfun->machine->function_return_reg != indirect_branch_keep \ 1184 && !s390_return_addr_from_memory ()) \ 1185 || (cfun->machine->function_return_mem != indirect_branch_keep \ 1186 && s390_return_addr_from_memory ())) 1187 1188 #define TARGET_INDIRECT_BRANCH_NOBP_JUMP \ 1189 (cfun->machine->indirect_branch_jump != indirect_branch_keep) 1190 1191 #define TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK \ 1192 (cfun->machine->indirect_branch_jump == indirect_branch_thunk \ 1193 || cfun->machine->indirect_branch_jump == indirect_branch_thunk_extern) 1194 1195 #define TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK \ 1196 (cfun->machine->indirect_branch_jump == indirect_branch_thunk_inline) 1197 1198 #define TARGET_INDIRECT_BRANCH_NOBP_CALL \ 1199 (cfun->machine->indirect_branch_call != indirect_branch_keep) 1200 1201 #ifndef TARGET_DEFAULT_INDIRECT_BRANCH_TABLE 1202 #define TARGET_DEFAULT_INDIRECT_BRANCH_TABLE 0 1203 #endif 1204 1205 #define TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL "__s390_indirect_jump_r%d" 1206 #define TARGET_INDIRECT_BRANCH_THUNK_NAME_EX "__s390_indirect_jump_r%duse_r%d" 1207 1208 #define TARGET_INDIRECT_BRANCH_TABLE s390_indirect_branch_table 1209 1210 #ifdef GENERATOR_FILE 1211 /* gencondmd.c is built before insn-flags.h. Use an arbitrary opaque value 1212 that cannot be optimized away by gen_insn. */ 1213 #define HAVE_TF(icode) TARGET_HARD_FLOAT 1214 #else 1215 #define HAVE_TF(icode) (HAVE_##icode##_fpr || HAVE_##icode##_vr) 1216 #endif 1217 1218 /* Dispatcher for movtf. */ 1219 #define EXPAND_MOVTF(icode) \ 1220 do \ 1221 { \ 1222 if (TARGET_VXE) \ 1223 emit_insn (gen_##icode##_vr (operands[0], operands[1])); \ 1224 else \ 1225 emit_insn (gen_##icode##_fpr (operands[0], operands[1])); \ 1226 DONE; \ 1227 } \ 1228 while (false) 1229 1230 /* Like EXPAND_MOVTF, but also legitimizes operands. */ 1231 #define EXPAND_TF(icode, nops) \ 1232 do \ 1233 { \ 1234 const size_t __nops = (nops); \ 1235 expand_operand ops[__nops]; \ 1236 create_output_operand (&ops[0], operands[0], GET_MODE (operands[0])); \ 1237 for (size_t i = 1; i < __nops; i++) \ 1238 create_input_operand (&ops[i], operands[i], GET_MODE (operands[i])); \ 1239 if (TARGET_VXE) \ 1240 expand_insn (CODE_FOR_##icode##_vr, __nops, ops); \ 1241 else \ 1242 expand_insn (CODE_FOR_##icode##_fpr, __nops, ops); \ 1243 DONE; \ 1244 } \ 1245 while (false) 1246 1247 #endif /* S390_H */ 1248