1/* This file contains the definitions and documentation for the 2 Register Transfer Expressions (rtx's) that make up the 3 Register Transfer Language (rtl) used in the Back End of the GNU compiler. 4 Copyright (C) 1987-2021 Free Software Foundation, Inc. 5 6This file is part of GCC. 7 8GCC is free software; you can redistribute it and/or modify it under 9the terms of the GNU General Public License as published by the Free 10Software Foundation; either version 3, or (at your option) any later 11version. 12 13GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14WARRANTY; without even the implied warranty of MERCHANTABILITY or 15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16for more details. 17 18You should have received a copy of the GNU General Public License 19along with GCC; see the file COPYING3. If not see 20<http://www.gnu.org/licenses/>. */ 21 22 23/* Expression definitions and descriptions for all targets are in this file. 24 Some will not be used for some targets. 25 26 The fields in the cpp macro call "DEF_RTL_EXPR()" 27 are used to create declarations in the C source of the compiler. 28 29 The fields are: 30 31 1. The internal name of the rtx used in the C source. 32 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". 33 By convention these are in UPPER_CASE. 34 35 2. The name of the rtx in the external ASCII format read by 36 read_rtx(), and printed by print_rtx(). 37 These names are stored in rtx_name[]. 38 By convention these are the internal (field 1) names in lower_case. 39 40 3. The print format, and type of each rtx->u.fld[] (field) in this rtx. 41 These formats are stored in rtx_format[]. 42 The meaning of the formats is documented in front of this array in rtl.c 43 44 4. The class of the rtx. These are stored in rtx_class and are accessed 45 via the GET_RTX_CLASS macro. They are defined as follows: 46 47 RTX_CONST_OBJ 48 an rtx code that can be used to represent a constant object 49 (e.g, CONST_INT) 50 RTX_OBJ 51 an rtx code that can be used to represent an object (e.g, REG, MEM) 52 RTX_COMPARE 53 an rtx code for a comparison (e.g, LT, GT) 54 RTX_COMM_COMPARE 55 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED) 56 RTX_UNARY 57 an rtx code for a unary arithmetic expression (e.g, NEG, NOT) 58 RTX_COMM_ARITH 59 an rtx code for a commutative binary operation (e.g,, PLUS, MULT) 60 RTX_TERNARY 61 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) 62 RTX_BIN_ARITH 63 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) 64 RTX_BITFIELD_OPS 65 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) 66 RTX_INSN 67 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) or 68 data that will be output as assembly pseudo-ops (DEBUG_INSN) 69 RTX_MATCH 70 an rtx code for something that matches in insns (e.g, MATCH_DUP) 71 RTX_AUTOINC 72 an rtx code for autoincrement addressing modes (e.g. POST_DEC) 73 RTX_EXTRA 74 everything else 75 76 All of the expressions that appear only in machine descriptions, 77 not in RTL used by the compiler itself, are at the end of the file. */ 78 79/* Unknown, or no such operation; the enumeration constant should have 80 value zero. */ 81DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) 82 83/* Used in the cselib routines to describe a value. Objects of this 84 kind are only allocated in cselib.c, in an alloc pool instead of in 85 GC memory. The only operand of a VALUE is a cselib_val. 86 var-tracking requires this to have a distinct integral value from 87 DECL codes in trees. */ 88DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ) 89 90/* The RTL generated for a DEBUG_EXPR_DECL. It links back to the 91 DEBUG_EXPR_DECL in the first operand. */ 92DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ) 93 94/* --------------------------------------------------------------------- 95 Expressions used in constructing lists. 96 --------------------------------------------------------------------- */ 97 98/* A linked list of expressions. */ 99DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA) 100 101/* A linked list of instructions. 102 The insns are represented in print by their uids. */ 103DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA) 104 105/* A linked list of integers. */ 106DEF_RTL_EXPR(INT_LIST, "int_list", "ie", RTX_EXTRA) 107 108/* SEQUENCE is used in late passes of the compiler to group insns for 109 one reason or another. 110 111 For example, after delay slot filling, branch instructions with filled 112 delay slots are represented as a SEQUENCE of length 1 + n_delay_slots, 113 with the branch instruction in XEXPVEC(seq, 0, 0) and the instructions 114 occupying the delay slots in the remaining XEXPVEC slots. 115 116 Another place where a SEQUENCE may appear, is in REG_FRAME_RELATED_EXPR 117 notes, to express complex operations that are not obvious from the insn 118 to which the REG_FRAME_RELATED_EXPR note is attached. In this usage of 119 SEQUENCE, the sequence vector slots do not hold real instructions but 120 only pseudo-instructions that can be translated to DWARF CFA expressions. 121 122 Some back ends also use SEQUENCE to group insns in bundles. 123 124 Much of the compiler infrastructure is not prepared to handle SEQUENCE 125 objects. Only passes after pass_free_cfg are expected to handle them. */ 126DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA) 127 128/* Represents a non-global base address. This is only used in alias.c. */ 129DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA) 130 131/* ---------------------------------------------------------------------- 132 Expression types used for things in the instruction chain. 133 134 All formats must start with "uu" to handle the chain. 135 Each insn expression holds an rtl instruction and its semantics 136 during back-end processing. 137 See macros in "rtl.h" for the meaning of each rtx->u.fld[]. 138 139 ---------------------------------------------------------------------- */ 140 141/* An annotation for variable assignment tracking. */ 142DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "uuBeiie", RTX_INSN) 143 144/* An instruction that cannot jump. */ 145DEF_RTL_EXPR(INSN, "insn", "uuBeiie", RTX_INSN) 146 147/* An instruction that can possibly jump. 148 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 149DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "uuBeiie0", RTX_INSN) 150 151/* An instruction that can possibly call a subroutine 152 but which will not change which instruction comes next 153 in the current function. 154 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE. 155 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 156DEF_RTL_EXPR(CALL_INSN, "call_insn", "uuBeiiee", RTX_INSN) 157 158/* Placeholder for tablejump JUMP_INSNs. The pattern of this kind 159 of rtx is always either an ADDR_VEC or an ADDR_DIFF_VEC. These 160 placeholders do not appear as real instructions inside a basic 161 block, but are considered active_insn_p instructions for historical 162 reasons, when jump table data was represented with JUMP_INSNs. */ 163DEF_RTL_EXPR(JUMP_TABLE_DATA, "jump_table_data", "uuBe0000", RTX_INSN) 164 165/* A marker that indicates that control will not flow through. */ 166DEF_RTL_EXPR(BARRIER, "barrier", "uu00000", RTX_EXTRA) 167 168/* Holds a label that is followed by instructions. 169 Operand: 170 3: is used in jump.c for the use-count of the label. 171 4: is used in the sh backend. 172 5: is a number that is unique in the entire compilation. 173 6: is the user-given name of the label, if any. */ 174DEF_RTL_EXPR(CODE_LABEL, "code_label", "uuB00is", RTX_EXTRA) 175 176/* Say where in the code a source line starts, for symbol table's sake. 177 Operand: 178 3: note-specific data 179 4: enum insn_note 180 5: unique number if insn_note == note_insn_deleted_label. */ 181DEF_RTL_EXPR(NOTE, "note", "uuB0ni", RTX_EXTRA) 182 183/* ---------------------------------------------------------------------- 184 Top level constituents of INSN, JUMP_INSN and CALL_INSN. 185 ---------------------------------------------------------------------- */ 186 187/* Conditionally execute code. 188 Operand 0 is the condition that if true, the code is executed. 189 Operand 1 is the code to be executed (typically a SET). 190 191 Semantics are that there are no side effects if the condition 192 is false. This pattern is created automatically by the if_convert 193 pass run after reload or by target-specific splitters. */ 194DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA) 195 196/* Several operations to be done in parallel (perhaps under COND_EXEC). */ 197DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA) 198 199/* A string that is passed through to the assembler as input. 200 One can obviously pass comments through by using the 201 assembler comment syntax. 202 These occur in an insn all by themselves as the PATTERN. 203 They also appear inside an ASM_OPERANDS 204 as a convenient way to hold a string. */ 205DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA) 206 207/* An assembler instruction with operands. 208 1st operand is the instruction template. 209 2nd operand is the constraint for the output. 210 3rd operand is the number of the output this expression refers to. 211 When an insn stores more than one value, a separate ASM_OPERANDS 212 is made for each output; this integer distinguishes them. 213 4th is a vector of values of input operands. 214 5th is a vector of modes and constraints for the input operands. 215 Each element is an ASM_INPUT containing a constraint string 216 and whose mode indicates the mode of the input operand. 217 6th is a vector of labels that may be branched to by the asm. 218 7th is the source line number. */ 219DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA) 220 221/* A machine-specific operation. 222 1st operand is a vector of operands being used by the operation so that 223 any needed reloads can be done. 224 2nd operand is a unique value saying which of a number of machine-specific 225 operations is to be performed. 226 (Note that the vector must be the first operand because of the way that 227 genrecog.c record positions within an insn.) 228 229 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL, 230 or inside an expression. 231 UNSPEC by itself or as a component of a PARALLEL 232 is currently considered not deletable. 233 234 FIXME: Replace all uses of UNSPEC that appears by itself or as a component 235 of a PARALLEL with USE. 236 */ 237DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA) 238 239/* Similar, but a volatile operation and one which may trap. */ 240DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA) 241 242/* ---------------------------------------------------------------------- 243 Table jump addresses. 244 ---------------------------------------------------------------------- */ 245 246/* Vector of addresses, stored as full words. 247 Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ 248DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA) 249 250/* Vector of address differences X0 - BASE, X1 - BASE, ... 251 First operand is BASE; the vector contains the X's. 252 The machine mode of this rtx says how much space to leave 253 for each difference and is adjusted by branch shortening if 254 CASE_VECTOR_SHORTEN_MODE is defined. 255 The third and fourth operands store the target labels with the 256 minimum and maximum addresses respectively. 257 The fifth operand stores flags for use by branch shortening. 258 Set at the start of shorten_branches: 259 min_align: the minimum alignment for any of the target labels. 260 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. 261 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. 262 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. 263 min_after_base: true iff minimum address target label is after BASE. 264 max_after_base: true iff maximum address target label is after BASE. 265 Set by the actual branch shortening process: 266 offset_unsigned: true iff offsets have to be treated as unsigned. 267 scale: scaling that is necessary to make offsets fit into the mode. 268 269 The third, fourth and fifth operands are only valid when 270 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing 271 compilation. */ 272DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA) 273 274/* Memory prefetch, with attributes supported on some targets. 275 Operand 1 is the address of the memory to fetch. 276 Operand 2 is 1 for a write access, 0 otherwise. 277 Operand 3 is the level of temporal locality; 0 means there is no 278 temporal locality and 1, 2, and 3 are for increasing levels of temporal 279 locality. 280 281 The attributes specified by operands 2 and 3 are ignored for targets 282 whose prefetch instructions do not support them. */ 283DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA) 284 285/* ---------------------------------------------------------------------- 286 At the top level of an instruction (perhaps under PARALLEL). 287 ---------------------------------------------------------------------- */ 288 289/* Assignment. 290 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 291 Operand 2 is the value stored there. 292 ALL assignment must use SET. 293 Instructions that do multiple assignments must use multiple SET, 294 under PARALLEL. */ 295DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA) 296 297/* Indicate something is used in a way that we don't want to explain. 298 For example, subroutine calls will use the register 299 in which the static chain is passed. 300 301 USE cannot appear as an operand of other rtx except for PARALLEL. 302 USE is not deletable, as it indicates that the operand 303 is used in some unknown way. */ 304DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) 305 306/* Indicate something is clobbered in a way that we don't want to explain. 307 For example, subroutine calls will clobber some physical registers 308 (the ones that are by convention not saved). 309 310 CLOBBER cannot appear as an operand of other rtx except for PARALLEL. 311 CLOBBER of a hard register appearing by itself (not within PARALLEL) 312 is considered undeletable before reload. */ 313DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) 314 315/* Call a subroutine. 316 Operand 1 is the address to call. 317 Operand 2 is the number of arguments. */ 318 319DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA) 320 321/* Return from a subroutine. */ 322 323DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) 324 325/* Like RETURN, but truly represents only a function return, while 326 RETURN may represent an insn that also performs other functions 327 of the function epilogue. Like RETURN, this may also occur in 328 conditional jumps. */ 329DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA) 330 331/* Special for EH return from subroutine. */ 332 333DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA) 334 335/* Conditional trap. 336 Operand 1 is the condition. 337 Operand 2 is the trap code. 338 For an unconditional trap, make the condition (const_int 1). */ 339DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA) 340 341/* ---------------------------------------------------------------------- 342 Primitive values for use in expressions. 343 ---------------------------------------------------------------------- */ 344 345/* numeric integer constant */ 346DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) 347 348/* numeric integer constant */ 349DEF_RTL_EXPR(CONST_WIDE_INT, "const_wide_int", "", RTX_CONST_OBJ) 350 351/* An rtx representation of a poly_wide_int. */ 352DEF_RTL_EXPR(CONST_POLY_INT, "const_poly_int", "", RTX_CONST_OBJ) 353 354/* fixed-point constant */ 355DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ) 356 357/* numeric floating point or integer constant. If the mode is 358 VOIDmode it is an int otherwise it has a floating point mode and a 359 floating point value. Operands hold the value. They are all 'w' 360 and there may be from 2 to 6; see real.h. */ 361DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ) 362 363/* Describes a vector constant. */ 364DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ) 365 366/* String constant. Used for attributes in machine descriptions and 367 for special cases in DWARF2 debug output. NOT used for source- 368 language string constants. */ 369DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ) 370 371/* This is used to encapsulate an expression whose value is constant 372 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be 373 recognized as a constant operand rather than by arithmetic instructions. */ 374 375DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ) 376 377/* program counter. Ordinary jumps are represented 378 by a SET whose first operand is (PC). */ 379DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ) 380 381/* A register. The "operand" is the register number, accessed with 382 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 383 then a hardware register is being referred to. The second operand 384 points to a reg_attrs structure. 385 This rtx needs to have as many (or more) fields as a MEM, since we 386 can change REG rtx's into MEMs during reload. */ 387DEF_RTL_EXPR(REG, "reg", "r", RTX_OBJ) 388 389/* A scratch register. This represents a register used only within a 390 single insn. It will be replaced by a REG during register allocation 391 or reload unless the constraint indicates that the register won't be 392 needed, in which case it can remain a SCRATCH. */ 393DEF_RTL_EXPR(SCRATCH, "scratch", "", RTX_OBJ) 394 395/* A reference to a part of another value. The first operand is the 396 complete value and the second is the byte offset of the selected part. */ 397DEF_RTL_EXPR(SUBREG, "subreg", "ep", RTX_EXTRA) 398 399/* This one-argument rtx is used for move instructions 400 that are guaranteed to alter only the low part of a destination. 401 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 402 has an unspecified effect on the high part of REG, 403 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) 404 is guaranteed to alter only the bits of REG that are in HImode. 405 406 The actual instruction used is probably the same in both cases, 407 but the register constraints may be tighter when STRICT_LOW_PART 408 is in use. */ 409 410DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA) 411 412/* (CONCAT a b) represents the virtual concatenation of a and b 413 to make a value that has as many bits as a and b put together. 414 This is used for complex values. Normally it appears only 415 in DECL_RTLs and during RTL generation, but not in the insn chain. */ 416DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ) 417 418/* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of 419 all An to make a value. This is an extension of CONCAT to larger 420 number of components. Like CONCAT, it should not appear in the 421 insn chain. Every element of the CONCATN is the same size. */ 422DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ) 423 424/* A memory location; operand is the address. The second operand is the 425 alias set to which this MEM belongs. We use `0' instead of `w' for this 426 field so that the field need not be specified in machine descriptions. */ 427DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ) 428 429/* Reference to an assembler label in the code for this function. 430 The operand is a CODE_LABEL found in the insn chain. */ 431DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ) 432 433/* Reference to a named label: 434 Operand 0: label name 435 Operand 1: tree from which this symbol is derived, or null. 436 This is either a DECL node, or some kind of constant. */ 437DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s0", RTX_CONST_OBJ) 438 439/* The condition code register is represented, in our imagination, 440 as a register holding a value that can be compared to zero. 441 In fact, the machine has already compared them and recorded the 442 results; but instructions that look at the condition code 443 pretend to be looking at the entire value and comparing it. */ 444DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ) 445 446/* ---------------------------------------------------------------------- 447 Expressions for operators in an rtl pattern 448 ---------------------------------------------------------------------- */ 449 450/* if_then_else. This is used in representing ordinary 451 conditional jump instructions. 452 Operand: 453 0: condition 454 1: then expr 455 2: else expr */ 456DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY) 457 458/* Comparison, produces a condition code result. */ 459DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH) 460 461/* plus */ 462DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH) 463 464/* Operand 0 minus operand 1. */ 465DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH) 466 467/* Minus operand 0. */ 468DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY) 469 470DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH) 471 472/* Multiplication with signed saturation */ 473DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH) 474/* Multiplication with unsigned saturation */ 475DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH) 476 477/* Operand 0 divided by operand 1. */ 478DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH) 479/* Division with signed saturation */ 480DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH) 481/* Division with unsigned saturation */ 482DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH) 483 484/* Remainder of operand 0 divided by operand 1. */ 485DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH) 486 487/* Unsigned divide and remainder. */ 488DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH) 489DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) 490 491/* Bitwise operations. */ 492DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) 493DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) 494DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) 495DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) 496 497/* Operand: 498 0: value to be shifted. 499 1: number of bits. */ 500DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */ 501DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */ 502DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */ 503DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */ 504DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ 505 506/* Minimum and maximum values of two operands. We need both signed and 507 unsigned forms. (We cannot use MIN for SMIN because it conflicts 508 with a macro of the same name.) The signed variants should be used 509 with floating point. Further, if both operands are zeros, or if either 510 operand is NaN, then it is unspecified which of the two operands is 511 returned as the result. */ 512 513DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) 514DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) 515DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH) 516DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH) 517 518/* These unary operations are used to represent incrementation 519 and decrementation as they occur in memory addresses. 520 The amount of increment or decrement are not represented 521 because they can be understood from the machine-mode of the 522 containing MEM. These operations exist in only two cases: 523 1. pushes onto the stack. 524 2. created automatically by the auto-inc-dec pass. */ 525DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC) 526DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC) 527DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC) 528DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC) 529 530/* These binary operations are used to represent generic address 531 side-effects in memory addresses, except for simple incrementation 532 or decrementation which use the above operations. They are 533 created automatically by the life_analysis pass in flow.c. 534 The first operand is a REG which is used as the address. 535 The second operand is an expression that is assigned to the 536 register, either before (PRE_MODIFY) or after (POST_MODIFY) 537 evaluating the address. 538 Currently, the compiler can only handle second operands of the 539 form (plus (reg) (reg)) and (plus (reg) (const_int)), where 540 the first operand of the PLUS has to be the same register as 541 the first operand of the *_MODIFY. */ 542DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC) 543DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC) 544 545/* Comparison operations. The first 6 are allowed only for integral, 546floating-point and vector modes. LTGT is only allowed for floating-point 547modes. The last 4 are allowed only for integral and vector modes. 548For floating-point operations, if either operand is a NaN, then NE returns 549true and the remaining operations return false. The operations other than 550EQ and NE may generate an exception on quiet NaNs. */ 551DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE) 552DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE) 553DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE) 554DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE) 555DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE) 556DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE) 557DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE) 558DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE) 559DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE) 560DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE) 561DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE) 562 563/* Additional floating-point unordered comparison flavors. */ 564DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE) 565DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE) 566 567/* These are equivalent to unordered or ... */ 568DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE) 569DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE) 570DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE) 571DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE) 572DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE) 573 574/* Represents the result of sign-extending the sole operand. 575 The machine modes of the operand and of the SIGN_EXTEND expression 576 determine how much sign-extension is going on. */ 577DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY) 578 579/* Similar for zero-extension (such as unsigned short to int). */ 580DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY) 581 582/* Similar but here the operand has a wider mode. */ 583DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY) 584 585/* Similar for extending floating-point values (such as SFmode to DFmode). */ 586DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY) 587DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY) 588 589/* Conversion of fixed point operand to floating point value. */ 590DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY) 591 592/* With fixed-point machine mode: 593 Conversion of floating point operand to fixed point value. 594 Value is defined only when the operand's value is an integer. 595 With floating-point machine mode (and operand with same mode): 596 Operand is rounded toward zero to produce an integer value 597 represented in floating point. */ 598DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY) 599 600/* Conversion of unsigned fixed point operand to floating point value. */ 601DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY) 602 603/* With fixed-point machine mode: 604 Conversion of floating point operand to *unsigned* fixed point value. 605 Value is defined only when the operand's value is an integer. */ 606DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY) 607 608/* Conversions involving fractional fixed-point types without saturation, 609 including: 610 fractional to fractional (of different precision), 611 signed integer to fractional, 612 fractional to signed integer, 613 floating point to fractional, 614 fractional to floating point. 615 NOTE: fractional can be either signed or unsigned for conversions. */ 616DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY) 617 618/* Conversions involving fractional fixed-point types and unsigned integer 619 without saturation, including: 620 unsigned integer to fractional, 621 fractional to unsigned integer. 622 NOTE: fractional can be either signed or unsigned for conversions. */ 623DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY) 624 625/* Conversions involving fractional fixed-point types with saturation, 626 including: 627 fractional to fractional (of different precision), 628 signed integer to fractional, 629 floating point to fractional. 630 NOTE: fractional can be either signed or unsigned for conversions. */ 631DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY) 632 633/* Conversions involving fractional fixed-point types and unsigned integer 634 with saturation, including: 635 unsigned integer to fractional. 636 NOTE: fractional can be either signed or unsigned for conversions. */ 637DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY) 638 639/* Absolute value */ 640DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY) 641 642/* Square root */ 643DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY) 644 645/* Swap bytes. */ 646DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY) 647 648/* Find first bit that is set. 649 Value is 1 + number of trailing zeros in the arg., 650 or 0 if arg is 0. */ 651DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY) 652 653/* Count number of leading redundant sign bits (number of leading 654 sign bits minus one). */ 655DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY) 656 657/* Count leading zeros. */ 658DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY) 659 660/* Count trailing zeros. */ 661DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY) 662 663/* Population count (number of 1 bits). */ 664DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY) 665 666/* Population parity (number of 1 bits modulo 2). */ 667DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY) 668 669/* Reference to a signed bit-field of specified size and position. 670 Operand 0 is the memory unit (usually SImode or QImode) which 671 contains the field's first bit. Operand 1 is the width, in bits. 672 Operand 2 is the number of bits in the memory unit before the 673 first bit of this field. 674 If BITS_BIG_ENDIAN is defined, the first bit is the msb and 675 operand 2 counts from the msb of the memory unit. 676 Otherwise, the first bit is the lsb and operand 2 counts from 677 the lsb of the memory unit. 678 This kind of expression cannot appear as an lvalue in RTL. */ 679DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS) 680 681/* Similar for unsigned bit-field. 682 But note! This kind of expression _can_ appear as an lvalue. */ 683DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS) 684 685/* For RISC machines. These save memory when splitting insns. */ 686 687/* HIGH are the high-order bits of a constant expression. */ 688DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ) 689 690/* LO_SUM is the sum of a register and the low-order bits 691 of a constant expression. */ 692DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ) 693 694/* Describes a merge operation between two vector values. 695 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask 696 that specifies where the parts of the result are taken from. Set bits 697 indicate operand 0, clear bits indicate operand 1. The parts are defined 698 by the mode of the vectors. */ 699DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY) 700 701/* Describes an operation that selects parts of a vector. 702 Operands 0 is the source vector, operand 1 is a PARALLEL that contains 703 a CONST_INT for each of the subparts of the result vector, giving the 704 number of the source subpart that should be stored into it. */ 705DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH) 706 707/* Describes a vector concat operation. Operands 0 and 1 are the source 708 vectors, the result is a vector that is as long as operands 0 and 1 709 combined and is the concatenation of the two source vectors. */ 710DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH) 711 712/* Describes an operation that converts a small vector into a larger one by 713 duplicating the input values. The output vector mode must have the same 714 submodes as the input vector mode, and the number of output parts must be 715 an integer multiple of the number of input parts. */ 716DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY) 717 718/* Creation of a vector in which element I has the value BASE + I * STEP, 719 where BASE is the first operand and STEP is the second. The result 720 must have a vector integer mode. */ 721DEF_RTL_EXPR(VEC_SERIES, "vec_series", "ee", RTX_BIN_ARITH) 722 723/* Addition with signed saturation */ 724DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH) 725 726/* Addition with unsigned saturation */ 727DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH) 728 729/* Operand 0 minus operand 1, with signed saturation. */ 730DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH) 731 732/* Negation with signed saturation. */ 733DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY) 734/* Negation with unsigned saturation. */ 735DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY) 736 737/* Absolute value with signed saturation. */ 738DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY) 739 740/* Shift left with signed saturation. */ 741DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH) 742 743/* Shift left with unsigned saturation. */ 744DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH) 745 746/* Operand 0 minus operand 1, with unsigned saturation. */ 747DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH) 748 749/* Signed saturating truncate. */ 750DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY) 751 752/* Unsigned saturating truncate. */ 753DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) 754 755/* Floating point multiply/add combined instruction. */ 756DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY) 757 758/* Information about the variable and its location. */ 759DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA) 760 761/* Used in VAR_LOCATION for a pointer to a decl that is no longer 762 addressable. */ 763DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ) 764 765/* Represents value that argument had on function entry. The 766 single argument is the DECL_INCOMING_RTL of the corresponding 767 parameter. */ 768DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ) 769 770/* Used in VAR_LOCATION for a reference to a parameter that has 771 been optimized away completely. */ 772DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ) 773 774/* Used in marker DEBUG_INSNs to avoid being recognized as an insn. */ 775DEF_RTL_EXPR(DEBUG_MARKER, "debug_marker", "", RTX_EXTRA) 776 777/* All expressions from this point forward appear only in machine 778 descriptions. */ 779#ifdef GENERATOR_FILE 780 781/* Pattern-matching operators: */ 782 783/* Use the function named by the second arg (the string) 784 as a predicate; if matched, store the structure that was matched 785 in the operand table at index specified by the first arg (the integer). 786 If the second arg is the null string, the structure is just stored. 787 788 A third string argument indicates to the register allocator restrictions 789 on where the operand can be allocated. 790 791 If the target needs no restriction on any instruction this field should 792 be the null string. 793 794 The string is prepended by: 795 '=' to indicate the operand is only written to. 796 '+' to indicate the operand is both read and written to. 797 798 Each character in the string represents an allocable class for an operand. 799 'g' indicates the operand can be any valid class. 800 'i' indicates the operand can be immediate (in the instruction) data. 801 'r' indicates the operand can be in a register. 802 'm' indicates the operand can be in memory. 803 'o' a subset of the 'm' class. Those memory addressing modes that 804 can be offset at compile time (have a constant added to them). 805 806 Other characters indicate target dependent operand classes and 807 are described in each target's machine description. 808 809 For instructions with more than one operand, sets of classes can be 810 separated by a comma to indicate the appropriate multi-operand constraints. 811 There must be a 1 to 1 correspondence between these sets of classes in 812 all operands for an instruction. 813 */ 814DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH) 815 816/* Match a SCRATCH or a register. When used to generate rtl, a 817 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies 818 the desired mode and the first argument is the operand number. 819 The second argument is the constraint. */ 820DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH) 821 822/* Apply a predicate, AND match recursively the operands of the rtx. 823 Operand 0 is the operand-number, as in match_operand. 824 Operand 1 is a predicate to apply (as a string, a function name). 825 Operand 2 is a vector of expressions, each of which must match 826 one subexpression of the rtx this construct is matching. */ 827DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH) 828 829/* Match a PARALLEL of arbitrary length. The predicate is applied 830 to the PARALLEL and the initial expressions in the PARALLEL are matched. 831 Operand 0 is the operand-number, as in match_operand. 832 Operand 1 is a predicate to apply to the PARALLEL. 833 Operand 2 is a vector of expressions, each of which must match the 834 corresponding element in the PARALLEL. */ 835DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH) 836 837/* Match only something equal to what is stored in the operand table 838 at the index specified by the argument. Use with MATCH_OPERAND. */ 839DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH) 840 841/* Match only something equal to what is stored in the operand table 842 at the index specified by the argument. Use with MATCH_OPERATOR. */ 843DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH) 844 845/* Match only something equal to what is stored in the operand table 846 at the index specified by the argument. Use with MATCH_PARALLEL. */ 847DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH) 848 849/* Appears only in define_predicate/define_special_predicate 850 expressions. Evaluates true only if the operand has an RTX code 851 from the set given by the argument (a comma-separated list). If the 852 second argument is present and nonempty, it is a sequence of digits 853 and/or letters which indicates the subexpression to test, using the 854 same syntax as genextract/genrecog's location strings: 0-9 for 855 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to 856 the result of the one before it. */ 857DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH) 858 859/* Used to inject a C conditional expression into an .md file. It can 860 appear in a predicate definition or an attribute expression. */ 861DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH) 862 863/* Insn (and related) definitions. */ 864 865/* Definition of the pattern for one kind of instruction. 866 Operand: 867 0: names this instruction. 868 If the name is the null string, the instruction is in the 869 machine description just to be recognized, and will never be emitted by 870 the tree to rtl expander. 871 1: is the pattern. 872 2: is a string which is a C expression 873 giving an additional condition for recognizing this pattern. 874 A null string means no extra condition. 875 3: is the action to execute if this pattern is matched. 876 If this assembler code template starts with a * then it is a fragment of 877 C code to run to decide on a template to use. Otherwise, it is the 878 template to use. 879 4: optionally, a vector of attributes for this insn. 880 */ 881DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA) 882 883/* Definition of a peephole optimization. 884 1st operand: vector of insn patterns to match 885 2nd operand: C expression that must be true 886 3rd operand: template or C code to produce assembler output. 887 4: optionally, a vector of attributes for this insn. 888 889 This form is deprecated; use define_peephole2 instead. */ 890DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA) 891 892/* Definition of a split operation. 893 1st operand: insn pattern to match 894 2nd operand: C expression that must be true 895 3rd operand: vector of insn patterns to place into a SEQUENCE 896 4th operand: optionally, some C code to execute before generating the 897 insns. This might, for example, create some RTX's and store them in 898 elements of `recog_data.operand' for use by the vector of 899 insn-patterns. 900 (`operands' is an alias here for `recog_data.operand'). */ 901DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA) 902 903/* Definition of an insn and associated split. 904 This is the concatenation, with a few modifications, of a define_insn 905 and a define_split which share the same pattern. 906 Operand: 907 0: names this instruction. 908 If the name is the null string, the instruction is in the 909 machine description just to be recognized, and will never be emitted by 910 the tree to rtl expander. 911 1: is the pattern. 912 2: is a string which is a C expression 913 giving an additional condition for recognizing this pattern. 914 A null string means no extra condition. 915 3: is the action to execute if this pattern is matched. 916 If this assembler code template starts with a * then it is a fragment of 917 C code to run to decide on a template to use. Otherwise, it is the 918 template to use. 919 4: C expression that must be true for split. This may start with "&&" 920 in which case the split condition is the logical and of the insn 921 condition and what follows the "&&" of this operand. 922 5: vector of insn patterns to place into a SEQUENCE 923 6: optionally, some C code to execute before generating the 924 insns. This might, for example, create some RTX's and store them in 925 elements of `recog_data.operand' for use by the vector of 926 insn-patterns. 927 (`operands' is an alias here for `recog_data.operand'). 928 7: optionally, a vector of attributes for this insn. */ 929DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA) 930 931/* A form of define_insn_and_split in which the split insn pattern (operand 5) 932 is determined automatically by replacing match_operands with match_dups 933 and match_operators with match_op_dups. The operands are the same as 934 define_insn_and_split but with operand 5 removed. */ 935DEF_RTL_EXPR(DEFINE_INSN_AND_REWRITE, "define_insn_and_rewrite", "sEsTsSV", RTX_EXTRA) 936 937/* Definition of an RTL peephole operation. 938 Follows the same arguments as define_split. */ 939DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) 940 941/* Define how to generate multiple insns for a standard insn name. 942 1st operand: the insn name. 943 2nd operand: vector of insn-patterns. 944 Use match_operand to substitute an element of `recog_data.operand'. 945 3rd operand: C expression that must be true for this to be available. 946 This may not test any operands. 947 4th operand: Extra C code to execute before generating the insns. 948 This might, for example, create some RTX's and store them in 949 elements of `recog_data.operand' for use by the vector of 950 insn-patterns. 951 (`operands' is an alias here for `recog_data.operand'). 952 5th: optionally, a vector of attributes for this expand. */ 953DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA) 954 955/* Define a requirement for delay slots. 956 1st operand: Condition involving insn attributes that, if true, 957 indicates that the insn requires the number of delay slots 958 shown. 959 2nd operand: Vector whose length is the three times the number of delay 960 slots required. 961 Each entry gives three conditions, each involving attributes. 962 The first must be true for an insn to occupy that delay slot 963 location. The second is true for all insns that can be 964 annulled if the branch is true and the third is true for all 965 insns that can be annulled if the branch is false. 966 967 Multiple DEFINE_DELAYs may be present. They indicate differing 968 requirements for delay slots. */ 969DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA) 970 971/* Define attribute computation for `asm' instructions. */ 972DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA) 973 974/* Definition of a conditional execution meta operation. Automatically 975 generates new instances of DEFINE_INSN, selected by having attribute 976 "predicable" true. The new pattern will contain a COND_EXEC and the 977 predicate at top-level. 978 979 Operand: 980 0: The predicate pattern. The top-level form should match a 981 relational operator. Operands should have only one alternative. 982 1: A C expression giving an additional condition for recognizing 983 the generated pattern. 984 2: A template or C code to produce assembler output. 985 3: A vector of attributes to append to the resulting cond_exec insn. */ 986DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA) 987 988/* Definition of an operand predicate. The difference between 989 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will 990 not warn about a match_operand with no mode if it has a predicate 991 defined with DEFINE_SPECIAL_PREDICATE. 992 993 Operand: 994 0: The name of the predicate. 995 1: A boolean expression which computes whether or not the predicate 996 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND, 997 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog 998 can calculate the set of RTX codes that can possibly match. 999 2: A C function body which must return true for the predicate to match. 1000 Optional. Use this when the test is too complicated to fit into a 1001 match_test expression. */ 1002DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA) 1003DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA) 1004 1005/* Definition of a register operand constraint. This simply maps the 1006 constraint string to a register class. 1007 1008 Operand: 1009 0: The name of the constraint (often, but not always, a single letter). 1010 1: A C expression which evaluates to the appropriate register class for 1011 this constraint. If this is not just a constant, it should look only 1012 at -m switches and the like. 1013 2: A docstring for this constraint, in Texinfo syntax; not currently 1014 used, in future will be incorporated into the manual's list of 1015 machine-specific operand constraints. */ 1016DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA) 1017 1018/* Definition of a non-register operand constraint. These look at the 1019 operand and decide whether it fits the constraint. 1020 1021 DEFINE_CONSTRAINT gets no special treatment if it fails to match. 1022 It is appropriate for constant-only constraints, and most others. 1023 1024 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made 1025 to match, if it doesn't already, by converting the operand to the form 1026 (mem (reg X)) where X is a base register. It is suitable for constraints 1027 that describe a subset of all memory references. 1028 1029 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made 1030 to match, if it doesn't already, by converting the operand to the form 1031 (reg X) where X is a base register. It is suitable for constraints that 1032 describe a subset of all address references. 1033 1034 When in doubt, use plain DEFINE_CONSTRAINT. 1035 1036 Operand: 1037 0: The name of the constraint (often, but not always, a single letter). 1038 1: A docstring for this constraint, in Texinfo syntax; not currently 1039 used, in future will be incorporated into the manual's list of 1040 machine-specific operand constraints. 1041 2: A boolean expression which computes whether or not the constraint 1042 matches. It should follow the same rules as a define_predicate 1043 expression, including the bit about specifying the set of RTX codes 1044 that could possibly match. MATCH_TEST subexpressions may make use of 1045 these variables: 1046 `op' - the RTL object defining the operand. 1047 `mode' - the mode of `op'. 1048 `ival' - INTVAL(op), if op is a CONST_INT. 1049 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE. 1050 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE. 1051 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point 1052 CONST_DOUBLE. 1053 Do not use ival/hval/lval/rval if op is not the appropriate kind of 1054 RTL object. */ 1055DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA) 1056DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA) 1057DEF_RTL_EXPR(DEFINE_SPECIAL_MEMORY_CONSTRAINT, "define_special_memory_constraint", "sse", RTX_EXTRA) 1058DEF_RTL_EXPR(DEFINE_RELAXED_MEMORY_CONSTRAINT, "define_relaxed_memory_constraint", "sse", RTX_EXTRA) 1059DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA) 1060 1061 1062/* Constructions for CPU pipeline description described by NDFAs. */ 1063 1064/* (define_cpu_unit string [string]) describes cpu functional 1065 units (separated by comma). 1066 1067 1st operand: Names of cpu functional units. 1068 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). 1069 1070 All define_reservations, define_cpu_units, and 1071 define_query_cpu_units should have unique names which may not be 1072 "nothing". */ 1073DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA) 1074 1075/* (define_query_cpu_unit string [string]) describes cpu functional 1076 units analogously to define_cpu_unit. The reservation of such 1077 units can be queried for automaton state. */ 1078DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA) 1079 1080/* (exclusion_set string string) means that each CPU functional unit 1081 in the first string cannot be reserved simultaneously with any 1082 unit whose name is in the second string and vise versa. CPU units 1083 in the string are separated by commas. For example, it is useful 1084 for description CPU with fully pipelined floating point functional 1085 unit which can execute simultaneously only single floating point 1086 insns or only double floating point insns. All CPU functional 1087 units in a set should belong to the same automaton. */ 1088DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA) 1089 1090/* (presence_set string string) means that each CPU functional unit in 1091 the first string cannot be reserved unless at least one of pattern 1092 of units whose names are in the second string is reserved. This is 1093 an asymmetric relation. CPU units or unit patterns in the strings 1094 are separated by commas. Pattern is one unit name or unit names 1095 separated by white-spaces. 1096 1097 For example, it is useful for description that slot1 is reserved 1098 after slot0 reservation for a VLIW processor. We could describe it 1099 by the following construction 1100 1101 (presence_set "slot1" "slot0") 1102 1103 Or slot1 is reserved only after slot0 and unit b0 reservation. In 1104 this case we could write 1105 1106 (presence_set "slot1" "slot0 b0") 1107 1108 All CPU functional units in a set should belong to the same 1109 automaton. */ 1110DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA) 1111 1112/* (final_presence_set string string) is analogous to `presence_set'. 1113 The difference between them is when checking is done. When an 1114 instruction is issued in given automaton state reflecting all 1115 current and planned unit reservations, the automaton state is 1116 changed. The first state is a source state, the second one is a 1117 result state. Checking for `presence_set' is done on the source 1118 state reservation, checking for `final_presence_set' is done on the 1119 result reservation. This construction is useful to describe a 1120 reservation which is actually two subsequent reservations. For 1121 example, if we use 1122 1123 (presence_set "slot1" "slot0") 1124 1125 the following insn will be never issued (because slot1 requires 1126 slot0 which is absent in the source state). 1127 1128 (define_reservation "insn_and_nop" "slot0 + slot1") 1129 1130 but it can be issued if we use analogous `final_presence_set'. */ 1131DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA) 1132 1133/* (absence_set string string) means that each CPU functional unit in 1134 the first string can be reserved only if each pattern of units 1135 whose names are in the second string is not reserved. This is an 1136 asymmetric relation (actually exclusion set is analogous to this 1137 one but it is symmetric). CPU units or unit patterns in the string 1138 are separated by commas. Pattern is one unit name or unit names 1139 separated by white-spaces. 1140 1141 For example, it is useful for description that slot0 cannot be 1142 reserved after slot1 or slot2 reservation for a VLIW processor. We 1143 could describe it by the following construction 1144 1145 (absence_set "slot2" "slot0, slot1") 1146 1147 Or slot2 cannot be reserved if slot0 and unit b0 are reserved or 1148 slot1 and unit b1 are reserved . In this case we could write 1149 1150 (absence_set "slot2" "slot0 b0, slot1 b1") 1151 1152 All CPU functional units in a set should to belong the same 1153 automaton. */ 1154DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA) 1155 1156/* (final_absence_set string string) is analogous to `absence_set' but 1157 checking is done on the result (state) reservation. See comments 1158 for `final_presence_set'. */ 1159DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA) 1160 1161/* (define_bypass number out_insn_names in_insn_names) names bypass 1162 with given latency (the first number) from insns given by the first 1163 string (see define_insn_reservation) into insns given by the second 1164 string. Insn names in the strings are separated by commas. The 1165 third operand is optional name of function which is additional 1166 guard for the bypass. The function will get the two insns as 1167 parameters. If the function returns zero the bypass will be 1168 ignored for this case. Additional guard is necessary to recognize 1169 complicated bypasses, e.g. when consumer is load address. If there 1170 are more one bypass with the same output and input insns, the 1171 chosen bypass is the first bypass with a guard in description whose 1172 guard function returns nonzero. If there is no such bypass, then 1173 bypass without the guard function is chosen. */ 1174DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA) 1175 1176/* (define_automaton string) describes names of automata generated and 1177 used for pipeline hazards recognition. The names are separated by 1178 comma. Actually it is possibly to generate the single automaton 1179 but unfortunately it can be very large. If we use more one 1180 automata, the summary size of the automata usually is less than the 1181 single one. The automaton name is used in define_cpu_unit and 1182 define_query_cpu_unit. All automata should have unique names. */ 1183DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA) 1184 1185/* (automata_option string) describes option for generation of 1186 automata. Currently there are the following options: 1187 1188 o "no-minimization" which makes no minimization of automata. This 1189 is only worth to do when we are debugging the description and 1190 need to look more accurately at reservations of states. 1191 1192 o "time" which means printing additional time statistics about 1193 generation of automata. 1194 1195 o "v" which means generation of file describing the result 1196 automata. The file has suffix `.dfa' and can be used for the 1197 description verification and debugging. 1198 1199 o "w" which means generation of warning instead of error for 1200 non-critical errors. 1201 1202 o "ndfa" which makes nondeterministic finite state automata. 1203 1204 o "progress" which means output of a progress bar showing how many 1205 states were generated so far for automaton being processed. */ 1206DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA) 1207 1208/* (define_reservation string string) names reservation (the first 1209 string) of cpu functional units (the 2nd string). Sometimes unit 1210 reservations for different insns contain common parts. In such 1211 case, you can describe common part and use its name (the 1st 1212 parameter) in regular expression in define_insn_reservation. All 1213 define_reservations, define_cpu_units, and define_query_cpu_units 1214 should have unique names which may not be "nothing". */ 1215DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA) 1216 1217/* (define_insn_reservation name default_latency condition regexpr) 1218 describes reservation of cpu functional units (the 3nd operand) for 1219 instruction which is selected by the condition (the 2nd parameter). 1220 The first parameter is used for output of debugging information. 1221 The reservations are described by a regular expression according 1222 the following syntax: 1223 1224 regexp = regexp "," oneof 1225 | oneof 1226 1227 oneof = oneof "|" allof 1228 | allof 1229 1230 allof = allof "+" repeat 1231 | repeat 1232 1233 repeat = element "*" number 1234 | element 1235 1236 element = cpu_function_unit_name 1237 | reservation_name 1238 | result_name 1239 | "nothing" 1240 | "(" regexp ")" 1241 1242 1. "," is used for describing start of the next cycle in 1243 reservation. 1244 1245 2. "|" is used for describing the reservation described by the 1246 first regular expression *or* the reservation described by the 1247 second regular expression *or* etc. 1248 1249 3. "+" is used for describing the reservation described by the 1250 first regular expression *and* the reservation described by the 1251 second regular expression *and* etc. 1252 1253 4. "*" is used for convenience and simply means sequence in 1254 which the regular expression are repeated NUMBER times with 1255 cycle advancing (see ","). 1256 1257 5. cpu functional unit name which means its reservation. 1258 1259 6. reservation name -- see define_reservation. 1260 1261 7. string "nothing" means no units reservation. */ 1262 1263DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA) 1264 1265/* Expressions used for insn attributes. */ 1266 1267/* Definition of an insn attribute. 1268 1st operand: name of the attribute 1269 2nd operand: comma-separated list of possible attribute values 1270 3rd operand: expression for the default value of the attribute. */ 1271DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA) 1272 1273/* Definition of an insn attribute that uses an existing enumerated type. 1274 1st operand: name of the attribute 1275 2nd operand: the name of the enumerated type 1276 3rd operand: expression for the default value of the attribute. */ 1277DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA) 1278 1279/* Marker for the name of an attribute. */ 1280DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA) 1281 1282/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and 1283 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that 1284 pattern. 1285 1286 (set_attr "name" "value") is equivalent to 1287 (set (attr "name") (const_string "value")) */ 1288DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA) 1289 1290/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to 1291 specify that attribute values are to be assigned according to the 1292 alternative matched. 1293 1294 The following three expressions are equivalent: 1295 1296 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") 1297 (eq_attrq "alternative" "2") (const_string "a2")] 1298 (const_string "a3"))) 1299 (set_attr_alternative "att" [(const_string "a1") (const_string "a2") 1300 (const_string "a3")]) 1301 (set_attr "att" "a1,a2,a3") 1302 */ 1303DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA) 1304 1305/* A conditional expression true if the value of the specified attribute of 1306 the current insn equals the specified value. The first operand is the 1307 attribute name and the second is the comparison value. */ 1308DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA) 1309 1310/* A special case of the above representing a set of alternatives. The first 1311 operand is bitmap of the set, the second one is the default value. */ 1312DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ww", RTX_EXTRA) 1313 1314/* A conditional expression which is true if the specified flag is 1315 true for the insn being scheduled in reorg. 1316 1317 genattr.c defines the following flags which can be tested by 1318 (attr_flag "foo") expressions in eligible_for_delay: forward, backward. */ 1319 1320DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA) 1321 1322/* General conditional. The first operand is a vector composed of pairs of 1323 expressions. The first element of each pair is evaluated, in turn. 1324 The value of the conditional is the second expression of the first pair 1325 whose first expression evaluates nonzero. If none of the expressions is 1326 true, the second operand will be used as the value of the conditional. */ 1327DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA) 1328 1329/* Definition of a pattern substitution meta operation on a DEFINE_EXPAND 1330 or a DEFINE_INSN. Automatically generates new instances of DEFINE_INSNs 1331 that match the substitution pattern. 1332 1333 Operand: 1334 0: The name of the substitition template. 1335 1: Input template to match to see if a substitution is applicable. 1336 2: A C expression giving an additional condition for the generated 1337 new define_expand or define_insn. 1338 3: Output tempalate to generate via substitution. 1339 1340 Within a DEFINE_SUBST template, the meaning of some RTL expressions is 1341 different from their usual interpretation: a MATCH_OPERAND matches any 1342 expression tree with matching machine mode or with VOIDmode. Likewise, 1343 MATCH_OP_DUP and MATCH_DUP match more liberally in a DEFINE_SUBST than 1344 in other RTL expressions. MATCH_OPERATOR matches all common operators 1345 but also UNSPEC, UNSPEC_VOLATILE, and MATCH_OPERATORS from the input 1346 DEFINE_EXPAND or DEFINE_INSN. */ 1347DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA) 1348 1349/* Substitution attribute to apply a DEFINE_SUBST to a pattern. 1350 1351 Operand: 1352 0: The name of the subst-attribute. 1353 1: The name of the DEFINE_SUBST to be applied for this attribute. 1354 2: String to substitute for the subst-attribute name in the pattern 1355 name, for the case that the DEFINE_SUBST is not applied (i.e. the 1356 unmodified version of the pattern). 1357 3: String to substitute for the subst-attribute name in the pattern 1358 name, for the case that the DEFINE_SUBST is applied to the patten. 1359 1360 The use of DEFINE_SUBST and DEFINE_SUBST_ATTR is explained in the 1361 GCC internals manual, under "RTL Templates Transformations". */ 1362DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA) 1363 1364#endif /* GENERATOR_FILE */ 1365 1366/* 1367Local variables: 1368mode:c 1369End: 1370*/ 1371