1 /* PR debug/44832 */
2 /* { dg-do compile } */
3 /* { dg-options "-O2 -fcompare-debug" } */
4 /* { dg-options "-O2 -fcompare-debug -fno-short-enums" {target short_enums} } */
5 /* { dg-require-effective-target int32plus } */
foo(void)6
7 struct rtx_def;
8 typedef struct rtx_def *rtx;
9 typedef const struct rtx_def *const_rtx;
10 struct rtvec_def;
11 typedef struct rtvec_def *rtvec;
12 extern int ix86_isa_flags;
13
bar(void)14 enum machine_mode
15 {
16 VOIDmode,
17 V8HImode,
18 V16QImode,
19 V4SImode,
20 V2DImode,
21 V32QImode,
22 MAX_MACHINE_MODE,
23
24 NUM_MACHINE_MODES = MAX_MACHINE_MODE
25 };
26 extern unsigned char mode_size[NUM_MACHINE_MODES];
27 extern const unsigned char mode_inner[NUM_MACHINE_MODES];
28 extern const unsigned char mode_nunits[NUM_MACHINE_MODES];
29 enum rtx_code {
30
31 CONST_INT ,
32
33 CONST_FIXED ,
34
35 CONST_DOUBLE
36
37 };
38 union rtunion_def
39 {
40 rtvec rt_rtvec;
41 };
42 typedef union rtunion_def rtunion;
43 struct rtx_def {
44
45 __extension__ enum rtx_code code: 16;
46
47 __extension__ enum machine_mode mode : 8;
48
49 union u {
50 rtunion fld[1];
51 } u;
52 };
53 struct rtvec_def {
54 rtx elem[1];
55 };
56 extern int rtx_equal_p (const_rtx, const_rtx);
57 extern rtx gen_reg_rtx (enum machine_mode);
58
59 extern void
60 ix86_expand_vector_init_concat (enum machine_mode mode,
61 rtx target, rtx *ops, int n);
62
63 static void
64 ix86_expand_vector_init_general (unsigned char mmx_ok, enum machine_mode mode,
65 rtx target, rtx vals)
66 {
67 rtx ops[32], op0, op1;
68 enum machine_mode half_mode = VOIDmode;
69 int n, i;
70
71 switch (mode)
72 {
73 case V4SImode:
74 case V2DImode:
75 n = mode_nunits[mode];
76 ix86_expand_vector_init_concat (mode, target, ops, n);
77 return;
78
79 case V32QImode:
80 goto half;
81 half:
82 {
83 typedef int eger;
84 if (mode != V4SImode)
85 ops[0] = 0;
86 }
87 n = mode_nunits[mode];
88 for (i = 0; i < n; i++)
89 ops[i] = (((((vals)->u.fld[0]).rt_rtvec))->elem[i]);
90 op0 = gen_reg_rtx (VOIDmode);
91 return;
92
93 case V16QImode:
94 if (!((ix86_isa_flags & (1 << 19)) != 0))
95 break;
96
97 case V8HImode:
98 if (!((ix86_isa_flags & (1 << 17)) != 0))
99 break;
100
101 n = mode_nunits[mode];
102 for (i = 0; i < n; i++)
103 ops[i] = (((((vals)->u.fld[0]).rt_rtvec))->elem[i]);
104 return;
105
106 default:
107 ;
108 }
109
110 {
111 int n_words;
112
113 n_words = ((unsigned short) mode_size[mode]) / 4;
114
115 if (n_words == 4)
116 ix86_expand_vector_init_general (0, V4SImode, 0, 0);
117 }
118 }
119
120
121 void
122 ix86_expand_vector_init (unsigned char mmx_ok, rtx target, rtx vals)
123 {
124 enum machine_mode mode = ((enum machine_mode) (target)->mode);
125 enum machine_mode inner_mode = ((enum machine_mode) mode_inner[mode]);
126 int n_elts = mode_nunits[mode];
127 int n_var = 0, one_var = -1;
128 unsigned char all_same = 1, all_const_zero = 1;
129 int i;
130 rtx x;
131
132 for (i = 0; i < n_elts; ++i)
133 {
134 x = (((((vals)->u.fld[0]).rt_rtvec))->elem[i]);
135 if (!((((enum rtx_code) (x)->code) == CONST_INT)
136 || ((enum rtx_code) (x)->code) == CONST_DOUBLE
137 || ((enum rtx_code) (x)->code) == CONST_FIXED))
138 n_var++, one_var = i;
139 else
140 all_const_zero = 0;
141 if (i > 0 && !rtx_equal_p (x, (((((vals)->u.fld[0]).rt_rtvec))->elem[0])))
142 all_same = 0;
143 }
144
145
146 if (n_var == 0)
147 {
148 return;
149 }
150
151 if (all_same)
152 return;
153
154 if (n_var == 1)
155 {
156 if (all_const_zero)
157 return;
158
159 }
160
161 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
162 }
163