1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */ 2 /* { dg-options "-O -msve-vector-bits=256 -mlittle-endian --save-temps" } */ 3 4 typedef char vnx16qi __attribute__((vector_size(32))); 5 typedef struct { vnx16qi a[4]; } vnx64qi; 6 7 typedef short vnx8hi __attribute__((vector_size(32))); 8 typedef struct { vnx8hi a[4]; } vnx32hi; 9 10 typedef int vnx4si __attribute__((vector_size(32))); 11 typedef struct { vnx4si a[4]; } vnx16si; 12 13 typedef long vnx2di __attribute__((vector_size(32))); 14 typedef struct { vnx2di a[4]; } vnx8di; 15 16 typedef float vnx4sf __attribute__((vector_size(32))); 17 typedef struct { vnx4sf a[4]; } vnx16sf; 18 19 typedef double vnx2df __attribute__((vector_size(32))); 20 typedef struct { vnx2df a[4]; } vnx8df; 21 22 #define TEST_TYPE(TYPE, REG1, REG2) \ 23 void \ 24 f_##TYPE (TYPE *a) \ 25 { \ 26 register TYPE x asm (#REG1) = a[0]; \ 27 asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ 28 register TYPE y asm (#REG2) = x; \ 29 asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ 30 : "=&w" (x) : "0" (x), "w" (y)); \ 31 a[1] = x; \ 32 } 33 34 TEST_TYPE (vnx64qi, z0, z4) 35 TEST_TYPE (vnx32hi, z6, z2) 36 TEST_TYPE (vnx16si, z12, z16) 37 TEST_TYPE (vnx8di, z17, z13) 38 TEST_TYPE (vnx16sf, z20, z16) 39 TEST_TYPE (vnx8df, z24, z28) 40 41 /* { dg-final { scan-assembler {\tldr\tz0, \[x0\]\n} } } */ 42 /* { dg-final { scan-assembler {\tldr\tz1, \[x0, #1, mul vl\]\n} } } */ 43 /* { dg-final { scan-assembler {\tldr\tz2, \[x0, #2, mul vl\]\n} } } */ 44 /* { dg-final { scan-assembler {\tldr\tz3, \[x0, #3, mul vl\]\n} } } */ 45 /* { dg-final { scan-assembler { test vnx64qi 1 z0\n} } } */ 46 /* { dg-final { scan-assembler {\tmov\tz4.d, z0.d\n} } } */ 47 /* { dg-final { scan-assembler {\tmov\tz5.d, z1.d\n} } } */ 48 /* { dg-final { scan-assembler {\tmov\tz6.d, z2.d\n} } } */ 49 /* { dg-final { scan-assembler {\tmov\tz7.d, z3.d\n} } } */ 50 /* { dg-final { scan-assembler { test vnx64qi 2 z0, z0, z4\n} } } */ 51 /* { dg-final { scan-assembler {\tstr\tz0, \[x0, #4, mul vl\]\n} } } */ 52 /* { dg-final { scan-assembler {\tstr\tz1, \[x0, #5, mul vl\]\n} } } */ 53 /* { dg-final { scan-assembler {\tstr\tz2, \[x0, #6, mul vl\]\n} } } */ 54 /* { dg-final { scan-assembler {\tstr\tz3, \[x0, #7, mul vl\]\n} } } */ 55 56 /* { dg-final { scan-assembler {\tldr\tz6, \[x0\]\n} } } */ 57 /* { dg-final { scan-assembler {\tldr\tz7, \[x0, #1, mul vl\]\n} } } */ 58 /* { dg-final { scan-assembler {\tldr\tz8, \[x0, #2, mul vl\]\n} } } */ 59 /* { dg-final { scan-assembler {\tldr\tz9, \[x0, #3, mul vl\]\n} } } */ 60 /* { dg-final { scan-assembler { test vnx32hi 1 z6\n} } } */ 61 /* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ 62 /* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ 63 /* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ 64 /* { dg-final { scan-assembler {\tmov\tz5.d, z9.d\n} } } */ 65 /* { dg-final { scan-assembler { test vnx32hi 2 z6, z6, z2\n} } } */ 66 /* { dg-final { scan-assembler {\tstr\tz6, \[x0, #4, mul vl\]\n} } } */ 67 /* { dg-final { scan-assembler {\tstr\tz7, \[x0, #5, mul vl\]\n} } } */ 68 /* { dg-final { scan-assembler {\tstr\tz8, \[x0, #6, mul vl\]\n} } } */ 69 /* { dg-final { scan-assembler {\tstr\tz9, \[x0, #7, mul vl\]\n} } } */ 70 71 /* { dg-final { scan-assembler {\tldr\tz12, \[x0\]\n} } } */ 72 /* { dg-final { scan-assembler {\tldr\tz13, \[x0, #1, mul vl\]\n} } } */ 73 /* { dg-final { scan-assembler {\tldr\tz14, \[x0, #2, mul vl\]\n} } } */ 74 /* { dg-final { scan-assembler {\tldr\tz15, \[x0, #3, mul vl\]\n} } } */ 75 /* { dg-final { scan-assembler { test vnx16si 1 z12\n} } } */ 76 /* { dg-final { scan-assembler {\tmov\tz16.d, z12.d\n} } } */ 77 /* { dg-final { scan-assembler {\tmov\tz17.d, z13.d\n} } } */ 78 /* { dg-final { scan-assembler {\tmov\tz18.d, z14.d\n} } } */ 79 /* { dg-final { scan-assembler {\tmov\tz19.d, z15.d\n} } } */ 80 /* { dg-final { scan-assembler { test vnx16si 2 z12, z12, z16\n} } } */ 81 /* { dg-final { scan-assembler {\tstr\tz12, \[x0, #4, mul vl\]\n} } } */ 82 /* { dg-final { scan-assembler {\tstr\tz13, \[x0, #5, mul vl\]\n} } } */ 83 /* { dg-final { scan-assembler {\tstr\tz14, \[x0, #6, mul vl\]\n} } } */ 84 /* { dg-final { scan-assembler {\tstr\tz15, \[x0, #7, mul vl\]\n} } } */ 85 86 /* { dg-final { scan-assembler {\tldr\tz17, \[x0\]\n} } } */ 87 /* { dg-final { scan-assembler {\tldr\tz18, \[x0, #1, mul vl\]\n} } } */ 88 /* { dg-final { scan-assembler {\tldr\tz19, \[x0, #2, mul vl\]\n} } } */ 89 /* { dg-final { scan-assembler {\tldr\tz20, \[x0, #3, mul vl\]\n} } } */ 90 /* { dg-final { scan-assembler { test vnx8di 1 z17\n} } } */ 91 /* { dg-final { scan-assembler {\tmov\tz13.d, z17.d\n} } } */ 92 /* { dg-final { scan-assembler {\tmov\tz14.d, z18.d\n} } } */ 93 /* { dg-final { scan-assembler {\tmov\tz15.d, z19.d\n} } } */ 94 /* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ 95 /* { dg-final { scan-assembler { test vnx8di 2 z17, z17, z13\n} } } */ 96 /* { dg-final { scan-assembler {\tstr\tz17, \[x0, #4, mul vl\]\n} } } */ 97 /* { dg-final { scan-assembler {\tstr\tz18, \[x0, #5, mul vl\]\n} } } */ 98 /* { dg-final { scan-assembler {\tstr\tz19, \[x0, #6, mul vl\]\n} } } */ 99 /* { dg-final { scan-assembler {\tstr\tz20, \[x0, #7, mul vl\]\n} } } */ 100 101 /* { dg-final { scan-assembler {\tldr\tz20, \[x0\]\n} } } */ 102 /* { dg-final { scan-assembler {\tldr\tz21, \[x0, #1, mul vl\]\n} } } */ 103 /* { dg-final { scan-assembler {\tldr\tz22, \[x0, #2, mul vl\]\n} } } */ 104 /* { dg-final { scan-assembler {\tldr\tz23, \[x0, #3, mul vl\]\n} } } */ 105 /* { dg-final { scan-assembler { test vnx16sf 1 z20\n} } } */ 106 /* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ 107 /* { dg-final { scan-assembler {\tmov\tz17.d, z21.d\n} } } */ 108 /* { dg-final { scan-assembler {\tmov\tz18.d, z22.d\n} } } */ 109 /* { dg-final { scan-assembler {\tmov\tz19.d, z23.d\n} } } */ 110 /* { dg-final { scan-assembler { test vnx16sf 2 z20, z20, z16\n} } } */ 111 /* { dg-final { scan-assembler {\tstr\tz20, \[x0, #4, mul vl\]\n} } } */ 112 /* { dg-final { scan-assembler {\tstr\tz21, \[x0, #5, mul vl\]\n} } } */ 113 /* { dg-final { scan-assembler {\tstr\tz22, \[x0, #6, mul vl\]\n} } } */ 114 /* { dg-final { scan-assembler {\tstr\tz23, \[x0, #7, mul vl\]\n} } } */ 115 116 /* { dg-final { scan-assembler {\tldr\tz24, \[x0\]\n} } } */ 117 /* { dg-final { scan-assembler {\tldr\tz25, \[x0, #1, mul vl\]\n} } } */ 118 /* { dg-final { scan-assembler {\tldr\tz26, \[x0, #2, mul vl\]\n} } } */ 119 /* { dg-final { scan-assembler {\tldr\tz27, \[x0, #3, mul vl\]\n} } } */ 120 /* { dg-final { scan-assembler { test vnx8df 1 z24\n} } } */ 121 /* { dg-final { scan-assembler {\tmov\tz28.d, z24.d\n} } } */ 122 /* { dg-final { scan-assembler {\tmov\tz29.d, z25.d\n} } } */ 123 /* { dg-final { scan-assembler {\tmov\tz30.d, z26.d\n} } } */ 124 /* { dg-final { scan-assembler {\tmov\tz31.d, z27.d\n} } } */ 125 /* { dg-final { scan-assembler { test vnx8df 2 z24, z24, z28\n} } } */ 126 /* { dg-final { scan-assembler {\tstr\tz24, \[x0, #4, mul vl\]\n} } } */ 127 /* { dg-final { scan-assembler {\tstr\tz25, \[x0, #5, mul vl\]\n} } } */ 128 /* { dg-final { scan-assembler {\tstr\tz26, \[x0, #6, mul vl\]\n} } } */ 129 /* { dg-final { scan-assembler {\tstr\tz27, \[x0, #7, mul vl\]\n} } } */ 130