1;; Code and mode itertator and attribute definitions for the ARM backend
2;; Copyright (C) 2010-2021 Free Software Foundation, Inc.
3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21
22;;----------------------------------------------------------------------------
23;; Mode iterators
24;;----------------------------------------------------------------------------
25
26;; A list of modes that are exactly 64 bits in size. This is used to expand
27;; some splits that are the same for all modes when operating on ARM
28;; registers.
29(define_mode_iterator ANY64 [DI DF V8QI V4HI V4HF V2SI V2SF])
30
31;; Additional definition of ANY64 that also includes the special V4BF mode.
32;; BFmode is allowed only on define_split between ARM registers.
33(define_mode_iterator ANY64_BF [DI DF V8QI V4HI V4BF V4HF V2SI V2SF])
34
35(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
36
37;; A list of integer modes that are up to one word long
38(define_mode_iterator QHSI [QI HI SI])
39
40;; A list of integer modes that are half and one word long
41(define_mode_iterator HSI [HI SI])
42
43;; A list of integer modes that are less than a word
44(define_mode_iterator NARROW [QI HI])
45
46;; A list of all the integer modes up to 64bit
47(define_mode_iterator QHSD [QI HI SI DI])
48
49;; A list of the 32bit and 64bit integer modes
50(define_mode_iterator SIDI [SI DI])
51
52;; A list of atomic compare and swap success return modes
53(define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")])
54
55;; A list of modes which the VFP unit can handle
56(define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")])
57
58;; Integer element sizes implemented by IWMMXT.
59(define_mode_iterator VMMX [V2SI V4HI V8QI])
60
61(define_mode_iterator VMMX2 [V4HI V2SI])
62
63;; Integer element sizes for shifts.
64(define_mode_iterator VSHFT [V4HI V2SI DI])
65
66;; Integer and float modes supported by Neon and IWMMXT.
67(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
68
69;; Integer and float modes supported by Neon, IWMMXT and MVE.
70(define_mode_iterator VNIM1 [V16QI V8HI V4SI V4SF V2DI])
71
72;; Integer and float modes supported by Neon and IWMMXT but not MVE.
73(define_mode_iterator VNINOTM1 [V2SI V4HI V8QI V2SF])
74
75;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
76(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
77
78;; Integer modes supported by Neon and IWMMXT
79(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
80
81;; Integer modes supported by Neon and IWMMXT, except V2DI
82(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
83
84;; Double-width vector modes, on which we support arithmetic (no HF!)
85(define_mode_iterator VD [V8QI V4HI V2SI V2SF])
86
87;; Double-width vector modes plus 64-bit elements for vreinterpret + vcreate.
88(define_mode_iterator VD_RE [V8QI V4HI V2SI V2SF DI])
89
90;; Double-width vector modes plus 64-bit elements.
91(define_mode_iterator VDX [V8QI V4HI V4HF V4BF V2SI V2SF DI])
92
93;; Double-width vector modes plus 64-bit elements, including V4BF.
94(define_mode_iterator VDXBF [V8QI V4HI V4HF (V4BF "TARGET_BF16_SIMD") V2SI V2SF DI])
95
96;; Double-width vector modes plus 64-bit elements, V4BF and V8BF.
97(define_mode_iterator VDXBF2 [V8QI V4HI V4HF V2SI V2SF DI (V4BF "TARGET_BF16_SIMD") (V8BF ("TARGET_BF16_SIMD"))])
98
99;; Double-width vector modes plus 64-bit elements,
100;; with V4BFmode added, suitable for moves.
101(define_mode_iterator VDXMOV [V8QI V4HI V4HF V4BF V2SI V2SF DI])
102
103;; Double-width vector modes, with V4HF - for vldN_lane and vstN_lane.
104(define_mode_iterator VD_LANE [V8QI V4HI V4HF V4BF V2SI V2SF])
105
106;; Double-width vector modes without floating-point elements.
107(define_mode_iterator VDI [V8QI V4HI V2SI])
108
109;; Quad-width vector modes supporting arithmetic (no HF!).
110(define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
111
112;; Quad-width vector modes, including V8HF.
113(define_mode_iterator VQ2 [V16QI V8HI V8HF V4SI V4SF])
114
115;; Quad-width vector modes, including V8BF.
116(define_mode_iterator VQ2BF [V16QI V8HI V8HF (V8BF "TARGET_BF16_SIMD") V4SI V4SF])
117
118;; Quad-width vector modes with 16- or 32-bit elements
119(define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF (V8BF "TARGET_BF16_SIMD")])
120
121;; Quad-width vector modes plus 64-bit elements.
122(define_mode_iterator VQX [V16QI V8HI V8HF V8BF V4SI V4SF V2DI])
123
124;; Quad-width vector modes plus 64-bit elements.
125(define_mode_iterator VQX_NOBF [V16QI V8HI V8HF V4SI V4SF V2DI])
126
127;; Quad-width vector modes plus 64-bit elements and V8BF.
128(define_mode_iterator VQXBF [V16QI V8HI V8HF (V8BF "TARGET_BF16_SIMD") V4SI V4SF V2DI])
129
130;; Quad-width vector modes without floating-point elements.
131(define_mode_iterator VQI [V16QI V8HI V4SI])
132
133;; Quad-width vector modes, with TImode and V8BFmode added, suitable for moves.
134(define_mode_iterator VQXMOV [V16QI V8HI V8HF V8BF V4SI V4SF V2DI TI])
135
136;; Opaque structure types wider than TImode.
137(define_mode_iterator VSTRUCT [(EI "!TARGET_HAVE_MVE") OI
138			       (CI "!TARGET_HAVE_MVE") XI])
139
140;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
141(define_mode_iterator VTAB [TI EI OI])
142
143;; Widenable modes.
144(define_mode_iterator VW [V8QI V4HI V2SI])
145
146;; Narrowable modes.
147(define_mode_iterator VN [V8HI V4SI V2DI])
148
149;; All supported vector modes (except singleton DImode).
150(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI])
151
152;; All supported floating-point vector modes (except V2DF).
153(define_mode_iterator VF [(V4HF "TARGET_NEON_FP16INST")
154			   (V8HF "TARGET_NEON_FP16INST") V2SF V4SF])
155
156;; Double vector modes.
157(define_mode_iterator VDF [V2SF V4HF])
158
159;; Quad vector Float modes with half/single elements.
160(define_mode_iterator VQ_HSF [V8HF V4SF])
161
162
163;; All supported vector modes (except those with 64-bit integer elements).
164(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
165
166;; All supported vector modes including 16-bit float modes.
167(define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF
168			     V8HF V4HF])
169
170;; Supported integer vector modes (not 64 bit elements).
171(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
172
173;; Supported integer vector modes (not singleton DI)
174(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
175
176;; Vector modes, including 64-bit integer elements.
177(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI
178			    V4HF V8HF V4BF V8BF V2SF V4SF DI V2DI])
179
180;; Vector modes including 64-bit integer elements, but no floats.
181(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
182
183;; Vector modes for H, S and D types.
184(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
185
186;; Vector modes for float->int conversions.
187(define_mode_iterator VCVTF [V2SF V4SF])
188
189;; Vector modes form int->float conversions.
190(define_mode_iterator VCVTI [V2SI V4SI])
191
192;; Vector modes for int->half conversions.
193(define_mode_iterator VCVTHI [V4HI V8HI])
194
195;; Vector modes for doubleword multiply-accumulate, etc. insns.
196(define_mode_iterator VMD [V4HI V2SI V2SF])
197
198;; Vector modes for quadword multiply-accumulate, etc. insns.
199(define_mode_iterator VMQ [V8HI V4SI V4SF])
200
201;; Above modes combined.
202(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
203
204;; As VMD, but integer modes only.
205(define_mode_iterator VMDI [V4HI V2SI])
206
207;; As VMQ, but integer modes only.
208(define_mode_iterator VMQI [V8HI V4SI])
209
210;; Above modes combined.
211(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
212
213;; Modes with 8-bit and 16-bit elements.
214(define_mode_iterator VX [V8QI V4HI V16QI V8HI])
215
216;; Modes with 8-bit elements.
217(define_mode_iterator VE [V8QI V16QI])
218
219;; V2DI only (for use with @ patterns).
220(define_mode_iterator V2DI_ONLY [V2DI])
221
222;; Modes with 64-bit elements only.
223(define_mode_iterator V64 [DI V2DI])
224
225;; Modes with 32-bit elements only.
226(define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
227
228;; Modes with 8-bit, 16-bit and 32-bit elements.
229(define_mode_iterator VU [V16QI V8HI V4SI])
230
231;; Vector modes for 16-bit floating-point support.
232(define_mode_iterator VH [V8HF V4HF])
233
234;; Modes with 16-bit elements only.
235(define_mode_iterator V16 [V4HI V4HF V8HI V8HF])
236
237;; 16-bit floating-point vector modes suitable for moving (includes BFmode).
238(define_mode_iterator VHFBF [V8HF V4HF V4BF V8BF])
239
240;; 16-bit floating-point vector modes suitable for moving (includes BFmode,
241;; without V8HF ).
242(define_mode_iterator VHFBF_split [V4HF V4BF V8BF])
243
244;; 16-bit floating-point scalar modes suitable for moving (includes BFmode).
245(define_mode_iterator HFBF [HF BF])
246
247;; Iterators used for fixed-point support.
248(define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])
249
250(define_mode_iterator ADDSUB [V4QQ V2HQ V2HA])
251
252(define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA])
253
254(define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA])
255
256(define_mode_iterator QMUL [HQ HA])
257
258;; Modes for polynomial or float values.
259(define_mode_iterator VPF [V8QI V16QI V2SF V4SF])
260
261;; Modes for BF16 convert instructions.
262(define_mode_iterator VBFCVT [V4BF V8BF])
263(define_mode_iterator VBFCVTM [V2SI SF])
264
265;; MVE mode iterator.
266(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
267(define_mode_iterator MVE_vecs [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
268(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
269(define_mode_iterator MVE_0 [V8HF V4SF])
270(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
271(define_mode_iterator MVE_3 [V16QI V8HI])
272(define_mode_iterator MVE_2 [V16QI V8HI V4SI])
273(define_mode_iterator MVE_5 [V8HI V4SI])
274(define_mode_iterator MVE_6 [V8HI V4SI])
275
276;;----------------------------------------------------------------------------
277;; Code iterators
278;;----------------------------------------------------------------------------
279
280;; The signed gt, ge comparisons
281(define_code_iterator GTGE [gt ge])
282
283;; The signed gt, ge, lt, le comparisons
284(define_code_iterator GLTE [gt ge lt le])
285
286;; The unsigned gt, ge comparisons
287(define_code_iterator GTUGEU [gtu geu])
288
289;; Comparisons for vc<cmp>
290(define_code_iterator COMPARISONS [eq gt ge le lt])
291;; Comparisons for MVE
292(define_code_iterator MVE_COMPARISONS [eq ge geu gt gtu le lt ne])
293(define_code_iterator MVE_FP_COMPARISONS [eq ge gt le lt ne])
294
295;; A list of ...
296(define_code_iterator IOR_XOR [ior xor])
297
298(define_code_iterator LOGICAL [and ior xor])
299
300;; Operations on two halves of a quadword vector.
301(define_code_iterator VQH_OPS [plus smin smax umin umax])
302
303;; Operations on two halves of a quadword vector,
304;; without unsigned variants (for use with *SFmode pattern).
305(define_code_iterator VQHS_OPS [plus smin smax])
306
307;; A list of widening operators
308(define_code_iterator SE [sign_extend zero_extend])
309
310;; Right shifts
311(define_code_iterator RSHIFTS [ashiftrt lshiftrt])
312
313;; Iterator for integer conversions
314(define_code_iterator FIXUORS [fix unsigned_fix])
315
316;; Binary operators whose second operand can be shifted.
317(define_code_iterator SHIFTABLE_OPS [plus minus ior xor and])
318
319;; Operations on the sign of a number.
320(define_code_iterator ABSNEG [abs neg])
321
322;; The PLUS and MINUS operators.
323(define_code_iterator PLUSMINUS [plus minus])
324
325;; Conversions.
326(define_code_iterator FCVT [unsigned_float float])
327
328;; Saturating addition, subtraction
329(define_code_iterator SSPLUSMINUS [ss_plus ss_minus])
330
331;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
332;; a stack pointer operand.  The minus operation is a candidate for an rsub
333;; and hence only plus is supported.
334(define_code_attr t2_binop0
335  [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")])
336
337;; The instruction to use when a SHIFTABLE_OPS has a shift operation as
338;; its first operand.
339(define_code_attr arith_shift_insn
340  [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")])
341
342(define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
343                          (gtu "gt") (geu "ge")])
344
345(define_code_attr mve_cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
346                              (gtu "hi") (geu "cs") (ne "ne")])
347
348(define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")])
349
350(define_code_attr mve_cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")
351                                (gtu "u") (geu "u") (ne "i")])
352
353(define_code_attr vfml_op [(plus "a") (minus "s")])
354
355(define_code_attr ss_op [(ss_plus "qadd") (ss_minus "qsub")])
356
357;;----------------------------------------------------------------------------
358;; Int iterators
359;;----------------------------------------------------------------------------
360
361(define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
362                            UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
363
364(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE
365				UNSPEC_VCLT UNSPEC_VCLE])
366
367(define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT
368				  UNSPEC_VCALE UNSPEC_VCALT])
369
370(define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA])
371
372(define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM
373                              UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN])
374
375(define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA])
376
377(define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U])
378
379(define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U])
380
381(define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U
382			    UNSPEC_VHADD_S UNSPEC_VHADD_U])
383
384(define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U])
385
386(define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN])
387
388(define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U])
389
390(define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE])
391
392(define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U])
393
394(define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE])
395
396(define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH])
397
398(define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE])
399
400(define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P])
401
402(define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE])
403
404(define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U])
405
406(define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U])
407
408(define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U])
409
410(define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U])
411
412(define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN])
413
414(define_int_iterator VABAL [UNSPEC_VABAL_S UNSPEC_VABAL_U])
415
416(define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U])
417
418(define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U])
419
420(define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U
421			      UNSPEC_VMIN UNSPEC_VMIN_U])
422
423(define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN])
424
425(define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM])
426
427(define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U])
428
429(define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U])
430
431(define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U
432			       UNSPEC_VPMIN UNSPEC_VPMIN_U])
433
434(define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN])
435
436(define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U])
437
438(define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N])
439
440(define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N])
441
442(define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N])
443
444(define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U
445				 UNSPEC_VCVTM_S UNSPEC_VCVTM_U
446				 UNSPEC_VCVTN_S UNSPEC_VCVTN_U
447				 UNSPEC_VCVTP_S UNSPEC_VCVTP_U])
448
449(define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U])
450
451;; Operators for FP16 instructions.
452(define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA
453			       UNSPEC_VRNDM UNSPEC_VRNDN
454			       UNSPEC_VRNDP UNSPEC_VRNDX])
455
456(define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U])
457
458(define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U])
459
460(define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U
461			   UNSPEC_VRSHL_S UNSPEC_VRSHL_U])
462
463(define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U
464			    UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U])
465
466(define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N
467			     UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N])
468
469(define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N])
470
471(define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N
472			       UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N])
473
474(define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N])
475
476(define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N])
477
478(define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N])
479
480(define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N
481			     UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N])
482
483(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
484                          UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW])
485
486(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
487
488(define_int_iterator CRYPTO_AES [UNSPEC_AESD UNSPEC_AESE])
489
490(define_int_iterator CRYPTO_BINARY [UNSPEC_SHA1SU1 UNSPEC_SHA256SU0])
491
492(define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H
493                                     UNSPEC_SHA256H2 UNSPEC_SHA256SU1])
494
495(define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M
496                                       UNSPEC_SHA1P])
497
498(define_int_iterator USXTB16 [UNSPEC_SXTB16 UNSPEC_UXTB16])
499(define_int_iterator SIMD32_NOGE_BINOP
500				[UNSPEC_QADD8 UNSPEC_QSUB8 UNSPEC_SHADD8
501				 UNSPEC_SHSUB8 UNSPEC_UHADD8 UNSPEC_UHSUB8
502				 UNSPEC_UQADD8 UNSPEC_UQSUB8
503				 UNSPEC_QADD16 UNSPEC_QASX UNSPEC_QSAX
504				 UNSPEC_QSUB16 UNSPEC_SHADD16 UNSPEC_SHASX
505				 UNSPEC_SHSAX UNSPEC_SHSUB16 UNSPEC_UHADD16
506				 UNSPEC_UHASX UNSPEC_UHSAX UNSPEC_UHSUB16
507				 UNSPEC_UQADD16 UNSPEC_UQASX UNSPEC_UQSAX
508				 UNSPEC_UQSUB16 UNSPEC_SMUSD UNSPEC_SMUSDX
509				 UNSPEC_SXTAB16 UNSPEC_UXTAB16 UNSPEC_USAD8])
510
511(define_int_iterator SIMD32_DIMODE [UNSPEC_SMLALD UNSPEC_SMLALDX
512				    UNSPEC_SMLSLD UNSPEC_SMLSLDX])
513
514(define_int_iterator SMLAWBT [UNSPEC_SMLAWB UNSPEC_SMLAWT])
515
516(define_int_iterator SIMD32_GE [UNSPEC_SADD8 UNSPEC_SSUB8 UNSPEC_UADD8
517				UNSPEC_USUB8 UNSPEC_SADD16 UNSPEC_SASX
518				UNSPEC_SSAX UNSPEC_SSUB16 UNSPEC_UADD16
519				UNSPEC_UASX UNSPEC_USAX UNSPEC_USUB16])
520
521(define_int_iterator SIMD32_TERNOP_Q [UNSPEC_SMLAD UNSPEC_SMLADX UNSPEC_SMLSD
522				      UNSPEC_SMLSDX])
523
524(define_int_iterator SIMD32_BINOP_Q [UNSPEC_SMUAD UNSPEC_SMUADX])
525
526(define_int_iterator USSAT16 [UNSPEC_SSAT16 UNSPEC_USAT16])
527
528(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
529
530(define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE])
531
532(define_int_iterator DOTPROD [UNSPEC_DOT_S UNSPEC_DOT_U])
533
534(define_int_iterator DOTPROD_I8MM [UNSPEC_DOT_US UNSPEC_DOT_SU])
535
536(define_int_iterator VFMLHALVES [UNSPEC_VFML_LO UNSPEC_VFML_HI])
537
538(define_int_iterator VCADD [UNSPEC_VCADD90 UNSPEC_VCADD270])
539(define_int_iterator VCMLA [UNSPEC_VCMLA UNSPEC_VCMLA90 UNSPEC_VCMLA180 UNSPEC_VCMLA270])
540
541(define_int_iterator MATMUL [UNSPEC_MATMUL_S UNSPEC_MATMUL_U UNSPEC_MATMUL_US])
542
543(define_int_iterator BF_MA [UNSPEC_BFMAB UNSPEC_BFMAT])
544
545(define_int_iterator CDE_VCX [UNSPEC_VCDE UNSPEC_VCDEA])
546
547;;----------------------------------------------------------------------------
548;; Mode attributes
549;;----------------------------------------------------------------------------
550
551;; Determine name of atomic compare and swap from success result mode.  This
552;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM.
553(define_mode_attr arch [(CC_Z "32") (SI "t1")])
554
555;; Determine element size suffix from vector mode.
556(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
557
558;; vtbl<n> suffix for NEON vector modes.
559(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
560
561;; fp16 or bf16 marker for 16-bit float modes.
562(define_mode_attr fporbf [(HF "fp16") (BF "bf16")])
563
564;; (Opposite) mode to convert to/from for NEON mode conversions.
565(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
566               (V4SI "V4SF") (V4SF "V4SI")])
567
568;; As above but in lower case.
569(define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
570                           (V4SI "v4sf") (V4SF "v4si")])
571
572;; (Opposite) mode to convert to/from for vector-half mode conversions.
573(define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI")
574			    (V8HI "V8HF") (V8HF "V8HI")])
575(define_mode_attr VH_cvtto [(V4HI "v4hf") (V4HF "v4hi")
576			    (V8HI "v8hf") (V8HF "v8hi")])
577
578;; Define element mode for each vector mode.
579(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
580			  (V4HI "HI") (V8HI "HI")
581			  (V4HF "HF") (V8HF "HF")
582			  (V4BF "BF") (V8BF "BF")
583			  (V2SI "SI") (V4SI "SI")
584			  (V2SF "SF") (V4SF "SF")
585			  (DI   "DI") (V2DI "DI")
586			  (V2DF "DF")])
587
588;; As above but in lower case.
589(define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi")
590			    (V4HI "hi") (V8HI "hi")
591			    (V4HF "hf") (V8HF "hf")
592			    (V4BF "bf") (V8BF "bf")
593			    (V2SI "si") (V4SI "si")
594			    (V2SF "sf") (V4SF "sf")
595			    (DI "di")   (V2DI "di")])
596
597;; Element modes for vector extraction, padded up to register size.
598
599(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
600             (V4HI "SI") (V8HI "SI")
601             (V2SI "SI") (V4SI "SI")
602             (V2SF "SF") (V4SF "SF")
603             (DI "DI") (V2DI "DI")])
604
605;; Mode of pair of elements for each vector mode, to define transfer
606;; size for structure lane/dup loads and stores.
607(define_mode_attr V_two_elem [(V8QI "HI")   (V16QI "HI")
608                              (V4HI "SI")   (V8HI "SI")
609                              (V4HF "SF")   (V8HF "SF")
610                              (V4BF "BF")   (V8BF "BF")
611                              (V2SI "V2SI") (V4SI "V2SI")
612                              (V2SF "V2SF") (V4SF "V2SF")
613                              (DI "V2DI")   (V2DI "V2DI")])
614
615;; Mode mapping for VFM[A,S]L instructions.
616(define_mode_attr VFML [(V2SF "V4HF") (V4SF "V8HF")])
617
618;; Mode mapping for VFM[A,S]L instructions for the vec_select result.
619(define_mode_attr VFMLSEL [(V2SF "V2HF") (V4SF "V4HF")])
620
621;; Mode mapping for VFM[A,S]L instructions for some awkward lane-wise forms.
622(define_mode_attr VFMLSEL2 [(V2SF "V8HF") (V4SF "V4HF")])
623
624;; Same as the above, but lowercase.
625(define_mode_attr vfmlsel2 [(V2SF "v8hf") (V4SF "v4hf")])
626
627;; Similar, for three elements.
628(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
629                                (V4HI "BLK") (V8HI "BLK")
630                                (V4HF "BLK") (V8HF "BLK")
631                                (V4BF "BLK") (V8BF "BLK")
632                                (V2SI "BLK") (V4SI "BLK")
633                                (V2SF "BLK") (V4SF "BLK")
634                                (DI "EI")    (V2DI "EI")])
635
636;; Similar, for four elements.
637(define_mode_attr V_four_elem [(V8QI "SI")   (V16QI "SI")
638                               (V4HI "V4HI") (V8HI "V4HI")
639                               (V4HF "V4HF") (V8HF "V4HF")
640                               (V4BF "V4BF") (V8BF "V4BF")
641                               (V2SI "V4SI") (V4SI "V4SI")
642                               (V2SF "V4SF") (V4SF "V4SF")
643                               (DI "OI")     (V2DI "OI")])
644
645;; Register width from element mode
646(define_mode_attr V_reg [(V8QI "P") (V16QI "q")
647			 (V4HI "P") (V8HI  "q")
648			 (V4HF "P") (V8HF  "q")
649			 (V4BF "P") (V8BF  "q")
650			 (V2SI "P") (V4SI  "q")
651			 (V2SF "P") (V4SF  "q")
652			 (DI   "P") (V2DI  "q")
653			 (V2HF "") (SF   "") (SI "")
654			 (DF    "P") (HF   "")])
655
656;; Output template to select the high VFP register of a mult-register value.
657(define_mode_attr V_hi [(V2SF "p") (V4SF  "f")])
658
659;; Output template to select the low VFP register of a mult-register value.
660(define_mode_attr V_lo [(V2SF "") (V4SF  "e")])
661
662;; Helper attribute for printing output templates for awkward forms of
663;; vfmlal/vfmlsl intrinsics.
664(define_mode_attr V_lane_reg [(V2SF "") (V4SF  "P")])
665
666;; Wider modes with the same number of elements.
667(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
668
669;; Narrower modes with the same number of elements.
670(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
671
672;; Narrower modes with double the number of elements.
673(define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
674				 (V4HI "V8QI") (V2SI "V4HI")  (DI "V2SI")])
675
676;; Modes with half the number of equal-sized elements.
677(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
678			  (V8HF "V4HF") (V4SI  "V2SI")
679			  (V4SF "V2SF") (V2DF "DF")
680			  (V2DI "DI") (V4HF "HF")
681			  (V4BF "BF") (V8BF  "V4BF")])
682
683;; Same, but lower-case.
684(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
685              (V4SI  "v2si") (V4SF "v2sf")
686                          (V2DI "di")])
687
688;; Modes with twice the number of equal-sized elements.
689(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
690			    (V2SI "V4SI") (V4HF "V8HF")
691			    (V2SF "V4SF") (DF "V2DF")
692			    (DI "V2DI")   (V4BF "V8BF")])
693
694;; Same, but lower-case.
695(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
696                (V2SI "v4si") (V2SF "v4sf")
697                            (DI "v2di")])
698
699;; Modes with double-width elements.
700(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
701                  (V4HI "V2SI") (V8HI "V4SI")
702                  (V2SI "DI")   (V4SI "V2DI")])
703
704;; Double-sized modes with the same element size.
705;; Used for neon_vdup_lane, where the second operand is double-sized
706;; even when the first one is quad.
707(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
708					(V4SI "V2SI") (V4SF "V2SF")
709					(V8QI "V8QI") (V4HI "V4HI")
710					(V2SI "V2SI") (V2SF "V2SF")
711					(V8BF "V4BF") (V4BF "V4BF")
712					(V8HF "V4HF") (V4HF "V4HF")])
713
714;; Mode of result of comparison operations (and bit-select operand 1).
715(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
716				(V4HI "V4HI") (V8HI  "V8HI")
717                                (V2SI "V2SI") (V4SI  "V4SI")
718				(V4HF "V4HI") (V8HF  "V8HI")
719				(V4BF "V4HI") (V8BF  "V8HI")
720                                (V2SF "V2SI") (V4SF  "V4SI")
721                                (DI   "DI")   (V2DI  "V2DI")])
722
723(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
724				(V4HI "v4hi") (V8HI  "v8hi")
725				(V2SI "v2si") (V4SI  "v4si")
726				(V4HF "v4hi") (V8HF  "v8hi")
727				(DI   "di")   (V2DI  "v2di")
728				(V2SF "v2si") (V4SF  "v4si")])
729
730;; Get element type from double-width mode, for operations where we
731;; don't care about signedness.
732(define_mode_attr V_if_elem [(V8QI "i8")  (V16QI "i8")
733			     (V4HI "i16") (V8HI  "i16")
734			     (V2SI "i32") (V4SI  "i32")
735			     (DI   "i64") (V2DI  "i64")
736			     (V2SF "f32") (V4SF  "f32")
737			     (SF   "f32") (DF    "f64")
738			     (HF   "f16") (V4HF  "f16")
739			     (V8HF "f16")])
740
741;; Same, but for operations which work on signed values.
742(define_mode_attr V_s_elem [(V8QI "s8")  (V16QI "s8")
743			    (V4HI "s16") (V8HI  "s16")
744			    (V2SI "s32") (V4SI  "s32")
745			    (DI   "s64") (V2DI  "s64")
746			    (V2SF "f32") (V4SF  "f32")
747			    (HF   "f16") (V4HF  "f16")
748			    (V8HF "f16")])
749
750;; Same, but for operations which work on unsigned values.
751(define_mode_attr V_u_elem [(V8QI "u8")  (V16QI "u8")
752                (V4HI "u16") (V8HI  "u16")
753                            (V2SI "u32") (V4SI  "u32")
754                            (DI   "u64") (V2DI  "u64")
755                            (V2SF "f32") (V4SF  "f32")])
756
757;; Element types for extraction of unsigned scalars.
758(define_mode_attr V_uf_sclr [(V8QI "u8")  (V16QI "u8")
759                 (V4HI "u16") (V8HI "u16")
760                             (V2SI "32") (V4SI "32")
761                             (V4HF "u16") (V8HF "u16")
762                             (V4BF "u16") (V8BF "u16")
763                             (V2SF "32") (V4SF "32")])
764
765(define_mode_attr V_sz_elem [(V8QI "8")  (V16QI "8")
766			     (V4HI "16") (V8HI  "16")
767			     (V2SI "32") (V4SI  "32")
768			     (DI   "64") (V2DI  "64")
769			     (V4HF "16") (V8HF "16")
770			     (V4BF "16") (V8BF "16")
771			     (V2SF "32") (V4SF  "32")])
772
773(define_mode_attr V_elem_ch [(V8QI "b")  (V16QI "b")
774			     (V4HI "h") (V8HI  "h")
775			     (V2SI "s") (V4SI  "s")
776			     (DI   "d") (V2DI  "d")
777			     (V2SF "s") (V4SF  "s")
778			     (V2SF "s") (V4SF  "s")])
779
780(define_mode_attr VH_elem_ch [(V4HI "s") (V8HI  "s")
781			      (V4HF "s") (V8HF  "s")
782			      (HF "s")])
783
784;; Element sizes for duplicating ARM registers to all elements of a vector.
785(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
786
787;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
788(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
789              (V4HI "TI") (V8HI  "OI")
790                          (V2SI "TI") (V4SI  "OI")
791                          (V2SF "TI") (V4SF  "OI")
792                          (DI   "TI") (V2DI  "OI")])
793
794;; Same, but lower-case.
795(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
796              (V4HI "ti") (V8HI  "oi")
797                          (V2SI "ti") (V4SI  "oi")
798                          (V2SF "ti") (V4SF  "oi")
799                          (DI   "ti") (V2DI  "oi")])
800
801;; Extra suffix on some 64-bit insn names (to avoid collision with standard
802;; names which we don't want to define).
803(define_mode_attr V_suf64 [(V8QI "") (V16QI "")
804                           (V4HI "") (V8HI "")
805                           (V2SI "") (V4SI "")
806                           (V2SF "") (V4SF "")
807                           (DI "_neon") (V2DI "")])
808
809;; To select the low 64 bits of a vector.
810(define_mode_attr V_bf_low [(V4BF "P") (V8BF "e")])
811
812;; To generate intermediate modes for BF16 scalar convert.
813(define_mode_attr V_bf_cvt_m [(V2SI "BF") (SF "V2SI")])
814
815
816;; Scalars to be presented to scalar multiplication instructions
817;; must satisfy the following constraints.
818;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
819;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
820
821;; This mode attribute is used to obtain the correct register constraints.
822
823(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
824					 (V8HI "x") (V4SI "t") (V4SF "t")
825					 (V8HF "x") (V4HF "x")])
826
827;; Predicates used for setting type for neon instructions
828
829(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
830				 (V4HI "false") (V8HI "false")
831				 (V2SI "false") (V4SI "false")
832				 (V4HF "true") (V8HF "true")
833				 (V2SF "true") (V4SF "true")
834				 (DI "false") (V2DI "false")])
835
836(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
837				   (V4HI "true") (V8HI "true")
838				   (V2SI "false") (V4SI "false")
839				   (V2SF "false") (V4SF "false")
840				   (DI "false") (V2DI "false")])
841
842(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
843			    (V4HI "true") (V8HI  "false")
844			    (V2SI "true") (V4SI  "false")
845			    (V2SF "true") (V4SF  "false")
846			    (DI   "true") (V2DI  "false")
847			    (V4BF "true") (V8BF  "false")
848			    (V4HF "true") (V8HF  "false")])
849
850(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
851				 (V4HF "4") (V8HF "8")
852				 (V4BF "4") (V8BF "8")
853                                 (V4HI "4") (V8HI "8")
854                                 (V2SI "2") (V4SI "4")
855                                 (V2SF "2") (V4SF "4")
856                                 (DI "1")   (V2DI "2")
857                                 (DF "1")   (V2DF "2")])
858
859;; Same as V_widen, but lower-case.
860(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
861
862;; Widen. Result is half the number of elements, but widened to double-width.
863(define_mode_attr V_unpack   [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
864
865;; Conditions to be used in extend<mode>di patterns.
866(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
867(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
868				      (QI "&& arm_arch6")])
869(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
870				   (HI "nonimmediate_operand")
871				   (QI "nonimmediate_operand")])
872(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
873				   (HI "nonimmediate_operand")
874				   (QI "arm_reg_or_extendqisi_mem_op")])
875(define_mode_attr qhs_extenddi_cstr [(SI "0,r,r") (HI "0,rm,rm") (QI "0,rUq,rm")])
876(define_mode_attr qhs_zextenddi_cstr [(SI "0,r") (HI "0,rm") (QI "0,rm")])
877
878;; Mode attributes used for fixed-point support.
879(define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")
880			       (V2UHA "16") (UHA "16")
881			       (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16")
882			       (V2HA "16") (HA "16") (SQ "") (SA "")])
883
884(define_mode_attr qaddsub_clob_q [(V4UQQ "0") (V2UHQ "0") (UQQ "0") (UHQ "0")
885			       (V2UHA "0") (UHA "0")
886			       (V4QQ "0") (V2HQ "0") (QQ "0") (HQ "0")
887			       (V2HA "0") (HA "0") (SQ "ARM_Q_BIT_READ")
888			       (SA "ARM_Q_BIT_READ")])
889
890;; Mode attribute for vshll.
891(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
892
893;; Mode attributes used for VFP support.
894(define_mode_attr F_constraint [(SF "t") (DF "w")])
895(define_mode_attr vfp_type [(SF "s") (DF "d")])
896(define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")])
897(define_mode_attr VF_constraint [(V4HF "t") (V8HF "t") (V2SF "t") (V4SF "w")])
898
899;; Mode attribute used to build the "type" attribute.
900(define_mode_attr q [(V8QI "") (V16QI "_q")
901		     (V4HI "") (V8HI "_q")
902		     (V2SI "") (V4SI "_q")
903		     (V4HF "") (V8HF "_q")
904		     (V2SF "") (V4SF "_q")
905		     (V4HF "") (V8HF "_q")
906		     (V4BF "") (V8BF "_q")
907		     (DI "")   (V2DI "_q")
908		     (DF "")   (V2DF "_q")
909		     (HF "")])
910
911(define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")])
912
913(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
914(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
915
916(define_mode_attr VSF2BF [(V2SF "V4BF") (V4SF "V8BF")])
917
918(define_mode_attr cde_suffix [(SI "") (DI "d")])
919(define_mode_attr cde_dest [(SI "%0") (DI "%0, %H0")])
920
921;;MVE mode attribute.
922(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
923			    (V4SF "V4SI")])
924(define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
925
926(define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")])
927(define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
928(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")
929				    (V8HF "Rd") (V4SF "Rf")])
930(define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
931
932(define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15")
933				   (V4SI "mve_imm_31")])
934(define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
935(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
936			     (V4SI "mve_imm_32")
937			     (V8HF "mve_imm_16") (V4SF "mve_imm_32")])
938(define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
939
940(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")])
941(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
942
943(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI  "h") (V4SI "w") (V8HF "h")
944			      (V4SF "w")])
945(define_mode_attr V_extr_elem [(V16QI "u8") (V8HI "u16") (V4SI "32")
946			       (V8HF "u16") (V4SF "32")])
947(define_mode_attr earlyclobber_32 [(V16QI "=w") (V8HI "=w") (V4SI "=&w")
948						(V8HF "=w") (V4SF "=&w")])
949
950;;----------------------------------------------------------------------------
951;; Code attributes
952;;----------------------------------------------------------------------------
953
954;; Determine the mode of a 'wide compare', ie where the carry flag is
955;; propagated into the comparison.
956(define_code_attr CC_EXTEND [(sign_extend "CC_NV") (zero_extend "CC_B")])
957
958;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
959(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
960                (umin "vmin") (umax "vmax")])
961
962;; Type attributes for vqh_ops and vqhs_ops iterators.
963(define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax")
964                (umin "minmax") (umax "minmax")])
965
966;; Signs of above, where relevant.
967(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
968                (umax "u")])
969
970;; Map rtl operator codes to optab names
971(define_code_attr optab
972 [(and "and")
973  (ior "ior")
974  (xor "xor")])
975
976;; Assembler mnemonics for signedness of widening operations.
977(define_code_attr US [(sign_extend "s") (zero_extend "u")])
978(define_code_attr Us [(sign_extend "") (zero_extend "u")])
979
980;; Signedness suffix for float->fixed conversions.  Empty for signed
981;; conversion.
982(define_code_attr su_optab [(fix "") (unsigned_fix "u")])
983
984;; Sign prefix to use in instruction type suffixes, i.e. s32, u32.
985(define_code_attr su [(fix "s") (unsigned_fix "u")])
986
987;; Right shifts
988(define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
989(define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
990
991;; String reprentations of operations on the sign of a number.
992(define_code_attr absneg_str [(abs "abs") (neg "neg")])
993
994;; Conversions.
995(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
996
997(define_code_attr float_sup [(unsigned_float "u") (float "s")])
998
999(define_code_attr float_SUP [(unsigned_float "U") (float "S")])
1000
1001;;----------------------------------------------------------------------------
1002;; Int attributes
1003;;----------------------------------------------------------------------------
1004
1005;; Mapping between vector UNSPEC operations and the signed ('s'),
1006;; unsigned ('u'), poly ('p') or float ('f') nature of their data type.
1007(define_int_attr sup [
1008  (UNSPEC_SXTB16 "s") (UNSPEC_UXTB16 "u")
1009  (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u")
1010  (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u")
1011  (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u")
1012  (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u")
1013  (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u")
1014  (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u")
1015  (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u")
1016  (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u")
1017  (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u")
1018  (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p")
1019  (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u")
1020  (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u")
1021  (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u")
1022  (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u")
1023  (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u")
1024  (UNSPEC_VABAL_S "s") (UNSPEC_VABAL_U "u")
1025  (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u")
1026  (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u")
1027  (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u")
1028  (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u")
1029  (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u")
1030  (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u")
1031  (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u")
1032  (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u")
1033  (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u")
1034  (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u")
1035  (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u")
1036  (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u")
1037  (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u")
1038  (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u")
1039  (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u")
1040  (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u")
1041  (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u")
1042  (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u")
1043  (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u")
1044  (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u")
1045  (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u")
1046  (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u")
1047  (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u")
1048  (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u")
1049  (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u")
1050  (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u")
1051  (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u")
1052  (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u")
1053  (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u")
1054  (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u")
1055  (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u")
1056  (UNSPEC_DOT_S "s") (UNSPEC_DOT_U "u")
1057  (UNSPEC_DOT_US "us") (UNSPEC_DOT_SU "su")
1058  (UNSPEC_SSAT16 "s") (UNSPEC_USAT16 "u")
1059  (UNSPEC_MATMUL_S "s") (UNSPEC_MATMUL_U "u") (UNSPEC_MATMUL_US "us")
1060])
1061
1062(define_int_attr vfml_half
1063 [(UNSPEC_VFML_HI "high") (UNSPEC_VFML_LO "low")])
1064
1065(define_int_attr vfml_half_selector
1066 [(UNSPEC_VFML_HI "true") (UNSPEC_VFML_LO "false")])
1067
1068(define_int_attr vcvth_op
1069 [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a")
1070  (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m")
1071  (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n")
1072  (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")])
1073
1074(define_int_attr fp16_rnd_str
1075  [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda")
1076   (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn")
1077   (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")])
1078
1079(define_int_attr fp16_rnd_insn
1080  [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta")
1081   (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn")
1082   (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")])
1083
1084(define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt")
1085			      (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le")
1086			      (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge")
1087			      (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le")
1088			      (UNSPEC_VCALT "lt")])
1089
1090(define_int_attr r [
1091  (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r")
1092  (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "")
1093  (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r")
1094  (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r")
1095  (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r")
1096  (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r")
1097])
1098
1099(define_int_attr maxmin [
1100  (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max")
1101  (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min")
1102  (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max")
1103  (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min")
1104])
1105
1106(define_int_attr fmaxmin [
1107  (UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")])
1108
1109(define_int_attr fmaxmin_op [
1110  (UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm")
1111])
1112
1113(define_int_attr shift_op [
1114  (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl")
1115  (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl")
1116  (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl")
1117  (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl")
1118  (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr")
1119  (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr")
1120  (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn")
1121  (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn")
1122  (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn")
1123  (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun")
1124  (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra")
1125  (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra")
1126])
1127
1128;; Standard names for floating point to integral rounding instructions.
1129(define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil")
1130                         (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor")
1131                         (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")])
1132
1133;; Suffixes for vrint instructions specifying rounding modes.
1134(define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p")
1135                               (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m")
1136                               (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")])
1137
1138;; Some of the vrint instuctions are predicable.
1139(define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no")
1140                                  (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
1141                                  (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
1142
1143(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional")
1144                              (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")
1145                              (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")])
1146
1147(define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p")
1148                                (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m")
1149                                (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")])
1150
1151(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1152                        (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb")
1153                        (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")])
1154
1155(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1156                        (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI")
1157                        (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")])
1158
1159(define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc")
1160                          (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd")
1161                          (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1")
1162                          (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c")
1163                          (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p")
1164                          (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h")
1165                          (UNSPEC_SHA256H2 "sha256h2")
1166                          (UNSPEC_SHA256SU1 "sha256su1")])
1167
1168(define_int_attr crypto_type
1169 [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese")
1170 (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc")
1171 (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow")
1172 (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast")
1173 (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow")
1174 (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast")
1175 (UNSPEC_SHA256SU1 "crypto_sha256_slow")])
1176
1177(define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8")
1178                          (UNSPEC_AESIMC "8") (UNSPEC_AESD "8")
1179                          (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32")
1180                          (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32")
1181                          (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32")
1182                          (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32")
1183                          (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")])
1184
1185(define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI")
1186                          (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI")
1187                          (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI")
1188                          (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI")
1189                          (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI")
1190                          (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI")
1191                          (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")])
1192
1193(define_int_attr rot [(UNSPEC_VCADD90 "90")
1194		      (UNSPEC_VCADD270 "270")
1195		      (UNSPEC_VCMUL "0")
1196		      (UNSPEC_VCMUL90 "90")
1197		      (UNSPEC_VCMUL180 "180")
1198		      (UNSPEC_VCMUL270 "270")
1199		      (UNSPEC_VCMLA "0")
1200		      (UNSPEC_VCMLA90 "90")
1201		      (UNSPEC_VCMLA180 "180")
1202		      (UNSPEC_VCMLA270 "270")])
1203
1204;; The complex operations when performed on a real complex number require two
1205;; instructions to perform the operation. e.g. complex multiplication requires
1206;; two VCMUL with a particular rotation value.
1207;;
1208;; These values can be looked up in rotsplit1 and rotsplit2.  as an example
1209;; VCMUL needs the first instruction to use #0 and the second #90.
1210(define_int_attr rotsplit1 [(UNSPEC_VCMLA "0")
1211			    (UNSPEC_VCMLA_CONJ "0")
1212			    (UNSPEC_VCMUL "0")
1213			    (UNSPEC_VCMUL_CONJ "0")
1214			    (UNSPEC_VCMLA180 "180")
1215			    (UNSPEC_VCMLA180_CONJ "180")])
1216
1217(define_int_attr rotsplit2 [(UNSPEC_VCMLA "90")
1218			    (UNSPEC_VCMLA_CONJ "270")
1219			    (UNSPEC_VCMUL "90")
1220			    (UNSPEC_VCMUL_CONJ "270")
1221			    (UNSPEC_VCMLA180 "270")
1222			    (UNSPEC_VCMLA180_CONJ "90")])
1223
1224(define_int_attr conj_op [(UNSPEC_VCMLA180 "")
1225			  (UNSPEC_VCMLA180_CONJ "_conj")
1226			  (UNSPEC_VCMLA "")
1227			  (UNSPEC_VCMLA_CONJ "_conj")
1228			  (UNSPEC_VCMUL "")
1229			  (UNSPEC_VCMUL_CONJ "_conj")])
1230
1231(define_int_attr mve_rot [(UNSPEC_VCADD90 "_rot90")
1232			  (UNSPEC_VCADD270 "_rot270")
1233			  (UNSPEC_VCMLA "")
1234			  (UNSPEC_VCMLA90 "_rot90")
1235			  (UNSPEC_VCMLA180 "_rot180")
1236			  (UNSPEC_VCMLA270 "_rot270")
1237			  (UNSPEC_VCMUL "")
1238			  (UNSPEC_VCMUL90 "_rot90")
1239			  (UNSPEC_VCMUL180 "_rot180")
1240			  (UNSPEC_VCMUL270 "_rot270")])
1241
1242(define_int_iterator VCMUL [UNSPEC_VCMUL UNSPEC_VCMUL90
1243			    UNSPEC_VCMUL180 UNSPEC_VCMUL270])
1244
1245(define_int_attr fcmac1 [(UNSPEC_VCMLA "a") (UNSPEC_VCMLA_CONJ "a")
1246			 (UNSPEC_VCMLA180 "s") (UNSPEC_VCMLA180_CONJ "s")])
1247
1248(define_int_attr simd32_op [(UNSPEC_QADD8 "qadd8") (UNSPEC_QSUB8 "qsub8")
1249			    (UNSPEC_SHADD8 "shadd8") (UNSPEC_SHSUB8 "shsub8")
1250			    (UNSPEC_UHADD8 "uhadd8") (UNSPEC_UHSUB8 "uhsub8")
1251			    (UNSPEC_UQADD8 "uqadd8") (UNSPEC_UQSUB8 "uqsub8")
1252			    (UNSPEC_QADD16 "qadd16") (UNSPEC_QASX "qasx")
1253			    (UNSPEC_QSAX "qsax") (UNSPEC_QSUB16 "qsub16")
1254			    (UNSPEC_SHADD16 "shadd16") (UNSPEC_SHASX "shasx")
1255			    (UNSPEC_SHSAX "shsax") (UNSPEC_SHSUB16 "shsub16")
1256			    (UNSPEC_UHADD16 "uhadd16") (UNSPEC_UHASX "uhasx")
1257			    (UNSPEC_UHSAX "uhsax") (UNSPEC_UHSUB16 "uhsub16")
1258			    (UNSPEC_UQADD16 "uqadd16") (UNSPEC_UQASX "uqasx")
1259			    (UNSPEC_UQSAX "uqsax") (UNSPEC_UQSUB16 "uqsub16")
1260			    (UNSPEC_SMUSD "smusd") (UNSPEC_SMUSDX "smusdx")
1261			    (UNSPEC_SXTAB16 "sxtab16") (UNSPEC_UXTAB16 "uxtab16")
1262			    (UNSPEC_USAD8 "usad8") (UNSPEC_SMLALD "smlald")
1263			    (UNSPEC_SMLALDX "smlaldx") (UNSPEC_SMLSLD "smlsld")
1264			    (UNSPEC_SMLSLDX "smlsldx")(UNSPEC_SADD8 "sadd8")
1265			    (UNSPEC_UADD8 "uadd8") (UNSPEC_SSUB8 "ssub8")
1266			    (UNSPEC_USUB8 "usub8") (UNSPEC_SADD16 "sadd16")
1267			    (UNSPEC_SASX "sasx") (UNSPEC_SSAX "ssax")
1268			    (UNSPEC_SSUB16 "ssub16") (UNSPEC_UADD16 "uadd16")
1269			    (UNSPEC_UASX "uasx") (UNSPEC_USAX "usax")
1270			    (UNSPEC_USUB16 "usub16") (UNSPEC_SMLAD "smlad")
1271			    (UNSPEC_SMLADX "smladx") (UNSPEC_SMLSD "smlsd")
1272			    (UNSPEC_SMLSDX "smlsdx") (UNSPEC_SMUAD "smuad")
1273			    (UNSPEC_SMUADX "smuadx") (UNSPEC_SSAT16 "ssat16")
1274			    (UNSPEC_USAT16 "usat16")])
1275
1276(define_int_attr mmla_sfx [(UNSPEC_MATMUL_S "s8") (UNSPEC_MATMUL_U "u8")
1277			   (UNSPEC_MATMUL_US "s8")])
1278;;MVE int attribute.
1279(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
1280		       (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
1281		       (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
1282		       (VREV64Q_U "u")
1283		       (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
1284		       (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
1285		       (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
1286		       (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
1287		       (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
1288		       (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
1289		       (VREV32Q_U "u")
1290		       (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
1291		       (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
1292		       (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
1293		       (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
1294		       (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
1295		       (VADDLVQ_P_U "u")
1296		       (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
1297		       (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
1298		       (VADDVQ_P_S "s")	(VADDVQ_P_U "u") (VBRSRQ_N_S "s")
1299		       (VBRSRQ_N_U "u")
1300		       (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
1301		       (VHADDQ_U "u") (VHSUBQ_N_S "s")	(VHSUBQ_N_U "u")
1302		       (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
1303		       (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u")
1304		       (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s")
1305		       (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
1306		       (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
1307		       (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
1308		       (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
1309		       (VMULQ_U "u")
1310		       (VQADDQ_N_S "s") (VQADDQ_N_U "u")
1311		       (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
1312		       (VQRSHLQ_U "u") (VQSHLQ_N_S "s")	(VQSHLQ_N_U "u")
1313		       (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
1314		       (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u")
1315		       (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s")
1316		       (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u")
1317		       (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s")
1318		       (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u")
1319		       (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s")
1320		       (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u")
1321		       (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
1322		       (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
1323		       (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
1324		       (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
1325		       (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
1326		       (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
1327		       (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
1328		       (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
1329		       (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
1330		       (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u")
1331		       (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s")
1332		       (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s")
1333		       (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u")
1334		       (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s")
1335		       (VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u")
1336		       (VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s")
1337		       (VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u")
1338		       (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s")
1339		       (VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u")
1340		       (VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s")
1341		       (VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u")
1342		       (VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s")
1343		       (VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u")
1344		       (VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s")
1345		       (VPSELQ_U "u") (VQDMLAHQ_N_S "s")
1346		       (VQDMLASHQ_N_S "s")
1347		       (VQRDMLAHQ_N_S "s")
1348		       (VQRDMLASHQ_N_S "s")
1349		       (VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u")
1350		       (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s")
1351		       (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u")
1352		       (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s")
1353		       (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")
1354		       (VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s")
1355		       (VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s")
1356		       (VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s")
1357		       (VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s")
1358		       (VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s")
1359		       (VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s")
1360		       (VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u")
1361		       (VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u")
1362		       (VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u")
1363		       (VREV16Q_M_S "s") (VREV16Q_M_U "u")
1364		       (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u")
1365		       (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u")
1366		       (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u")
1367		       (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u")
1368		       (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s")
1369		       (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u")
1370		       (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s")
1371		       (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s")
1372		       (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u")
1373		       (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u")
1374		       (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u")
1375		       (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
1376		       (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
1377		       (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
1378		       (VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
1379		       (VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
1380		       (VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
1381		       (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
1382		       (VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
1383		       (VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
1384		       (VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
1385		       (VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u")
1386		       (VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u")
1387		       (VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
1388		       (VQDMLASHQ_M_N_S "s")
1389		       (VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
1390		       (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
1391		       (VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
1392		       (VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
1393		       (VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
1394		       (VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
1395		       (VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
1396		       (VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
1397		       (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
1398		       (VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
1399		       (VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
1400		       (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
1401		       (VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
1402		       (VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
1403		       (VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
1404		       (VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s")
1405		       (VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u")
1406		       (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s")
1407		       (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u")
1408		       (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u")
1409		       (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")
1410		       (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u")
1411		       (VSHRNTQ_M_N_U "u") (VSHRNTQ_M_N_S "s")
1412		       (VSHRNBQ_M_N_S "s") (VSHRNBQ_M_N_U "u")
1413		       (VSHLLTQ_M_N_S "s") (VSHLLTQ_M_N_U "u")
1414		       (VSHLLBQ_M_N_S "s") (VSHLLBQ_M_N_U "u")
1415		       (VRSHRNTQ_M_N_S "s") (VRSHRNTQ_M_N_U "u")
1416		       (VRSHRNBQ_M_N_U "u") (VRSHRNBQ_M_N_S "s")
1417		       (VQSHRNTQ_M_N_U "u") (VQSHRNTQ_M_N_S "s")
1418		       (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u")
1419		       (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
1420		       (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
1421		       (VMLALDAVAXQ_P_S "s")
1422		       (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")
1423		       (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
1424		       (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
1425		       (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
1426		       (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")
1427		       (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s")
1428		       (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u")
1429		       (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s")
1430		       (VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u")
1431		       (VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s")
1432		       (VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u")
1433		       (VLDRWQGSO_S "s") (VLDRWQGSO_U "u") (VST1Q_S "s")
1434		       (VST1Q_U "u") (VSTRHQSO_S "s") (VSTRHQSO_U "u")
1435		       (VSTRHQSSO_S "s") (VSTRHQSSO_U "u") (VSTRHQ_S "s")
1436		       (VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u")
1437		       (VSTRDQSB_S "s") (VSTRDQSB_U "u") (VSTRDQSO_S "s")
1438		       (VSTRDQSO_U "u") (VSTRDQSSO_S "s") (VSTRDQSSO_U "u")
1439		       (VSTRWQSO_U "u") (VSTRWQSO_S "s") (VSTRWQSSO_U "u")
1440		       (VSTRWQSSO_S "s") (VSTRWQSBWB_S "s") (VSTRWQSBWB_U "u")
1441		       (VLDRWQGBWB_S "s") (VLDRWQGBWB_U "u") (VLDRDQGBWB_S "s")
1442		       (VLDRDQGBWB_U "u") (VSTRDQSBWB_S "s") (VADCQ_M_S "s")
1443		       (VSTRDQSBWB_U "u") (VSBCQ_U "u")  (VSBCQ_M_U "u")
1444		       (VSBCQ_S "s")  (VSBCQ_M_S "s") (VSBCIQ_U "u")
1445		       (VSBCIQ_M_U "u") (VSBCIQ_S "s") (VSBCIQ_M_S "s")
1446		       (VADCQ_U "u")  (VADCQ_M_U "u") (VADCQ_S "s")
1447		       (VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s")
1448		       (VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48")
1449		       (UQRSHLL_64 "64") (UQRSHLL_48 "48") (VSHLCQ_M_S "s")
1450		       (VSHLCQ_M_U "u")])
1451
1452(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
1453			(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
1454			(VCTP32Q_M "32") (VCTP64Q_M "64")])
1455
1456;; Both kinds of return insn.
1457(define_code_iterator RETURNS [return simple_return])
1458(define_code_attr return_str [(return "") (simple_return "simple_")])
1459(define_code_attr return_simple_p [(return "false") (simple_return "true")])
1460(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)")
1461                               (simple_return " && use_simple_return_p ()")])
1462(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)")
1463                               (simple_return " && use_simple_return_p ()")])
1464
1465;; Attributes for VQRDMLAH/VQRDMLSH
1466(define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")])
1467
1468;; Attributes for VFMA_LANE/ VFMS_LANE
1469(define_int_attr neon_vfm_lane_as
1470 [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")])
1471
1472;; An iterator for the CDP coprocessor instructions
1473(define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2])
1474(define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")])
1475(define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")])
1476
1477;; An iterator for the LDC coprocessor instruction
1478(define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2
1479			   VUNSPEC_LDCL VUNSPEC_LDC2L])
1480(define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2")
1481		      (VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")])
1482(define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2")
1483		      (VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")])
1484
1485;; An iterator for the STC coprocessor instructions
1486(define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2
1487			   VUNSPEC_STCL VUNSPEC_STC2L])
1488(define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2")
1489		      (VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")])
1490(define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2")
1491		      (VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")])
1492
1493;; An iterator for the MCR coprocessor instructions
1494(define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2])
1495
1496(define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")])
1497(define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")])
1498
1499;; An iterator for the MRC coprocessor instructions
1500(define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2])
1501
1502(define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")])
1503(define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")])
1504
1505;; An iterator for the MCRR coprocessor instructions
1506(define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2])
1507
1508(define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")])
1509(define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")])
1510
1511;; An iterator for the MRRC coprocessor instructions
1512(define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2])
1513
1514(define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")])
1515(define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")])
1516
1517(define_int_attr opsuffix [(UNSPEC_DOT_S "s8")
1518			   (UNSPEC_DOT_U "u8")
1519			   (UNSPEC_DOT_US "s8")
1520			   (UNSPEC_DOT_SU "u8")
1521			   ])
1522
1523(define_int_attr smlaw_op [(UNSPEC_SMLAWB "smlawb") (UNSPEC_SMLAWT "smlawt")])
1524
1525;; An iterator for VFMA<bt>
1526(define_int_attr bt [(UNSPEC_BFMAB "b") (UNSPEC_BFMAT "t")])
1527
1528;; An iterator for CDE MVE accumulator/non-accumulator versions.
1529(define_int_attr a [(UNSPEC_VCDE "") (UNSPEC_VCDEA "a")])
1530
1531;; MVE int iterator.
1532(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
1533(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
1534(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
1535(define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
1536(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
1537(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
1538(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
1539(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
1540(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
1541(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
1542(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
1543(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
1544(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
1545(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
1546(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
1547(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
1548(define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M])
1549(define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
1550(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
1551(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
1552(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
1553(define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
1554(define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
1555(define_int_iterator VABDQ [VABDQ_S VABDQ_U])
1556(define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
1557(define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
1558(define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
1559(define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
1560(define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
1561(define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
1562(define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
1563(define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S])
1564(define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S])
1565(define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S])
1566(define_int_iterator VMINQ [VMINQ_S VMINQ_U])
1567(define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
1568(define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
1569(define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
1570(define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
1571(define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
1572(define_int_iterator VMULQ [VMULQ_U VMULQ_S])
1573(define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
1574(define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
1575(define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
1576(define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
1577(define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U])
1578(define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U])
1579(define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U])
1580(define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S])
1581(define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S])
1582(define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U])
1583(define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U])
1584(define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U])
1585(define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U])
1586(define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S])
1587(define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U])
1588(define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S])
1589(define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U])
1590(define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U])
1591(define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U])
1592(define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
1593(define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
1594(define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
1595(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
1596(define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
1597(define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
1598(define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
1599(define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
1600(define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
1601(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
1602(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
1603(define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
1604(define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
1605(define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
1606(define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U])
1607(define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S])
1608(define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U])
1609(define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U])
1610(define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U])
1611(define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U])
1612(define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U])
1613(define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U])
1614(define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U])
1615(define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U])
1616(define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U])
1617(define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U])
1618(define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U])
1619(define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U])
1620(define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U])
1621(define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U])
1622(define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U])
1623(define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U])
1624(define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U])
1625(define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U])
1626(define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S])
1627(define_int_iterator VQDMLASHQ_N [VQDMLASHQ_N_S])
1628(define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S])
1629(define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S])
1630(define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U])
1631(define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U])
1632(define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U])
1633(define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U])
1634(define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U])
1635(define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U])
1636(define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U])
1637(define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S])
1638(define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U])
1639(define_int_iterator VMOVLTQ_M [VMOVLTQ_M_U VMOVLTQ_M_S])
1640(define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S])
1641(define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S])
1642(define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U])
1643(define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U])
1644(define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U])
1645(define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S])
1646(define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S])
1647(define_int_iterator VMOVLBQ_M [VMOVLBQ_M_U VMOVLBQ_M_S])
1648(define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U])
1649(define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S])
1650(define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S])
1651(define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U])
1652(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S])
1653(define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S])
1654(define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S])
1655(define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S])
1656(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U])
1657(define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U])
1658(define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U])
1659(define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U])
1660(define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U])
1661(define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U])
1662(define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S])
1663(define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U])
1664(define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S])
1665(define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U])
1666(define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U])
1667(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
1668(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
1669(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
1670(define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U])
1671(define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S])
1672(define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U])
1673(define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U])
1674(define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S])
1675(define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U])
1676(define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U])
1677(define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U])
1678(define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U])
1679(define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U])
1680(define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S])
1681(define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S])
1682(define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U])
1683(define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S])
1684(define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S])
1685(define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S])
1686(define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S])
1687(define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S])
1688(define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
1689(define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
1690(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
1691(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
1692(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
1693(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
1694(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
1695(define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U])
1696(define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S])
1697(define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S])
1698(define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
1699(define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
1700(define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
1701(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S])
1702(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
1703(define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
1704(define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
1705(define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U])
1706(define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U])
1707(define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U])
1708(define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U])
1709(define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U])
1710(define_int_iterator VMLALDAVAQ_P [VMLALDAVAQ_P_U VMLALDAVAQ_P_S])
1711(define_int_iterator VMLALDAVAXQ_P [VMLALDAVAXQ_P_S])
1712(define_int_iterator VQRSHRNBQ_M_N [VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S])
1713(define_int_iterator VQRSHRNTQ_M_N [VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U])
1714(define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S])
1715(define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U])
1716(define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S])
1717(define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S])
1718(define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S])
1719(define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S])
1720(define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U])
1721(define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U])
1722(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U])
1723(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U])
1724(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U])
1725(define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
1726(define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])
1727(define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
1728(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U])
1729(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U])
1730(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U])
1731(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U])
1732(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U])
1733(define_int_iterator VLDRDGBQ [VLDRDQGB_S VLDRDQGB_U])
1734(define_int_iterator VLDRDGOQ [VLDRDQGO_S VLDRDQGO_U])
1735(define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U])
1736(define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U])
1737(define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U])
1738(define_int_iterator VST1Q [VST1Q_S VST1Q_U])
1739(define_int_iterator VSTRHSOQ [VSTRHQSO_S VSTRHQSO_U])
1740(define_int_iterator VSTRHSSOQ [VSTRHQSSO_S VSTRHQSSO_U])
1741(define_int_iterator VSTRHQ [VSTRHQ_S VSTRHQ_U])
1742(define_int_iterator VSTRWQ [VSTRWQ_S VSTRWQ_U])
1743(define_int_iterator VSTRDSBQ [VSTRDQSB_S VSTRDQSB_U])
1744(define_int_iterator VSTRDSOQ [VSTRDQSO_S VSTRDQSO_U])
1745(define_int_iterator VSTRDSSOQ [VSTRDQSSO_S VSTRDQSSO_U])
1746(define_int_iterator VSTRWSOQ [VSTRWQSO_S VSTRWQSO_U])
1747(define_int_iterator VSTRWSSOQ [VSTRWQSSO_S VSTRWQSSO_U])
1748(define_int_iterator VSTRWSBWBQ [VSTRWQSBWB_S VSTRWQSBWB_U])
1749(define_int_iterator VLDRWGBWBQ [VLDRWQGBWB_S VLDRWQGBWB_U])
1750(define_int_iterator VSTRDSBWBQ [VSTRDQSBWB_S VSTRDQSBWB_U])
1751(define_int_iterator VLDRDGBWBQ [VLDRDQGBWB_S VLDRDQGBWB_U])
1752(define_int_iterator VADCIQ [VADCIQ_U VADCIQ_S])
1753(define_int_iterator VADCIQ_M [VADCIQ_M_U VADCIQ_M_S])
1754(define_int_iterator VSBCQ [VSBCQ_U VSBCQ_S])
1755(define_int_iterator VSBCQ_M [VSBCQ_M_U VSBCQ_M_S])
1756(define_int_iterator VSBCIQ [VSBCIQ_U VSBCIQ_S])
1757(define_int_iterator VSBCIQ_M [VSBCIQ_M_U VSBCIQ_M_S])
1758(define_int_iterator VADCQ [VADCQ_U VADCQ_S])
1759(define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S])
1760(define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48])
1761(define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48])
1762(define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U])
1763
1764;; Define iterators for VCMLA operations
1765(define_int_iterator VCMLA_OP [UNSPEC_VCMLA
1766			       UNSPEC_VCMLA_CONJ
1767			       UNSPEC_VCMLA180
1768			       UNSPEC_VCMLA180_CONJ])
1769
1770;; Define iterators for VCMLA operations as MUL
1771(define_int_iterator VCMUL_OP [UNSPEC_VCMUL
1772			       UNSPEC_VCMUL_CONJ])
1773