1;;  Machine Description for Renesas RL78 processors
2;;  Copyright (C) 2011-2013 Free Software Foundation, Inc.
3;;  Contributed by Red Hat.
4
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11
12;; GCC is distributed in the hope that it will be useful,
13;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15;; GNU General Public License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21; Constraints in use:
22
23; core:
24; V X g i m n o p r s < >
25; 0..9
26; I..Q - integers
27;   Int8 = 0..255
28;   Int3 = 1..7
29;   J = -255..0
30;   K = 1
31;   L = -1
32;   M = 0
33;   N = 2
34;   O = -2
35;   P = 1..15
36
37; E..H - float constants
38
39; RL78-specific
40; a x b c d e h l w - 8-bit regs
41; A B D T S - 16-bit regs
42; R = all regular registers (A-L)
43; Y - any valid memory
44; Wxx - various memory addressing modes
45; Qxx - conditionals
46; v = virtual registers
47; Zxx = specific virtual registers
48
49(define_constraint "Int8"
50  "Integer constant in the range 0 @dots{} 255."
51  (and (match_code "const_int")
52       (match_test "IN_RANGE (ival, 0, 255)")))
53
54(define_constraint "Int3"
55  "Integer constant in the range 1 @dots{} 7."
56  (and (match_code "const_int")
57       (match_test "IN_RANGE (ival, 1, 7)")))
58
59(define_constraint "J"
60  "Integer constant in the range -255 @dots{} 0"
61  (and (match_code "const_int")
62       (match_test "IN_RANGE (ival, -255, 0)")))
63
64(define_constraint "K"
65  "Integer constant 1."
66  (and (match_code "const_int")
67       (match_test "IN_RANGE (ival, 1, 1)")))
68
69(define_constraint "L"
70  "Integer constant -1."
71  (and (match_code "const_int")
72       (match_test "IN_RANGE (ival, -1, -1)")))
73
74(define_constraint "M"
75  "Integer constant 0."
76  (and (match_code "const_int")
77       (match_test "IN_RANGE (ival, 0, 0)")))
78
79(define_constraint "N"
80  "Integer constant 2."
81  (and (match_code "const_int")
82       (match_test "IN_RANGE (ival, 2, 2)")))
83
84(define_constraint "O"
85  "Integer constant -2."
86  (and (match_code "const_int")
87       (match_test "IN_RANGE (ival, -2, -2)")))
88
89(define_constraint "P"
90  "Integer constant 1..15"
91  (and (match_code "const_int")
92       (match_test "IN_RANGE (ival, 1, 15)")))
93
94(define_register_constraint "R" "QI_REGS"
95 "@code{A} through @code{L} registers.")
96
97(define_register_constraint "a" "AREG"
98 "The @code{A} register.")
99
100(define_register_constraint "x" "XREG"
101 "The @code{X} register.")
102
103(define_register_constraint "b" "BREG"
104 "The @code{B} register.")
105
106(define_register_constraint "c" "CREG"
107 "The @code{C} register.")
108
109(define_register_constraint "d" "DREG"
110 "The @code{D} register.")
111
112(define_register_constraint "e" "EREG"
113 "The @code{E} register.")
114
115(define_register_constraint "h" "HREG"
116 "The @code{H} register.")
117
118(define_register_constraint "l" "LREG"
119 "The @code{L} register.")
120
121(define_register_constraint "w" "PSWREG"
122 "The @code{PSW} register.")
123
124(define_register_constraint "A" "AXREG"
125 "The @code{AX} register.")
126
127(define_register_constraint "B" "BCREG"
128 "The @code{BC} register.")
129
130(define_register_constraint "D" "DEREG"
131 "The @code{DE} register.")
132
133; because H + L = T, assuming A=1.
134(define_register_constraint "T" "HLREG"
135 "The @code{HL} register.")
136
137(define_register_constraint "S" "SPREG"
138 "The @code{SP} register.")
139
140(define_register_constraint "v" "V_REGS"
141 "The virtual registers.")
142
143(define_register_constraint "Z08W" "R8W_REGS"
144 "The R8 register, HImode.")
145
146(define_register_constraint "Z10W" "R10W_REGS"
147 "The R10 register, HImode.")
148
149(define_register_constraint "Zint" "INT_REGS"
150 "The interrupt registers.")
151
152; All the memory addressing schemes the RL78 supports
153; of the form W {register} {bytes of offset}
154;          or W {register} {register}
155
156; absolute address
157(define_memory_constraint "Wab"
158  "[addr]"
159  (and (match_code "mem")
160       (ior (match_test "CONSTANT_P (XEXP (op, 0))")
161	    (match_test "GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF"))
162	    )
163  )
164
165(define_memory_constraint "Wbc"
166  "word16[BC]"
167  (and (match_code "mem")
168       (ior
169	(and (match_code "reg" "0")
170	     (match_test "REGNO (XEXP (op, 0)) == BC_REG"))
171	(and (match_code "plus" "0")
172	     (and (and (match_code "reg" "00")
173		       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == BC_REG"))
174		       (match_test "uword_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
175       )
176  )
177
178(define_memory_constraint "Wde"
179  "[DE]"
180  (and (match_code "mem")
181       (and (match_code "reg" "0")
182	    (match_test "REGNO (XEXP (op, 0)) == DE_REG")))
183  )
184
185(define_memory_constraint "Wca"
186  "[AX..HL] for calls"
187  (and (match_code "mem")
188       (and (match_code "reg" "0")
189	    (match_test "REGNO (XEXP (op, 0)) <= HL_REG")))
190  )
191
192(define_memory_constraint "Wcv"
193  "[AX..HL,r8-r23] for calls"
194  (and (match_code "mem")
195       (and (match_code "reg" "0")
196	    (match_test "REGNO (XEXP (op, 0)) < 24")))
197  )
198
199(define_memory_constraint "Wd2"
200  "word16[DE]"
201  (and (match_code "mem")
202       (ior
203	(and (match_code "reg" "0")
204	     (match_test "REGNO (XEXP (op, 0)) == DE_REG"))
205	(and (match_code "plus" "0")
206	     (and (and (match_code "reg" "00")
207		       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == DE_REG"))
208		       (match_test "uword_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
209       )
210  )
211
212(define_memory_constraint "Whl"
213  "[HL]"
214  (and (match_code "mem")
215       (and (match_code "reg" "0")
216	    (match_test "REGNO (XEXP (op, 0)) == HL_REG")))
217  )
218
219(define_memory_constraint "Wh1"
220  "byte8[HL]"
221  (and (match_code "mem")
222       (and (match_code "plus" "0")
223	    (and (and (match_code "reg" "00")
224		      (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == HL_REG"))
225		      (match_test "ubyte_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
226  )
227
228(define_memory_constraint "Whb"
229  "[HL+B]"
230  (and (match_code "mem")
231       (match_test "rl78_hl_b_c_addr_p (XEXP (op, 0))"))
232  )
233
234(define_memory_constraint "Ws1"
235  "word8[SP]"
236  (and (match_code "mem")
237       (ior
238	(and (match_code "reg" "0")
239	     (match_test "REGNO (XEXP (op, 0)) == SP_REG"))
240	(and (match_code "plus" "0")
241	     (and (and (match_code "reg" "00")
242		       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG"))
243		       (match_test "ubyte_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
244       )
245  )
246
247(define_memory_constraint "Wfr"
248  "ES/CS far pointer"
249  (and (match_code "mem")
250       (match_test "rl78_far_p (op)"))
251  )
252
253(define_memory_constraint "Y"
254  "any near legitimate memory access"
255  (and (match_code "mem")
256       (match_test "!rl78_far_p (op) && rl78_as_legitimate_address (VOIDmode, XEXP (op, 0), true, ADDR_SPACE_GENERIC)"))
257)
258
259
260(define_memory_constraint "Qbi"
261  "built-in compare types"
262  (match_code "eq,ne,gtu,ltu,geu,leu"))
263
264(define_memory_constraint "Qsc"
265  "synthetic compares"
266  (match_code "gt,lt,ge,le"))
267