1;; Predicate definitions for POWER and PowerPC. 2;; Copyright (C) 2005-2013 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Return 1 for anything except PARALLEL. 21(define_predicate "any_operand" 22 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")) 23 24;; Return 1 for any PARALLEL. 25(define_predicate "any_parallel_operand" 26 (match_code "parallel")) 27 28;; Return 1 if op is COUNT register. 29(define_predicate "count_register_operand" 30 (and (match_code "reg") 31 (match_test "REGNO (op) == CTR_REGNO 32 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) 33 34;; Return 1 if op is an Altivec register. 35(define_predicate "altivec_register_operand" 36 (match_operand 0 "register_operand") 37{ 38 if (GET_CODE (op) == SUBREG) 39 op = SUBREG_REG (op); 40 41 if (!REG_P (op)) 42 return 0; 43 44 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 45 return 1; 46 47 return ALTIVEC_REGNO_P (REGNO (op)); 48}) 49 50;; Return 1 if op is a VSX register. 51(define_predicate "vsx_register_operand" 52 (match_operand 0 "register_operand") 53{ 54 if (GET_CODE (op) == SUBREG) 55 op = SUBREG_REG (op); 56 57 if (!REG_P (op)) 58 return 0; 59 60 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 61 return 1; 62 63 return VSX_REGNO_P (REGNO (op)); 64}) 65 66;; Return 1 if op is a vector register that operates on floating point vectors 67;; (either altivec or VSX). 68(define_predicate "vfloat_operand" 69 (match_operand 0 "register_operand") 70{ 71 if (GET_CODE (op) == SUBREG) 72 op = SUBREG_REG (op); 73 74 if (!REG_P (op)) 75 return 0; 76 77 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 78 return 1; 79 80 return VFLOAT_REGNO_P (REGNO (op)); 81}) 82 83;; Return 1 if op is a vector register that operates on integer vectors 84;; (only altivec, VSX doesn't support integer vectors) 85(define_predicate "vint_operand" 86 (match_operand 0 "register_operand") 87{ 88 if (GET_CODE (op) == SUBREG) 89 op = SUBREG_REG (op); 90 91 if (!REG_P (op)) 92 return 0; 93 94 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 95 return 1; 96 97 return VINT_REGNO_P (REGNO (op)); 98}) 99 100;; Return 1 if op is a vector register to do logical operations on (and, or, 101;; xor, etc.) 102(define_predicate "vlogical_operand" 103 (match_operand 0 "register_operand") 104{ 105 if (GET_CODE (op) == SUBREG) 106 op = SUBREG_REG (op); 107 108 if (!REG_P (op)) 109 return 0; 110 111 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 112 return 1; 113 114 return VLOGICAL_REGNO_P (REGNO (op)); 115}) 116 117;; Return 1 if op is the carry register. 118(define_predicate "ca_operand" 119 (and (match_code "reg") 120 (match_test "CA_REGNO_P (REGNO (op))"))) 121 122;; Return 1 if op is a signed 5-bit constant integer. 123(define_predicate "s5bit_cint_operand" 124 (and (match_code "const_int") 125 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) 126 127;; Return 1 if op is a unsigned 3-bit constant integer. 128(define_predicate "u3bit_cint_operand" 129 (and (match_code "const_int") 130 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) 131 132;; Return 1 if op is a unsigned 5-bit constant integer. 133(define_predicate "u5bit_cint_operand" 134 (and (match_code "const_int") 135 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) 136 137;; Return 1 if op is a signed 8-bit constant integer. 138;; Integer multiplication complete more quickly 139(define_predicate "s8bit_cint_operand" 140 (and (match_code "const_int") 141 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) 142 143;; Return 1 if op is a unsigned 10-bit constant integer. 144(define_predicate "u10bit_cint_operand" 145 (and (match_code "const_int") 146 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023"))) 147 148;; Return 1 if op is a constant integer that can fit in a D field. 149(define_predicate "short_cint_operand" 150 (and (match_code "const_int") 151 (match_test "satisfies_constraint_I (op)"))) 152 153;; Return 1 if op is a constant integer that can fit in an unsigned D field. 154(define_predicate "u_short_cint_operand" 155 (and (match_code "const_int") 156 (match_test "satisfies_constraint_K (op)"))) 157 158;; Return 1 if op is a constant integer that cannot fit in a signed D field. 159(define_predicate "non_short_cint_operand" 160 (and (match_code "const_int") 161 (match_test "(unsigned HOST_WIDE_INT) 162 (INTVAL (op) + 0x8000) >= 0x10000"))) 163 164;; Return 1 if op is a positive constant integer that is an exact power of 2. 165(define_predicate "exact_log2_cint_operand" 166 (and (match_code "const_int") 167 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) 168 169;; Match op = 0 or op = 1. 170(define_predicate "const_0_to_1_operand" 171 (and (match_code "const_int") 172 (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) 173 174;; Match op = 0..3. 175(define_predicate "const_0_to_3_operand" 176 (and (match_code "const_int") 177 (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) 178 179;; Match op = 2 or op = 3. 180(define_predicate "const_2_to_3_operand" 181 (and (match_code "const_int") 182 (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) 183 184;; Match op = 0..15 185(define_predicate "const_0_to_15_operand" 186 (and (match_code "const_int") 187 (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) 188 189;; Return 1 if op is a register that is not special. 190(define_predicate "gpc_reg_operand" 191 (match_operand 0 "register_operand") 192{ 193 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode)) 194 return 0; 195 196 if (GET_CODE (op) == SUBREG) 197 op = SUBREG_REG (op); 198 199 if (!REG_P (op)) 200 return 0; 201 202 if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op))) 203 return 1; 204 205 if (TARGET_VSX && VSX_REGNO_P (REGNO (op))) 206 return 1; 207 208 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op)); 209}) 210 211;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't 212;; allow floating point or vector registers. 213(define_predicate "int_reg_operand" 214 (match_operand 0 "register_operand") 215{ 216 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode)) 217 return 0; 218 219 if (GET_CODE (op) == SUBREG) 220 op = SUBREG_REG (op); 221 222 if (!REG_P (op)) 223 return 0; 224 225 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 226 return 1; 227 228 return INT_REGNO_P (REGNO (op)); 229}) 230 231;; Like int_reg_operand, but only return true for base registers 232(define_predicate "base_reg_operand" 233 (match_operand 0 "int_reg_operand") 234{ 235 if (GET_CODE (op) == SUBREG) 236 op = SUBREG_REG (op); 237 238 if (!REG_P (op)) 239 return 0; 240 241 return (REGNO (op) != FIRST_GPR_REGNO); 242}) 243 244;; Return 1 if op is a HTM specific SPR register. 245(define_predicate "htm_spr_reg_operand" 246 (match_operand 0 "register_operand") 247{ 248 if (!TARGET_HTM) 249 return 0; 250 251 if (GET_CODE (op) == SUBREG) 252 op = SUBREG_REG (op); 253 254 if (!REG_P (op)) 255 return 0; 256 257 switch (REGNO (op)) 258 { 259 case TFHAR_REGNO: 260 case TFIAR_REGNO: 261 case TEXASR_REGNO: 262 return 1; 263 default: 264 break; 265 } 266 267 /* Unknown SPR. */ 268 return 0; 269}) 270 271;; Return 1 if op is a general purpose register that is an even register 272;; which suitable for a load/store quad operation 273(define_predicate "quad_int_reg_operand" 274 (match_operand 0 "register_operand") 275{ 276 HOST_WIDE_INT r; 277 278 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC) 279 return 0; 280 281 if (GET_CODE (op) == SUBREG) 282 op = SUBREG_REG (op); 283 284 if (!REG_P (op)) 285 return 0; 286 287 r = REGNO (op); 288 if (r >= FIRST_PSEUDO_REGISTER) 289 return 1; 290 291 return (INT_REGNO_P (r) && ((r & 1) == 0)); 292}) 293 294;; Return 1 if op is a register that is a condition register field. 295(define_predicate "cc_reg_operand" 296 (match_operand 0 "register_operand") 297{ 298 if (GET_CODE (op) == SUBREG) 299 op = SUBREG_REG (op); 300 301 if (!REG_P (op)) 302 return 0; 303 304 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 305 return 1; 306 307 return CR_REGNO_P (REGNO (op)); 308}) 309 310;; Return 1 if op is a register that is a condition register field not cr0. 311(define_predicate "cc_reg_not_cr0_operand" 312 (match_operand 0 "register_operand") 313{ 314 if (GET_CODE (op) == SUBREG) 315 op = SUBREG_REG (op); 316 317 if (!REG_P (op)) 318 return 0; 319 320 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 321 return 1; 322 323 return CR_REGNO_NOT_CR0_P (REGNO (op)); 324}) 325 326;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0. 327(define_predicate "cc_reg_not_micro_cr0_operand" 328 (match_operand 0 "register_operand") 329{ 330 if (GET_CODE (op) == SUBREG) 331 op = SUBREG_REG (op); 332 333 if (!REG_P (op)) 334 return 0; 335 336 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 337 return 1; 338 339 if (rs6000_gen_cell_microcode) 340 return CR_REGNO_NOT_CR0_P (REGNO (op)); 341 else 342 return CR_REGNO_P (REGNO (op)); 343}) 344 345;; Return 1 if op is a constant integer valid for D field 346;; or non-special register register. 347(define_predicate "reg_or_short_operand" 348 (if_then_else (match_code "const_int") 349 (match_operand 0 "short_cint_operand") 350 (match_operand 0 "gpc_reg_operand"))) 351 352;; Return 1 if op is a constant integer valid whose negation is valid for 353;; D field or non-special register register. 354;; Do not allow a constant zero because all patterns that call this 355;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than 356;; or equal to const, which does not work for zero. 357(define_predicate "reg_or_neg_short_operand" 358 (if_then_else (match_code "const_int") 359 (match_test "satisfies_constraint_P (op) 360 && INTVAL (op) != 0") 361 (match_operand 0 "gpc_reg_operand"))) 362 363;; Return 1 if op is a constant integer valid for DS field 364;; or non-special register. 365(define_predicate "reg_or_aligned_short_operand" 366 (if_then_else (match_code "const_int") 367 (and (match_operand 0 "short_cint_operand") 368 (match_test "!(INTVAL (op) & 3)")) 369 (match_operand 0 "gpc_reg_operand"))) 370 371;; Return 1 if op is a constant integer whose high-order 16 bits are zero 372;; or non-special register. 373(define_predicate "reg_or_u_short_operand" 374 (if_then_else (match_code "const_int") 375 (match_operand 0 "u_short_cint_operand") 376 (match_operand 0 "gpc_reg_operand"))) 377 378;; Return 1 if op is any constant integer 379;; or non-special register. 380(define_predicate "reg_or_cint_operand" 381 (ior (match_code "const_int") 382 (match_operand 0 "gpc_reg_operand"))) 383 384;; Return 1 if op is a constant integer valid for addition with addis, addi. 385(define_predicate "add_cint_operand" 386 (and (match_code "const_int") 387 (match_test "(unsigned HOST_WIDE_INT) 388 (INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000)) 389 < (unsigned HOST_WIDE_INT) 0x100000000ll"))) 390 391;; Return 1 if op is a constant integer valid for addition 392;; or non-special register. 393(define_predicate "reg_or_add_cint_operand" 394 (if_then_else (match_code "const_int") 395 (match_operand 0 "add_cint_operand") 396 (match_operand 0 "gpc_reg_operand"))) 397 398;; Return 1 if op is a constant integer valid for subtraction 399;; or non-special register. 400(define_predicate "reg_or_sub_cint_operand" 401 (if_then_else (match_code "const_int") 402 (match_test "(HOST_BITS_PER_WIDE_INT == 32 403 && (mode == SImode || - INTVAL (op) < 0x7fff8000)) 404 || ((unsigned HOST_WIDE_INT) (- INTVAL (op) 405 + (mode == SImode 406 ? 0x80000000 : 0x80008000)) 407 < (unsigned HOST_WIDE_INT) 0x100000000ll)") 408 (match_operand 0 "gpc_reg_operand"))) 409 410;; Return 1 if op is any 32-bit unsigned constant integer 411;; or non-special register. 412(define_predicate "reg_or_logical_cint_operand" 413 (if_then_else (match_code "const_int") 414 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 415 && INTVAL (op) >= 0) 416 || ((INTVAL (op) & GET_MODE_MASK (mode) 417 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") 418 (if_then_else (match_code "const_double") 419 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 420 && mode == DImode 421 && CONST_DOUBLE_HIGH (op) == 0") 422 (match_operand 0 "gpc_reg_operand")))) 423 424;; Like reg_or_logical_cint_operand, but allow vsx registers 425(define_predicate "vsx_reg_or_cint_operand" 426 (ior (match_operand 0 "vsx_register_operand") 427 (match_operand 0 "reg_or_logical_cint_operand"))) 428 429;; Return 1 if operand is a CONST_DOUBLE that can be set in a register 430;; with no more than one instruction per word. 431(define_predicate "easy_fp_constant" 432 (match_code "const_double") 433{ 434 long k[4]; 435 REAL_VALUE_TYPE rv; 436 437 if (GET_MODE (op) != mode 438 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode)) 439 return 0; 440 441 /* Consider all constants with -msoft-float to be easy. */ 442 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE 443 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT))) 444 && mode != DImode) 445 return 1; 446 447 /* The constant 0.0 is easy under VSX. */ 448 if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode) 449 && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode)) 450 return 1; 451 452 if (DECIMAL_FLOAT_MODE_P (mode)) 453 return 0; 454 455 /* If we are using V.4 style PIC, consider all constants to be hard. */ 456 if (flag_pic && DEFAULT_ABI == ABI_V4) 457 return 0; 458 459#ifdef TARGET_RELOCATABLE 460 /* Similarly if we are using -mrelocatable, consider all constants 461 to be hard. */ 462 if (TARGET_RELOCATABLE) 463 return 0; 464#endif 465 466 switch (mode) 467 { 468 case TFmode: 469 if (TARGET_E500_DOUBLE) 470 return 0; 471 472 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); 473 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); 474 475 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 476 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 477 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 478 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); 479 480 case DFmode: 481 /* The constant 0.f is easy under VSX. */ 482 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode)) 483 return 1; 484 485 /* Force constants to memory before reload to utilize 486 compress_float_constant. 487 Avoid this when flag_unsafe_math_optimizations is enabled 488 because RDIV division to reciprocal optimization is not able 489 to regenerate the division. */ 490 if (TARGET_E500_DOUBLE 491 || (!reload_in_progress && !reload_completed 492 && !flag_unsafe_math_optimizations)) 493 return 0; 494 495 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); 496 REAL_VALUE_TO_TARGET_DOUBLE (rv, k); 497 498 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 499 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); 500 501 case SFmode: 502 /* The constant 0.f is easy. */ 503 if (op == CONST0_RTX (SFmode)) 504 return 1; 505 506 /* Force constants to memory before reload to utilize 507 compress_float_constant. 508 Avoid this when flag_unsafe_math_optimizations is enabled 509 because RDIV division to reciprocal optimization is not able 510 to regenerate the division. */ 511 if (!reload_in_progress && !reload_completed 512 && !flag_unsafe_math_optimizations) 513 return 0; 514 515 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); 516 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]); 517 518 return num_insns_constant_wide (k[0]) == 1; 519 520 case DImode: 521 return ((TARGET_POWERPC64 522 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) 523 || (num_insns_constant (op, DImode) <= 2)); 524 525 case SImode: 526 return 1; 527 528 default: 529 gcc_unreachable (); 530 } 531}) 532 533;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a 534;; vector register without using memory. 535(define_predicate "easy_vector_constant" 536 (match_code "const_vector") 537{ 538 /* As the paired vectors are actually FPRs it seems that there is 539 no easy way to load a CONST_VECTOR without using memory. */ 540 if (TARGET_PAIRED_FLOAT) 541 return false; 542 543 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) 544 { 545 if (zero_constant (op, mode)) 546 return true; 547 548 return easy_altivec_constant (op, mode); 549 } 550 551 if (SPE_VECTOR_MODE (mode)) 552 { 553 int cst, cst2; 554 if (zero_constant (op, mode)) 555 return true; 556 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) 557 return false; 558 559 /* Limit SPE vectors to 15 bits signed. These we can generate with: 560 li r0, CONSTANT1 561 evmergelo r0, r0, r0 562 li r0, CONSTANT2 563 564 I don't know how efficient it would be to allow bigger constants, 565 considering we'll have an extra 'ori' for every 'li'. I doubt 5 566 instructions is better than a 64-bit memory load, but I don't 567 have the e500 timing specs. */ 568 if (mode == V2SImode) 569 { 570 cst = INTVAL (CONST_VECTOR_ELT (op, 0)); 571 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); 572 return cst >= -0x7fff && cst <= 0x7fff 573 && cst2 >= -0x7fff && cst2 <= 0x7fff; 574 } 575 } 576 577 return false; 578}) 579 580;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. 581(define_predicate "easy_vector_constant_add_self" 582 (and (match_code "const_vector") 583 (and (match_test "TARGET_ALTIVEC") 584 (match_test "easy_altivec_constant (op, mode)"))) 585{ 586 HOST_WIDE_INT val; 587 int elt; 588 if (mode == V2DImode || mode == V2DFmode) 589 return 0; 590 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; 591 val = const_vector_elt_as_int (op, elt); 592 val = ((val & 0xff) ^ 0x80) - 0x80; 593 return EASY_VECTOR_15_ADD_SELF (val); 594}) 595 596;; Same as easy_vector_constant but only for EASY_VECTOR_MSB. 597(define_predicate "easy_vector_constant_msb" 598 (and (match_code "const_vector") 599 (and (match_test "TARGET_ALTIVEC") 600 (match_test "easy_altivec_constant (op, mode)"))) 601{ 602 HOST_WIDE_INT val; 603 int elt; 604 if (mode == V2DImode || mode == V2DFmode) 605 return 0; 606 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; 607 val = const_vector_elt_as_int (op, elt); 608 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode)); 609}) 610 611;; Return 1 if operand is constant zero (scalars and vectors). 612(define_predicate "zero_constant" 613 (and (match_code "const_int,const_double,const_vector") 614 (match_test "op == CONST0_RTX (mode)"))) 615 616;; Return 1 if operand is 0.0. 617(define_predicate "zero_fp_constant" 618 (and (match_code "const_double") 619 (match_test "SCALAR_FLOAT_MODE_P (mode) 620 && op == CONST0_RTX (mode)"))) 621 622;; Return 1 if the operand is in volatile memory. Note that during the 623;; RTL generation phase, memory_operand does not return TRUE for volatile 624;; memory references. So this function allows us to recognize volatile 625;; references where it's safe. 626(define_predicate "volatile_mem_operand" 627 (and (and (match_code "mem") 628 (match_test "MEM_VOLATILE_P (op)")) 629 (if_then_else (match_test "reload_completed") 630 (match_operand 0 "memory_operand") 631 (if_then_else (match_test "reload_in_progress") 632 (match_test "strict_memory_address_p (mode, XEXP (op, 0))") 633 (match_test "memory_address_p (mode, XEXP (op, 0))"))))) 634 635;; Return 1 if the operand is an offsettable memory operand. 636(define_predicate "offsettable_mem_operand" 637 (and (match_operand 0 "memory_operand") 638 (match_test "offsettable_nonstrict_memref_p (op)"))) 639 640;; Return 1 if the operand is suitable for load/store quad memory. 641;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). 642(define_predicate "quad_memory_operand" 643 (match_code "mem") 644{ 645 rtx addr, op0, op1; 646 int ret; 647 648 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) 649 ret = 0; 650 651 else if (!memory_operand (op, mode)) 652 ret = 0; 653 654 else if (GET_MODE_SIZE (GET_MODE (op)) != 16) 655 ret = 0; 656 657 else if (MEM_ALIGN (op) < 128) 658 ret = 0; 659 660 else 661 { 662 addr = XEXP (op, 0); 663 if (int_reg_operand (addr, Pmode)) 664 ret = 1; 665 666 else if (GET_CODE (addr) != PLUS) 667 ret = 0; 668 669 else 670 { 671 op0 = XEXP (addr, 0); 672 op1 = XEXP (addr, 1); 673 ret = (int_reg_operand (op0, Pmode) 674 && GET_CODE (op1) == CONST_INT 675 && IN_RANGE (INTVAL (op1), -32768, 32767) 676 && (INTVAL (op1) & 15) == 0); 677 } 678 } 679 680 if (TARGET_DEBUG_ADDR) 681 { 682 fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false"); 683 debug_rtx (op); 684 } 685 686 return ret; 687}) 688 689;; Return 1 if the operand is an indexed or indirect memory operand. 690(define_predicate "indexed_or_indirect_operand" 691 (match_code "mem") 692{ 693 op = XEXP (op, 0); 694 if (VECTOR_MEM_ALTIVEC_P (mode) 695 && GET_CODE (op) == AND 696 && GET_CODE (XEXP (op, 1)) == CONST_INT 697 && INTVAL (XEXP (op, 1)) == -16) 698 op = XEXP (op, 0); 699 700 return indexed_or_indirect_address (op, mode); 701}) 702 703;; Like indexed_or_indirect_operand, but also allow a GPR register if direct 704;; moves are supported. 705(define_predicate "reg_or_indexed_operand" 706 (match_code "mem,reg") 707{ 708 if (MEM_P (op)) 709 return indexed_or_indirect_operand (op, mode); 710 else if (TARGET_DIRECT_MOVE) 711 return register_operand (op, mode); 712 return 713 0; 714}) 715 716;; Return 1 if the operand is an indexed or indirect memory operand with an 717;; AND -16 in it, used to recognize when we need to switch to Altivec loads 718;; to realign loops instead of VSX (altivec silently ignores the bottom bits, 719;; while VSX uses the full address and traps) 720(define_predicate "altivec_indexed_or_indirect_operand" 721 (match_code "mem") 722{ 723 op = XEXP (op, 0); 724 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) 725 && GET_CODE (op) == AND 726 && GET_CODE (XEXP (op, 1)) == CONST_INT 727 && INTVAL (XEXP (op, 1)) == -16) 728 return indexed_or_indirect_address (XEXP (op, 0), mode); 729 730 return 0; 731}) 732 733;; Return 1 if the operand is an indexed or indirect address. 734(define_special_predicate "indexed_or_indirect_address" 735 (and (match_test "REG_P (op) 736 || (GET_CODE (op) == PLUS 737 /* Omit testing REG_P (XEXP (op, 0)). */ 738 && REG_P (XEXP (op, 1)))") 739 (match_operand 0 "address_operand"))) 740 741;; Return 1 if the operand is an index-form address. 742(define_special_predicate "indexed_address" 743 (match_test "(GET_CODE (op) == PLUS 744 && REG_P (XEXP (op, 0)) 745 && REG_P (XEXP (op, 1)))")) 746 747;; Return 1 if the operand is a MEM with an update-form address. This may 748;; also include update-indexed form. 749(define_special_predicate "update_address_mem" 750 (match_test "(MEM_P (op) 751 && (GET_CODE (XEXP (op, 0)) == PRE_INC 752 || GET_CODE (XEXP (op, 0)) == PRE_DEC 753 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))")) 754 755;; Return 1 if the operand is a MEM with an update-indexed-form address. Note 756;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the 757;; increment is based on the mode size and will therefor always be a const. 758(define_special_predicate "update_indexed_address_mem" 759 (match_test "(MEM_P (op) 760 && GET_CODE (XEXP (op, 0)) == PRE_MODIFY 761 && indexed_address (XEXP (XEXP (op, 0), 1), mode))")) 762 763;; Used for the destination of the fix_truncdfsi2 expander. 764;; If stfiwx will be used, the result goes to memory; otherwise, 765;; we're going to emit a store and a load of a subreg, so the dest is a 766;; register. 767(define_predicate "fix_trunc_dest_operand" 768 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT") 769 (match_operand 0 "memory_operand") 770 (match_operand 0 "gpc_reg_operand"))) 771 772;; Return 1 if the operand is either a non-special register or can be used 773;; as the operand of a `mode' add insn. 774(define_predicate "add_operand" 775 (if_then_else (match_code "const_int") 776 (match_test "satisfies_constraint_I (op) 777 || satisfies_constraint_L (op)") 778 (match_operand 0 "gpc_reg_operand"))) 779 780;; Return 1 if OP is a constant but not a valid add_operand. 781(define_predicate "non_add_cint_operand" 782 (and (match_code "const_int") 783 (match_test "!satisfies_constraint_I (op) 784 && !satisfies_constraint_L (op)"))) 785 786;; Return 1 if the operand is a constant that can be used as the operand 787;; of an OR or XOR. 788(define_predicate "logical_const_operand" 789 (match_code "const_int,const_double") 790{ 791 HOST_WIDE_INT opl, oph; 792 793 if (GET_CODE (op) == CONST_INT) 794 { 795 opl = INTVAL (op) & GET_MODE_MASK (mode); 796 797 if (HOST_BITS_PER_WIDE_INT <= 32 798 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) 799 return 0; 800 } 801 else if (GET_CODE (op) == CONST_DOUBLE) 802 { 803 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT); 804 805 opl = CONST_DOUBLE_LOW (op); 806 oph = CONST_DOUBLE_HIGH (op); 807 if (oph != 0) 808 return 0; 809 } 810 else 811 return 0; 812 813 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 814 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); 815}) 816 817;; Return 1 if the operand is a non-special register or a constant that 818;; can be used as the operand of an OR or XOR. 819(define_predicate "logical_operand" 820 (ior (match_operand 0 "gpc_reg_operand") 821 (match_operand 0 "logical_const_operand"))) 822 823;; Return 1 if op is a constant that is not a logical operand, but could 824;; be split into one. 825(define_predicate "non_logical_cint_operand" 826 (and (match_code "const_int,const_double") 827 (and (not (match_operand 0 "logical_operand")) 828 (match_operand 0 "reg_or_logical_cint_operand")))) 829 830;; Return 1 if op is a constant that can be encoded in a 32-bit mask, 831;; suitable for use with rlwinm (no more than two 1->0 or 0->1 832;; transitions). Reject all ones and all zeros, since these should have 833;; been optimized away and confuse the making of MB and ME. 834(define_predicate "mask_operand" 835 (match_code "const_int") 836{ 837 HOST_WIDE_INT c, lsb; 838 839 c = INTVAL (op); 840 841 if (TARGET_POWERPC64) 842 { 843 /* Fail if the mask is not 32-bit. */ 844 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0) 845 return 0; 846 847 /* Fail if the mask wraps around because the upper 32-bits of the 848 mask will all be 1s, contrary to GCC's internal view. */ 849 if ((c & 0x80000001) == 0x80000001) 850 return 0; 851 } 852 853 /* We don't change the number of transitions by inverting, 854 so make sure we start with the LS bit zero. */ 855 if (c & 1) 856 c = ~c; 857 858 /* Reject all zeros or all ones. */ 859 if (c == 0) 860 return 0; 861 862 /* Find the first transition. */ 863 lsb = c & -c; 864 865 /* Invert to look for a second transition. */ 866 c = ~c; 867 868 /* Erase first transition. */ 869 c &= -lsb; 870 871 /* Find the second transition (if any). */ 872 lsb = c & -c; 873 874 /* Match if all the bits above are 1's (or c is zero). */ 875 return c == -lsb; 876}) 877 878;; Return 1 for the PowerPC64 rlwinm corner case. 879(define_predicate "mask_operand_wrap" 880 (match_code "const_int") 881{ 882 HOST_WIDE_INT c, lsb; 883 884 c = INTVAL (op); 885 886 if ((c & 0x80000001) != 0x80000001) 887 return 0; 888 889 c = ~c; 890 if (c == 0) 891 return 0; 892 893 lsb = c & -c; 894 c = ~c; 895 c &= -lsb; 896 lsb = c & -c; 897 return c == -lsb; 898}) 899 900;; Return 1 if the operand is a constant that is a PowerPC64 mask 901;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1 902;; transition). Reject all zeros, since zero should have been 903;; optimized away and confuses the making of MB and ME. 904(define_predicate "mask64_operand" 905 (match_code "const_int") 906{ 907 HOST_WIDE_INT c, lsb; 908 909 c = INTVAL (op); 910 911 /* Reject all zeros. */ 912 if (c == 0) 913 return 0; 914 915 /* We don't change the number of transitions by inverting, 916 so make sure we start with the LS bit zero. */ 917 if (c & 1) 918 c = ~c; 919 920 /* Find the first transition. */ 921 lsb = c & -c; 922 923 /* Match if all the bits above are 1's (or c is zero). */ 924 return c == -lsb; 925}) 926 927;; Like mask64_operand, but allow up to three transitions. This 928;; predicate is used by insn patterns that generate two rldicl or 929;; rldicr machine insns. 930(define_predicate "mask64_2_operand" 931 (match_code "const_int") 932{ 933 HOST_WIDE_INT c, lsb; 934 935 c = INTVAL (op); 936 937 /* Disallow all zeros. */ 938 if (c == 0) 939 return 0; 940 941 /* We don't change the number of transitions by inverting, 942 so make sure we start with the LS bit zero. */ 943 if (c & 1) 944 c = ~c; 945 946 /* Find the first transition. */ 947 lsb = c & -c; 948 949 /* Invert to look for a second transition. */ 950 c = ~c; 951 952 /* Erase first transition. */ 953 c &= -lsb; 954 955 /* Find the second transition. */ 956 lsb = c & -c; 957 958 /* Invert to look for a third transition. */ 959 c = ~c; 960 961 /* Erase second transition. */ 962 c &= -lsb; 963 964 /* Find the third transition (if any). */ 965 lsb = c & -c; 966 967 /* Match if all the bits above are 1's (or c is zero). */ 968 return c == -lsb; 969}) 970 971;; Like and_operand, but also match constants that can be implemented 972;; with two rldicl or rldicr insns. 973(define_predicate "and64_2_operand" 974 (ior (match_operand 0 "mask64_2_operand") 975 (if_then_else (match_test "fixed_regs[CR0_REGNO]") 976 (match_operand 0 "gpc_reg_operand") 977 (match_operand 0 "logical_operand")))) 978 979;; Return 1 if the operand is either a non-special register or a 980;; constant that can be used as the operand of a logical AND. 981(define_predicate "and_operand" 982 (ior (match_operand 0 "mask_operand") 983 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode") 984 (match_operand 0 "mask64_operand")) 985 (if_then_else (match_test "fixed_regs[CR0_REGNO]") 986 (match_operand 0 "gpc_reg_operand") 987 (match_operand 0 "logical_operand"))))) 988 989;; Return 1 if the operand is either a logical operand or a short cint operand. 990(define_predicate "scc_eq_operand" 991 (ior (match_operand 0 "logical_operand") 992 (match_operand 0 "short_cint_operand"))) 993 994;; Return 1 if the operand is a general non-special register or memory operand. 995(define_predicate "reg_or_mem_operand" 996 (ior (match_operand 0 "memory_operand") 997 (ior (and (match_code "mem") 998 (match_test "macho_lo_sum_memory_operand (op, mode)")) 999 (ior (match_operand 0 "volatile_mem_operand") 1000 (match_operand 0 "gpc_reg_operand"))))) 1001 1002;; Return 1 if the operand is either an easy FP constant or memory or reg. 1003(define_predicate "reg_or_none500mem_operand" 1004 (if_then_else (match_code "mem") 1005 (and (match_test "!TARGET_E500_DOUBLE") 1006 (ior (match_operand 0 "memory_operand") 1007 (ior (match_test "macho_lo_sum_memory_operand (op, mode)") 1008 (match_operand 0 "volatile_mem_operand")))) 1009 (match_operand 0 "gpc_reg_operand"))) 1010 1011;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand. 1012(define_predicate "zero_reg_mem_operand" 1013 (ior (match_operand 0 "zero_fp_constant") 1014 (match_operand 0 "reg_or_mem_operand"))) 1015 1016;; Return 1 if the operand is a general register or memory operand without 1017;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC 1018;; lwa instruction. 1019(define_predicate "lwa_operand" 1020 (match_code "reg,subreg,mem") 1021{ 1022 rtx inner, addr, offset; 1023 1024 inner = op; 1025 if (reload_completed && GET_CODE (inner) == SUBREG) 1026 inner = SUBREG_REG (inner); 1027 1028 if (gpc_reg_operand (inner, mode)) 1029 return true; 1030 if (!memory_operand (inner, mode)) 1031 return false; 1032 addr = XEXP (inner, 0); 1033 if (GET_CODE (addr) == PRE_INC 1034 || GET_CODE (addr) == PRE_DEC 1035 || (GET_CODE (addr) == PRE_MODIFY 1036 && !legitimate_indexed_address_p (XEXP (addr, 1), 0))) 1037 return false; 1038 if (GET_CODE (addr) == LO_SUM 1039 && GET_CODE (XEXP (addr, 0)) == REG 1040 && GET_CODE (XEXP (addr, 1)) == CONST) 1041 addr = XEXP (XEXP (addr, 1), 0); 1042 if (GET_CODE (addr) != PLUS) 1043 return true; 1044 offset = XEXP (addr, 1); 1045 if (GET_CODE (offset) != CONST_INT) 1046 return true; 1047 return INTVAL (offset) % 4 == 0; 1048}) 1049 1050;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. 1051(define_predicate "symbol_ref_operand" 1052 (and (match_code "symbol_ref") 1053 (match_test "(mode == VOIDmode || GET_MODE (op) == mode) 1054 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))"))) 1055 1056;; Return 1 if op is an operand that can be loaded via the GOT. 1057;; or non-special register register field no cr0 1058(define_predicate "got_operand" 1059 (match_code "symbol_ref,const,label_ref")) 1060 1061;; Return 1 if op is a simple reference that can be loaded via the GOT, 1062;; excluding labels involving addition. 1063(define_predicate "got_no_const_operand" 1064 (match_code "symbol_ref,label_ref")) 1065 1066;; Return 1 if op is a SYMBOL_REF for a TLS symbol. 1067(define_predicate "rs6000_tls_symbol_ref" 1068 (and (match_code "symbol_ref") 1069 (match_test "RS6000_SYMBOL_REF_TLS_P (op)"))) 1070 1071;; Return 1 if the operand, used inside a MEM, is a valid first argument 1072;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. 1073(define_predicate "call_operand" 1074 (if_then_else (match_code "reg") 1075 (match_test "REGNO (op) == LR_REGNO 1076 || REGNO (op) == CTR_REGNO 1077 || REGNO (op) >= FIRST_PSEUDO_REGISTER") 1078 (match_code "symbol_ref"))) 1079 1080;; Return 1 if the operand is a SYMBOL_REF for a function known to be in 1081;; this file. 1082(define_predicate "current_file_function_operand" 1083 (and (match_code "symbol_ref") 1084 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) 1085 && ((SYMBOL_REF_LOCAL_P (op) 1086 && ((DEFAULT_ABI != ABI_AIX 1087 && DEFAULT_ABI != ABI_ELFv2) 1088 || !SYMBOL_REF_EXTERNAL_P (op))) 1089 || (op == XEXP (DECL_RTL (current_function_decl), 1090 0)))"))) 1091 1092;; Return 1 if this operand is a valid input for a move insn. 1093(define_predicate "input_operand" 1094 (match_code "symbol_ref,const,reg,subreg,mem, 1095 const_double,const_vector,const_int") 1096{ 1097 /* Memory is always valid. */ 1098 if (memory_operand (op, mode)) 1099 return 1; 1100 1101 /* For floating-point, easy constants are valid. */ 1102 if (SCALAR_FLOAT_MODE_P (mode) 1103 && easy_fp_constant (op, mode)) 1104 return 1; 1105 1106 /* Allow any integer constant. */ 1107 if (GET_MODE_CLASS (mode) == MODE_INT 1108 && (GET_CODE (op) == CONST_INT 1109 || GET_CODE (op) == CONST_DOUBLE)) 1110 return 1; 1111 1112 /* Allow easy vector constants. */ 1113 if (GET_CODE (op) == CONST_VECTOR 1114 && easy_vector_constant (op, mode)) 1115 return 1; 1116 1117 /* Do not allow invalid E500 subregs. */ 1118 if ((TARGET_E500_DOUBLE || TARGET_SPE) 1119 && GET_CODE (op) == SUBREG 1120 && invalid_e500_subreg (op, mode)) 1121 return 0; 1122 1123 /* For floating-point or multi-word mode, the only remaining valid type 1124 is a register. */ 1125 if (SCALAR_FLOAT_MODE_P (mode) 1126 || GET_MODE_SIZE (mode) > UNITS_PER_WORD) 1127 return register_operand (op, mode); 1128 1129 /* The only cases left are integral modes one word or smaller (we 1130 do not get called for MODE_CC values). These can be in any 1131 register. */ 1132 if (register_operand (op, mode)) 1133 return 1; 1134 1135 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region 1136 to be valid. */ 1137 if (DEFAULT_ABI == ABI_V4 1138 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) 1139 && small_data_operand (op, Pmode)) 1140 return 1; 1141 1142 return 0; 1143}) 1144 1145;; Return 1 if this operand is a valid input for a vsx_splat insn. 1146(define_predicate "splat_input_operand" 1147 (match_code "symbol_ref,const,reg,subreg,mem, 1148 const_double,const_vector,const_int") 1149{ 1150 if (MEM_P (op)) 1151 { 1152 if (! volatile_ok && MEM_VOLATILE_P (op)) 1153 return 0; 1154 if (mode == DFmode) 1155 mode = V2DFmode; 1156 else if (mode == DImode) 1157 mode = V2DImode; 1158 else 1159 gcc_unreachable (); 1160 return memory_address_addr_space_p (mode, XEXP (op, 0), 1161 MEM_ADDR_SPACE (op)); 1162 } 1163 return input_operand (op, mode); 1164}) 1165 1166;; Return true if OP is a non-immediate operand and not an invalid 1167;; SUBREG operation on the e500. 1168(define_predicate "rs6000_nonimmediate_operand" 1169 (match_code "reg,subreg,mem") 1170{ 1171 if ((TARGET_E500_DOUBLE || TARGET_SPE) 1172 && GET_CODE (op) == SUBREG 1173 && invalid_e500_subreg (op, mode)) 1174 return 0; 1175 1176 return nonimmediate_operand (op, mode); 1177}) 1178 1179;; Return true if operand is boolean operator. 1180(define_predicate "boolean_operator" 1181 (match_code "and,ior,xor")) 1182 1183;; Return true if operand is OR-form of boolean operator. 1184(define_predicate "boolean_or_operator" 1185 (match_code "ior,xor")) 1186 1187;; Return true if operand is an equality operator. 1188(define_special_predicate "equality_operator" 1189 (match_code "eq,ne")) 1190 1191;; Return true if operand is MIN or MAX operator. 1192(define_predicate "min_max_operator" 1193 (match_code "smin,smax,umin,umax")) 1194 1195;; Return 1 if OP is a comparison operation that is valid for a branch 1196;; instruction. We check the opcode against the mode of the CC value. 1197;; validate_condition_mode is an assertion. 1198(define_predicate "branch_comparison_operator" 1199 (and (match_operand 0 "comparison_operator") 1200 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC") 1201 (match_test "validate_condition_mode (GET_CODE (op), 1202 GET_MODE (XEXP (op, 0))), 1203 1")))) 1204 1205(define_predicate "rs6000_cbranch_operator" 1206 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS") 1207 (match_operand 0 "ordered_comparison_operator") 1208 (match_operand 0 "comparison_operator"))) 1209 1210;; Return 1 if OP is a comparison operation that is valid for an SCC insn -- 1211;; it must be a positive comparison. 1212(define_predicate "scc_comparison_operator" 1213 (and (match_operand 0 "branch_comparison_operator") 1214 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 1215 1216;; Return 1 if OP is a comparison operation whose inverse would be valid for 1217;; an SCC insn. 1218(define_predicate "scc_rev_comparison_operator" 1219 (and (match_operand 0 "branch_comparison_operator") 1220 (match_code "ne,le,ge,leu,geu,ordered"))) 1221 1222;; Return 1 if OP is a comparison operation that is valid for a branch 1223;; insn, which is true if the corresponding bit in the CC register is set. 1224(define_predicate "branch_positive_comparison_operator" 1225 (and (match_operand 0 "branch_comparison_operator") 1226 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 1227 1228;; Return 1 if OP is a load multiple operation, known to be a PARALLEL. 1229(define_predicate "load_multiple_operation" 1230 (match_code "parallel") 1231{ 1232 int count = XVECLEN (op, 0); 1233 unsigned int dest_regno; 1234 rtx src_addr; 1235 int i; 1236 1237 /* Perform a quick check so we don't blow up below. */ 1238 if (count <= 1 1239 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1240 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 1241 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) 1242 return 0; 1243 1244 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1245 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); 1246 1247 for (i = 1; i < count; i++) 1248 { 1249 rtx elt = XVECEXP (op, 0, i); 1250 1251 if (GET_CODE (elt) != SET 1252 || GET_CODE (SET_DEST (elt)) != REG 1253 || GET_MODE (SET_DEST (elt)) != SImode 1254 || REGNO (SET_DEST (elt)) != dest_regno + i 1255 || GET_CODE (SET_SRC (elt)) != MEM 1256 || GET_MODE (SET_SRC (elt)) != SImode 1257 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS 1258 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) 1259 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT 1260 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) 1261 return 0; 1262 } 1263 1264 return 1; 1265}) 1266 1267;; Return 1 if OP is a store multiple operation, known to be a PARALLEL. 1268;; The second vector element is a CLOBBER. 1269(define_predicate "store_multiple_operation" 1270 (match_code "parallel") 1271{ 1272 int count = XVECLEN (op, 0) - 1; 1273 unsigned int src_regno; 1274 rtx dest_addr; 1275 int i; 1276 1277 /* Perform a quick check so we don't blow up below. */ 1278 if (count <= 1 1279 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1280 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM 1281 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) 1282 return 0; 1283 1284 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 1285 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); 1286 1287 for (i = 1; i < count; i++) 1288 { 1289 rtx elt = XVECEXP (op, 0, i + 1); 1290 1291 if (GET_CODE (elt) != SET 1292 || GET_CODE (SET_SRC (elt)) != REG 1293 || GET_MODE (SET_SRC (elt)) != SImode 1294 || REGNO (SET_SRC (elt)) != src_regno + i 1295 || GET_CODE (SET_DEST (elt)) != MEM 1296 || GET_MODE (SET_DEST (elt)) != SImode 1297 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS 1298 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) 1299 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT 1300 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) 1301 return 0; 1302 } 1303 1304 return 1; 1305}) 1306 1307;; Return 1 if OP is valid for a save_world call in prologue, known to be 1308;; a PARLLEL. 1309(define_predicate "save_world_operation" 1310 (match_code "parallel") 1311{ 1312 int index; 1313 int i; 1314 rtx elt; 1315 int count = XVECLEN (op, 0); 1316 1317 if (count != 54) 1318 return 0; 1319 1320 index = 0; 1321 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1322 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 1323 return 0; 1324 1325 for (i=1; i <= 18; i++) 1326 { 1327 elt = XVECEXP (op, 0, index++); 1328 if (GET_CODE (elt) != SET 1329 || GET_CODE (SET_DEST (elt)) != MEM 1330 || ! memory_operand (SET_DEST (elt), DFmode) 1331 || GET_CODE (SET_SRC (elt)) != REG 1332 || GET_MODE (SET_SRC (elt)) != DFmode) 1333 return 0; 1334 } 1335 1336 for (i=1; i <= 12; i++) 1337 { 1338 elt = XVECEXP (op, 0, index++); 1339 if (GET_CODE (elt) != SET 1340 || GET_CODE (SET_DEST (elt)) != MEM 1341 || GET_CODE (SET_SRC (elt)) != REG 1342 || GET_MODE (SET_SRC (elt)) != V4SImode) 1343 return 0; 1344 } 1345 1346 for (i=1; i <= 19; i++) 1347 { 1348 elt = XVECEXP (op, 0, index++); 1349 if (GET_CODE (elt) != SET 1350 || GET_CODE (SET_DEST (elt)) != MEM 1351 || ! memory_operand (SET_DEST (elt), Pmode) 1352 || GET_CODE (SET_SRC (elt)) != REG 1353 || GET_MODE (SET_SRC (elt)) != Pmode) 1354 return 0; 1355 } 1356 1357 elt = XVECEXP (op, 0, index++); 1358 if (GET_CODE (elt) != SET 1359 || GET_CODE (SET_DEST (elt)) != MEM 1360 || ! memory_operand (SET_DEST (elt), Pmode) 1361 || GET_CODE (SET_SRC (elt)) != REG 1362 || REGNO (SET_SRC (elt)) != CR2_REGNO 1363 || GET_MODE (SET_SRC (elt)) != Pmode) 1364 return 0; 1365 1366 if (GET_CODE (XVECEXP (op, 0, index++)) != SET 1367 || GET_CODE (XVECEXP (op, 0, index++)) != SET) 1368 return 0; 1369 return 1; 1370}) 1371 1372;; Return 1 if OP is valid for a restore_world call in epilogue, known to be 1373;; a PARLLEL. 1374(define_predicate "restore_world_operation" 1375 (match_code "parallel") 1376{ 1377 int index; 1378 int i; 1379 rtx elt; 1380 int count = XVECLEN (op, 0); 1381 1382 if (count != 59) 1383 return 0; 1384 1385 index = 0; 1386 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN 1387 || GET_CODE (XVECEXP (op, 0, index++)) != USE 1388 || GET_CODE (XVECEXP (op, 0, index++)) != USE 1389 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) 1390 return 0; 1391 1392 elt = XVECEXP (op, 0, index++); 1393 if (GET_CODE (elt) != SET 1394 || GET_CODE (SET_SRC (elt)) != MEM 1395 || ! memory_operand (SET_SRC (elt), Pmode) 1396 || GET_CODE (SET_DEST (elt)) != REG 1397 || REGNO (SET_DEST (elt)) != CR2_REGNO 1398 || GET_MODE (SET_DEST (elt)) != Pmode) 1399 return 0; 1400 1401 for (i=1; i <= 19; i++) 1402 { 1403 elt = XVECEXP (op, 0, index++); 1404 if (GET_CODE (elt) != SET 1405 || GET_CODE (SET_SRC (elt)) != MEM 1406 || ! memory_operand (SET_SRC (elt), Pmode) 1407 || GET_CODE (SET_DEST (elt)) != REG 1408 || GET_MODE (SET_DEST (elt)) != Pmode) 1409 return 0; 1410 } 1411 1412 for (i=1; i <= 12; i++) 1413 { 1414 elt = XVECEXP (op, 0, index++); 1415 if (GET_CODE (elt) != SET 1416 || GET_CODE (SET_SRC (elt)) != MEM 1417 || GET_CODE (SET_DEST (elt)) != REG 1418 || GET_MODE (SET_DEST (elt)) != V4SImode) 1419 return 0; 1420 } 1421 1422 for (i=1; i <= 18; i++) 1423 { 1424 elt = XVECEXP (op, 0, index++); 1425 if (GET_CODE (elt) != SET 1426 || GET_CODE (SET_SRC (elt)) != MEM 1427 || ! memory_operand (SET_SRC (elt), DFmode) 1428 || GET_CODE (SET_DEST (elt)) != REG 1429 || GET_MODE (SET_DEST (elt)) != DFmode) 1430 return 0; 1431 } 1432 1433 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1434 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1435 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1436 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1437 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 1438 return 0; 1439 return 1; 1440}) 1441 1442;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL. 1443(define_predicate "vrsave_operation" 1444 (match_code "parallel") 1445{ 1446 int count = XVECLEN (op, 0); 1447 unsigned int dest_regno, src_regno; 1448 int i; 1449 1450 if (count <= 1 1451 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1452 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 1453 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE 1454 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE) 1455 return 0; 1456 1457 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1458 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); 1459 1460 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) 1461 return 0; 1462 1463 for (i = 1; i < count; i++) 1464 { 1465 rtx elt = XVECEXP (op, 0, i); 1466 1467 if (GET_CODE (elt) != CLOBBER 1468 && GET_CODE (elt) != SET) 1469 return 0; 1470 } 1471 1472 return 1; 1473}) 1474 1475;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL. 1476(define_predicate "mfcr_operation" 1477 (match_code "parallel") 1478{ 1479 int count = XVECLEN (op, 0); 1480 int i; 1481 1482 /* Perform a quick check so we don't blow up below. */ 1483 if (count < 1 1484 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1485 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1486 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1487 return 0; 1488 1489 for (i = 0; i < count; i++) 1490 { 1491 rtx exp = XVECEXP (op, 0, i); 1492 rtx unspec; 1493 int maskval; 1494 rtx src_reg; 1495 1496 src_reg = XVECEXP (SET_SRC (exp), 0, 0); 1497 1498 if (GET_CODE (src_reg) != REG 1499 || GET_MODE (src_reg) != CCmode 1500 || ! CR_REGNO_P (REGNO (src_reg))) 1501 return 0; 1502 1503 if (GET_CODE (exp) != SET 1504 || GET_CODE (SET_DEST (exp)) != REG 1505 || GET_MODE (SET_DEST (exp)) != SImode 1506 || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) 1507 return 0; 1508 unspec = SET_SRC (exp); 1509 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); 1510 1511 if (GET_CODE (unspec) != UNSPEC 1512 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR 1513 || XVECLEN (unspec, 0) != 2 1514 || XVECEXP (unspec, 0, 0) != src_reg 1515 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT 1516 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1517 return 0; 1518 } 1519 return 1; 1520}) 1521 1522;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL. 1523(define_predicate "mtcrf_operation" 1524 (match_code "parallel") 1525{ 1526 int count = XVECLEN (op, 0); 1527 int i; 1528 rtx src_reg; 1529 1530 /* Perform a quick check so we don't blow up below. */ 1531 if (count < 1 1532 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1533 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1534 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1535 return 0; 1536 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); 1537 1538 if (GET_CODE (src_reg) != REG 1539 || GET_MODE (src_reg) != SImode 1540 || ! INT_REGNO_P (REGNO (src_reg))) 1541 return 0; 1542 1543 for (i = 0; i < count; i++) 1544 { 1545 rtx exp = XVECEXP (op, 0, i); 1546 rtx unspec; 1547 int maskval; 1548 1549 if (GET_CODE (exp) != SET 1550 || GET_CODE (SET_DEST (exp)) != REG 1551 || GET_MODE (SET_DEST (exp)) != CCmode 1552 || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) 1553 return 0; 1554 unspec = SET_SRC (exp); 1555 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); 1556 1557 if (GET_CODE (unspec) != UNSPEC 1558 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR 1559 || XVECLEN (unspec, 0) != 2 1560 || XVECEXP (unspec, 0, 0) != src_reg 1561 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT 1562 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1563 return 0; 1564 } 1565 return 1; 1566}) 1567 1568;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL. 1569(define_predicate "crsave_operation" 1570 (match_code "parallel") 1571{ 1572 int count = XVECLEN (op, 0); 1573 int i; 1574 1575 for (i = 1; i < count; i++) 1576 { 1577 rtx exp = XVECEXP (op, 0, i); 1578 1579 if (GET_CODE (exp) != USE 1580 || GET_CODE (XEXP (exp, 0)) != REG 1581 || GET_MODE (XEXP (exp, 0)) != CCmode 1582 || ! CR_REGNO_P (REGNO (XEXP (exp, 0)))) 1583 return 0; 1584 } 1585 return 1; 1586}) 1587 1588;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. 1589(define_predicate "lmw_operation" 1590 (match_code "parallel") 1591{ 1592 int count = XVECLEN (op, 0); 1593 unsigned int dest_regno; 1594 rtx src_addr; 1595 unsigned int base_regno; 1596 HOST_WIDE_INT offset; 1597 int i; 1598 1599 /* Perform a quick check so we don't blow up below. */ 1600 if (count <= 1 1601 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1602 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 1603 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) 1604 return 0; 1605 1606 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1607 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); 1608 1609 if (dest_regno > 31 1610 || count != 32 - (int) dest_regno) 1611 return 0; 1612 1613 if (legitimate_indirect_address_p (src_addr, 0)) 1614 { 1615 offset = 0; 1616 base_regno = REGNO (src_addr); 1617 if (base_regno == 0) 1618 return 0; 1619 } 1620 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false)) 1621 { 1622 offset = INTVAL (XEXP (src_addr, 1)); 1623 base_regno = REGNO (XEXP (src_addr, 0)); 1624 } 1625 else 1626 return 0; 1627 1628 for (i = 0; i < count; i++) 1629 { 1630 rtx elt = XVECEXP (op, 0, i); 1631 rtx newaddr; 1632 rtx addr_reg; 1633 HOST_WIDE_INT newoffset; 1634 1635 if (GET_CODE (elt) != SET 1636 || GET_CODE (SET_DEST (elt)) != REG 1637 || GET_MODE (SET_DEST (elt)) != SImode 1638 || REGNO (SET_DEST (elt)) != dest_regno + i 1639 || GET_CODE (SET_SRC (elt)) != MEM 1640 || GET_MODE (SET_SRC (elt)) != SImode) 1641 return 0; 1642 newaddr = XEXP (SET_SRC (elt), 0); 1643 if (legitimate_indirect_address_p (newaddr, 0)) 1644 { 1645 newoffset = 0; 1646 addr_reg = newaddr; 1647 } 1648 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) 1649 { 1650 addr_reg = XEXP (newaddr, 0); 1651 newoffset = INTVAL (XEXP (newaddr, 1)); 1652 } 1653 else 1654 return 0; 1655 if (REGNO (addr_reg) != base_regno 1656 || newoffset != offset + 4 * i) 1657 return 0; 1658 } 1659 1660 return 1; 1661}) 1662 1663;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL. 1664(define_predicate "stmw_operation" 1665 (match_code "parallel") 1666{ 1667 int count = XVECLEN (op, 0); 1668 unsigned int src_regno; 1669 rtx dest_addr; 1670 unsigned int base_regno; 1671 HOST_WIDE_INT offset; 1672 int i; 1673 1674 /* Perform a quick check so we don't blow up below. */ 1675 if (count <= 1 1676 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1677 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM 1678 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) 1679 return 0; 1680 1681 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 1682 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); 1683 1684 if (src_regno > 31 1685 || count != 32 - (int) src_regno) 1686 return 0; 1687 1688 if (legitimate_indirect_address_p (dest_addr, 0)) 1689 { 1690 offset = 0; 1691 base_regno = REGNO (dest_addr); 1692 if (base_regno == 0) 1693 return 0; 1694 } 1695 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false)) 1696 { 1697 offset = INTVAL (XEXP (dest_addr, 1)); 1698 base_regno = REGNO (XEXP (dest_addr, 0)); 1699 } 1700 else 1701 return 0; 1702 1703 for (i = 0; i < count; i++) 1704 { 1705 rtx elt = XVECEXP (op, 0, i); 1706 rtx newaddr; 1707 rtx addr_reg; 1708 HOST_WIDE_INT newoffset; 1709 1710 if (GET_CODE (elt) != SET 1711 || GET_CODE (SET_SRC (elt)) != REG 1712 || GET_MODE (SET_SRC (elt)) != SImode 1713 || REGNO (SET_SRC (elt)) != src_regno + i 1714 || GET_CODE (SET_DEST (elt)) != MEM 1715 || GET_MODE (SET_DEST (elt)) != SImode) 1716 return 0; 1717 newaddr = XEXP (SET_DEST (elt), 0); 1718 if (legitimate_indirect_address_p (newaddr, 0)) 1719 { 1720 newoffset = 0; 1721 addr_reg = newaddr; 1722 } 1723 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) 1724 { 1725 addr_reg = XEXP (newaddr, 0); 1726 newoffset = INTVAL (XEXP (newaddr, 1)); 1727 } 1728 else 1729 return 0; 1730 if (REGNO (addr_reg) != base_regno 1731 || newoffset != offset + 4 * i) 1732 return 0; 1733 } 1734 1735 return 1; 1736}) 1737 1738;; Return 1 if OP is a stack tie operand. 1739(define_predicate "tie_operand" 1740 (match_code "parallel") 1741{ 1742 return (GET_CODE (XVECEXP (op, 0, 0)) == SET 1743 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM 1744 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode 1745 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx); 1746}) 1747 1748;; Match a small code model toc reference (or medium and large 1749;; model toc references before reload). 1750(define_predicate "small_toc_ref" 1751 (match_code "unspec,plus") 1752{ 1753 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode)) 1754 op = XEXP (op, 0); 1755 1756 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; 1757}) 1758 1759;; Match the first insn (addis) in fusing the combination of addis and loads to 1760;; GPR registers on power8. 1761(define_predicate "fusion_gpr_addis" 1762 (match_code "const_int,high,plus") 1763{ 1764 HOST_WIDE_INT value; 1765 rtx int_const; 1766 1767 if (GET_CODE (op) == HIGH) 1768 return 1; 1769 1770 if (CONST_INT_P (op)) 1771 int_const = op; 1772 1773 else if (GET_CODE (op) == PLUS 1774 && base_reg_operand (XEXP (op, 0), Pmode) 1775 && CONST_INT_P (XEXP (op, 1))) 1776 int_const = XEXP (op, 1); 1777 1778 else 1779 return 0; 1780 1781 /* Power8 currently will only do the fusion if the top 11 bits of the addis 1782 value are all 1's or 0's. */ 1783 value = INTVAL (int_const); 1784 if ((value & (HOST_WIDE_INT)0xffff) != 0) 1785 return 0; 1786 1787 if ((value & (HOST_WIDE_INT)0xffff0000) == 0) 1788 return 0; 1789 1790 return (IN_RANGE (value >> 16, -32, 31)); 1791}) 1792 1793;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis 1794;; and loads to GPR registers on power8. 1795(define_predicate "fusion_gpr_mem_load" 1796 (match_code "mem,sign_extend,zero_extend") 1797{ 1798 rtx addr, base, offset; 1799 1800 /* Handle sign/zero extend. */ 1801 if (GET_CODE (op) == ZERO_EXTEND 1802 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND)) 1803 { 1804 op = XEXP (op, 0); 1805 mode = GET_MODE (op); 1806 } 1807 1808 if (!MEM_P (op)) 1809 return 0; 1810 1811 switch (mode) 1812 { 1813 case QImode: 1814 case HImode: 1815 case SImode: 1816 break; 1817 1818 case DImode: 1819 if (!TARGET_POWERPC64) 1820 return 0; 1821 break; 1822 1823 default: 1824 return 0; 1825 } 1826 1827 addr = XEXP (op, 0); 1828 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 1829 return 0; 1830 1831 base = XEXP (addr, 0); 1832 if (!base_reg_operand (base, GET_MODE (base))) 1833 return 0; 1834 1835 offset = XEXP (addr, 1); 1836 1837 if (GET_CODE (addr) == PLUS) 1838 return satisfies_constraint_I (offset); 1839 1840 else if (GET_CODE (addr) == LO_SUM) 1841 { 1842 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) 1843 return small_toc_ref (offset, GET_MODE (offset)); 1844 1845 else if (TARGET_ELF && !TARGET_POWERPC64) 1846 return CONSTANT_P (offset); 1847 } 1848 1849 return 0; 1850}) 1851 1852;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the 1853;; memory field with both the addis and the memory offset. Sign extension 1854;; is not handled here, since lha and lwa are not fused. 1855(define_predicate "fusion_gpr_mem_combo" 1856 (match_code "mem,zero_extend") 1857{ 1858 rtx addr, base, offset; 1859 1860 /* Handle zero extend. */ 1861 if (GET_CODE (op) == ZERO_EXTEND) 1862 { 1863 op = XEXP (op, 0); 1864 mode = GET_MODE (op); 1865 } 1866 1867 if (!MEM_P (op)) 1868 return 0; 1869 1870 switch (mode) 1871 { 1872 case QImode: 1873 case HImode: 1874 case SImode: 1875 break; 1876 1877 case DImode: 1878 if (!TARGET_POWERPC64) 1879 return 0; 1880 break; 1881 1882 default: 1883 return 0; 1884 } 1885 1886 addr = XEXP (op, 0); 1887 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 1888 return 0; 1889 1890 base = XEXP (addr, 0); 1891 if (!fusion_gpr_addis (base, GET_MODE (base))) 1892 return 0; 1893 1894 offset = XEXP (addr, 1); 1895 if (GET_CODE (addr) == PLUS) 1896 return satisfies_constraint_I (offset); 1897 1898 else if (GET_CODE (addr) == LO_SUM) 1899 { 1900 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) 1901 return small_toc_ref (offset, GET_MODE (offset)); 1902 1903 else if (TARGET_ELF && !TARGET_POWERPC64) 1904 return CONSTANT_P (offset); 1905 } 1906 1907 return 0; 1908}) 1909