1 /* Definitions of target machine for GNU compiler, for IBM S/390 2 Copyright (C) 1999-2013 Free Software Foundation, Inc. 3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4 Ulrich Weigand (uweigand@de.ibm.com). 5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com) 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it under 10 the terms of the GNU General Public License as published by the Free 11 Software Foundation; either version 3, or (at your option) any later 12 version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15 WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #ifndef _S390_H 24 #define _S390_H 25 26 /* Optional architectural facilities supported by the processor. */ 27 28 enum processor_flags 29 { 30 PF_IEEE_FLOAT = 1, 31 PF_ZARCH = 2, 32 PF_LONG_DISPLACEMENT = 4, 33 PF_EXTIMM = 8, 34 PF_DFP = 16, 35 PF_Z10 = 32, 36 PF_Z196 = 64, 37 PF_ZEC12 = 128, 38 PF_TX = 256 39 }; 40 41 /* This is necessary to avoid a warning about comparing different enum 42 types. */ 43 #define s390_tune_attr ((enum attr_cpu)s390_tune) 44 45 /* These flags indicate that the generated code should run on a cpu 46 providing the respective hardware facility regardless of the 47 current cpu mode (ESA or z/Architecture). */ 48 49 #define TARGET_CPU_IEEE_FLOAT \ 50 (s390_arch_flags & PF_IEEE_FLOAT) 51 #define TARGET_CPU_ZARCH \ 52 (s390_arch_flags & PF_ZARCH) 53 #define TARGET_CPU_LONG_DISPLACEMENT \ 54 (s390_arch_flags & PF_LONG_DISPLACEMENT) 55 #define TARGET_CPU_EXTIMM \ 56 (s390_arch_flags & PF_EXTIMM) 57 #define TARGET_CPU_DFP \ 58 (s390_arch_flags & PF_DFP) 59 #define TARGET_CPU_Z10 \ 60 (s390_arch_flags & PF_Z10) 61 #define TARGET_CPU_Z196 \ 62 (s390_arch_flags & PF_Z196) 63 #define TARGET_CPU_ZEC12 \ 64 (s390_arch_flags & PF_ZEC12) 65 #define TARGET_CPU_HTM \ 66 (s390_arch_flags & PF_TX) 67 68 /* These flags indicate that the generated code should run on a cpu 69 providing the respective hardware facility when run in 70 z/Architecture mode. */ 71 72 #define TARGET_LONG_DISPLACEMENT \ 73 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) 74 #define TARGET_EXTIMM \ 75 (TARGET_ZARCH && TARGET_CPU_EXTIMM) 76 #define TARGET_DFP \ 77 (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) 78 #define TARGET_Z10 \ 79 (TARGET_ZARCH && TARGET_CPU_Z10) 80 #define TARGET_Z196 \ 81 (TARGET_ZARCH && TARGET_CPU_Z196) 82 #define TARGET_ZEC12 \ 83 (TARGET_ZARCH && TARGET_CPU_ZEC12) 84 #define TARGET_HTM (TARGET_OPT_HTM) 85 86 87 #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) 88 89 /* Run-time target specification. */ 90 91 /* Defaults for option flags defined only on some subtargets. */ 92 #ifndef TARGET_TPF_PROFILING 93 #define TARGET_TPF_PROFILING 0 94 #endif 95 96 /* This will be overridden by OS headers. */ 97 #define TARGET_TPF 0 98 99 /* Target CPU builtins. */ 100 #define TARGET_CPU_CPP_BUILTINS() \ 101 do \ 102 { \ 103 builtin_assert ("cpu=s390"); \ 104 builtin_assert ("machine=s390"); \ 105 builtin_define ("__s390__"); \ 106 if (TARGET_ZARCH) \ 107 builtin_define ("__zarch__"); \ 108 if (TARGET_64BIT) \ 109 builtin_define ("__s390x__"); \ 110 if (TARGET_LONG_DOUBLE_128) \ 111 builtin_define ("__LONG_DOUBLE_128__"); \ 112 if (TARGET_HTM) \ 113 builtin_define ("__HTM__"); \ 114 } \ 115 while (0) 116 117 #ifdef DEFAULT_TARGET_64BIT 118 #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP | MASK_OPT_HTM) 119 #else 120 #define TARGET_DEFAULT 0 121 #endif 122 123 /* Support for configure-time defaults. */ 124 #define OPTION_DEFAULT_SPECS \ 125 { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ 126 { "arch", "%{!march=*:-march=%(VALUE)}" }, \ 127 { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } 128 129 /* Defaulting rules. */ 130 #ifdef DEFAULT_TARGET_64BIT 131 #define DRIVER_SELF_SPECS \ 132 "%{!m31:%{!m64:-m64}}", \ 133 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ 134 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" 135 #else 136 #define DRIVER_SELF_SPECS \ 137 "%{!m31:%{!m64:-m31}}", \ 138 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ 139 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" 140 #endif 141 142 /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ 143 #define S390_TDC_POSITIVE_ZERO (1 << 11) 144 #define S390_TDC_NEGATIVE_ZERO (1 << 10) 145 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) 146 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) 147 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) 148 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) 149 #define S390_TDC_POSITIVE_INFINITY (1 << 5) 150 #define S390_TDC_NEGATIVE_INFINITY (1 << 4) 151 #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) 152 #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) 153 #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) 154 #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) 155 156 /* The following values are different for DFP. */ 157 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) 158 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) 159 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) 160 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) 161 162 /* For signbit, the BFP-DFP-difference makes no difference. */ 163 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ 164 | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ 165 | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ 166 | S390_TDC_NEGATIVE_INFINITY \ 167 | S390_TDC_NEGATIVE_QUIET_NAN \ 168 | S390_TDC_NEGATIVE_SIGNALING_NAN ) 169 170 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ 171 | S390_TDC_NEGATIVE_INFINITY ) 172 173 /* This is used by float.h to define the float_t and double_t data 174 types. For historical reasons both are double on s390 what cannot 175 be changed anymore. */ 176 #define TARGET_FLT_EVAL_METHOD 1 177 178 /* Target machine storage layout. */ 179 180 /* Everything is big-endian. */ 181 #define BITS_BIG_ENDIAN 1 182 #define BYTES_BIG_ENDIAN 1 183 #define WORDS_BIG_ENDIAN 1 184 185 #define STACK_SIZE_MODE (Pmode) 186 187 #ifndef IN_LIBGCC2 188 189 /* Width of a word, in units (bytes). */ 190 #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) 191 192 /* Width of a pointer. To be used instead of UNITS_PER_WORD in 193 ABI-relevant contexts. This always matches 194 GET_MODE_SIZE (Pmode). */ 195 #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) 196 #define MIN_UNITS_PER_WORD 4 197 #define MAX_BITS_PER_WORD 64 198 #else 199 200 /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether 201 the library should export TImode functions or not. Thus, we have 202 to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ 203 #ifdef __s390x__ 204 #define UNITS_PER_WORD 8 205 #else 206 #define UNITS_PER_WORD 4 207 #endif 208 #endif 209 210 /* Width of a pointer, in bits. */ 211 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) 212 213 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 214 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) 215 216 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 217 #define STACK_BOUNDARY 64 218 219 /* Allocation boundary (in *bits*) for the code of a function. */ 220 #define FUNCTION_BOUNDARY 64 221 222 /* There is no point aligning anything to a rounder boundary than this. */ 223 #define BIGGEST_ALIGNMENT 64 224 225 /* Alignment of field after `int : 0' in a structure. */ 226 #define EMPTY_FIELD_BOUNDARY 32 227 228 /* Alignment on even addresses for LARL instruction. */ 229 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) 230 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) 231 232 /* Alignment is not required by the hardware. */ 233 #define STRICT_ALIGNMENT 0 234 235 /* Mode of stack savearea. 236 FUNCTION is VOIDmode because calling convention maintains SP. 237 BLOCK needs Pmode for SP. 238 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 239 #define STACK_SAVEAREA_MODE(LEVEL) \ 240 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 241 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) 242 243 244 /* Type layout. */ 245 246 /* Sizes in bits of the source language data types. */ 247 #define SHORT_TYPE_SIZE 16 248 #define INT_TYPE_SIZE 32 249 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) 250 #define LONG_LONG_TYPE_SIZE 64 251 #define FLOAT_TYPE_SIZE 32 252 #define DOUBLE_TYPE_SIZE 64 253 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) 254 255 /* Define this to set long double type size to use in libgcc2.c, which can 256 not depend on target_flags. */ 257 #ifdef __LONG_DOUBLE_128__ 258 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 259 #else 260 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 261 #endif 262 263 /* Work around target_flags dependency in ada/targtyps.c. */ 264 #define WIDEST_HARDWARE_FP_SIZE 64 265 266 /* We use "unsigned char" as default. */ 267 #define DEFAULT_SIGNED_CHAR 0 268 269 270 /* Register usage. */ 271 272 /* We have 16 general purpose registers (registers 0-15), 273 and 16 floating point registers (registers 16-31). 274 (On non-IEEE machines, we have only 4 fp registers.) 275 276 Amongst the general purpose registers, some are used 277 for specific purposes: 278 GPR 11: Hard frame pointer (if needed) 279 GPR 12: Global offset table pointer (if needed) 280 GPR 13: Literal pool base register 281 GPR 14: Return address register 282 GPR 15: Stack pointer 283 284 Registers 32-35 are 'fake' hard registers that do not 285 correspond to actual hardware: 286 Reg 32: Argument pointer 287 Reg 33: Condition code 288 Reg 34: Frame pointer 289 Reg 35: Return address pointer 290 291 Registers 36 and 37 are mapped to access registers 292 0 and 1, used to implement thread-local storage. */ 293 294 #define FIRST_PSEUDO_REGISTER 38 295 296 /* Standard register usage. */ 297 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) 298 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) 299 #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) 300 #define CC_REGNO_P(N) ((N) == 33) 301 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) 302 #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) 303 304 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 305 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) 306 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 307 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 308 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) 309 #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) 310 311 /* Set up fixed registers and calling convention: 312 313 GPRs 0-5 are always call-clobbered, 314 GPRs 6-15 are always call-saved. 315 GPR 12 is fixed if used as GOT pointer. 316 GPR 13 is always fixed (as literal pool pointer). 317 GPR 14 is always fixed on S/390 machines (as return address). 318 GPR 15 is always fixed (as stack pointer). 319 The 'fake' hard registers are call-clobbered and fixed. 320 The access registers are call-saved and fixed. 321 322 On 31-bit, FPRs 18-19 are call-clobbered; 323 on 64-bit, FPRs 24-31 are call-clobbered. 324 The remaining FPRs are call-saved. */ 325 326 #define FIXED_REGISTERS \ 327 { 0, 0, 0, 0, \ 328 0, 0, 0, 0, \ 329 0, 0, 0, 0, \ 330 0, 1, 1, 1, \ 331 0, 0, 0, 0, \ 332 0, 0, 0, 0, \ 333 0, 0, 0, 0, \ 334 0, 0, 0, 0, \ 335 1, 1, 1, 1, \ 336 1, 1 } 337 338 #define CALL_USED_REGISTERS \ 339 { 1, 1, 1, 1, \ 340 1, 1, 0, 0, \ 341 0, 0, 0, 0, \ 342 0, 1, 1, 1, \ 343 1, 1, 1, 1, \ 344 1, 1, 1, 1, \ 345 1, 1, 1, 1, \ 346 1, 1, 1, 1, \ 347 1, 1, 1, 1, \ 348 1, 1 } 349 350 #define CALL_REALLY_USED_REGISTERS \ 351 { 1, 1, 1, 1, \ 352 1, 1, 0, 0, \ 353 0, 0, 0, 0, \ 354 0, 0, 0, 0, \ 355 1, 1, 1, 1, \ 356 1, 1, 1, 1, \ 357 1, 1, 1, 1, \ 358 1, 1, 1, 1, \ 359 1, 1, 1, 1, \ 360 0, 0 } 361 362 /* Preferred register allocation order. */ 363 #define REG_ALLOC_ORDER \ 364 { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ 365 16, 17, 18, 19, 20, 21, 22, 23, \ 366 24, 25, 26, 27, 28, 29, 30, 31, \ 367 15, 32, 33, 34, 35, 36, 37 } 368 369 370 /* Fitting values into registers. */ 371 372 /* Integer modes <= word size fit into any GPR. 373 Integer modes > word size fit into successive GPRs, starting with 374 an even-numbered register. 375 SImode and DImode fit into FPRs as well. 376 377 Floating point modes <= word size fit into any FPR or GPR. 378 Floating point modes > word size (i.e. DFmode on 32-bit) fit 379 into any FPR, or an even-odd GPR pair. 380 TFmode fits only into an even-odd FPR pair. 381 382 Complex floating point modes fit either into two FPRs, or into 383 successive GPRs (again starting with an even number). 384 TCmode fits only into two successive even-odd FPR pairs. 385 386 Condition code modes fit only into the CC register. */ 387 388 /* Because all registers in a class have the same size HARD_REGNO_NREGS 389 is equivalent to CLASS_MAX_NREGS. */ 390 #define HARD_REGNO_NREGS(REGNO, MODE) \ 391 s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE)) 392 393 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 394 s390_hard_regno_mode_ok ((REGNO), (MODE)) 395 396 #define HARD_REGNO_RENAME_OK(FROM, TO) \ 397 s390_hard_regno_rename_ok (FROM, TO) 398 399 #define MODES_TIEABLE_P(MODE1, MODE2) \ 400 (((MODE1) == SFmode || (MODE1) == DFmode) \ 401 == ((MODE2) == SFmode || (MODE2) == DFmode)) 402 403 /* When generating code that runs in z/Architecture mode, 404 but conforms to the 31-bit ABI, GPRs can hold 8 bytes; 405 the ABI guarantees only that the lower 4 bytes are 406 saved across calls, however. */ 407 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 408 (!TARGET_64BIT && TARGET_ZARCH \ 409 && GET_MODE_SIZE (MODE) > 4 \ 410 && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32)) 411 412 /* Maximum number of registers to represent a value of mode MODE 413 in a register of class CLASS. */ 414 #define CLASS_MAX_NREGS(CLASS, MODE) \ 415 s390_class_max_nregs ((CLASS), (MODE)) 416 417 /* If a 4-byte value is loaded into a FPR, it is placed into the 418 *upper* half of the register, not the lower. Therefore, we 419 cannot use SUBREGs to switch between modes in FP registers. 420 Likewise for access registers, since they have only half the 421 word size on 64-bit. */ 422 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 423 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 424 ? ((reg_classes_intersect_p (FP_REGS, CLASS) \ 425 && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8)) \ 426 || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0) 427 428 /* Register classes. */ 429 430 /* We use the following register classes: 431 GENERAL_REGS All general purpose registers 432 ADDR_REGS All general purpose registers except %r0 433 (These registers can be used in address generation) 434 FP_REGS All floating point registers 435 CC_REGS The condition code register 436 ACCESS_REGS The access registers 437 438 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS 439 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS 440 GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS 441 ADDR_CC_REGS Union of ADDR_REGS and CC_REGS 442 443 NO_REGS No registers 444 ALL_REGS All registers 445 446 Note that the 'fake' frame pointer and argument pointer registers 447 are included amongst the address registers here. */ 448 449 enum reg_class 450 { 451 NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, 452 ADDR_CC_REGS, GENERAL_CC_REGS, 453 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, 454 ALL_REGS, LIM_REG_CLASSES 455 }; 456 #define N_REG_CLASSES (int) LIM_REG_CLASSES 457 458 #define REG_CLASS_NAMES \ 459 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ 460 "ADDR_CC_REGS", "GENERAL_CC_REGS", \ 461 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } 462 463 /* Class -> register mapping. */ 464 #define REG_CLASS_CONTENTS \ 465 { \ 466 { 0x00000000, 0x00000000 }, /* NO_REGS */ \ 467 { 0x00000000, 0x00000002 }, /* CC_REGS */ \ 468 { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ 469 { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ 470 { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ 471 { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ 472 { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ 473 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ 474 { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ 475 { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ 476 { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \ 477 } 478 479 /* In some case register allocation order is not enough for IRA to 480 generate a good code. The following macro (if defined) increases 481 cost of REGNO for a pseudo approximately by pseudo usage frequency 482 multiplied by the macro value. 483 484 We avoid usage of BASE_REGNUM by nonzero macro value because the 485 reload can decide not to use the hard register because some 486 constant was forced to be in memory. */ 487 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ 488 (regno == BASE_REGNUM ? 0.0 : 0.5) 489 490 /* Register -> class mapping. */ 491 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; 492 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 493 494 /* ADDR_REGS can be used as base or index register. */ 495 #define INDEX_REG_CLASS ADDR_REGS 496 #define BASE_REG_CLASS ADDR_REGS 497 498 /* Check whether REGNO is a hard register of the suitable class 499 or a pseudo register currently allocated to one such. */ 500 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 501 (((REGNO) < FIRST_PSEUDO_REGISTER \ 502 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ 503 || ADDR_REGNO_P (reg_renumber[REGNO])) 504 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 505 506 507 /* We need secondary memory to move data between GPRs and FPRs. With 508 DFP the ldgr lgdr instructions are available. But these 509 instructions do not handle GPR pairs so it is not possible for 31 510 bit. */ 511 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 512 ((CLASS1) != (CLASS2) \ 513 && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS) \ 514 && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8)) 515 516 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit 517 because the movsi and movsf patterns don't handle r/f moves. */ 518 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 519 (GET_MODE_BITSIZE (MODE) < 32 \ 520 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 521 : MODE) 522 523 524 /* Stack layout and calling conventions. */ 525 526 /* Our stack grows from higher to lower addresses. However, local variables 527 are accessed by positive offsets, and function arguments are stored at 528 increasing addresses. */ 529 #define STACK_GROWS_DOWNWARD 530 #define FRAME_GROWS_DOWNWARD 1 531 /* #undef ARGS_GROW_DOWNWARD */ 532 533 /* The basic stack layout looks like this: the stack pointer points 534 to the register save area for called functions. Above that area 535 is the location to place outgoing arguments. Above those follow 536 dynamic allocations (alloca), and finally the local variables. */ 537 538 /* Offset from stack-pointer to first location of outgoing args. */ 539 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) 540 541 /* Offset within stack frame to start allocating local variables at. */ 542 #define STARTING_FRAME_OFFSET 0 543 544 /* Offset from the stack pointer register to an item dynamically 545 allocated on the stack, e.g., by `alloca'. */ 546 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 547 (STACK_POINTER_OFFSET + crtl->outgoing_args_size) 548 549 /* Offset of first parameter from the argument pointer register value. 550 We have a fake argument pointer register that points directly to 551 the argument area. */ 552 #define FIRST_PARM_OFFSET(FNDECL) 0 553 554 /* Defining this macro makes __builtin_frame_address(0) and 555 __builtin_return_address(0) work with -fomit-frame-pointer. */ 556 #define INITIAL_FRAME_ADDRESS_RTX \ 557 (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) 558 559 /* The return address of the current frame is retrieved 560 from the initial value of register RETURN_REGNUM. 561 For frames farther back, we use the stack slot where 562 the corresponding RETURN_REGNUM register was saved. */ 563 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ 564 (TARGET_PACKED_STACK ? \ 565 plus_constant (Pmode, (FRAME), \ 566 STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) 567 568 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of 569 builtin_frame_address. Otherwise arg pointer - 570 STACK_POINTER_OFFSET would be returned for 571 __builtin_frame_address(0) what might result in an address pointing 572 somewhere into the middle of the local variables since the packed 573 stack layout generally does not need all the bytes in the register 574 save area. */ 575 #define FRAME_ADDR_RTX(FRAME) \ 576 DYNAMIC_CHAIN_ADDRESS ((FRAME)) 577 578 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 579 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) 580 581 /* In 31-bit mode, we need to mask off the high bit of return addresses. */ 582 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) 583 584 585 /* Exception handling. */ 586 587 /* Describe calling conventions for DWARF-2 exception handling. */ 588 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) 589 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET 590 #define DWARF_FRAME_RETURN_COLUMN 14 591 592 /* Describe how we implement __builtin_eh_return. */ 593 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) 594 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) 595 596 /* Select a format to encode pointers in exception handling data. */ 597 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 598 (flag_pic \ 599 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 600 : DW_EH_PE_absptr) 601 602 /* Register save slot alignment. */ 603 #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) 604 605 /* Let the assembler generate debug line info. */ 606 #define DWARF2_ASM_LINE_DEBUG_INFO 1 607 608 609 /* Frame registers. */ 610 611 #define STACK_POINTER_REGNUM 15 612 #define FRAME_POINTER_REGNUM 34 613 #define HARD_FRAME_POINTER_REGNUM 11 614 #define ARG_POINTER_REGNUM 32 615 #define RETURN_ADDRESS_POINTER_REGNUM 35 616 617 /* The static chain must be call-clobbered, but not used for 618 function argument passing. As register 1 is clobbered by 619 the trampoline code, we only have one option. */ 620 #define STATIC_CHAIN_REGNUM 0 621 622 /* Number of hardware registers that go into the DWARF-2 unwind info. 623 To avoid ABI incompatibility, this number must not change even as 624 'fake' hard registers are added or removed. */ 625 #define DWARF_FRAME_REGISTERS 34 626 627 628 /* Frame pointer and argument pointer elimination. */ 629 630 #define ELIMINABLE_REGS \ 631 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 632 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 633 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 634 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 635 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 636 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 637 { BASE_REGNUM, BASE_REGNUM }} 638 639 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 640 (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) 641 642 643 /* Stack arguments. */ 644 645 /* We need current_function_outgoing_args to be valid. */ 646 #define ACCUMULATE_OUTGOING_ARGS 1 647 648 649 /* Register arguments. */ 650 651 typedef struct s390_arg_structure 652 { 653 int gprs; /* gpr so far */ 654 int fprs; /* fpr so far */ 655 } 656 CUMULATIVE_ARGS; 657 658 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ 659 ((CUM).gprs=0, (CUM).fprs=0) 660 661 /* Arguments can be placed in general registers 2 to 6, or in floating 662 point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 663 bit. */ 664 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ 665 (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19))) 666 667 668 /* Only gpr 2 and fpr 0 are ever used as return registers. */ 669 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) 670 671 672 /* Function entry and exit. */ 673 674 /* When returning from a function, the stack pointer does not matter. */ 675 #define EXIT_IGNORE_STACK 1 676 677 678 /* Profiling. */ 679 680 #define FUNCTION_PROFILER(FILE, LABELNO) \ 681 s390_function_profiler ((FILE), ((LABELNO))) 682 683 #define PROFILE_BEFORE_PROLOGUE 1 684 685 686 /* Trampolines for nested functions. */ 687 688 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) 689 #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD 690 691 /* Addressing modes, and classification of registers for them. */ 692 693 /* Recognize any constant value that is a valid address. */ 694 #define CONSTANT_ADDRESS_P(X) 0 695 696 /* Maximum number of registers that can appear in a valid memory address. */ 697 #define MAX_REGS_PER_ADDRESS 2 698 699 /* This definition replaces the formerly used 'm' constraint with a 700 different constraint letter in order to avoid changing semantics of 701 the 'm' constraint when accepting new address formats in 702 TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here 703 must not be used in insn definitions or inline assemblies. */ 704 #define TARGET_MEM_CONSTRAINT 'e' 705 706 /* Try a machine-dependent way of reloading an illegitimate address 707 operand. If we find one, push the reload and jump to WIN. This 708 macro is used in only one place: `find_reloads_address' in reload.c. */ 709 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ 710 do { \ 711 rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \ 712 if (new_rtx) \ 713 { \ 714 (AD) = new_rtx; \ 715 goto WIN; \ 716 } \ 717 } while (0) 718 719 /* Helper macro for s390.c and s390.md to check for symbolic constants. */ 720 #define SYMBOLIC_CONST(X) \ 721 (GET_CODE (X) == SYMBOL_REF \ 722 || GET_CODE (X) == LABEL_REF \ 723 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 724 725 #define TLS_SYMBOLIC_CONST(X) \ 726 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ 727 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) 728 729 730 /* Condition codes. */ 731 732 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 733 return the mode to be used for the comparison. */ 734 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) 735 736 /* Relative costs of operations. */ 737 738 /* A C expression for the cost of a branch instruction. A value of 1 739 is the default; other values are interpreted relative to that. */ 740 #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost 741 742 /* Nonzero if access to memory by bytes is slow and undesirable. */ 743 #define SLOW_BYTE_ACCESS 1 744 745 /* An integer expression for the size in bits of the largest integer machine 746 mode that should actually be used. We allow pairs of registers. */ 747 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 748 749 /* The maximum number of bytes that a single instruction can move quickly 750 between memory and registers or between two memory locations. */ 751 #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) 752 #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) 753 #define MAX_MOVE_MAX 16 754 755 /* Determine whether to use move_by_pieces or block move insn. */ 756 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ 757 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ 758 || (TARGET_ZARCH && (SIZE) == 8) ) 759 760 /* Determine whether to use clear_by_pieces or block clear insn. */ 761 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ 762 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ 763 || (TARGET_ZARCH && (SIZE) == 8) ) 764 765 /* This macro is used to determine whether store_by_pieces should be 766 called to "memcpy" storage when the source is a constant string. */ 767 #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN) 768 769 /* Likewise to decide whether to "memset" storage with byte values 770 other than zero. */ 771 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN) 772 773 /* Don't perform CSE on function addresses. */ 774 #define NO_FUNCTION_CSE 775 776 /* This value is used in tree-sra to decide whether it might benefical 777 to split a struct move into several word-size moves. For S/390 778 only small values make sense here since struct moves are relatively 779 cheap thanks to mvc so the small default value chosen for archs 780 with memmove patterns should be ok. But this value is multiplied 781 in tree-sra with UNITS_PER_WORD to make a decision so we adjust it 782 here to compensate for that factor since mvc costs exactly the same 783 on 31 and 64 bit. */ 784 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) 785 786 787 /* Sections. */ 788 789 /* Output before read-only data. */ 790 #define TEXT_SECTION_ASM_OP ".text" 791 792 /* Output before writable (initialized) data. */ 793 #define DATA_SECTION_ASM_OP ".data" 794 795 /* Output before writable (uninitialized) data. */ 796 #define BSS_SECTION_ASM_OP ".bss" 797 798 /* S/390 constant pool breaks the devices in crtstuff.c to control section 799 in where code resides. We have to write it as asm code. */ 800 #ifndef __s390x__ 801 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 802 asm (SECTION_OP "\n\ 803 bras\t%r2,1f\n\ 804 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ 805 1: l\t%r3,0(%r2)\n\ 806 bas\t%r14,0(%r3,%r2)\n\ 807 .previous"); 808 #endif 809 810 811 /* Position independent code. */ 812 813 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) 814 815 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 816 817 818 /* Assembler file format. */ 819 820 /* Character to start a comment. */ 821 #define ASM_COMMENT_START "#" 822 823 /* Declare an uninitialized external linkage data object. */ 824 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 825 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 826 827 /* Globalizing directive for a label. */ 828 #define GLOBAL_ASM_OP ".globl " 829 830 /* Advance the location counter to a multiple of 2**LOG bytes. */ 831 #define ASM_OUTPUT_ALIGN(FILE, LOG) \ 832 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) 833 834 /* Advance the location counter by SIZE bytes. */ 835 #define ASM_OUTPUT_SKIP(FILE, SIZE) \ 836 fprintf ((FILE), "\t.set\t.,.+" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 837 838 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ 839 #define LOCAL_LABEL_PREFIX "." 840 841 #define LABEL_ALIGN(LABEL) \ 842 s390_label_align (LABEL) 843 844 /* How to refer to registers in assembler output. This sequence is 845 indexed by compiler's hard-register-number (see above). */ 846 #define REGISTER_NAMES \ 847 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ 848 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ 849 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ 850 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ 851 "%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \ 852 } 853 854 /* Print operand X (an rtx) in assembler syntax to file FILE. */ 855 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 856 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 857 858 /* Output an element of a case-vector that is absolute. */ 859 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 860 do { \ 861 char buf[32]; \ 862 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ 863 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 864 assemble_name ((FILE), buf); \ 865 fputc ('\n', (FILE)); \ 866 } while (0) 867 868 /* Output an element of a case-vector that is relative. */ 869 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 870 do { \ 871 char buf[32]; \ 872 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ 873 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 874 assemble_name ((FILE), buf); \ 875 fputc ('-', (FILE)); \ 876 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ 877 assemble_name ((FILE), buf); \ 878 fputc ('\n', (FILE)); \ 879 } while (0) 880 881 #undef ASM_OUTPUT_FUNCTION_LABEL 882 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 883 s390_asm_output_function_label (FILE, NAME, DECL) 884 885 /* Miscellaneous parameters. */ 886 887 /* Specify the machine mode that this machine uses for the index in the 888 tablejump instruction. */ 889 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) 890 891 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 892 is done just by pretending it is already truncated. */ 893 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 894 895 /* Specify the machine mode that pointers have. 896 After generation of rtl, the compiler makes no further distinction 897 between pointers and any other objects of this machine mode. */ 898 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) 899 900 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ 901 #define POINTERS_EXTEND_UNSIGNED -1 902 903 /* A function address in a call instruction is a byte address (for 904 indexing purposes) so give the MEM rtx a byte's mode. */ 905 #define FUNCTION_MODE QImode 906 907 /* Specify the value which is used when clz operand is zero. */ 908 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) 909 910 /* Machine-specific symbol_ref flags. */ 911 #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0) 912 #define SYMBOL_REF_ALIGN1_P(X) \ 913 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1)) 914 #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1) 915 #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \ 916 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED)) 917 918 /* Check whether integer displacement is in range. */ 919 #define DISP_IN_RANGE(d) \ 920 (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \ 921 : ((d) >= 0 && (d) <= 4095)) 922 923 /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ 924 #define READ_CAN_USE_WRITE_PREFETCH 1 925 926 extern const int processor_flags_table[]; 927 #endif 928