1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "backend.h"
25 #include "target.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "cfghooks.h"
29 #include "df.h"
30 #include "tm_p.h"
31 #include "optabs.h"
32 #include "regs.h"
33 #include "emit-rtl.h"
34 #include "recog.h"
35 #include "cgraph.h"
36 #include "diagnostic-core.h"
37 #include "conditions.h"
38 #include "insn-attr.h"
39 #include "alias.h"
40 #include "varasm.h"
41 #include "stor-layout.h"
42 #include "calls.h"
43 #include "explow.h"
44 #include "expr.h"
45 #include "reload.h"
46 #include "output.h"
47 #include "tm-constrs.h"
48 #include "builtins.h"
49
50 /* This file should be included last. */
51 #include "target-def.h"
52
53 /* Usable when we have an amount to add or subtract, and want the
54 optimal size of the insn. */
55 #define ADDITIVE_SIZE_MODIFIER(size) \
56 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
57
58 #define LOSE_AND_RETURN(msgid, x) \
59 do \
60 { \
61 cris_operand_lossage (msgid, x); \
62 return; \
63 } while (0)
64
65 enum cris_retinsn_type
66 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP };
67
68 /* Per-function machine data. */
69 struct GTY(()) machine_function
70 {
71 int needs_return_address_on_stack;
72
73 /* This is the number of registers we save in the prologue due to
74 stdarg. */
75 int stdarg_regs;
76
77 enum cris_retinsn_type return_type;
78 };
79
80 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
81 pattern. */
82 static char cris_output_insn_is_bound = 0;
83
84 /* In code for output macros, this is how we know whether e.g. constant
85 goes in code or in a static initializer. */
86 static int in_code = 0;
87
88 /* Fix for reg_overlap_mentioned_p. */
89 static int cris_reg_overlap_mentioned_p (rtx, rtx);
90
91 static machine_mode cris_promote_function_mode (const_tree, machine_mode,
92 int *, const_tree, int);
93
94 static unsigned int cris_atomic_align_for_mode (machine_mode);
95
96 static void cris_print_base (rtx, FILE *);
97
98 static void cris_print_index (rtx, FILE *);
99
100 static void cris_output_addr_const (FILE *, rtx);
101
102 static struct machine_function * cris_init_machine_status (void);
103
104 static rtx cris_struct_value_rtx (tree, int);
105
106 static void cris_setup_incoming_varargs (cumulative_args_t, machine_mode,
107 tree type, int *, int);
108
109 static int cris_initial_frame_pointer_offset (void);
110
111 static void cris_operand_lossage (const char *, rtx);
112
113 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
114
115 static void cris_print_operand (FILE *, rtx, int);
116
117 static void cris_print_operand_address (FILE *, machine_mode, rtx);
118
119 static bool cris_print_operand_punct_valid_p (unsigned char code);
120
121 static bool cris_output_addr_const_extra (FILE *, rtx);
122
123 static void cris_conditional_register_usage (void);
124
125 static void cris_asm_output_mi_thunk
126 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
127
128 static void cris_file_start (void);
129 static void cris_init_libfuncs (void);
130
131 static reg_class_t cris_preferred_reload_class (rtx, reg_class_t);
132
133 static int cris_register_move_cost (machine_mode, reg_class_t, reg_class_t);
134 static int cris_memory_move_cost (machine_mode, reg_class_t, bool);
135 static bool cris_rtx_costs (rtx, machine_mode, int, int, int *, bool);
136 static int cris_address_cost (rtx, machine_mode, addr_space_t, bool);
137 static bool cris_pass_by_reference (cumulative_args_t, machine_mode,
138 const_tree, bool);
139 static int cris_arg_partial_bytes (cumulative_args_t, machine_mode,
140 tree, bool);
141 static rtx cris_function_arg (cumulative_args_t, machine_mode,
142 const_tree, bool);
143 static rtx cris_function_incoming_arg (cumulative_args_t,
144 machine_mode, const_tree, bool);
145 static void cris_function_arg_advance (cumulative_args_t, machine_mode,
146 const_tree, bool);
147 static rtx_insn *cris_md_asm_adjust (vec<rtx> &, vec<rtx> &,
148 vec<const char *> &,
149 vec<rtx> &, HARD_REG_SET &);
150 static bool cris_cannot_force_const_mem (machine_mode, rtx);
151
152 static void cris_option_override (void);
153
154 static bool cris_frame_pointer_required (void);
155
156 static void cris_asm_trampoline_template (FILE *);
157 static void cris_trampoline_init (rtx, tree, rtx);
158
159 static rtx cris_function_value(const_tree, const_tree, bool);
160 static rtx cris_libcall_value (machine_mode, const_rtx);
161 static bool cris_function_value_regno_p (const unsigned int);
162 static void cris_file_end (void);
163
164 /* This is the parsed result of the "-max-stack-stackframe=" option. If
165 it (still) is zero, then there was no such option given. */
166 int cris_max_stackframe = 0;
167
168 /* This is the parsed result of the "-march=" option, if given. */
169 int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
170
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
173 #undef TARGET_ASM_ALIGNED_SI_OP
174 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
175 #undef TARGET_ASM_ALIGNED_DI_OP
176 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
177
178 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
179 available in ELF. These "normal" pseudos do not have any alignment
180 constraints or side-effects. */
181 #undef TARGET_ASM_UNALIGNED_HI_OP
182 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
183
184 #undef TARGET_ASM_UNALIGNED_SI_OP
185 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
186
187 #undef TARGET_ASM_UNALIGNED_DI_OP
188 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
189
190 #undef TARGET_PRINT_OPERAND
191 #define TARGET_PRINT_OPERAND cris_print_operand
192 #undef TARGET_PRINT_OPERAND_ADDRESS
193 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
194 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
195 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
196 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
197 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
198
199 #undef TARGET_CONDITIONAL_REGISTER_USAGE
200 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
201
202 #undef TARGET_ASM_OUTPUT_MI_THUNK
203 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
204 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
205 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
206
207 #undef TARGET_ASM_FILE_START
208 #define TARGET_ASM_FILE_START cris_file_start
209 #undef TARGET_ASM_FILE_END
210 #define TARGET_ASM_FILE_END cris_file_end
211
212 #undef TARGET_INIT_LIBFUNCS
213 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
214
215 #undef TARGET_LEGITIMATE_ADDRESS_P
216 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
217
218 #undef TARGET_LEGITIMATE_CONSTANT_P
219 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p
220
221 #undef TARGET_PREFERRED_RELOAD_CLASS
222 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
223
224 #undef TARGET_REGISTER_MOVE_COST
225 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
226 #undef TARGET_MEMORY_MOVE_COST
227 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
228 #undef TARGET_RTX_COSTS
229 #define TARGET_RTX_COSTS cris_rtx_costs
230 #undef TARGET_ADDRESS_COST
231 #define TARGET_ADDRESS_COST cris_address_cost
232
233 #undef TARGET_PROMOTE_FUNCTION_MODE
234 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
235
236 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
237 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
238
239 #undef TARGET_STRUCT_VALUE_RTX
240 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
241 #undef TARGET_SETUP_INCOMING_VARARGS
242 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
243 #undef TARGET_PASS_BY_REFERENCE
244 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
245 #undef TARGET_ARG_PARTIAL_BYTES
246 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
247 #undef TARGET_FUNCTION_ARG
248 #define TARGET_FUNCTION_ARG cris_function_arg
249 #undef TARGET_FUNCTION_INCOMING_ARG
250 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
251 #undef TARGET_FUNCTION_ARG_ADVANCE
252 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
253 #undef TARGET_MD_ASM_ADJUST
254 #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust
255
256 #undef TARGET_CANNOT_FORCE_CONST_MEM
257 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem
258
259 #undef TARGET_FRAME_POINTER_REQUIRED
260 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
261
262 #undef TARGET_OPTION_OVERRIDE
263 #define TARGET_OPTION_OVERRIDE cris_option_override
264
265 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
266 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
267 #undef TARGET_TRAMPOLINE_INIT
268 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
269
270 #undef TARGET_FUNCTION_VALUE
271 #define TARGET_FUNCTION_VALUE cris_function_value
272 #undef TARGET_LIBCALL_VALUE
273 #define TARGET_LIBCALL_VALUE cris_libcall_value
274 #undef TARGET_FUNCTION_VALUE_REGNO_P
275 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
276
277 struct gcc_target targetm = TARGET_INITIALIZER;
278
279 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
280
281 bool
cris_movem_load_rest_p(rtx op,int offs)282 cris_movem_load_rest_p (rtx op, int offs)
283 {
284 unsigned int reg_count = XVECLEN (op, 0) - offs;
285 rtx src_addr;
286 int i;
287 rtx elt;
288 int setno;
289 int regno_dir = 1;
290 unsigned int regno = 0;
291
292 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
293 other than (MEM reg). */
294 if (reg_count <= 1
295 || GET_CODE (XVECEXP (op, 0, offs)) != SET
296 || !REG_P (SET_DEST (XVECEXP (op, 0, offs)))
297 || !MEM_P (SET_SRC (XVECEXP (op, 0, offs))))
298 return false;
299
300 /* Check a possible post-inc indicator. */
301 if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS)
302 {
303 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0);
304 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1);
305
306 reg_count--;
307
308 if (reg_count == 1
309 || !REG_P (reg)
310 || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1)))
311 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1)))
312 || !CONST_INT_P (inc)
313 || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4)
314 return false;
315 i = offs + 2;
316 }
317 else
318 i = offs + 1;
319
320 if (!TARGET_V32)
321 {
322 regno_dir = -1;
323 regno = reg_count - 1;
324 }
325
326 elt = XVECEXP (op, 0, offs);
327 src_addr = XEXP (SET_SRC (elt), 0);
328
329 if (GET_CODE (elt) != SET
330 || !REG_P (SET_DEST (elt))
331 || GET_MODE (SET_DEST (elt)) != SImode
332 || REGNO (SET_DEST (elt)) != regno
333 || !MEM_P (SET_SRC (elt))
334 || GET_MODE (SET_SRC (elt)) != SImode
335 || !memory_address_p (SImode, src_addr))
336 return false;
337
338 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
339 {
340 rtx elt = XVECEXP (op, 0, i);
341 regno += regno_dir;
342
343 if (GET_CODE (elt) != SET
344 || !REG_P (SET_DEST (elt))
345 || GET_MODE (SET_DEST (elt)) != SImode
346 || REGNO (SET_DEST (elt)) != regno
347 || !MEM_P (SET_SRC (elt))
348 || GET_MODE (SET_SRC (elt)) != SImode
349 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
350 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
351 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
352 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4)
353 return false;
354 }
355
356 return true;
357 }
358
359 /* Worker function for predicate for the parallel contents in a movem
360 to-memory. */
361
362 bool
cris_store_multiple_op_p(rtx op)363 cris_store_multiple_op_p (rtx op)
364 {
365 int reg_count = XVECLEN (op, 0);
366 rtx dest;
367 rtx dest_addr;
368 rtx dest_base;
369 int i;
370 rtx elt;
371 int setno;
372 int regno_dir = 1;
373 int regno = 0;
374 int offset = 0;
375
376 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
377 other than (MEM reg) and (MEM (PLUS reg const)). */
378 if (reg_count <= 1)
379 return false;
380
381 elt = XVECEXP (op, 0, 0);
382
383 if (GET_CODE (elt) != SET)
384 return false;
385
386 dest = SET_DEST (elt);
387
388 if (!REG_P (SET_SRC (elt)) || !MEM_P (dest))
389 return false;
390
391 dest_addr = XEXP (dest, 0);
392
393 /* Check a possible post-inc indicator. */
394 if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS)
395 {
396 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0);
397 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1);
398
399 reg_count--;
400
401 if (reg_count == 1
402 || !REG_P (reg)
403 || !REG_P (SET_DEST (XVECEXP (op, 0, 1)))
404 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1)))
405 || !CONST_INT_P (inc)
406 /* Support increment by number of registers, and by the offset
407 of the destination, if it has the form (MEM (PLUS reg
408 offset)). */
409 || !((REG_P (dest_addr)
410 && REGNO (dest_addr) == REGNO (reg)
411 && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4)
412 || (GET_CODE (dest_addr) == PLUS
413 && REG_P (XEXP (dest_addr, 0))
414 && REGNO (XEXP (dest_addr, 0)) == REGNO (reg)
415 && CONST_INT_P (XEXP (dest_addr, 1))
416 && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc))))
417 return false;
418
419 i = 2;
420 }
421 else
422 i = 1;
423
424 if (!TARGET_V32)
425 {
426 regno_dir = -1;
427 regno = reg_count - 1;
428 }
429
430 if (GET_CODE (elt) != SET
431 || !REG_P (SET_SRC (elt))
432 || GET_MODE (SET_SRC (elt)) != SImode
433 || REGNO (SET_SRC (elt)) != (unsigned int) regno
434 || !MEM_P (SET_DEST (elt))
435 || GET_MODE (SET_DEST (elt)) != SImode)
436 return false;
437
438 if (REG_P (dest_addr))
439 {
440 dest_base = dest_addr;
441 offset = 0;
442 }
443 else if (GET_CODE (dest_addr) == PLUS
444 && REG_P (XEXP (dest_addr, 0))
445 && CONST_INT_P (XEXP (dest_addr, 1)))
446 {
447 dest_base = XEXP (dest_addr, 0);
448 offset = INTVAL (XEXP (dest_addr, 1));
449 }
450 else
451 return false;
452
453 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
454 {
455 rtx elt = XVECEXP (op, 0, i);
456 regno += regno_dir;
457
458 if (GET_CODE (elt) != SET
459 || !REG_P (SET_SRC (elt))
460 || GET_MODE (SET_SRC (elt)) != SImode
461 || REGNO (SET_SRC (elt)) != (unsigned int) regno
462 || !MEM_P (SET_DEST (elt))
463 || GET_MODE (SET_DEST (elt)) != SImode
464 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
465 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base)
466 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
467 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset)
468 return false;
469 }
470
471 return true;
472 }
473
474 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
475
476 static void
cris_conditional_register_usage(void)477 cris_conditional_register_usage (void)
478 {
479 /* FIXME: This isn't nice. We should be able to use that register for
480 something else if the PIC table isn't needed. */
481 if (flag_pic)
482 fixed_regs[PIC_OFFSET_TABLE_REGNUM]
483 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
484
485 /* Allow use of ACR (PC in pre-V32) and tweak order. */
486 if (TARGET_V32)
487 {
488 static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32;
489 unsigned int i;
490
491 fixed_regs[CRIS_ACR_REGNUM] = 0;
492
493 for (i = 0;
494 i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]);
495 i++)
496 reg_alloc_order[i] = reg_alloc_order_v32[i];
497 }
498
499 if (TARGET_HAS_MUL_INSNS)
500 fixed_regs[CRIS_MOF_REGNUM] = 0;
501
502 /* On early versions, we must use the 16-bit condition-code register,
503 which has another name. */
504 if (cris_cpu_version < 8)
505 reg_names[CRIS_CC0_REGNUM] = "ccr";
506 }
507
508 /* Return crtl->uses_pic_offset_table. For use in cris.md,
509 since some generated files do not include function.h. */
510
511 int
cris_cfun_uses_pic_table(void)512 cris_cfun_uses_pic_table (void)
513 {
514 return crtl->uses_pic_offset_table;
515 }
516
517 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM.
518 We can't put PIC addresses in the constant pool, not even the ones that
519 can be reached as pc-relative as we can't tell when or how to do that. */
520
521 static bool
cris_cannot_force_const_mem(machine_mode mode ATTRIBUTE_UNUSED,rtx x)522 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
523 {
524 enum cris_symbol_type t = cris_symbol_type_of (x);
525
526 return
527 t == cris_unspec
528 || t == cris_got_symbol
529 || t == cris_rel_symbol;
530 }
531
532 /* Given an rtx, return the text string corresponding to the CODE of X.
533 Intended for use in the assembly language output section of a
534 define_insn. */
535
536 const char *
cris_op_str(rtx x)537 cris_op_str (rtx x)
538 {
539 cris_output_insn_is_bound = 0;
540 switch (GET_CODE (x))
541 {
542 case PLUS:
543 return "add";
544 break;
545
546 case MINUS:
547 return "sub";
548 break;
549
550 case MULT:
551 /* This function is for retrieving a part of an instruction name for
552 an operator, for immediate output. If that ever happens for
553 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
554 we notice. */
555 internal_error ("MULT case in cris_op_str");
556 break;
557
558 case DIV:
559 return "div";
560 break;
561
562 case AND:
563 return "and";
564 break;
565
566 case IOR:
567 return "or";
568 break;
569
570 case XOR:
571 return "xor";
572 break;
573
574 case NOT:
575 return "not";
576 break;
577
578 case ASHIFT:
579 return "lsl";
580 break;
581
582 case LSHIFTRT:
583 return "lsr";
584 break;
585
586 case ASHIFTRT:
587 return "asr";
588 break;
589
590 case UMIN:
591 /* Used to control the sign/zero-extend character for the 'E' modifier.
592 BOUND has none. */
593 cris_output_insn_is_bound = 1;
594 return "bound";
595 break;
596
597 default:
598 return "Unknown operator";
599 break;
600 }
601 }
602
603 /* Emit an error message when we're in an asm, and a fatal error for
604 "normal" insns. Formatted output isn't easily implemented, since we
605 use output_operand_lossage to output the actual message and handle the
606 categorization of the error. */
607
608 static void
cris_operand_lossage(const char * msgid,rtx op)609 cris_operand_lossage (const char *msgid, rtx op)
610 {
611 debug_rtx (op);
612 output_operand_lossage ("%s", msgid);
613 }
614
615 /* Print an index part of an address to file. */
616
617 static void
cris_print_index(rtx index,FILE * file)618 cris_print_index (rtx index, FILE *file)
619 {
620 /* Make the index "additive" unless we'll output a negative number, in
621 which case the sign character is free (as in free beer). */
622 if (!CONST_INT_P (index) || INTVAL (index) >= 0)
623 putc ('+', file);
624
625 if (REG_P (index))
626 fprintf (file, "$%s.b", reg_names[REGNO (index)]);
627 else if (CRIS_CONSTANT_P (index))
628 cris_output_addr_const (file, index);
629 else if (GET_CODE (index) == MULT)
630 {
631 fprintf (file, "$%s.",
632 reg_names[REGNO (XEXP (index, 0))]);
633
634 putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file);
635 }
636 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0)))
637 {
638 rtx inner = XEXP (index, 0);
639 rtx inner_inner = XEXP (inner, 0);
640
641 if (GET_CODE (inner_inner) == POST_INC)
642 {
643 fprintf (file, "[$%s+].",
644 reg_names[REGNO (XEXP (inner_inner, 0))]);
645 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
646 }
647 else
648 {
649 fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]);
650
651 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
652 }
653 }
654 else if (MEM_P (index))
655 {
656 rtx inner = XEXP (index, 0);
657 if (GET_CODE (inner) == POST_INC)
658 fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]);
659 else
660 fprintf (file, "[$%s].d", reg_names[REGNO (inner)]);
661 }
662 else
663 cris_operand_lossage ("unexpected index-type in cris_print_index",
664 index);
665 }
666
667 /* Print a base rtx of an address to file. */
668
669 static void
cris_print_base(rtx base,FILE * file)670 cris_print_base (rtx base, FILE *file)
671 {
672 if (REG_P (base))
673 fprintf (file, "$%s", reg_names[REGNO (base)]);
674 else if (GET_CODE (base) == POST_INC)
675 {
676 gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM);
677 fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]);
678 }
679 else
680 cris_operand_lossage ("unexpected base-type in cris_print_base",
681 base);
682 }
683
684 /* Usable as a guard in expressions. */
685
686 int
cris_fatal(char * arg)687 cris_fatal (char *arg)
688 {
689 internal_error (arg);
690
691 /* We'll never get here; this is just to appease compilers. */
692 return 0;
693 }
694
695 /* Return nonzero if REGNO is an ordinary register that *needs* to be
696 saved together with other registers, possibly by a MOVEM instruction,
697 or is saved for target-independent reasons. There may be
698 target-dependent reasons to save the register anyway; this is just a
699 wrapper for a complicated conditional. */
700
701 static int
cris_reg_saved_in_regsave_area(unsigned int regno,bool got_really_used)702 cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used)
703 {
704 return
705 (((df_regs_ever_live_p (regno)
706 && !call_used_regs[regno])
707 || (regno == PIC_OFFSET_TABLE_REGNUM
708 && (got_really_used
709 /* It is saved anyway, if there would be a gap. */
710 || (flag_pic
711 && df_regs_ever_live_p (regno + 1)
712 && !call_used_regs[regno + 1]))))
713 && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed)
714 && regno != CRIS_SRP_REGNUM)
715 || (crtl->calls_eh_return
716 && (regno == EH_RETURN_DATA_REGNO (0)
717 || regno == EH_RETURN_DATA_REGNO (1)
718 || regno == EH_RETURN_DATA_REGNO (2)
719 || regno == EH_RETURN_DATA_REGNO (3)));
720 }
721
722 /* The PRINT_OPERAND worker. */
723
724 static void
cris_print_operand(FILE * file,rtx x,int code)725 cris_print_operand (FILE *file, rtx x, int code)
726 {
727 rtx operand = x;
728
729 /* Size-strings corresponding to MULT expressions. */
730 static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
731
732 /* New code entries should just be added to the switch below. If
733 handling is finished, just return. If handling was just a
734 modification of the operand, the modified operand should be put in
735 "operand", and then do a break to let default handling
736 (zero-modifier) output the operand. */
737
738 switch (code)
739 {
740 case 'b':
741 /* Print the unsigned supplied integer as if it were signed
742 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
743 if (!satisfies_constraint_O (x))
744 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x);
745 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
746 INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535));
747 return;
748
749 case 'x':
750 /* Print assembler code for operator. */
751 fprintf (file, "%s", cris_op_str (operand));
752 return;
753
754 case 'o':
755 {
756 /* A movem modifier working on a parallel; output the register
757 name. */
758 int regno;
759
760 if (GET_CODE (x) != PARALLEL)
761 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x);
762
763 /* The second item can be (set reg (plus reg const)) to denote a
764 postincrement. */
765 regno
766 = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS
767 ? XVECLEN (x, 0) - 2
768 : XVECLEN (x, 0) - 1);
769
770 fprintf (file, "$%s", reg_names [regno]);
771 }
772 return;
773
774 case 'O':
775 {
776 /* A similar movem modifier; output the memory operand. */
777 rtx addr;
778
779 if (GET_CODE (x) != PARALLEL)
780 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x);
781
782 /* The lowest mem operand is in the first item, but perhaps it
783 needs to be output as postincremented. */
784 addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0)))
785 ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0)
786 : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0);
787
788 /* The second item can be a (set reg (plus reg const)) to denote
789 a modification. */
790 if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS)
791 {
792 /* It's a post-increment, if the address is a naked (reg). */
793 if (REG_P (addr))
794 addr = gen_rtx_POST_INC (SImode, addr);
795 else
796 {
797 /* Otherwise, it's a side-effect; RN=RN+M. */
798 fprintf (file, "[$%s=$%s%s%d]",
799 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))],
800 reg_names [REGNO (XEXP (addr, 0))],
801 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+",
802 (int) INTVAL (XEXP (addr, 1)));
803 return;
804 }
805 }
806 output_address (VOIDmode, addr);
807 }
808 return;
809
810 case 'p':
811 /* Adjust a power of two to its log2. */
812 if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 )
813 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x);
814 fprintf (file, "%d", exact_log2 (INTVAL (x)));
815 return;
816
817 case 's':
818 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
819 respectively. This modifier also terminates the inhibiting
820 effects of the 'x' modifier. */
821 cris_output_insn_is_bound = 0;
822 if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
823 {
824 if (INTVAL (x) >= 0)
825 {
826 if (INTVAL (x) <= 255)
827 putc ('b', file);
828 else if (INTVAL (x) <= 65535)
829 putc ('w', file);
830 else
831 putc ('d', file);
832 }
833 else
834 putc ('d', file);
835 return;
836 }
837
838 /* For a non-integer, print the size of the operand. */
839 putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode)
840 ? 'd' : GET_MODE (x) == HImode ? 'w'
841 : GET_MODE (x) == QImode ? 'b'
842 /* If none of the above, emit an erroneous size letter. */
843 : 'X',
844 file);
845 return;
846
847 case 'z':
848 /* Const_int: print b for -127 <= x <= 255,
849 w for -32768 <= x <= 65535, else die. */
850 if (!CONST_INT_P (x)
851 || INTVAL (x) < -32768 || INTVAL (x) > 65535)
852 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x);
853 putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file);
854 return;
855
856 case 'Z':
857 /* If this is a GOT-symbol, print the size-letter corresponding to
858 -fpic/-fPIC. For everything else, print "d". */
859 putc ((flag_pic == 1
860 && GET_CODE (x) == CONST
861 && GET_CODE (XEXP (x, 0)) == UNSPEC
862 && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD)
863 ? 'w' : 'd', file);
864 return;
865
866 case '#':
867 /* Output a 'nop' if there's nothing for the delay slot.
868 This method stolen from the sparc files. */
869 if (dbr_sequence_length () == 0)
870 fputs ("\n\tnop", file);
871 return;
872
873 case '!':
874 /* Output directive for alignment padded with "nop" insns.
875 Optimizing for size, it's plain 4-byte alignment, otherwise we
876 align the section to a cache-line (32 bytes) and skip at max 2
877 bytes, i.e. we skip if it's the last insn on a cache-line. The
878 latter is faster by a small amount (for two test-programs 99.6%
879 and 99.9%) and larger by a small amount (ditto 100.1% and
880 100.2%). This is supposed to be the simplest yet performance-
881 wise least intrusive way to make sure the immediately following
882 (supposed) muls/mulu insn isn't located at the end of a
883 cache-line. */
884 if (TARGET_MUL_BUG)
885 fputs (optimize_size
886 ? ".p2alignw 2,0x050f\n\t"
887 : ".p2alignw 5,0x050f,2\n\t", file);
888 return;
889
890 case ':':
891 /* The PIC register. */
892 if (! flag_pic)
893 internal_error ("invalid use of ':' modifier");
894 fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]);
895 return;
896
897 case 'H':
898 /* Print high (most significant) part of something. */
899 switch (GET_CODE (operand))
900 {
901 case CONST_INT:
902 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
903 value is kept here, and so may be other than 0 or -1. */
904 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
905 INTVAL (operand_subword (operand, 1, 0, DImode)));
906 return;
907
908 case CONST_DOUBLE:
909 /* High part of a long long constant. */
910 if (GET_MODE (operand) == VOIDmode)
911 {
912 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
913 return;
914 }
915 else
916 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
917
918 case REG:
919 /* Print reg + 1. Check that there's not an attempt to print
920 high-parts of registers like stack-pointer or higher, except
921 for SRP (where the "high part" is MOF). */
922 if (REGNO (operand) > STACK_POINTER_REGNUM - 2
923 && (REGNO (operand) != CRIS_SRP_REGNUM
924 || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM
925 || fixed_regs[CRIS_MOF_REGNUM] != 0))
926 LOSE_AND_RETURN ("bad register", operand);
927 fprintf (file, "$%s", reg_names[REGNO (operand) + 1]);
928 return;
929
930 case MEM:
931 /* Adjust memory address to high part. */
932 {
933 rtx adj_mem = operand;
934 int size
935 = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT;
936
937 /* Adjust so we can use two SImode in DImode.
938 Calling adj_offsettable_operand will make sure it is an
939 offsettable address. Don't do this for a postincrement
940 though; it should remain as it was. */
941 if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC)
942 adj_mem
943 = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2);
944
945 output_address (VOIDmode, XEXP (adj_mem, 0));
946 return;
947 }
948
949 default:
950 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
951 }
952
953 case 'L':
954 /* Strip the MEM expression. */
955 operand = XEXP (operand, 0);
956 break;
957
958 case 'e':
959 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
960 iterators and attributes in cris.md to avoid the need for %x
961 and %E (and %e) and state passed between those modifiers. */
962 cris_output_insn_is_bound = 0;
963 /* FALL THROUGH. */
964 case 'E':
965 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
966 cris_output_insn_is_bound is nonzero. */
967 if (GET_CODE (operand) != SIGN_EXTEND
968 && GET_CODE (operand) != ZERO_EXTEND
969 && !CONST_INT_P (operand))
970 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x);
971
972 if (cris_output_insn_is_bound)
973 {
974 cris_output_insn_is_bound = 0;
975 return;
976 }
977
978 putc (GET_CODE (operand) == SIGN_EXTEND
979 || (CONST_INT_P (operand) && INTVAL (operand) < 0)
980 ? 's' : 'u', file);
981 return;
982
983 case 'm':
984 /* Print the size letter of the inner element. We can do it by
985 calling ourselves with the 's' modifier. */
986 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
987 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x);
988 cris_print_operand (file, XEXP (operand, 0), 's');
989 return;
990
991 case 'M':
992 /* Print the least significant part of operand. */
993 if (GET_CODE (operand) == CONST_DOUBLE)
994 {
995 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
996 return;
997 }
998 else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand))
999 {
1000 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1001 INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1));
1002 return;
1003 }
1004 /* Otherwise the least significant part equals the normal part,
1005 so handle it normally. */
1006 break;
1007
1008 case 'A':
1009 /* When emitting an add for the high part of a DImode constant, we
1010 want to use addq for 0 and adds.w for -1. */
1011 if (!CONST_INT_P (operand))
1012 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x);
1013 fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq");
1014 return;
1015
1016 case 'P':
1017 /* For const_int operands, print the additive mnemonic and the
1018 modified operand (byte-sized operands don't save anything):
1019 N=MIN_INT..-65536: add.d N
1020 -65535..-64: subu.w -N
1021 -63..-1: subq -N
1022 0..63: addq N
1023 64..65535: addu.w N
1024 65536..MAX_INT: add.d N.
1025 (Emitted mnemonics are capitalized to simplify testing.)
1026 For anything else (N.B: only register is valid), print "add.d". */
1027 if (REG_P (operand))
1028 {
1029 fprintf (file, "Add.d ");
1030
1031 /* Deal with printing the operand by dropping through to the
1032 normal path. */
1033 break;
1034 }
1035 else
1036 {
1037 int val;
1038 gcc_assert (CONST_INT_P (operand));
1039
1040 val = INTVAL (operand);
1041 if (!IN_RANGE (val, -65535, 65535))
1042 fprintf (file, "Add.d %d", val);
1043 else if (val <= -64)
1044 fprintf (file, "Subu.w %d", -val);
1045 else if (val <= -1)
1046 fprintf (file, "Subq %d", -val);
1047 else if (val <= 63)
1048 fprintf (file, "Addq %d", val);
1049 else if (val <= 65535)
1050 fprintf (file, "Addu.w %d", val);
1051 return;
1052 }
1053 break;
1054
1055 case 'q':
1056 /* If the operand is an integer -31..31, print "q" else ".d". */
1057 if (CONST_INT_P (operand) && IN_RANGE (INTVAL (operand), -31, 31))
1058 fprintf (file, "q");
1059 else
1060 fprintf (file, ".d");
1061 return;
1062
1063 case 'd':
1064 /* If this is a GOT symbol, force it to be emitted as :GOT and
1065 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1066 Avoid making this too much of a special case. */
1067 if (flag_pic == 1 && CRIS_CONSTANT_P (operand))
1068 {
1069 int flag_pic_save = flag_pic;
1070
1071 flag_pic = 2;
1072 cris_output_addr_const (file, operand);
1073 flag_pic = flag_pic_save;
1074 return;
1075 }
1076 break;
1077
1078 case 'D':
1079 /* When emitting an sub for the high part of a DImode constant, we
1080 want to use subq for 0 and subs.w for -1. */
1081 if (!CONST_INT_P (operand))
1082 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x);
1083 fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq");
1084 return;
1085
1086 case 'S':
1087 /* Print the operand as the index-part of an address.
1088 Easiest way out is to use cris_print_index. */
1089 cris_print_index (operand, file);
1090 return;
1091
1092 case 'T':
1093 /* Print the size letter for an operand to a MULT, which must be a
1094 const_int with a suitable value. */
1095 if (!CONST_INT_P (operand) || INTVAL (operand) > 4)
1096 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x);
1097 fprintf (file, "%s", mults[INTVAL (operand)]);
1098 return;
1099
1100 case 'u':
1101 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1102 if (flag_pic == 1
1103 && GET_CODE (operand) == CONST
1104 && GET_CODE (XEXP (operand, 0)) == UNSPEC
1105 && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD)
1106 fprintf (file, "u.w");
1107 else
1108 fprintf (file, ".d");
1109 return;
1110
1111 case 0:
1112 /* No code, print as usual. */
1113 break;
1114
1115 default:
1116 LOSE_AND_RETURN ("invalid operand modifier letter", x);
1117 }
1118
1119 /* Print an operand as without a modifier letter. */
1120 switch (GET_CODE (operand))
1121 {
1122 case REG:
1123 if (REGNO (operand) > 15
1124 && REGNO (operand) != CRIS_MOF_REGNUM
1125 && REGNO (operand) != CRIS_SRP_REGNUM
1126 && REGNO (operand) != CRIS_CC0_REGNUM)
1127 internal_error ("internal error: bad register: %d", REGNO (operand));
1128 fprintf (file, "$%s", reg_names[REGNO (operand)]);
1129 return;
1130
1131 case MEM:
1132 output_address (GET_MODE (operand), XEXP (operand, 0));
1133 return;
1134
1135 case CONST_DOUBLE:
1136 if (GET_MODE (operand) == VOIDmode)
1137 /* A long long constant. */
1138 output_addr_const (file, operand);
1139 else
1140 {
1141 /* Only single precision is allowed as plain operands the
1142 moment. */
1143 long l;
1144
1145 /* FIXME: Perhaps check overflow of the "single". */
1146 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operand), l);
1147
1148 fprintf (file, "0x%lx", l);
1149 }
1150 return;
1151
1152 case UNSPEC:
1153 /* Fall through. */
1154 case CONST:
1155 cris_output_addr_const (file, operand);
1156 return;
1157
1158 case MULT:
1159 case ASHIFT:
1160 {
1161 /* For a (MULT (reg X) const_int) we output "rX.S". */
1162 int i = CONST_INT_P (XEXP (operand, 1))
1163 ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0));
1164 rtx reg = CONST_INT_P (XEXP (operand, 1))
1165 ? XEXP (operand, 0) : XEXP (operand, 1);
1166
1167 if (!REG_P (reg)
1168 || (!CONST_INT_P (XEXP (operand, 0))
1169 && !CONST_INT_P (XEXP (operand, 1))))
1170 LOSE_AND_RETURN ("unexpected multiplicative operand", x);
1171
1172 cris_print_base (reg, file);
1173 fprintf (file, ".%c",
1174 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b'
1175 : i == 4 ? 'd'
1176 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w'
1177 : 'd');
1178 return;
1179 }
1180
1181 default:
1182 /* No need to handle all strange variants, let output_addr_const
1183 do it for us. */
1184 if (CRIS_CONSTANT_P (operand))
1185 {
1186 cris_output_addr_const (file, operand);
1187 return;
1188 }
1189
1190 LOSE_AND_RETURN ("unexpected operand", x);
1191 }
1192 }
1193
1194 static bool
cris_print_operand_punct_valid_p(unsigned char code)1195 cris_print_operand_punct_valid_p (unsigned char code)
1196 {
1197 return (code == '#' || code == '!' || code == ':');
1198 }
1199
1200 /* The PRINT_OPERAND_ADDRESS worker. */
1201
1202 static void
cris_print_operand_address(FILE * file,machine_mode,rtx x)1203 cris_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x)
1204 {
1205 /* All these were inside MEM:s so output indirection characters. */
1206 putc ('[', file);
1207
1208 if (CONSTANT_ADDRESS_P (x))
1209 cris_output_addr_const (file, x);
1210 else if (cris_base_or_autoincr_p (x, true))
1211 cris_print_base (x, file);
1212 else if (GET_CODE (x) == PLUS)
1213 {
1214 rtx x1, x2;
1215
1216 x1 = XEXP (x, 0);
1217 x2 = XEXP (x, 1);
1218 if (cris_base_p (x1, true))
1219 {
1220 cris_print_base (x1, file);
1221 cris_print_index (x2, file);
1222 }
1223 else if (cris_base_p (x2, true))
1224 {
1225 cris_print_base (x2, file);
1226 cris_print_index (x1, file);
1227 }
1228 else
1229 LOSE_AND_RETURN ("unrecognized address", x);
1230 }
1231 else if (MEM_P (x))
1232 {
1233 /* A DIP. Output more indirection characters. */
1234 putc ('[', file);
1235 cris_print_base (XEXP (x, 0), file);
1236 putc (']', file);
1237 }
1238 else
1239 LOSE_AND_RETURN ("unrecognized address", x);
1240
1241 putc (']', file);
1242 }
1243
1244 /* The RETURN_ADDR_RTX worker.
1245 We mark that the return address is used, either by EH or
1246 __builtin_return_address, for use by the function prologue and
1247 epilogue. FIXME: This isn't optimal; we just use the mark in the
1248 prologue and epilogue to say that the return address is to be stored
1249 in the stack frame. We could return SRP for leaf-functions and use the
1250 initial-value machinery. */
1251
1252 rtx
cris_return_addr_rtx(int count,rtx frameaddr ATTRIBUTE_UNUSED)1253 cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED)
1254 {
1255 cfun->machine->needs_return_address_on_stack = 1;
1256
1257 /* The return-address is stored just above the saved frame-pointer (if
1258 present). Apparently we can't eliminate from the frame-pointer in
1259 that direction, so use the incoming args (maybe pretended) pointer. */
1260 return count == 0
1261 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, virtual_incoming_args_rtx, -4))
1262 : NULL_RTX;
1263 }
1264
1265 /* Accessor used in cris.md:return because cfun->machine isn't available
1266 there. */
1267
1268 bool
cris_return_address_on_stack(void)1269 cris_return_address_on_stack (void)
1270 {
1271 return df_regs_ever_live_p (CRIS_SRP_REGNUM)
1272 || cfun->machine->needs_return_address_on_stack;
1273 }
1274
1275 /* Accessor used in cris.md:return because cfun->machine isn't available
1276 there. */
1277
1278 bool
cris_return_address_on_stack_for_return(void)1279 cris_return_address_on_stack_for_return (void)
1280 {
1281 return cfun->machine->return_type == CRIS_RETINSN_RET ? false
1282 : cris_return_address_on_stack ();
1283 }
1284
1285 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1286 handles FP -> SP elimination offset. */
1287
1288 static int
cris_initial_frame_pointer_offset(void)1289 cris_initial_frame_pointer_offset (void)
1290 {
1291 int regno;
1292
1293 /* Initial offset is 0 if we don't have a frame pointer. */
1294 int offs = 0;
1295 bool got_really_used = false;
1296
1297 if (crtl->uses_pic_offset_table)
1298 {
1299 push_topmost_sequence ();
1300 got_really_used
1301 = reg_used_between_p (pic_offset_table_rtx, get_insns (),
1302 NULL);
1303 pop_topmost_sequence ();
1304 }
1305
1306 /* And 4 for each register pushed. */
1307 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1308 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1309 offs += 4;
1310
1311 /* And then, last, we add the locals allocated. */
1312 offs += get_frame_size ();
1313
1314 /* And more; the accumulated args size. */
1315 offs += crtl->outgoing_args_size;
1316
1317 /* Then round it off, in case we use aligned stack. */
1318 if (TARGET_STACK_ALIGN)
1319 offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1;
1320
1321 return offs;
1322 }
1323
1324 /* The INITIAL_ELIMINATION_OFFSET worker.
1325 Calculate the difference between imaginary registers such as frame
1326 pointer and the stack pointer. Used to eliminate the frame pointer
1327 and imaginary arg pointer. */
1328
1329 int
cris_initial_elimination_offset(int fromreg,int toreg)1330 cris_initial_elimination_offset (int fromreg, int toreg)
1331 {
1332 int fp_sp_offset
1333 = cris_initial_frame_pointer_offset ();
1334
1335 /* We should be able to use regs_ever_live and related prologue
1336 information here, or alpha should not as well. */
1337 bool return_address_on_stack = cris_return_address_on_stack ();
1338
1339 /* Here we act as if the frame-pointer were needed. */
1340 int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
1341
1342 if (fromreg == ARG_POINTER_REGNUM
1343 && toreg == FRAME_POINTER_REGNUM)
1344 return ap_fp_offset;
1345
1346 /* Between the frame pointer and the stack are only "normal" stack
1347 variables and saved registers. */
1348 if (fromreg == FRAME_POINTER_REGNUM
1349 && toreg == STACK_POINTER_REGNUM)
1350 return fp_sp_offset;
1351
1352 /* We need to balance out the frame pointer here. */
1353 if (fromreg == ARG_POINTER_REGNUM
1354 && toreg == STACK_POINTER_REGNUM)
1355 return ap_fp_offset + fp_sp_offset - 4;
1356
1357 gcc_unreachable ();
1358 }
1359
1360 /* Nonzero if X is a hard reg that can be used as an index. */
1361 static inline bool
reg_ok_for_base_p(const_rtx x,bool strict)1362 reg_ok_for_base_p (const_rtx x, bool strict)
1363 {
1364 return ((! strict && ! HARD_REGISTER_P (x))
1365 || REGNO_OK_FOR_BASE_P (REGNO (x)));
1366 }
1367
1368 /* Nonzero if X is a hard reg that can be used as an index. */
1369 static inline bool
reg_ok_for_index_p(const_rtx x,bool strict)1370 reg_ok_for_index_p (const_rtx x, bool strict)
1371 {
1372 return reg_ok_for_base_p (x, strict);
1373 }
1374
1375 /* No symbol can be used as an index (or more correct, as a base) together
1376 with a register with PIC; the PIC register must be there. */
1377
1378 bool
cris_constant_index_p(const_rtx x)1379 cris_constant_index_p (const_rtx x)
1380 {
1381 return (CRIS_CONSTANT_P (x) && (!flag_pic || cris_valid_pic_const (x, true)));
1382 }
1383
1384 /* True if X is a valid base register. */
1385
1386 bool
cris_base_p(const_rtx x,bool strict)1387 cris_base_p (const_rtx x, bool strict)
1388 {
1389 return (REG_P (x) && reg_ok_for_base_p (x, strict));
1390 }
1391
1392 /* True if X is a valid index register. */
1393
1394 static inline bool
cris_index_p(const_rtx x,bool strict)1395 cris_index_p (const_rtx x, bool strict)
1396 {
1397 return (REG_P (x) && reg_ok_for_index_p (x, strict));
1398 }
1399
1400 /* True if X is a valid base register with or without autoincrement. */
1401
1402 bool
cris_base_or_autoincr_p(const_rtx x,bool strict)1403 cris_base_or_autoincr_p (const_rtx x, bool strict)
1404 {
1405 return (cris_base_p (x, strict)
1406 || (GET_CODE (x) == POST_INC
1407 && cris_base_p (XEXP (x, 0), strict)
1408 && REGNO (XEXP (x, 0)) != CRIS_ACR_REGNUM));
1409 }
1410
1411 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1412
1413 bool
cris_bdap_index_p(const_rtx x,bool strict)1414 cris_bdap_index_p (const_rtx x, bool strict)
1415 {
1416 return ((MEM_P (x)
1417 && GET_MODE (x) == SImode
1418 && cris_base_or_autoincr_p (XEXP (x, 0), strict))
1419 || (GET_CODE (x) == SIGN_EXTEND
1420 && MEM_P (XEXP (x, 0))
1421 && (GET_MODE (XEXP (x, 0)) == HImode
1422 || GET_MODE (XEXP (x, 0)) == QImode)
1423 && cris_base_or_autoincr_p (XEXP (XEXP (x, 0), 0), strict)));
1424 }
1425
1426 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1427
1428 bool
cris_biap_index_p(const_rtx x,bool strict)1429 cris_biap_index_p (const_rtx x, bool strict)
1430 {
1431 return (cris_index_p (x, strict)
1432 || (GET_CODE (x) == MULT
1433 && cris_index_p (XEXP (x, 0), strict)
1434 && cris_scale_int_operand (XEXP (x, 1), VOIDmode)));
1435 }
1436
1437 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1438
1439 A PIC operand looks like a normal symbol here. At output we dress it
1440 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1441 symbol) so we exclude all addressing modes where we can't replace a
1442 plain "symbol" with that. A global PIC symbol does not fit anywhere
1443 here (but is thankfully a general_operand in itself). A local PIC
1444 symbol is valid for the plain "symbol + offset" case. */
1445
1446 bool
cris_legitimate_address_p(machine_mode mode,rtx x,bool strict)1447 cris_legitimate_address_p (machine_mode mode, rtx x, bool strict)
1448 {
1449 const_rtx x1, x2;
1450
1451 if (cris_base_or_autoincr_p (x, strict))
1452 return true;
1453 else if (TARGET_V32)
1454 /* Nothing else is valid then. */
1455 return false;
1456 else if (cris_constant_index_p (x))
1457 return true;
1458 /* Indexed? */
1459 else if (GET_CODE (x) == PLUS)
1460 {
1461 x1 = XEXP (x, 0);
1462 x2 = XEXP (x, 1);
1463 /* BDAP o, Rd. */
1464 if ((cris_base_p (x1, strict) && cris_constant_index_p (x2))
1465 || (cris_base_p (x2, strict) && cris_constant_index_p (x1))
1466 /* BDAP Rs[+], Rd. */
1467 || (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1468 && ((cris_base_p (x1, strict)
1469 && cris_bdap_index_p (x2, strict))
1470 || (cris_base_p (x2, strict)
1471 && cris_bdap_index_p (x1, strict))
1472 /* BIAP.m Rs, Rd */
1473 || (cris_base_p (x1, strict)
1474 && cris_biap_index_p (x2, strict))
1475 || (cris_base_p (x2, strict)
1476 && cris_biap_index_p (x1, strict)))))
1477 return true;
1478 }
1479 else if (MEM_P (x))
1480 {
1481 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1482 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1483 && cris_base_or_autoincr_p (XEXP (x, 0), strict))
1484 return true;
1485 }
1486
1487 return false;
1488 }
1489
1490 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle
1491 PIC constants that aren't legitimized. FIXME: there used to be a
1492 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle
1493 PIC constants, but no more (4.7 era); testcase: glibc init-first.c.
1494 While that may be seen as a bug, that guarantee seems a wart by design,
1495 so don't bother; fix the documentation instead. */
1496
1497 bool
cris_legitimate_constant_p(machine_mode mode ATTRIBUTE_UNUSED,rtx x)1498 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1499 {
1500 enum cris_symbol_type t;
1501
1502 if (flag_pic)
1503 return LEGITIMATE_PIC_OPERAND_P (x);
1504
1505 t = cris_symbol_type_of (x);
1506
1507 return
1508 t == cris_no_symbol
1509 || t == cris_offsettable_symbol
1510 || t == cris_unspec;
1511 }
1512
1513 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1514
1515 bool
cris_reload_address_legitimized(rtx x,machine_mode mode ATTRIBUTE_UNUSED,int opnum ATTRIBUTE_UNUSED,int itype,int ind_levels ATTRIBUTE_UNUSED)1516 cris_reload_address_legitimized (rtx x,
1517 machine_mode mode ATTRIBUTE_UNUSED,
1518 int opnum ATTRIBUTE_UNUSED,
1519 int itype,
1520 int ind_levels ATTRIBUTE_UNUSED)
1521 {
1522 enum reload_type type = (enum reload_type) itype;
1523 rtx op0, op1;
1524 rtx *op1p;
1525
1526 if (GET_CODE (x) != PLUS)
1527 return false;
1528
1529 if (TARGET_V32)
1530 return false;
1531
1532 op0 = XEXP (x, 0);
1533 op1 = XEXP (x, 1);
1534 op1p = &XEXP (x, 1);
1535
1536 if (!REG_P (op1))
1537 return false;
1538
1539 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0)))
1540 {
1541 rtx op00 = XEXP (op0, 0);
1542 rtx op000 = XEXP (op00, 0);
1543 rtx *op000p = &XEXP (op00, 0);
1544
1545 if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode)
1546 && (REG_P (op000)
1547 || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0)))))
1548 {
1549 bool something_reloaded = false;
1550
1551 if (GET_CODE (op000) == POST_INC
1552 && REG_P (XEXP (op000, 0))
1553 && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER)
1554 /* No, this gets too complicated and is too rare to care
1555 about trying to improve on the general code Here.
1556 As the return-value is an all-or-nothing indicator, we
1557 punt on the other register too. */
1558 return false;
1559
1560 if ((REG_P (op000)
1561 && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER))
1562 {
1563 /* The address of the inner mem is a pseudo or wrong
1564 reg: reload that. */
1565 push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS,
1566 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
1567 something_reloaded = true;
1568 }
1569
1570 if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER)
1571 {
1572 /* Base register is a pseudo or wrong reg: reload it. */
1573 push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS,
1574 GET_MODE (x), VOIDmode, 0, 0,
1575 opnum, type);
1576 something_reloaded = true;
1577 }
1578
1579 gcc_assert (something_reloaded);
1580
1581 return true;
1582 }
1583 }
1584
1585 return false;
1586 }
1587
1588
1589 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1590
1591 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1592 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1593 out a constant into the constant pool, we will trap this case and
1594 return something a bit more sane. FIXME: Check if this is a bug.
1595 Beware that we must not "override" classes that can be specified as
1596 constraint letters, or else asm operands using them will fail when
1597 they need to be reloaded. FIXME: Investigate whether that constitutes
1598 a bug. */
1599
1600 static reg_class_t
cris_preferred_reload_class(rtx x ATTRIBUTE_UNUSED,reg_class_t rclass)1601 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass)
1602 {
1603 if (rclass != ACR_REGS
1604 && rclass != MOF_REGS
1605 && rclass != MOF_SRP_REGS
1606 && rclass != SRP_REGS
1607 && rclass != CC0_REGS
1608 && rclass != SPECIAL_REGS)
1609 return GENERAL_REGS;
1610
1611 return rclass;
1612 }
1613
1614 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1615
1616 static int
cris_register_move_cost(machine_mode mode ATTRIBUTE_UNUSED,reg_class_t from,reg_class_t to)1617 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
1618 reg_class_t from, reg_class_t to)
1619 {
1620 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1621 their move cost within that class is higher. How about 7? That's 3
1622 for a move to a GENERAL_REGS register, 3 for the move from the
1623 GENERAL_REGS register, and 1 for the increased register pressure.
1624 Also, it's higher than the memory move cost, as it should.
1625 We also do this for ALL_REGS, since we don't want that class to be
1626 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1627 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1628 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1629 used when a GENERAL_REGS should be used, even if there are call-saved
1630 GENERAL_REGS left to allocate. This is because the fall-back when
1631 the most preferred register class isn't available, isn't the next
1632 (or next good) wider register class, but the *most widest* register
1633 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1634
1635 if ((reg_classes_intersect_p (from, SPECIAL_REGS)
1636 && reg_classes_intersect_p (to, SPECIAL_REGS))
1637 || from == ALL_REGS || to == ALL_REGS)
1638 return 7;
1639
1640 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1641 generally prefer GENERAL_REGS. */
1642 if (reg_classes_intersect_p (from, SPECIAL_REGS)
1643 || reg_classes_intersect_p (to, SPECIAL_REGS))
1644 return 3;
1645
1646 return 2;
1647 }
1648
1649 /* Worker function for TARGET_MEMORY_MOVE_COST.
1650
1651 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1652 suffice. */
1653
1654 static int
cris_memory_move_cost(machine_mode mode,reg_class_t rclass ATTRIBUTE_UNUSED,bool in ATTRIBUTE_UNUSED)1655 cris_memory_move_cost (machine_mode mode,
1656 reg_class_t rclass ATTRIBUTE_UNUSED,
1657 bool in ATTRIBUTE_UNUSED)
1658 {
1659 if (mode == QImode
1660 || mode == HImode)
1661 return 4;
1662 else
1663 return 6;
1664 }
1665
1666 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1667 FIXME: this code is historical; its functionality should be
1668 refactored to look at insn attributes and moved to
1669 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1670
1671 static void
cris_normal_notice_update_cc(rtx exp,rtx insn)1672 cris_normal_notice_update_cc (rtx exp, rtx insn)
1673 {
1674 /* "Normal" means, for:
1675 (set (cc0) (...)):
1676 CC is (...).
1677
1678 (set (reg) (...)):
1679 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1680 register or (v32 and (...) is -32..-1), then CC does not change.
1681 CC_NO_OVERFLOW unless (...) is reg or mem.
1682
1683 (set (mem) (...)):
1684 CC does not change.
1685
1686 (set (pc) (...)):
1687 CC does not change.
1688
1689 (parallel
1690 (set (reg1) (mem (bdap/biap)))
1691 (set (reg2) (bdap/biap))):
1692 CC is (reg1) and (mem (reg2))
1693
1694 (parallel
1695 (set (mem (bdap/biap)) (reg1)) [or 0]
1696 (set (reg2) (bdap/biap))):
1697 CC does not change.
1698
1699 (where reg and mem includes strict_low_parts variants thereof)
1700
1701 For all others, assume CC is clobbered.
1702 Note that we do not have to care about setting CC_NO_OVERFLOW,
1703 since the overflow flag is set to 0 (i.e. right) for
1704 instructions where it does not have any sane sense, but where
1705 other flags have meanings. (This includes shifts; the carry is
1706 not set by them).
1707
1708 Note that there are other parallel constructs we could match,
1709 but we don't do that yet. */
1710
1711 if (GET_CODE (exp) == SET)
1712 {
1713 /* FIXME: Check when this happens. It looks like we should
1714 actually do a CC_STATUS_INIT here to be safe. */
1715 if (SET_DEST (exp) == pc_rtx)
1716 return;
1717
1718 /* Record CC0 changes, so we do not have to output multiple
1719 test insns. */
1720 if (SET_DEST (exp) == cc0_rtx)
1721 {
1722 CC_STATUS_INIT;
1723
1724 if (GET_CODE (SET_SRC (exp)) == COMPARE
1725 && XEXP (SET_SRC (exp), 1) == const0_rtx)
1726 cc_status.value1 = XEXP (SET_SRC (exp), 0);
1727 else
1728 cc_status.value1 = SET_SRC (exp);
1729
1730 /* Handle flags for the special btstq on one bit. */
1731 if (GET_CODE (cc_status.value1) == ZERO_EXTRACT
1732 && XEXP (cc_status.value1, 1) == const1_rtx)
1733 {
1734 if (CONST_INT_P (XEXP (cc_status.value1, 0)))
1735 /* Using cmpq. */
1736 cc_status.flags = CC_INVERTED;
1737 else
1738 /* A one-bit btstq. */
1739 cc_status.flags = CC_Z_IN_NOT_N;
1740 }
1741
1742 else if (GET_CODE (SET_SRC (exp)) == COMPARE)
1743 {
1744 if (!REG_P (XEXP (SET_SRC (exp), 0))
1745 && XEXP (SET_SRC (exp), 1) != const0_rtx)
1746 /* For some reason gcc will not canonicalize compare
1747 operations, reversing the sign by itself if
1748 operands are in wrong order. */
1749 /* (But NOT inverted; eq is still eq.) */
1750 cc_status.flags = CC_REVERSED;
1751
1752 /* This seems to be overlooked by gcc. FIXME: Check again.
1753 FIXME: Is it really safe? */
1754 cc_status.value2
1755 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)),
1756 XEXP (SET_SRC (exp), 0),
1757 XEXP (SET_SRC (exp), 1));
1758 }
1759 return;
1760 }
1761 else if (REG_P (SET_DEST (exp))
1762 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1763 && REG_P (XEXP (SET_DEST (exp), 0))))
1764 {
1765 /* A register is set; normally CC is set to show that no
1766 test insn is needed. Catch the exceptions. */
1767
1768 /* If not to cc0, then no "set"s in non-natural mode give
1769 ok cc0... */
1770 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
1771 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
1772 {
1773 /* ... except add:s and sub:s in DImode. */
1774 if (GET_MODE (SET_DEST (exp)) == DImode
1775 && (GET_CODE (SET_SRC (exp)) == PLUS
1776 || GET_CODE (SET_SRC (exp)) == MINUS))
1777 {
1778 CC_STATUS_INIT;
1779 cc_status.value1 = SET_DEST (exp);
1780 cc_status.value2 = SET_SRC (exp);
1781
1782 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1783 cc_status.value2))
1784 cc_status.value2 = 0;
1785
1786 /* Add and sub may set V, which gets us
1787 unoptimizable results in "gt" and "le" condition
1788 codes. */
1789 cc_status.flags |= CC_NO_OVERFLOW;
1790
1791 return;
1792 }
1793 }
1794 else if (SET_SRC (exp) == const0_rtx
1795 || (REG_P (SET_SRC (exp))
1796 && (REGNO (SET_SRC (exp))
1797 > CRIS_LAST_GENERAL_REGISTER))
1798 || (TARGET_V32
1799 && REG_P (SET_DEST (exp))
1800 && satisfies_constraint_I (SET_SRC (exp))))
1801 {
1802 /* There's no CC0 change for this case. Just check
1803 for overlap. */
1804 if (cc_status.value1
1805 && modified_in_p (cc_status.value1, insn))
1806 cc_status.value1 = 0;
1807
1808 if (cc_status.value2
1809 && modified_in_p (cc_status.value2, insn))
1810 cc_status.value2 = 0;
1811
1812 return;
1813 }
1814 else
1815 {
1816 CC_STATUS_INIT;
1817 cc_status.value1 = SET_DEST (exp);
1818 cc_status.value2 = SET_SRC (exp);
1819
1820 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1821 cc_status.value2))
1822 cc_status.value2 = 0;
1823
1824 /* Some operations may set V, which gets us
1825 unoptimizable results in "gt" and "le" condition
1826 codes. */
1827 if (GET_CODE (SET_SRC (exp)) == PLUS
1828 || GET_CODE (SET_SRC (exp)) == MINUS
1829 || GET_CODE (SET_SRC (exp)) == NEG)
1830 cc_status.flags |= CC_NO_OVERFLOW;
1831
1832 /* For V32, nothing with a register destination sets
1833 C and V usefully. */
1834 if (TARGET_V32)
1835 cc_status.flags |= CC_NO_OVERFLOW;
1836
1837 return;
1838 }
1839 }
1840 else if (MEM_P (SET_DEST (exp))
1841 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1842 && MEM_P (XEXP (SET_DEST (exp), 0))))
1843 {
1844 /* When SET to MEM, then CC is not changed (except for
1845 overlap). */
1846 if (cc_status.value1
1847 && modified_in_p (cc_status.value1, insn))
1848 cc_status.value1 = 0;
1849
1850 if (cc_status.value2
1851 && modified_in_p (cc_status.value2, insn))
1852 cc_status.value2 = 0;
1853
1854 return;
1855 }
1856 }
1857 else if (GET_CODE (exp) == PARALLEL)
1858 {
1859 if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
1860 && GET_CODE (XVECEXP (exp, 0, 1)) == SET
1861 && REG_P (XEXP (XVECEXP (exp, 0, 1), 0)))
1862 {
1863 if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0))
1864 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1)))
1865 {
1866 CC_STATUS_INIT;
1867
1868 /* For "move.S [rx=ry+o],rz", say CC reflects
1869 value1=rz and value2=[rx] */
1870 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1871 cc_status.value2
1872 = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1),
1873 XEXP (XVECEXP (exp, 0, 1), 0));
1874
1875 /* Huh? A side-effect cannot change the destination
1876 register. */
1877 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1878 cc_status.value2))
1879 internal_error ("internal error: sideeffect-insn affecting main effect");
1880
1881 /* For V32, moves to registers don't set C and V. */
1882 if (TARGET_V32)
1883 cc_status.flags |= CC_NO_OVERFLOW;
1884 return;
1885 }
1886 else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1))
1887 || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx)
1888 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0)))
1889 {
1890 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1891 say flags are not changed, except for overlap. */
1892 if (cc_status.value1
1893 && modified_in_p (cc_status.value1, insn))
1894 cc_status.value1 = 0;
1895
1896 if (cc_status.value2
1897 && modified_in_p (cc_status.value2, insn))
1898 cc_status.value2 = 0;
1899
1900 return;
1901 }
1902 }
1903 }
1904
1905 /* If we got here, the case wasn't covered by the code above. */
1906 CC_STATUS_INIT;
1907 }
1908
1909 /* This function looks into the pattern to see how this insn affects
1910 condition codes.
1911
1912 Used when to eliminate test insns before a condition-code user,
1913 such as a "scc" insn or a conditional branch. This includes
1914 checking if the entities that cc was updated by, are changed by the
1915 operation.
1916
1917 Currently a jumble of the old peek-inside-the-insn and the newer
1918 check-cc-attribute methods. */
1919
1920 void
cris_notice_update_cc(rtx exp,rtx_insn * insn)1921 cris_notice_update_cc (rtx exp, rtx_insn *insn)
1922 {
1923 enum attr_cc attrval = get_attr_cc (insn);
1924
1925 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1926 to still set CC_REVERSED as below, since that's required by some
1927 compare insn alternatives. (FIXME: GCC should do this virtual
1928 operand swap by itself.) A test-case that may otherwise fail is
1929 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1930 if (TARGET_CCINIT)
1931 {
1932 CC_STATUS_INIT;
1933
1934 if (attrval == CC_REV)
1935 cc_status.flags = CC_REVERSED;
1936 return;
1937 }
1938
1939 /* Slowly, we're converting to using attributes to control the setting
1940 of condition-code status. */
1941 switch (attrval)
1942 {
1943 case CC_NONE:
1944 /* Even if it is "none", a setting may clobber a previous
1945 cc-value, so check. */
1946 if (GET_CODE (exp) == SET)
1947 {
1948 if (cc_status.value1
1949 && modified_in_p (cc_status.value1, insn))
1950 cc_status.value1 = 0;
1951
1952 if (cc_status.value2
1953 && modified_in_p (cc_status.value2, insn))
1954 cc_status.value2 = 0;
1955 }
1956 return;
1957
1958 case CC_CLOBBER:
1959 CC_STATUS_INIT;
1960 return;
1961
1962 case CC_REV:
1963 case CC_NOOV32:
1964 case CC_NORMAL:
1965 cris_normal_notice_update_cc (exp, insn);
1966
1967 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1968 can change bge => bpl and blt => bmi by passing on to the cc0
1969 user that V should not be considered; bgt and ble are taken
1970 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1971 if (attrval == CC_NOOV32 && TARGET_V32)
1972 cc_status.flags |= CC_NO_OVERFLOW;
1973 return;
1974
1975 default:
1976 internal_error ("unknown cc_attr value");
1977 }
1978
1979 CC_STATUS_INIT;
1980 }
1981
1982 /* Return != 0 if the return sequence for the current function is short,
1983 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1984 registers must be saved, so return 0 then. */
1985
1986 bool
cris_simple_epilogue(void)1987 cris_simple_epilogue (void)
1988 {
1989 unsigned int regno;
1990 unsigned int reglimit = STACK_POINTER_REGNUM;
1991 bool got_really_used = false;
1992
1993 if (! reload_completed
1994 || frame_pointer_needed
1995 || get_frame_size () != 0
1996 || crtl->args.pretend_args_size
1997 || crtl->args.size
1998 || crtl->outgoing_args_size
1999 || crtl->calls_eh_return
2000
2001 /* If we're not supposed to emit prologue and epilogue, we must
2002 not emit return-type instructions. */
2003 || !TARGET_PROLOGUE_EPILOGUE)
2004 return false;
2005
2006 /* Can't return from stacked return address with v32. */
2007 if (TARGET_V32 && cris_return_address_on_stack ())
2008 return false;
2009
2010 if (crtl->uses_pic_offset_table)
2011 {
2012 push_topmost_sequence ();
2013 got_really_used
2014 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL);
2015 pop_topmost_sequence ();
2016 }
2017
2018 /* No simple epilogue if there are saved registers. */
2019 for (regno = 0; regno < reglimit; regno++)
2020 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2021 return false;
2022
2023 return true;
2024 }
2025
2026 /* Emit checking that MEM is aligned for an access in MODE, failing
2027 that, executing a "break 8" (or call to abort, if "break 8" is
2028 disabled). */
2029
2030 void
cris_emit_trap_for_misalignment(rtx mem)2031 cris_emit_trap_for_misalignment (rtx mem)
2032 {
2033 rtx addr, reg, ok_label, andop;
2034 rtx_insn *jmp;
2035 int natural_alignment;
2036 gcc_assert (MEM_P (mem));
2037
2038 natural_alignment = GET_MODE_SIZE (GET_MODE (mem));
2039 addr = XEXP (mem, 0);
2040 reg = force_reg (Pmode, addr);
2041 ok_label = gen_label_rtx ();
2042
2043 /* This will yield a btstq without a separate register used, usually -
2044 with the exception for PRE hoisting the "and" but not the branch
2045 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2046 andop = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1));
2047 emit_cmp_and_jump_insns (force_reg (SImode, andop), const0_rtx, EQ,
2048 NULL_RTX, Pmode, 1, ok_label);
2049 jmp = get_last_insn ();
2050 gcc_assert (JUMP_P (jmp));
2051
2052 predict_insn_def (jmp, PRED_NORETURN, TAKEN);
2053 expand_builtin_trap ();
2054 emit_label (ok_label);
2055 }
2056
2057 /* Expand a return insn (just one insn) marked as using SRP or stack
2058 slot depending on parameter ON_STACK. */
2059
2060 void
cris_expand_return(bool on_stack)2061 cris_expand_return (bool on_stack)
2062 {
2063 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2064 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2065 GCC expect just (return) to do the right thing when optimizing, so
2066 we do that until they're fixed. Currently, all return insns in a
2067 function must be the same (not really a limiting factor) so we need
2068 to check that it doesn't change half-way through. */
2069 emit_jump_insn (ret_rtx);
2070
2071 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
2072 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
2073
2074 cfun->machine->return_type
2075 = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET;
2076 }
2077
2078 /* Compute a (partial) cost for rtx X. Return true if the complete
2079 cost has been computed, and false if subexpressions should be
2080 scanned. In either case, *TOTAL contains the cost result. */
2081
2082 static bool
cris_rtx_costs(rtx x,machine_mode mode,int outer_code,int opno,int * total,bool speed)2083 cris_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno,
2084 int *total, bool speed)
2085 {
2086 int code = GET_CODE (x);
2087
2088 switch (code)
2089 {
2090 case CONST_INT:
2091 {
2092 HOST_WIDE_INT val = INTVAL (x);
2093 if (val == 0)
2094 *total = 0;
2095 else if (val < 32 && val >= -32)
2096 *total = 1;
2097 /* Eight or 16 bits are a word and cycle more expensive. */
2098 else if (val <= 32767 && val >= -32768)
2099 *total = 2;
2100 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2101 another word. FIXME: This isn't linear to 16 bits. */
2102 else
2103 *total = 4;
2104 return true;
2105 }
2106
2107 case LABEL_REF:
2108 *total = 6;
2109 return true;
2110
2111 case CONST:
2112 case SYMBOL_REF:
2113 *total = 6;
2114 return true;
2115
2116 case CONST_DOUBLE:
2117 if (x != CONST0_RTX (mode == VOIDmode ? DImode : mode))
2118 *total = 12;
2119 else
2120 /* Make 0.0 cheap, else test-insns will not be used. */
2121 *total = 0;
2122 return true;
2123
2124 case MULT:
2125 /* If we have one arm of an ADDI, make sure it gets the cost of
2126 one insn, i.e. zero cost for this operand, and just the cost
2127 of the PLUS, as the insn is created by combine from a PLUS
2128 and an ASHIFT, and the MULT cost below would make the
2129 combined value be larger than the separate insns. The insn
2130 validity is checked elsewhere by combine.
2131
2132 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2133 function should be rewritten. */
2134 if (outer_code == PLUS && cris_biap_index_p (x, false))
2135 {
2136 *total = 0;
2137 return true;
2138 }
2139
2140 /* Identify values that are no powers of two. Powers of 2 are
2141 taken care of already and those values should not be changed. */
2142 if (!CONST_INT_P (XEXP (x, 1))
2143 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
2144 {
2145 /* If we have a multiply insn, then the cost is between
2146 1 and 2 "fast" instructions. */
2147 if (TARGET_HAS_MUL_INSNS)
2148 {
2149 *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2150 return true;
2151 }
2152
2153 /* Estimate as 4 + 4 * #ofbits. */
2154 *total = COSTS_N_INSNS (132);
2155 return true;
2156 }
2157 return false;
2158
2159 case UDIV:
2160 case MOD:
2161 case UMOD:
2162 case DIV:
2163 if (!CONST_INT_P (XEXP (x, 1))
2164 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
2165 {
2166 /* Estimate this as 4 + 8 * #of bits. */
2167 *total = COSTS_N_INSNS (260);
2168 return true;
2169 }
2170 return false;
2171
2172 case AND:
2173 if (CONST_INT_P (XEXP (x, 1))
2174 /* Two constants may actually happen before optimization. */
2175 && !CONST_INT_P (XEXP (x, 0))
2176 && !satisfies_constraint_I (XEXP (x, 1)))
2177 {
2178 *total
2179 = (rtx_cost (XEXP (x, 0), mode, (enum rtx_code) outer_code,
2180 opno, speed) + 2
2181 + 2 * GET_MODE_NUNITS (mode));
2182 return true;
2183 }
2184 return false;
2185
2186 case ZERO_EXTRACT:
2187 if (outer_code != COMPARE)
2188 return false;
2189 /* fall through */
2190
2191 case ZERO_EXTEND: case SIGN_EXTEND:
2192 *total = rtx_cost (XEXP (x, 0), VOIDmode, (enum rtx_code) outer_code,
2193 opno, speed);
2194 return true;
2195
2196 default:
2197 return false;
2198 }
2199 }
2200
2201 /* The ADDRESS_COST worker. */
2202
2203 static int
cris_address_cost(rtx x,machine_mode mode ATTRIBUTE_UNUSED,addr_space_t as ATTRIBUTE_UNUSED,bool speed ATTRIBUTE_UNUSED)2204 cris_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED,
2205 addr_space_t as ATTRIBUTE_UNUSED,
2206 bool speed ATTRIBUTE_UNUSED)
2207 {
2208 /* The metric to use for the cost-macros is unclear.
2209 The metric used here is (the number of cycles needed) / 2,
2210 where we consider equal a cycle for a word of code and a cycle to
2211 read memory. FIXME: Adding "+ 1" to all values would avoid
2212 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2213 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2214 Unfortunately(?) such a hack would expose other pessimizations,
2215 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2216 loop there, without apparent reason. */
2217
2218 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2219 if (cris_base_or_autoincr_p (x, false))
2220 return 0;
2221
2222 /* An indirect mem must be a DIP. This means two bytes extra for code,
2223 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2224 if (MEM_P (x))
2225 return (2 + 4) / 2;
2226
2227 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2228 an extra DIP prefix and 4 bytes of constant in most cases. */
2229 if (CONSTANT_P (x))
2230 return (2 + 4) / 2;
2231
2232 /* Handle BIAP and BDAP prefixes. */
2233 if (GET_CODE (x) == PLUS)
2234 {
2235 rtx tem1 = XEXP (x, 0);
2236 rtx tem2 = XEXP (x, 1);
2237
2238 /* Local extended canonicalization rule: the first operand must
2239 be REG, unless it's an operation (MULT). */
2240 if (!REG_P (tem1) && GET_CODE (tem1) != MULT)
2241 tem1 = tem2, tem2 = XEXP (x, 0);
2242
2243 /* We'll "assume" we have canonical RTX now. */
2244 gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT);
2245
2246 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2247 recognize the typical MULT which is always in tem1 because of
2248 insn canonicalization. */
2249 if ((GET_CODE (tem1) == MULT && cris_biap_index_p (tem1, false))
2250 || REG_P (tem2))
2251 return 2 / 2;
2252
2253 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2254 PLUS is always found in tem2. */
2255 if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128)
2256 return 2 / 2;
2257
2258 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2259 bytes. */
2260 if (satisfies_constraint_L (tem2))
2261 return (2 + 2) / 2;
2262
2263 /* A BDAP with some other constant is 2 bytes extra. */
2264 if (CRIS_CONSTANT_P (tem2))
2265 return (2 + 2 + 2) / 2;
2266
2267 /* BDAP with something indirect should have a higher cost than
2268 BIAP with register. FIXME: Should it cost like a MEM or more? */
2269 return (2 + 2 + 2) / 2;
2270 }
2271
2272 /* What else? Return a high cost. It matters only for valid
2273 addressing modes. */
2274 return 10;
2275 }
2276
2277 /* Check various objections to the side-effect. Used in the test-part
2278 of an anonymous insn describing an insn with a possible side-effect.
2279 Returns nonzero if the implied side-effect is ok.
2280
2281 code : PLUS or MULT
2282 ops : An array of rtx:es. lreg, rreg, rval,
2283 The variables multop and other_op are indexes into this,
2284 or -1 if they are not applicable.
2285 lreg : The register that gets assigned in the side-effect.
2286 rreg : One register in the side-effect expression
2287 rval : The other register, or an int.
2288 multop : An integer to multiply rval with.
2289 other_op : One of the entities of the main effect,
2290 whose mode we must consider. */
2291
2292 int
cris_side_effect_mode_ok(enum rtx_code code,rtx * ops,int lreg,int rreg,int rval,int multop,int other_op)2293 cris_side_effect_mode_ok (enum rtx_code code, rtx *ops,
2294 int lreg, int rreg, int rval,
2295 int multop, int other_op)
2296 {
2297 /* Find what value to multiply with, for rx =ry + rz * n. */
2298 int mult = multop < 0 ? 1 : INTVAL (ops[multop]);
2299
2300 rtx reg_rtx = ops[rreg];
2301 rtx val_rtx = ops[rval];
2302
2303 /* The operands may be swapped. Canonicalize them in reg_rtx and
2304 val_rtx, where reg_rtx always is a reg (for this constraint to
2305 match). */
2306 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed))
2307 reg_rtx = val_rtx, val_rtx = ops[rreg];
2308
2309 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2310 we have no business. */
2311 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed))
2312 return 0;
2313
2314 /* Don't do this when -mno-split. */
2315 if (!TARGET_SIDE_EFFECT_PREFIXES)
2316 return 0;
2317
2318 /* The mult expression may be hidden in lreg. FIXME: Add more
2319 commentary about that. */
2320 if (GET_CODE (val_rtx) == MULT)
2321 {
2322 mult = INTVAL (XEXP (val_rtx, 1));
2323 val_rtx = XEXP (val_rtx, 0);
2324 code = MULT;
2325 }
2326
2327 /* First check the "other operand". */
2328 if (other_op >= 0)
2329 {
2330 if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD)
2331 return 0;
2332
2333 /* Check if the lvalue register is the same as the "other
2334 operand". If so, the result is undefined and we shouldn't do
2335 this. FIXME: Check again. */
2336 if ((cris_base_p (ops[lreg], reload_in_progress || reload_completed)
2337 && cris_base_p (ops[other_op],
2338 reload_in_progress || reload_completed)
2339 && REGNO (ops[lreg]) == REGNO (ops[other_op]))
2340 || rtx_equal_p (ops[other_op], ops[lreg]))
2341 return 0;
2342 }
2343
2344 /* Do not accept frame_pointer_rtx as any operand. */
2345 if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx
2346 || ops[rval] == frame_pointer_rtx
2347 || (other_op >= 0 && ops[other_op] == frame_pointer_rtx))
2348 return 0;
2349
2350 if (code == PLUS
2351 && ! cris_base_p (val_rtx, reload_in_progress || reload_completed))
2352 {
2353
2354 /* Do not allow rx = rx + n if a normal add or sub with same size
2355 would do. */
2356 if (rtx_equal_p (ops[lreg], reg_rtx)
2357 && CONST_INT_P (val_rtx)
2358 && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63))
2359 return 0;
2360
2361 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2362 if (CRIS_CONSTANT_P (val_rtx))
2363 return 1;
2364
2365 if (MEM_P (val_rtx)
2366 && cris_base_or_autoincr_p (XEXP (val_rtx, 0),
2367 reload_in_progress || reload_completed))
2368 return 1;
2369
2370 if (GET_CODE (val_rtx) == SIGN_EXTEND
2371 && MEM_P (XEXP (val_rtx, 0))
2372 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx, 0), 0),
2373 reload_in_progress || reload_completed))
2374 return 1;
2375
2376 /* If we got here, it's not a valid addressing mode. */
2377 return 0;
2378 }
2379 else if (code == MULT
2380 || (code == PLUS
2381 && cris_base_p (val_rtx,
2382 reload_in_progress || reload_completed)))
2383 {
2384 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2385 if (rtx_equal_p (ops[lreg], reg_rtx)
2386 || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx)))
2387 return 0;
2388
2389 /* Do not allow bad multiply-values. */
2390 if (mult != 1 && mult != 2 && mult != 4)
2391 return 0;
2392
2393 /* Only allow r + ... */
2394 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed))
2395 return 0;
2396
2397 /* If we got here, all seems ok.
2398 (All checks need to be done above). */
2399 return 1;
2400 }
2401
2402 /* If we get here, the caller got its initial tests wrong. */
2403 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2404 }
2405
2406 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2407 insn for other reasons. */
2408
2409 bool
cris_cc0_user_requires_cmp(rtx insn)2410 cris_cc0_user_requires_cmp (rtx insn)
2411 {
2412 rtx_insn *cc0_user = NULL;
2413 rtx body;
2414 rtx set;
2415
2416 gcc_assert (insn != NULL);
2417
2418 if (!TARGET_V32)
2419 return false;
2420
2421 cc0_user = next_cc0_user (insn);
2422 if (cc0_user == NULL)
2423 return false;
2424
2425 body = PATTERN (cc0_user);
2426 set = single_set (cc0_user);
2427
2428 /* Users can be sCC and bCC. */
2429 if (JUMP_P (cc0_user)
2430 && GET_CODE (body) == SET
2431 && SET_DEST (body) == pc_rtx
2432 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
2433 && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx)
2434 {
2435 return
2436 GET_CODE (XEXP (SET_SRC (body), 0)) == GT
2437 || GET_CODE (XEXP (SET_SRC (body), 0)) == LE;
2438 }
2439 else if (set)
2440 {
2441 return
2442 GET_CODE (SET_SRC (body)) == GT
2443 || GET_CODE (SET_SRC (body)) == LE;
2444 }
2445
2446 gcc_unreachable ();
2447 }
2448
2449 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2450 does not handle the case where the IN operand is strict_low_part; it
2451 does handle it for X. Test-case in Axis-20010516. This function takes
2452 care of that for THIS port. FIXME: strict_low_part is going away
2453 anyway. */
2454
2455 static int
cris_reg_overlap_mentioned_p(rtx x,rtx in)2456 cris_reg_overlap_mentioned_p (rtx x, rtx in)
2457 {
2458 /* The function reg_overlap_mentioned now handles when X is
2459 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2460 if (GET_CODE (in) == STRICT_LOW_PART)
2461 in = XEXP (in, 0);
2462
2463 return reg_overlap_mentioned_p (x, in);
2464 }
2465
2466 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2467 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2468 elsewhere. */
2469
2470 bool
cris_valid_pic_const(const_rtx x,bool any_operand)2471 cris_valid_pic_const (const_rtx x, bool any_operand)
2472 {
2473 gcc_assert (flag_pic);
2474
2475 switch (GET_CODE (x))
2476 {
2477 case CONST_INT:
2478 case CONST_DOUBLE:
2479 return true;
2480 default:
2481 ;
2482 }
2483
2484 if (GET_CODE (x) != CONST)
2485 return false;
2486
2487 x = XEXP (x, 0);
2488
2489 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2490 if (GET_CODE (x) == PLUS
2491 && GET_CODE (XEXP (x, 0)) == UNSPEC
2492 && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL
2493 || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL)
2494 && CONST_INT_P (XEXP (x, 1)))
2495 x = XEXP (x, 0);
2496
2497 if (GET_CODE (x) == UNSPEC)
2498 switch (XINT (x, 1))
2499 {
2500 /* A PCREL operand is only valid for call and movsi. */
2501 case CRIS_UNSPEC_PLT_PCREL:
2502 case CRIS_UNSPEC_PCREL:
2503 return !any_operand;
2504
2505 case CRIS_UNSPEC_PLT_GOTREL:
2506 case CRIS_UNSPEC_PLTGOTREAD:
2507 case CRIS_UNSPEC_GOTREAD:
2508 case CRIS_UNSPEC_GOTREL:
2509 return true;
2510 default:
2511 gcc_unreachable ();
2512 }
2513
2514 return cris_symbol_type_of (x) == cris_no_symbol;
2515 }
2516
2517 /* Helper function to find the right symbol-type to generate,
2518 given the original (non-PIC) representation. */
2519
2520 enum cris_symbol_type
cris_symbol_type_of(const_rtx x)2521 cris_symbol_type_of (const_rtx x)
2522 {
2523 switch (GET_CODE (x))
2524 {
2525 case SYMBOL_REF:
2526 return flag_pic
2527 ? (SYMBOL_REF_LOCAL_P (x)
2528 ? cris_rel_symbol : cris_got_symbol)
2529 : cris_offsettable_symbol;
2530
2531 case LABEL_REF:
2532 return flag_pic ? cris_rel_symbol : cris_offsettable_symbol;
2533
2534 case CONST:
2535 return cris_symbol_type_of (XEXP (x, 0));
2536
2537 case PLUS:
2538 case MINUS:
2539 {
2540 enum cris_symbol_type t1 = cris_symbol_type_of (XEXP (x, 0));
2541 enum cris_symbol_type t2 = cris_symbol_type_of (XEXP (x, 1));
2542
2543 gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol);
2544
2545 if (t1 == cris_got_symbol || t2 == cris_got_symbol)
2546 return cris_got_symbol_needing_fixup;
2547
2548 return t1 != cris_no_symbol ? t1 : t2;
2549 }
2550
2551 case CONST_INT:
2552 case CONST_DOUBLE:
2553 return cris_no_symbol;
2554
2555 case UNSPEC:
2556 return cris_unspec;
2557
2558 default:
2559 fatal_insn ("unrecognized supposed constant", x);
2560 }
2561
2562 gcc_unreachable ();
2563 }
2564
2565 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2566
2567 int
cris_legitimate_pic_operand(rtx x)2568 cris_legitimate_pic_operand (rtx x)
2569 {
2570 /* Symbols are not valid PIC operands as-is; just constants. */
2571 return cris_valid_pic_const (x, true);
2572 }
2573
2574 /* Queue an .ident string in the queue of top-level asm statements.
2575 If the front-end is done, we must be being called from toplev.c.
2576 In that case, do nothing. */
2577 void
cris_asm_output_ident(const char * string)2578 cris_asm_output_ident (const char *string)
2579 {
2580 if (symtab->state != PARSING)
2581 return;
2582
2583 default_asm_output_ident_directive (string);
2584 }
2585
2586 /* The ASM_OUTPUT_CASE_END worker. */
2587
2588 void
cris_asm_output_case_end(FILE * stream,int num,rtx table)2589 cris_asm_output_case_end (FILE *stream, int num, rtx table)
2590 {
2591 /* Step back, over the label for the table, to the actual casejump and
2592 assert that we find only what's expected. */
2593 rtx whole_jump_insn = prev_nonnote_nondebug_insn (table);
2594 gcc_assert (whole_jump_insn != NULL_RTX && LABEL_P (whole_jump_insn));
2595 whole_jump_insn = prev_nonnote_nondebug_insn (whole_jump_insn);
2596 gcc_assert (whole_jump_insn != NULL_RTX
2597 && (JUMP_P (whole_jump_insn)
2598 || (TARGET_V32 && INSN_P (whole_jump_insn)
2599 && GET_CODE (PATTERN (whole_jump_insn)) == SEQUENCE)));
2600 /* Get the pattern of the casejump, so we can extract the default label. */
2601 whole_jump_insn = PATTERN (whole_jump_insn);
2602
2603 if (TARGET_V32)
2604 {
2605 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2606 filled. We also output the offset word a little differently. */
2607 rtx parallel_jump
2608 = (GET_CODE (whole_jump_insn) == SEQUENCE
2609 ? PATTERN (XVECEXP (whole_jump_insn, 0, 0)) : whole_jump_insn);
2610
2611 asm_fprintf (stream,
2612 "\t.word %LL%d-.%s\n",
2613 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2614 (parallel_jump, 0, 0),
2615 1), 2), 0)),
2616 (TARGET_PDEBUG ? "; default" : ""));
2617 return;
2618 }
2619
2620 asm_fprintf (stream,
2621 "\t.word %LL%d-%LL%d%s\n",
2622 CODE_LABEL_NUMBER (XEXP
2623 (XEXP
2624 (XEXP (XVECEXP (whole_jump_insn, 0, 0), 1),
2625 2), 0)),
2626 num,
2627 (TARGET_PDEBUG ? "; default" : ""));
2628 }
2629
2630 /* The TARGET_OPTION_OVERRIDE worker.
2631 As is the norm, this also parses -mfoo=bar type parameters. */
2632
2633 static void
cris_option_override(void)2634 cris_option_override (void)
2635 {
2636 if (cris_max_stackframe_str)
2637 {
2638 cris_max_stackframe = atoi (cris_max_stackframe_str);
2639
2640 /* Do some sanity checking. */
2641 if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000)
2642 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2643 cris_max_stackframe, 0x20000000);
2644 }
2645
2646 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2647 if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO)
2648 cris_cpu_version = CRIS_CPU_SVINTO;
2649 else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4)
2650 cris_cpu_version = CRIS_CPU_ETRAX4;
2651
2652 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2653 if (cris_cpu_str)
2654 {
2655 cris_cpu_version
2656 = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1);
2657
2658 if (strcmp ("etrax4", cris_cpu_str) == 0)
2659 cris_cpu_version = 3;
2660
2661 if (strcmp ("svinto", cris_cpu_str) == 0
2662 || strcmp ("etrax100", cris_cpu_str) == 0)
2663 cris_cpu_version = 8;
2664
2665 if (strcmp ("ng", cris_cpu_str) == 0
2666 || strcmp ("etrax100lx", cris_cpu_str) == 0)
2667 cris_cpu_version = 10;
2668
2669 if (cris_cpu_version < 0 || cris_cpu_version > 32)
2670 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2671 cris_cpu_str);
2672
2673 /* Set the target flags. */
2674 if (cris_cpu_version >= CRIS_CPU_ETRAX4)
2675 target_flags |= MASK_ETRAX4_ADD;
2676
2677 /* If this is Svinto or higher, align for 32 bit accesses. */
2678 if (cris_cpu_version >= CRIS_CPU_SVINTO)
2679 target_flags
2680 |= (MASK_SVINTO | MASK_ALIGN_BY_32
2681 | MASK_STACK_ALIGN | MASK_CONST_ALIGN
2682 | MASK_DATA_ALIGN);
2683
2684 /* Note that we do not add new flags when it can be completely
2685 described with a macro that uses -mcpu=X. So
2686 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2687 }
2688
2689 if (cris_tune_str)
2690 {
2691 int cris_tune
2692 = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1);
2693
2694 if (strcmp ("etrax4", cris_tune_str) == 0)
2695 cris_tune = 3;
2696
2697 if (strcmp ("svinto", cris_tune_str) == 0
2698 || strcmp ("etrax100", cris_tune_str) == 0)
2699 cris_tune = 8;
2700
2701 if (strcmp ("ng", cris_tune_str) == 0
2702 || strcmp ("etrax100lx", cris_tune_str) == 0)
2703 cris_tune = 10;
2704
2705 if (cris_tune < 0 || cris_tune > 32)
2706 error ("unknown CRIS cpu version specification in -mtune= : %s",
2707 cris_tune_str);
2708
2709 if (cris_tune >= CRIS_CPU_SVINTO)
2710 /* We have currently nothing more to tune than alignment for
2711 memory accesses. */
2712 target_flags
2713 |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN
2714 | MASK_DATA_ALIGN | MASK_ALIGN_BY_32);
2715 }
2716
2717 if (cris_cpu_version >= CRIS_CPU_V32)
2718 target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG);
2719
2720 if (flag_pic)
2721 {
2722 /* Use error rather than warning, so invalid use is easily
2723 detectable. Still change to the values we expect, to avoid
2724 further errors. */
2725 if (! TARGET_LINUX)
2726 {
2727 error ("-fPIC and -fpic are not supported in this configuration");
2728 flag_pic = 0;
2729 }
2730
2731 /* Turn off function CSE. We need to have the addresses reach the
2732 call expanders to get PLT-marked, as they could otherwise be
2733 compared against zero directly or indirectly. After visiting the
2734 call expanders they will then be cse:ed, as the call expanders
2735 force_reg the addresses, effectively forcing flag_no_function_cse
2736 to 0. */
2737 flag_no_function_cse = 1;
2738 }
2739
2740 /* Set the per-function-data initializer. */
2741 init_machine_status = cris_init_machine_status;
2742 }
2743
2744 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2745
2746 static void
cris_asm_output_mi_thunk(FILE * stream,tree thunkdecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,tree funcdecl)2747 cris_asm_output_mi_thunk (FILE *stream,
2748 tree thunkdecl ATTRIBUTE_UNUSED,
2749 HOST_WIDE_INT delta,
2750 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2751 tree funcdecl)
2752 {
2753 /* Make sure unwind info is emitted for the thunk if needed. */
2754 final_start_function (emit_barrier (), stream, 1);
2755
2756 if (delta > 0)
2757 fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2758 ADDITIVE_SIZE_MODIFIER (delta), delta,
2759 reg_names[CRIS_FIRST_ARG_REG]);
2760 else if (delta < 0)
2761 fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2762 ADDITIVE_SIZE_MODIFIER (-delta), -delta,
2763 reg_names[CRIS_FIRST_ARG_REG]);
2764
2765 if (flag_pic)
2766 {
2767 const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0);
2768
2769 name = (* targetm.strip_name_encoding) (name);
2770
2771 if (TARGET_V32)
2772 {
2773 fprintf (stream, "\tba ");
2774 assemble_name (stream, name);
2775 fprintf (stream, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX);
2776 }
2777 else
2778 {
2779 fprintf (stream, "add.d ");
2780 assemble_name (stream, name);
2781 fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX);
2782 }
2783 }
2784 else
2785 {
2786 fprintf (stream, "jump ");
2787 assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0));
2788 fprintf (stream, "\n");
2789
2790 if (TARGET_V32)
2791 fprintf (stream, "\tnop\n");
2792 }
2793
2794 final_end_function ();
2795 }
2796
2797 /* Boilerplate emitted at start of file.
2798
2799 NO_APP *only at file start* means faster assembly. It also means
2800 comments are not allowed. In some cases comments will be output
2801 for debugging purposes. Make sure they are allowed then. */
2802 static void
cris_file_start(void)2803 cris_file_start (void)
2804 {
2805 /* These expressions can vary at run time, so we cannot put
2806 them into TARGET_INITIALIZER. */
2807 targetm.asm_file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name);
2808
2809 default_file_start ();
2810 }
2811
2812 /* Output that goes at the end of the file, similarly. */
2813
2814 static void
cris_file_end(void)2815 cris_file_end (void)
2816 {
2817 /* For CRIS, the default is to assume *no* executable stack, so output
2818 an executable-stack-note only when needed. */
2819 if (TARGET_LINUX && trampolines_created)
2820 file_end_indicate_exec_stack ();
2821 }
2822
2823 /* Rename the function calls for integer multiply and divide. */
2824 static void
cris_init_libfuncs(void)2825 cris_init_libfuncs (void)
2826 {
2827 set_optab_libfunc (smul_optab, SImode, "__Mul");
2828 set_optab_libfunc (sdiv_optab, SImode, "__Div");
2829 set_optab_libfunc (udiv_optab, SImode, "__Udiv");
2830 set_optab_libfunc (smod_optab, SImode, "__Mod");
2831 set_optab_libfunc (umod_optab, SImode, "__Umod");
2832
2833 /* Atomic data being unaligned is unfortunately a reality.
2834 Deal with it. */
2835 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS)
2836 {
2837 set_optab_libfunc (sync_compare_and_swap_optab, SImode,
2838 "__cris_atcmpxchgr32");
2839 set_optab_libfunc (sync_compare_and_swap_optab, HImode,
2840 "__cris_atcmpxchgr16");
2841 }
2842 }
2843
2844 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2845 mark functions. */
2846
2847 void
cris_init_expanders(void)2848 cris_init_expanders (void)
2849 {
2850 /* Nothing here at the moment. */
2851 }
2852
2853 /* Zero initialization is OK for all current fields. */
2854
2855 static struct machine_function *
cris_init_machine_status(void)2856 cris_init_machine_status (void)
2857 {
2858 return ggc_cleared_alloc<machine_function> ();
2859 }
2860
2861 /* Split a 2 word move (DI or presumably DF) into component parts.
2862 Originally a copy of gen_split_move_double in m32r.c. */
2863
2864 rtx
cris_split_movdx(rtx * operands)2865 cris_split_movdx (rtx *operands)
2866 {
2867 machine_mode mode = GET_MODE (operands[0]);
2868 rtx dest = operands[0];
2869 rtx src = operands[1];
2870 rtx val;
2871
2872 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2873 longer happen; after reload there are no SUBREGs any more, and we're
2874 only called after reload. */
2875 CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
2876
2877 start_sequence ();
2878 if (REG_P (dest))
2879 {
2880 int dregno = REGNO (dest);
2881
2882 /* Reg-to-reg copy. */
2883 if (REG_P (src))
2884 {
2885 int sregno = REGNO (src);
2886
2887 int reverse = (dregno == sregno + 1);
2888
2889 /* We normally copy the low-numbered register first. However, if
2890 the first register operand 0 is the same as the second register of
2891 operand 1, we must copy in the opposite order. */
2892 emit_insn (gen_rtx_SET (operand_subword (dest, reverse, TRUE, mode),
2893 operand_subword (src, reverse, TRUE, mode)));
2894
2895 emit_insn (gen_rtx_SET (operand_subword (dest, !reverse, TRUE, mode),
2896 operand_subword (src, !reverse, TRUE, mode)));
2897 }
2898 /* Constant-to-reg copy. */
2899 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
2900 {
2901 rtx words[2];
2902 split_double (src, &words[0], &words[1]);
2903 emit_insn (gen_rtx_SET (operand_subword (dest, 0, TRUE, mode),
2904 words[0]));
2905
2906 emit_insn (gen_rtx_SET (operand_subword (dest, 1, TRUE, mode),
2907 words[1]));
2908 }
2909 /* Mem-to-reg copy. */
2910 else if (MEM_P (src))
2911 {
2912 /* If the high-address word is used in the address, we must load it
2913 last. Otherwise, load it first. */
2914 rtx addr = XEXP (src, 0);
2915 int reverse = (refers_to_regno_p (dregno, addr) != 0);
2916
2917 /* The original code implies that we can't do
2918 move.x [rN+],rM move.x [rN],rM+1
2919 when rN is dead, because of REG_NOTES damage. That is
2920 consistent with what I've seen, so don't try it.
2921
2922 We have two different cases here; if the addr is POST_INC,
2923 just pass it through, otherwise add constants. */
2924
2925 if (GET_CODE (addr) == POST_INC)
2926 {
2927 rtx mem;
2928 rtx insn;
2929
2930 /* Whenever we emit insns with post-incremented
2931 addresses ourselves, we must add a post-inc note
2932 manually. */
2933 mem = change_address (src, SImode, addr);
2934 insn
2935 = gen_rtx_SET (operand_subword (dest, 0, TRUE, mode), mem);
2936 insn = emit_insn (insn);
2937 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2938 REG_NOTES (insn)
2939 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2940 REG_NOTES (insn));
2941
2942 mem = copy_rtx (mem);
2943 insn
2944 = gen_rtx_SET (operand_subword (dest, 1, TRUE, mode), mem);
2945 insn = emit_insn (insn);
2946 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2947 REG_NOTES (insn)
2948 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2949 REG_NOTES (insn));
2950 }
2951 else
2952 {
2953 /* Make sure we don't get any other addresses with
2954 embedded postincrements. They should be stopped in
2955 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2956 safety. */
2957 if (side_effects_p (addr))
2958 fatal_insn ("unexpected side-effects in address", addr);
2959
2960 emit_insn (gen_rtx_SET
2961 (operand_subword (dest, reverse, TRUE, mode),
2962 change_address
2963 (src, SImode,
2964 plus_constant (Pmode, addr,
2965 reverse * UNITS_PER_WORD))));
2966 emit_insn (gen_rtx_SET
2967 (operand_subword (dest, ! reverse, TRUE, mode),
2968 change_address
2969 (src, SImode,
2970 plus_constant (Pmode, addr,
2971 (! reverse) *
2972 UNITS_PER_WORD))));
2973 }
2974 }
2975 else
2976 internal_error ("unknown src");
2977 }
2978 /* Reg-to-mem copy or clear mem. */
2979 else if (MEM_P (dest)
2980 && (REG_P (src)
2981 || src == const0_rtx
2982 || src == CONST0_RTX (DFmode)))
2983 {
2984 rtx addr = XEXP (dest, 0);
2985
2986 if (GET_CODE (addr) == POST_INC)
2987 {
2988 rtx mem;
2989 rtx insn;
2990
2991 /* Whenever we emit insns with post-incremented addresses
2992 ourselves, we must add a post-inc note manually. */
2993 mem = change_address (dest, SImode, addr);
2994 insn
2995 = gen_rtx_SET (mem, operand_subword (src, 0, TRUE, mode));
2996 insn = emit_insn (insn);
2997 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2998 REG_NOTES (insn)
2999 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
3000 REG_NOTES (insn));
3001
3002 mem = copy_rtx (mem);
3003 insn = gen_rtx_SET (mem, operand_subword (src, 1, TRUE, mode));
3004 insn = emit_insn (insn);
3005 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
3006 REG_NOTES (insn)
3007 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
3008 REG_NOTES (insn));
3009 }
3010 else
3011 {
3012 /* Make sure we don't get any other addresses with embedded
3013 postincrements. They should be stopped in
3014 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
3015 if (side_effects_p (addr))
3016 fatal_insn ("unexpected side-effects in address", addr);
3017
3018 emit_insn (gen_rtx_SET
3019 (change_address (dest, SImode, addr),
3020 operand_subword (src, 0, TRUE, mode)));
3021
3022 emit_insn (gen_rtx_SET
3023 (change_address (dest, SImode,
3024 plus_constant (Pmode, addr,
3025 UNITS_PER_WORD)),
3026 operand_subword (src, 1, TRUE, mode)));
3027 }
3028 }
3029
3030 else
3031 internal_error ("unknown dest");
3032
3033 val = get_insns ();
3034 end_sequence ();
3035 return val;
3036 }
3037
3038 /* The expander for the prologue pattern name. */
3039
3040 void
cris_expand_prologue(void)3041 cris_expand_prologue (void)
3042 {
3043 int regno;
3044 int size = get_frame_size ();
3045 /* Shorten the used name for readability. */
3046 int cfoa_size = crtl->outgoing_args_size;
3047 int last_movem_reg = -1;
3048 int framesize = 0;
3049 rtx mem, insn;
3050 int return_address_on_stack = cris_return_address_on_stack ();
3051 int got_really_used = false;
3052 int n_movem_regs = 0;
3053 int pretend = crtl->args.pretend_args_size;
3054
3055 /* Don't do anything if no prologues or epilogues are wanted. */
3056 if (!TARGET_PROLOGUE_EPILOGUE)
3057 return;
3058
3059 CRIS_ASSERT (size >= 0);
3060
3061 if (crtl->uses_pic_offset_table)
3062 {
3063 /* A reference may have been optimized out (like the abort () in
3064 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3065 it's still used. */
3066 push_topmost_sequence ();
3067 got_really_used
3068 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL);
3069 pop_topmost_sequence ();
3070 }
3071
3072 /* Align the size to what's best for the CPU model. */
3073 if (TARGET_STACK_ALIGN)
3074 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
3075
3076 if (pretend)
3077 {
3078 /* See also cris_setup_incoming_varargs where
3079 cfun->machine->stdarg_regs is set. There are other setters of
3080 crtl->args.pretend_args_size than stdarg handling, like
3081 for an argument passed with parts in R13 and stack. We must
3082 not store R13 into the pretend-area for that case, as GCC does
3083 that itself. "Our" store would be marked as redundant and GCC
3084 will attempt to remove it, which will then be flagged as an
3085 internal error; trying to remove a frame-related insn. */
3086 int stdarg_regs = cfun->machine->stdarg_regs;
3087
3088 framesize += pretend;
3089
3090 for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1;
3091 stdarg_regs > 0;
3092 regno--, pretend -= 4, stdarg_regs--)
3093 {
3094 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3095 plus_constant (Pmode,
3096 stack_pointer_rtx,
3097 -4)));
3098 /* FIXME: When dwarf2 frame output and unless asynchronous
3099 exceptions, make dwarf2 bundle together all stack
3100 adjustments like it does for registers between stack
3101 adjustments. */
3102 RTX_FRAME_RELATED_P (insn) = 1;
3103
3104 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3105 set_mem_alias_set (mem, get_varargs_alias_set ());
3106 insn = emit_move_insn (mem, gen_raw_REG (SImode, regno));
3107
3108 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3109 the value isn't restored, so we don't want to tell dwarf2
3110 that it's been stored to stack, else EH handling info would
3111 get confused. */
3112 }
3113
3114 /* For other setters of crtl->args.pretend_args_size, we
3115 just adjust the stack by leaving the remaining size in
3116 "pretend", handled below. */
3117 }
3118
3119 /* Save SRP if not a leaf function. */
3120 if (return_address_on_stack)
3121 {
3122 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3123 plus_constant (Pmode, stack_pointer_rtx,
3124 -4 - pretend)));
3125 pretend = 0;
3126 RTX_FRAME_RELATED_P (insn) = 1;
3127
3128 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3129 set_mem_alias_set (mem, get_frame_alias_set ());
3130 insn = emit_move_insn (mem, gen_raw_REG (SImode, CRIS_SRP_REGNUM));
3131 RTX_FRAME_RELATED_P (insn) = 1;
3132 framesize += 4;
3133 }
3134
3135 /* Set up the frame pointer, if needed. */
3136 if (frame_pointer_needed)
3137 {
3138 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3139 plus_constant (Pmode, stack_pointer_rtx,
3140 -4 - pretend)));
3141 pretend = 0;
3142 RTX_FRAME_RELATED_P (insn) = 1;
3143
3144 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3145 set_mem_alias_set (mem, get_frame_alias_set ());
3146 insn = emit_move_insn (mem, frame_pointer_rtx);
3147 RTX_FRAME_RELATED_P (insn) = 1;
3148
3149 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3150 RTX_FRAME_RELATED_P (insn) = 1;
3151
3152 framesize += 4;
3153 }
3154
3155 /* Between frame-pointer and saved registers lie the area for local
3156 variables. If we get here with "pretended" size remaining, count
3157 it into the general stack size. */
3158 size += pretend;
3159
3160 /* Get a contiguous sequence of registers, starting with R0, that need
3161 to be saved. */
3162 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
3163 {
3164 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3165 {
3166 n_movem_regs++;
3167
3168 /* Check if movem may be used for registers so far. */
3169 if (regno == last_movem_reg + 1)
3170 /* Yes, update next expected register. */
3171 last_movem_reg = regno;
3172 else
3173 {
3174 /* We cannot use movem for all registers. We have to flush
3175 any movem:ed registers we got so far. */
3176 if (last_movem_reg != -1)
3177 {
3178 int n_saved
3179 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
3180
3181 /* It is a win to use a side-effect assignment for
3182 64 <= size <= 128. But side-effect on movem was
3183 not usable for CRIS v0..3. Also only do it if
3184 side-effects insns are allowed. */
3185 if ((last_movem_reg + 1) * 4 + size >= 64
3186 && (last_movem_reg + 1) * 4 + size <= 128
3187 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
3188 && TARGET_SIDE_EFFECT_PREFIXES)
3189 {
3190 mem
3191 = gen_rtx_MEM (SImode,
3192 plus_constant (Pmode, stack_pointer_rtx,
3193 -(n_saved * 4 + size)));
3194 set_mem_alias_set (mem, get_frame_alias_set ());
3195 insn
3196 = cris_emit_movem_store (mem, GEN_INT (n_saved),
3197 -(n_saved * 4 + size),
3198 true);
3199 }
3200 else
3201 {
3202 insn
3203 = gen_rtx_SET (stack_pointer_rtx,
3204 plus_constant (Pmode, stack_pointer_rtx,
3205 -(n_saved * 4 + size)));
3206 insn = emit_insn (insn);
3207 RTX_FRAME_RELATED_P (insn) = 1;
3208
3209 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3210 set_mem_alias_set (mem, get_frame_alias_set ());
3211 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
3212 0, true);
3213 }
3214
3215 framesize += n_saved * 4 + size;
3216 last_movem_reg = -1;
3217 size = 0;
3218 }
3219
3220 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3221 plus_constant (Pmode,
3222 stack_pointer_rtx,
3223 -4 - size)));
3224 RTX_FRAME_RELATED_P (insn) = 1;
3225
3226 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3227 set_mem_alias_set (mem, get_frame_alias_set ());
3228 insn = emit_move_insn (mem, gen_raw_REG (SImode, regno));
3229 RTX_FRAME_RELATED_P (insn) = 1;
3230
3231 framesize += 4 + size;
3232 size = 0;
3233 }
3234 }
3235 }
3236
3237 /* Check after, if we could movem all registers. This is the normal case. */
3238 if (last_movem_reg != -1)
3239 {
3240 int n_saved
3241 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
3242
3243 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3244 do it if side-effects insns are allowed. */
3245 if ((last_movem_reg + 1) * 4 + size >= 64
3246 && (last_movem_reg + 1) * 4 + size <= 128
3247 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
3248 && TARGET_SIDE_EFFECT_PREFIXES)
3249 {
3250 mem
3251 = gen_rtx_MEM (SImode,
3252 plus_constant (Pmode, stack_pointer_rtx,
3253 -(n_saved * 4 + size)));
3254 set_mem_alias_set (mem, get_frame_alias_set ());
3255 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
3256 -(n_saved * 4 + size), true);
3257 }
3258 else
3259 {
3260 insn
3261 = gen_rtx_SET (stack_pointer_rtx,
3262 plus_constant (Pmode, stack_pointer_rtx,
3263 -(n_saved * 4 + size)));
3264 insn = emit_insn (insn);
3265 RTX_FRAME_RELATED_P (insn) = 1;
3266
3267 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3268 set_mem_alias_set (mem, get_frame_alias_set ());
3269 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true);
3270 }
3271
3272 framesize += n_saved * 4 + size;
3273 /* We have to put outgoing argument space after regs. */
3274 if (cfoa_size)
3275 {
3276 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3277 plus_constant (Pmode,
3278 stack_pointer_rtx,
3279 -cfoa_size)));
3280 RTX_FRAME_RELATED_P (insn) = 1;
3281 framesize += cfoa_size;
3282 }
3283 }
3284 else if ((size + cfoa_size) > 0)
3285 {
3286 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3287 plus_constant (Pmode,
3288 stack_pointer_rtx,
3289 -(cfoa_size + size))));
3290 RTX_FRAME_RELATED_P (insn) = 1;
3291 framesize += size + cfoa_size;
3292 }
3293
3294 /* Set up the PIC register, if it is used. */
3295 if (got_really_used)
3296 {
3297 rtx got
3298 = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT);
3299 emit_move_insn (pic_offset_table_rtx, got);
3300
3301 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3302 follow exceptional paths and tries to delete the GOT load as
3303 unused, if it isn't used on the non-exceptional paths. Other
3304 ports have similar or other cover-ups, or plain bugs marking
3305 the GOT register load as maybe-dead. To see this, remove the
3306 line below and try libsupc++/vec.cc or a trivial
3307 "static void y (); void x () {try {y ();} catch (...) {}}". */
3308 emit_use (pic_offset_table_rtx);
3309 }
3310
3311 if (cris_max_stackframe && framesize > cris_max_stackframe)
3312 warning (0, "stackframe too big: %d bytes", framesize);
3313 }
3314
3315 /* The expander for the epilogue pattern. */
3316
3317 void
cris_expand_epilogue(void)3318 cris_expand_epilogue (void)
3319 {
3320 int regno;
3321 int size = get_frame_size ();
3322 int last_movem_reg = -1;
3323 int argspace_offset = crtl->outgoing_args_size;
3324 int pretend = crtl->args.pretend_args_size;
3325 rtx mem;
3326 bool return_address_on_stack = cris_return_address_on_stack ();
3327 /* A reference may have been optimized out
3328 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3329 so check that it's still used. */
3330 int got_really_used = false;
3331 int n_movem_regs = 0;
3332
3333 if (!TARGET_PROLOGUE_EPILOGUE)
3334 return;
3335
3336 if (crtl->uses_pic_offset_table)
3337 {
3338 /* A reference may have been optimized out (like the abort () in
3339 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3340 it's still used. */
3341 push_topmost_sequence ();
3342 got_really_used
3343 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL);
3344 pop_topmost_sequence ();
3345 }
3346
3347 /* Align byte count of stack frame. */
3348 if (TARGET_STACK_ALIGN)
3349 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
3350
3351 /* Check how many saved regs we can movem. They start at r0 and must
3352 be contiguous. */
3353 for (regno = 0;
3354 regno < FIRST_PSEUDO_REGISTER;
3355 regno++)
3356 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3357 {
3358 n_movem_regs++;
3359
3360 if (regno == last_movem_reg + 1)
3361 last_movem_reg = regno;
3362 else
3363 break;
3364 }
3365
3366 /* If there was only one register that really needed to be saved
3367 through movem, don't use movem. */
3368 if (n_movem_regs == 1)
3369 last_movem_reg = -1;
3370
3371 /* Now emit "normal" move insns for all regs higher than the movem
3372 regs. */
3373 for (regno = FIRST_PSEUDO_REGISTER - 1;
3374 regno > last_movem_reg;
3375 regno--)
3376 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3377 {
3378 rtx insn;
3379
3380 if (argspace_offset)
3381 {
3382 /* There is an area for outgoing parameters located before
3383 the saved registers. We have to adjust for that. */
3384 emit_insn (gen_rtx_SET (stack_pointer_rtx,
3385 plus_constant (Pmode, stack_pointer_rtx,
3386 argspace_offset)));
3387 /* Make sure we only do this once. */
3388 argspace_offset = 0;
3389 }
3390
3391 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3392 stack_pointer_rtx));
3393 set_mem_alias_set (mem, get_frame_alias_set ());
3394 insn = emit_move_insn (gen_raw_REG (SImode, regno), mem);
3395
3396 /* Whenever we emit insns with post-incremented addresses
3397 ourselves, we must add a post-inc note manually. */
3398 REG_NOTES (insn)
3399 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3400 }
3401
3402 /* If we have any movem-restore, do it now. */
3403 if (last_movem_reg != -1)
3404 {
3405 rtx insn;
3406
3407 if (argspace_offset)
3408 {
3409 emit_insn (gen_rtx_SET (stack_pointer_rtx,
3410 plus_constant (Pmode, stack_pointer_rtx,
3411 argspace_offset)));
3412 argspace_offset = 0;
3413 }
3414
3415 mem = gen_rtx_MEM (SImode,
3416 gen_rtx_POST_INC (SImode, stack_pointer_rtx));
3417 set_mem_alias_set (mem, get_frame_alias_set ());
3418 insn
3419 = emit_insn (cris_gen_movem_load (mem,
3420 GEN_INT (last_movem_reg + 1), 0));
3421 /* Whenever we emit insns with post-incremented addresses
3422 ourselves, we must add a post-inc note manually. */
3423 if (side_effects_p (PATTERN (insn)))
3424 REG_NOTES (insn)
3425 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3426 }
3427
3428 /* If we don't clobber all of the allocated stack area (we've already
3429 deallocated saved registers), GCC might want to schedule loads from
3430 the stack to *after* the stack-pointer restore, which introduces an
3431 interrupt race condition. This happened for the initial-value
3432 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3433 other failure for that test). It also happened for the stack slot
3434 for the return value in (one version of)
3435 linux/fs/dcache.c:__d_lookup, at least with "-O2
3436 -fno-omit-frame-pointer". */
3437
3438 /* Restore frame pointer if necessary. */
3439 if (frame_pointer_needed)
3440 {
3441 rtx insn;
3442
3443 emit_insn (gen_cris_frame_deallocated_barrier ());
3444
3445 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
3446 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3447 stack_pointer_rtx));
3448 set_mem_alias_set (mem, get_frame_alias_set ());
3449 insn = emit_move_insn (frame_pointer_rtx, mem);
3450
3451 /* Whenever we emit insns with post-incremented addresses
3452 ourselves, we must add a post-inc note manually. */
3453 REG_NOTES (insn)
3454 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3455 }
3456 else if ((size + argspace_offset) != 0)
3457 {
3458 emit_insn (gen_cris_frame_deallocated_barrier ());
3459
3460 /* If there was no frame-pointer to restore sp from, we must
3461 explicitly deallocate local variables. */
3462
3463 /* Handle space for outgoing parameters that hasn't been handled
3464 yet. */
3465 size += argspace_offset;
3466
3467 emit_insn (gen_rtx_SET (stack_pointer_rtx,
3468 plus_constant (Pmode, stack_pointer_rtx, size)));
3469 }
3470
3471 /* If this function has no pushed register parameters
3472 (stdargs/varargs), and if it is not a leaf function, then we have
3473 the return address on the stack. */
3474 if (return_address_on_stack && pretend == 0)
3475 {
3476 if (TARGET_V32 || crtl->calls_eh_return)
3477 {
3478 rtx mem;
3479 rtx insn;
3480 rtx srpreg = gen_raw_REG (SImode, CRIS_SRP_REGNUM);
3481 mem = gen_rtx_MEM (SImode,
3482 gen_rtx_POST_INC (SImode,
3483 stack_pointer_rtx));
3484 set_mem_alias_set (mem, get_frame_alias_set ());
3485 insn = emit_move_insn (srpreg, mem);
3486
3487 /* Whenever we emit insns with post-incremented addresses
3488 ourselves, we must add a post-inc note manually. */
3489 REG_NOTES (insn)
3490 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3491
3492 if (crtl->calls_eh_return)
3493 emit_insn (gen_addsi3 (stack_pointer_rtx,
3494 stack_pointer_rtx,
3495 gen_raw_REG (SImode, CRIS_STACKADJ_REG)));
3496 cris_expand_return (false);
3497 }
3498 else
3499 cris_expand_return (true);
3500
3501 return;
3502 }
3503
3504 /* If we pushed some register parameters, then adjust the stack for
3505 them. */
3506 if (pretend != 0)
3507 {
3508 /* If SRP is stored on the way, we need to restore it first. */
3509 if (return_address_on_stack)
3510 {
3511 rtx mem;
3512 rtx srpreg = gen_raw_REG (SImode, CRIS_SRP_REGNUM);
3513 rtx insn;
3514
3515 mem = gen_rtx_MEM (SImode,
3516 gen_rtx_POST_INC (SImode,
3517 stack_pointer_rtx));
3518 set_mem_alias_set (mem, get_frame_alias_set ());
3519 insn = emit_move_insn (srpreg, mem);
3520
3521 /* Whenever we emit insns with post-incremented addresses
3522 ourselves, we must add a post-inc note manually. */
3523 REG_NOTES (insn)
3524 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3525 }
3526
3527 emit_insn (gen_rtx_SET (stack_pointer_rtx,
3528 plus_constant (Pmode, stack_pointer_rtx,
3529 pretend)));
3530 }
3531
3532 /* Perform the "physical" unwinding that the EH machinery calculated. */
3533 if (crtl->calls_eh_return)
3534 emit_insn (gen_addsi3 (stack_pointer_rtx,
3535 stack_pointer_rtx,
3536 gen_raw_REG (SImode, CRIS_STACKADJ_REG)));
3537 cris_expand_return (false);
3538 }
3539
3540 /* Worker function for generating movem from mem for load_multiple. */
3541
3542 rtx
cris_gen_movem_load(rtx src,rtx nregs_rtx,int nprefix)3543 cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix)
3544 {
3545 int nregs = INTVAL (nregs_rtx);
3546 rtvec vec;
3547 int eltno = 1;
3548 int i;
3549 rtx srcreg = XEXP (src, 0);
3550 unsigned int regno = nregs - 1;
3551 int regno_inc = -1;
3552
3553 if (TARGET_V32)
3554 {
3555 regno = 0;
3556 regno_inc = 1;
3557 }
3558
3559 if (GET_CODE (srcreg) == POST_INC)
3560 srcreg = XEXP (srcreg, 0);
3561
3562 CRIS_ASSERT (REG_P (srcreg));
3563
3564 /* Don't use movem for just one insn. The insns are equivalent except
3565 for the pipeline hazard (on v32); movem does not forward the loaded
3566 registers so there's a three cycles penalty for their use. */
3567 if (nregs == 1)
3568 return gen_movsi (gen_rtx_REG (SImode, 0), src);
3569
3570 vec = rtvec_alloc (nprefix + nregs
3571 + (GET_CODE (XEXP (src, 0)) == POST_INC));
3572
3573 if (GET_CODE (XEXP (src, 0)) == POST_INC)
3574 {
3575 RTVEC_ELT (vec, nprefix + 1)
3576 = gen_rtx_SET (srcreg, plus_constant (Pmode, srcreg, nregs * 4));
3577 eltno++;
3578 }
3579
3580 src = replace_equiv_address (src, srcreg);
3581 RTVEC_ELT (vec, nprefix)
3582 = gen_rtx_SET (gen_rtx_REG (SImode, regno), src);
3583 regno += regno_inc;
3584
3585 for (i = 1; i < nregs; i++, eltno++)
3586 {
3587 RTVEC_ELT (vec, nprefix + eltno)
3588 = gen_rtx_SET (gen_rtx_REG (SImode, regno),
3589 adjust_address_nv (src, SImode, i * 4));
3590 regno += regno_inc;
3591 }
3592
3593 return gen_rtx_PARALLEL (VOIDmode, vec);
3594 }
3595
3596 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3597 are added that the dwarf2 machinery understands. */
3598
3599 rtx
cris_emit_movem_store(rtx dest,rtx nregs_rtx,int increment,bool frame_related)3600 cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment,
3601 bool frame_related)
3602 {
3603 int nregs = INTVAL (nregs_rtx);
3604 rtvec vec;
3605 int eltno = 1;
3606 int i;
3607 rtx insn;
3608 rtx destreg = XEXP (dest, 0);
3609 unsigned int regno = nregs - 1;
3610 int regno_inc = -1;
3611
3612 if (TARGET_V32)
3613 {
3614 regno = 0;
3615 regno_inc = 1;
3616 }
3617
3618 if (GET_CODE (destreg) == POST_INC)
3619 increment += nregs * 4;
3620
3621 if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS)
3622 destreg = XEXP (destreg, 0);
3623
3624 CRIS_ASSERT (REG_P (destreg));
3625
3626 /* Don't use movem for just one insn. The insns are equivalent except
3627 for the pipeline hazard (on v32); movem does not forward the loaded
3628 registers so there's a three cycles penalty for use. */
3629 if (nregs == 1)
3630 {
3631 rtx mov = gen_rtx_SET (dest, gen_rtx_REG (SImode, 0));
3632
3633 if (increment == 0)
3634 {
3635 insn = emit_insn (mov);
3636 if (frame_related)
3637 RTX_FRAME_RELATED_P (insn) = 1;
3638 return insn;
3639 }
3640
3641 /* If there was a request for a side-effect, create the ordinary
3642 parallel. */
3643 vec = rtvec_alloc (2);
3644
3645 RTVEC_ELT (vec, 0) = mov;
3646 RTVEC_ELT (vec, 1) = gen_rtx_SET (destreg, plus_constant (Pmode, destreg,
3647 increment));
3648 if (frame_related)
3649 {
3650 RTX_FRAME_RELATED_P (mov) = 1;
3651 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3652 }
3653 }
3654 else
3655 {
3656 vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0));
3657 RTVEC_ELT (vec, 0)
3658 = gen_rtx_SET (replace_equiv_address (dest,
3659 plus_constant (Pmode, destreg,
3660 increment)),
3661 gen_rtx_REG (SImode, regno));
3662 regno += regno_inc;
3663
3664 /* The dwarf2 info wants this mark on each component in a parallel
3665 that's part of the prologue (though it's optional on the first
3666 component). */
3667 if (frame_related)
3668 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1;
3669
3670 if (increment != 0)
3671 {
3672 RTVEC_ELT (vec, 1)
3673 = gen_rtx_SET (destreg, plus_constant (Pmode, destreg,
3674 increment != 0
3675 ? increment : nregs * 4));
3676 eltno++;
3677
3678 if (frame_related)
3679 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3680
3681 /* Don't call adjust_address_nv on a post-incremented address if
3682 we can help it. */
3683 if (GET_CODE (XEXP (dest, 0)) == POST_INC)
3684 dest = replace_equiv_address (dest, destreg);
3685 }
3686
3687 for (i = 1; i < nregs; i++, eltno++)
3688 {
3689 RTVEC_ELT (vec, eltno)
3690 = gen_rtx_SET (adjust_address_nv (dest, SImode, i * 4),
3691 gen_rtx_REG (SImode, regno));
3692 if (frame_related)
3693 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1;
3694 regno += regno_inc;
3695 }
3696 }
3697
3698 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
3699
3700 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3701 we need to keep the stack adjustment separate, after the
3702 MEM-setters. Else the stack-adjustment in the second component of
3703 the parallel would be mishandled; the offsets for the SETs that
3704 follow it would be wrong. We prepare for this by adding a
3705 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3706 followed by the increment. Note that we have FRAME_RELATED_P on
3707 all the SETs, including the original stack adjustment SET in the
3708 parallel. */
3709 if (frame_related)
3710 {
3711 if (increment != 0)
3712 {
3713 rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1));
3714 XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0));
3715 for (i = 1; i < nregs; i++)
3716 XVECEXP (seq, 0, i)
3717 = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1));
3718 XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1));
3719 add_reg_note (insn, REG_FRAME_RELATED_EXPR, seq);
3720 }
3721
3722 RTX_FRAME_RELATED_P (insn) = 1;
3723 }
3724
3725 return insn;
3726 }
3727
3728 /* Worker function for expanding the address for PIC function calls. */
3729
3730 void
cris_expand_pic_call_address(rtx * opp,rtx * markerp)3731 cris_expand_pic_call_address (rtx *opp, rtx *markerp)
3732 {
3733 rtx op = *opp;
3734
3735 gcc_assert (flag_pic && MEM_P (op));
3736 op = XEXP (op, 0);
3737
3738 /* It might be that code can be generated that jumps to 0 (or to a
3739 specific address). Don't die on that. (There is a
3740 testcase.) */
3741 if (CONSTANT_P (op) && !CONST_INT_P (op))
3742 {
3743 enum cris_symbol_type t = cris_symbol_type_of (op);
3744
3745 CRIS_ASSERT (can_create_pseudo_p ());
3746
3747 /* For local symbols (non-PLT), just get the plain symbol
3748 reference into a register. For symbols that can be PLT, make
3749 them PLT. */
3750 if (t == cris_rel_symbol)
3751 {
3752 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3753 into a register caused performance regression for 3.2.1,
3754 observable in __floatdidf and elsewhere in libgcc. */
3755 if (TARGET_V32)
3756 {
3757 rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op);
3758 HOST_WIDE_INT offs = get_integer_term (op);
3759
3760 /* We can't get calls to sym+N, N integer, can we? */
3761 gcc_assert (offs == 0);
3762
3763 op = gen_rtx_CONST (Pmode,
3764 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
3765 CRIS_UNSPEC_PCREL));
3766 }
3767 else
3768 op = force_reg (Pmode, op);
3769
3770 /* A local call. */
3771 *markerp = const0_rtx;
3772 }
3773 else if (t == cris_got_symbol)
3774 {
3775 if (TARGET_AVOID_GOTPLT)
3776 {
3777 /* Change a "jsr sym" into (allocate register rM, rO)
3778 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM"
3779 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3780 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))"
3781 for v32. */
3782 rtx tem, rm, ro;
3783
3784 crtl->uses_pic_offset_table = 1;
3785 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3786 TARGET_V32
3787 ? CRIS_UNSPEC_PLT_PCREL
3788 : CRIS_UNSPEC_PLT_GOTREL);
3789 tem = gen_rtx_CONST (Pmode, tem);
3790 if (TARGET_V32)
3791 op = tem;
3792 else
3793 {
3794 rm = gen_reg_rtx (Pmode);
3795 emit_move_insn (rm, tem);
3796 ro = gen_reg_rtx (Pmode);
3797 if (expand_binop (Pmode, add_optab, rm,
3798 pic_offset_table_rtx,
3799 ro, 0, OPTAB_LIB_WIDEN) != ro)
3800 internal_error ("expand_binop failed in movsi got");
3801 op = ro;
3802 }
3803 }
3804 else
3805 {
3806 /* Change a "jsr sym" into (allocate register rM, rO)
3807 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3808 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3809 marked as not trapping and not aliasing. No "move.d
3810 [rO],rP" as that would invite to re-use of a value
3811 that should not be reused. FIXME: Need a peephole2
3812 for cases when this is cse:d from the call, to change
3813 back to just get the PLT entry address, so we don't
3814 resolve the same symbol over and over (the memory
3815 access of the PLTGOT isn't constant). */
3816 rtx tem, mem, rm, ro;
3817
3818 gcc_assert (can_create_pseudo_p ());
3819 crtl->uses_pic_offset_table = 1;
3820 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3821 CRIS_UNSPEC_PLTGOTREAD);
3822 rm = gen_reg_rtx (Pmode);
3823 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3824 ro = gen_reg_rtx (Pmode);
3825 if (expand_binop (Pmode, add_optab, rm,
3826 pic_offset_table_rtx,
3827 ro, 0, OPTAB_LIB_WIDEN) != ro)
3828 internal_error ("expand_binop failed in movsi got");
3829 mem = gen_rtx_MEM (Pmode, ro);
3830
3831 /* This MEM doesn't alias anything. Whether it aliases
3832 other same symbols is unimportant. */
3833 set_mem_alias_set (mem, new_alias_set ());
3834 MEM_NOTRAP_P (mem) = 1;
3835 op = mem;
3836 }
3837
3838 /* We need to prepare this call to go through the PLT; we
3839 need to make GOT available. */
3840 *markerp = pic_offset_table_rtx;
3841 }
3842 else
3843 /* Can't possibly get anything else for a function-call, right? */
3844 fatal_insn ("unidentifiable call op", op);
3845
3846 /* If the validizing variant is called, it will try to validize
3847 the address as a valid any-operand constant, but as it's only
3848 valid for calls and moves, it will fail and always be forced
3849 into a register. */
3850 *opp = replace_equiv_address_nv (*opp, op);
3851 }
3852 else
3853 /* Can't tell what locality a call to a non-constant address has;
3854 better make the GOT register alive at it.
3855 FIXME: Can we see whether the register has known constant
3856 contents? */
3857 *markerp = pic_offset_table_rtx;
3858 }
3859
3860 /* Make sure operands are in the right order for an addsi3 insn as
3861 generated by a define_split. Nothing but REG_P as the first
3862 operand is recognized by addsi3 after reload. OPERANDS contains
3863 the operands, with the first at OPERANDS[N] and the second at
3864 OPERANDS[N+1]. */
3865
3866 void
cris_order_for_addsi3(rtx * operands,int n)3867 cris_order_for_addsi3 (rtx *operands, int n)
3868 {
3869 if (!REG_P (operands[n]))
3870 {
3871 rtx tem = operands[n];
3872 operands[n] = operands[n + 1];
3873 operands[n + 1] = tem;
3874 }
3875 }
3876
3877 /* Use from within code, from e.g. PRINT_OPERAND and
3878 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3879 different things depending on whether code operand or constant is
3880 emitted. */
3881
3882 static void
cris_output_addr_const(FILE * file,rtx x)3883 cris_output_addr_const (FILE *file, rtx x)
3884 {
3885 in_code++;
3886 output_addr_const (file, x);
3887 in_code--;
3888 }
3889
3890 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3891
3892 void
cris_asm_output_symbol_ref(FILE * file,rtx x)3893 cris_asm_output_symbol_ref (FILE *file, rtx x)
3894 {
3895 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3896
3897 if (flag_pic && in_code > 0)
3898 {
3899 const char *origstr = XSTR (x, 0);
3900 const char *str;
3901 str = (* targetm.strip_name_encoding) (origstr);
3902 assemble_name (file, str);
3903
3904 /* Sanity check. */
3905 if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3906 output_operand_lossage ("PIC register isn't set up");
3907 }
3908 else
3909 assemble_name (file, XSTR (x, 0));
3910 }
3911
3912 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3913
3914 void
cris_asm_output_label_ref(FILE * file,char * buf)3915 cris_asm_output_label_ref (FILE *file, char *buf)
3916 {
3917 if (flag_pic && in_code > 0)
3918 {
3919 assemble_name (file, buf);
3920
3921 /* Sanity check. */
3922 if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3923 internal_error ("emitting PIC operand, but PIC register "
3924 "isn%'t set up");
3925 }
3926 else
3927 assemble_name (file, buf);
3928 }
3929
3930 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3931
3932 static bool
cris_output_addr_const_extra(FILE * file,rtx xconst)3933 cris_output_addr_const_extra (FILE *file, rtx xconst)
3934 {
3935 switch (GET_CODE (xconst))
3936 {
3937 rtx x;
3938
3939 case UNSPEC:
3940 x = XVECEXP (xconst, 0, 0);
3941 CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
3942 || GET_CODE (x) == LABEL_REF
3943 || GET_CODE (x) == CONST);
3944 output_addr_const (file, x);
3945 switch (XINT (xconst, 1))
3946 {
3947 case CRIS_UNSPEC_PCREL:
3948 /* We only get this with -fpic/PIC to tell it apart from an
3949 invalid symbol. We can't tell here, but it should only
3950 be the operand of a call or movsi. */
3951 gcc_assert (TARGET_V32 && flag_pic);
3952 break;
3953
3954 case CRIS_UNSPEC_PLT_PCREL:
3955 gcc_assert (TARGET_V32);
3956 fprintf (file, ":PLT");
3957 break;
3958
3959 case CRIS_UNSPEC_PLT_GOTREL:
3960 gcc_assert (!TARGET_V32);
3961 fprintf (file, ":PLTG");
3962 break;
3963
3964 case CRIS_UNSPEC_GOTREL:
3965 gcc_assert (!TARGET_V32);
3966 fprintf (file, ":GOTOFF");
3967 break;
3968
3969 case CRIS_UNSPEC_GOTREAD:
3970 if (flag_pic == 1)
3971 fprintf (file, ":GOT16");
3972 else
3973 fprintf (file, ":GOT");
3974 break;
3975
3976 case CRIS_UNSPEC_PLTGOTREAD:
3977 if (flag_pic == 1)
3978 fprintf (file, CRIS_GOTPLT_SUFFIX "16");
3979 else
3980 fprintf (file, CRIS_GOTPLT_SUFFIX);
3981 break;
3982
3983 default:
3984 gcc_unreachable ();
3985 }
3986 return true;
3987
3988 default:
3989 return false;
3990 }
3991 }
3992
3993 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3994
3995 static rtx
cris_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED,int incoming ATTRIBUTE_UNUSED)3996 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
3997 int incoming ATTRIBUTE_UNUSED)
3998 {
3999 return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM);
4000 }
4001
4002 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4003
4004 static void
cris_setup_incoming_varargs(cumulative_args_t ca_v,machine_mode mode ATTRIBUTE_UNUSED,tree type ATTRIBUTE_UNUSED,int * pretend_arg_size,int second_time)4005 cris_setup_incoming_varargs (cumulative_args_t ca_v,
4006 machine_mode mode ATTRIBUTE_UNUSED,
4007 tree type ATTRIBUTE_UNUSED,
4008 int *pretend_arg_size,
4009 int second_time)
4010 {
4011 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
4012
4013 if (ca->regs < CRIS_MAX_ARGS_IN_REGS)
4014 {
4015 int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs;
4016 cfun->machine->stdarg_regs = stdarg_regs;
4017 *pretend_arg_size = stdarg_regs * 4;
4018 }
4019
4020 if (TARGET_PDEBUG)
4021 fprintf (asm_out_file,
4022 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
4023 ca->regs, *pretend_arg_size, second_time);
4024 }
4025
4026 /* Return true if TYPE must be passed by invisible reference.
4027 For cris, we pass <= 8 bytes by value, others by reference. */
4028
4029 static bool
cris_pass_by_reference(cumulative_args_t ca ATTRIBUTE_UNUSED,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)4030 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
4031 machine_mode mode, const_tree type,
4032 bool named ATTRIBUTE_UNUSED)
4033 {
4034 return (targetm.calls.must_pass_in_stack (mode, type)
4035 || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8);
4036 }
4037
4038 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4039 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4040 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4041
4042 machine_mode
cris_promote_function_mode(const_tree type ATTRIBUTE_UNUSED,machine_mode mode,int * punsignedp ATTRIBUTE_UNUSED,const_tree fntype ATTRIBUTE_UNUSED,int for_return)4043 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
4044 machine_mode mode,
4045 int *punsignedp ATTRIBUTE_UNUSED,
4046 const_tree fntype ATTRIBUTE_UNUSED,
4047 int for_return)
4048 {
4049 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4050 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4051 Maybe pointless as of now, but let's keep the old behavior. */
4052 if (for_return == 1)
4053 return mode;
4054 return CRIS_PROMOTED_MODE (mode, *punsignedp, type);
4055 }
4056
4057 /* Atomic types require alignment to be at least their "natural" size. */
4058
4059 static unsigned int
cris_atomic_align_for_mode(machine_mode mode)4060 cris_atomic_align_for_mode (machine_mode mode)
4061 {
4062 return GET_MODE_BITSIZE (mode);
4063 }
4064
4065 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4066 time being. */
4067
4068 static rtx
cris_function_value(const_tree type,const_tree func ATTRIBUTE_UNUSED,bool outgoing ATTRIBUTE_UNUSED)4069 cris_function_value(const_tree type,
4070 const_tree func ATTRIBUTE_UNUSED,
4071 bool outgoing ATTRIBUTE_UNUSED)
4072 {
4073 return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG);
4074 }
4075
4076 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4077 time being. */
4078
4079 static rtx
cris_libcall_value(machine_mode mode,const_rtx fun ATTRIBUTE_UNUSED)4080 cris_libcall_value (machine_mode mode,
4081 const_rtx fun ATTRIBUTE_UNUSED)
4082 {
4083 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG);
4084 }
4085
4086 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4087 time being. */
4088
4089 static bool
cris_function_value_regno_p(const unsigned int regno)4090 cris_function_value_regno_p (const unsigned int regno)
4091 {
4092 return (regno == CRIS_FIRST_ARG_REG);
4093 }
4094
4095 static int
cris_arg_partial_bytes(cumulative_args_t ca,machine_mode mode,tree type,bool named ATTRIBUTE_UNUSED)4096 cris_arg_partial_bytes (cumulative_args_t ca, machine_mode mode,
4097 tree type, bool named ATTRIBUTE_UNUSED)
4098 {
4099 if (get_cumulative_args (ca)->regs == CRIS_MAX_ARGS_IN_REGS - 1
4100 && !targetm.calls.must_pass_in_stack (mode, type)
4101 && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4
4102 && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8)
4103 return UNITS_PER_WORD;
4104 else
4105 return 0;
4106 }
4107
4108 static rtx
cris_function_arg_1(cumulative_args_t ca_v,machine_mode mode ATTRIBUTE_UNUSED,const_tree type ATTRIBUTE_UNUSED,bool named,bool incoming)4109 cris_function_arg_1 (cumulative_args_t ca_v,
4110 machine_mode mode ATTRIBUTE_UNUSED,
4111 const_tree type ATTRIBUTE_UNUSED,
4112 bool named, bool incoming)
4113 {
4114 const CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
4115
4116 if ((!incoming || named) && ca->regs < CRIS_MAX_ARGS_IN_REGS)
4117 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG + ca->regs);
4118 else
4119 return NULL_RTX;
4120 }
4121
4122 /* Worker function for TARGET_FUNCTION_ARG.
4123 The void_type_node is sent as a "closing" call. */
4124
4125 static rtx
cris_function_arg(cumulative_args_t ca,machine_mode mode,const_tree type,bool named)4126 cris_function_arg (cumulative_args_t ca, machine_mode mode,
4127 const_tree type, bool named)
4128 {
4129 return cris_function_arg_1 (ca, mode, type, named, false);
4130 }
4131
4132 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4133
4134 The differences between this and the previous, is that this one checks
4135 that an argument is named, since incoming stdarg/varargs arguments are
4136 pushed onto the stack, and we don't have to check against the "closing"
4137 void_type_node TYPE parameter. */
4138
4139 static rtx
cris_function_incoming_arg(cumulative_args_t ca,machine_mode mode,const_tree type,bool named)4140 cris_function_incoming_arg (cumulative_args_t ca, machine_mode mode,
4141 const_tree type, bool named)
4142 {
4143 return cris_function_arg_1 (ca, mode, type, named, true);
4144 }
4145
4146 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4147
4148 static void
cris_function_arg_advance(cumulative_args_t ca_v,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)4149 cris_function_arg_advance (cumulative_args_t ca_v, machine_mode mode,
4150 const_tree type, bool named ATTRIBUTE_UNUSED)
4151 {
4152 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
4153
4154 ca->regs += (3 + CRIS_FUNCTION_ARG_SIZE (mode, type)) / 4;
4155 }
4156
4157 /* Worker function for TARGET_MD_ASM_ADJUST. */
4158
4159 static rtx_insn *
cris_md_asm_adjust(vec<rtx> & outputs,vec<rtx> & inputs,vec<const char * > & constraints,vec<rtx> & clobbers,HARD_REG_SET & clobbered_regs)4160 cris_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &inputs,
4161 vec<const char *> &constraints,
4162 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
4163 {
4164 /* For the time being, all asms clobber condition codes.
4165 Revisit when there's a reasonable use for inputs/outputs
4166 that mention condition codes. */
4167 clobbers.safe_push (gen_rtx_REG (CCmode, CRIS_CC0_REGNUM));
4168 SET_HARD_REG_BIT (clobbered_regs, CRIS_CC0_REGNUM);
4169
4170 /* Determine if the source using MOF. If it is, automatically
4171 clobbering MOF would cause it to have impossible constraints. */
4172
4173 /* Look for a use of the MOF constraint letter: h. */
4174 for (unsigned i = 0, n = constraints.length(); i < n; ++i)
4175 if (strchr (constraints[i], 'h') != NULL)
4176 return NULL;
4177
4178 /* Look for an output or an input that touches MOF. */
4179 rtx mof_reg = gen_rtx_REG (SImode, CRIS_MOF_REGNUM);
4180 for (unsigned i = 0, n = outputs.length(); i < n; ++i)
4181 if (reg_overlap_mentioned_p (mof_reg, outputs[i]))
4182 return NULL;
4183 for (unsigned i = 0, n = inputs.length(); i < n; ++i)
4184 if (reg_overlap_mentioned_p (mof_reg, inputs[i]))
4185 return NULL;
4186
4187 /* No direct reference to MOF or its constraint.
4188 Clobber it for backward compatibility. */
4189 clobbers.safe_push (mof_reg);
4190 SET_HARD_REG_BIT (clobbered_regs, CRIS_MOF_REGNUM);
4191 return NULL;
4192 }
4193
4194 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4195
4196 Really only needed if the stack frame has variable length (alloca
4197 or variable sized local arguments (GNU C extension). See PR39499 and
4198 PR38609 for the reason this isn't just 0. */
4199
4200 bool
cris_frame_pointer_required(void)4201 cris_frame_pointer_required (void)
4202 {
4203 return !crtl->sp_is_unchanging;
4204 }
4205
4206 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4207
4208 This looks too complicated, and it is. I assigned r7 to be the
4209 static chain register, but it is call-saved, so we have to save it,
4210 and come back to restore it after the call, so we have to save srp...
4211 Anyway, trampolines are rare enough that we can cope with this
4212 somewhat lack of elegance.
4213 (Do not be tempted to "straighten up" whitespace in the asms; the
4214 assembler #NO_APP state mandates strict spacing). */
4215 /* ??? See the i386 regparm=3 implementation that pushes the static
4216 chain value to the stack in the trampoline, and uses a call-saved
4217 register when called directly. */
4218
4219 static void
cris_asm_trampoline_template(FILE * f)4220 cris_asm_trampoline_template (FILE *f)
4221 {
4222 if (TARGET_V32)
4223 {
4224 /* This normally-unused nop insn acts as an instruction to
4225 the simulator to flush its instruction cache. None of
4226 the other instructions in the trampoline template suits
4227 as a trigger for V32. The pc-relative addressing mode
4228 works nicely as a trigger for V10.
4229 FIXME: Have specific V32 template (possibly avoiding the
4230 use of a special instruction). */
4231 fprintf (f, "\tclearf x\n");
4232 /* We have to use a register as an intermediate, choosing
4233 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4234 so we can use it for address indirection and jsr target. */
4235 fprintf (f, "\tmove $r1,$mof\n");
4236 /* +4 */
4237 fprintf (f, "\tmove.d 0,$r1\n");
4238 fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]);
4239 fprintf (f, "\taddq 6,$r1\n");
4240 fprintf (f, "\tmove $mof,[$r1]\n");
4241 fprintf (f, "\taddq 6,$r1\n");
4242 fprintf (f, "\tmove $srp,[$r1]\n");
4243 /* +20 */
4244 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4245 /* +26 */
4246 fprintf (f, "\tmove.d 0,$r1\n");
4247 fprintf (f, "\tjsr $r1\n");
4248 fprintf (f, "\tsetf\n");
4249 /* +36 */
4250 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4251 /* +42 */
4252 fprintf (f, "\tmove.d 0,$r1\n");
4253 /* +48 */
4254 fprintf (f, "\tmove.d 0,$r9\n");
4255 fprintf (f, "\tjump $r9\n");
4256 fprintf (f, "\tsetf\n");
4257 }
4258 else
4259 {
4260 fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]);
4261 fprintf (f, "\tmove $srp,[$pc+22]\n");
4262 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4263 fprintf (f, "\tjsr 0\n");
4264 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4265 fprintf (f, "\tjump 0\n");
4266 }
4267 }
4268
4269 /* Implement TARGET_TRAMPOLINE_INIT. */
4270
4271 static void
cris_trampoline_init(rtx m_tramp,tree fndecl,rtx chain_value)4272 cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
4273 {
4274 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
4275 rtx tramp = XEXP (m_tramp, 0);
4276 rtx mem;
4277
4278 emit_block_move (m_tramp, assemble_trampoline_template (),
4279 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
4280
4281 if (TARGET_V32)
4282 {
4283 mem = adjust_address (m_tramp, SImode, 6);
4284 emit_move_insn (mem, plus_constant (Pmode, tramp, 38));
4285 mem = adjust_address (m_tramp, SImode, 22);
4286 emit_move_insn (mem, chain_value);
4287 mem = adjust_address (m_tramp, SImode, 28);
4288 emit_move_insn (mem, fnaddr);
4289 }
4290 else
4291 {
4292 mem = adjust_address (m_tramp, SImode, 10);
4293 emit_move_insn (mem, chain_value);
4294 mem = adjust_address (m_tramp, SImode, 16);
4295 emit_move_insn (mem, fnaddr);
4296 }
4297
4298 /* Note that there is no need to do anything with the cache for
4299 sake of a trampoline. */
4300 }
4301
4302
4303 #if 0
4304 /* Various small functions to replace macros. Only called from a
4305 debugger. They might collide with gcc functions or system functions,
4306 so only emit them when '#if 1' above. */
4307
4308 enum rtx_code Get_code (rtx);
4309
4310 enum rtx_code
4311 Get_code (rtx x)
4312 {
4313 return GET_CODE (x);
4314 }
4315
4316 const char *Get_mode (rtx);
4317
4318 const char *
4319 Get_mode (rtx x)
4320 {
4321 return GET_MODE_NAME (GET_MODE (x));
4322 }
4323
4324 rtx Xexp (rtx, int);
4325
4326 rtx
4327 Xexp (rtx x, int n)
4328 {
4329 return XEXP (x, n);
4330 }
4331
4332 rtx Xvecexp (rtx, int, int);
4333
4334 rtx
4335 Xvecexp (rtx x, int n, int m)
4336 {
4337 return XVECEXP (x, n, m);
4338 }
4339
4340 int Get_rtx_len (rtx);
4341
4342 int
4343 Get_rtx_len (rtx x)
4344 {
4345 return GET_RTX_LENGTH (GET_CODE (x));
4346 }
4347
4348 /* Use upper-case to distinguish from local variables that are sometimes
4349 called next_insn and prev_insn. */
4350
4351 rtx Next_insn (rtx);
4352
4353 rtx
4354 Next_insn (rtx insn)
4355 {
4356 return NEXT_INSN (insn);
4357 }
4358
4359 rtx Prev_insn (rtx);
4360
4361 rtx
4362 Prev_insn (rtx insn)
4363 {
4364 return PREV_INSN (insn);
4365 }
4366 #endif
4367
4368 #include "gt-cris.h"
4369
4370 /*
4371 * Local variables:
4372 * eval: (c-set-style "gnu")
4373 * indent-tabs-mode: t
4374 * End:
4375 */
4376