1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2016 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
24 split.
25
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
33
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
37 allocations;
38 o some heuristics to choose insn alternative to improve the
39 inheritance;
40 o early clobbers etc.
41
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
45 changed.
46
47 There is special code for preventing all LRA and this pass cycling
48 in case of bugs.
49
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
54
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
57 traversal of EBBs.
58
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
62
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
65 ... => ...
66 reload_p2 <- p reload_p2 <- new_p
67
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
70 pseudo*.
71
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
75
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
82 insns.
83
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
86
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
89 ... =>
90 ... r <- s (new insn -- restore)
91 ... <- r ... <- r
92
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
95
96 Splitting is done:
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
101
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
106
107 #undef REG_OK_STRICT
108
109 #include "config.h"
110 #include "system.h"
111 #include "coretypes.h"
112 #include "backend.h"
113 #include "target.h"
114 #include "rtl.h"
115 #include "tree.h"
116 #include "predict.h"
117 #include "df.h"
118 #include "tm_p.h"
119 #include "expmed.h"
120 #include "optabs.h"
121 #include "regs.h"
122 #include "ira.h"
123 #include "recog.h"
124 #include "output.h"
125 #include "addresses.h"
126 #include "expr.h"
127 #include "cfgrtl.h"
128 #include "rtl-error.h"
129 #include "params.h"
130 #include "lra.h"
131 #include "lra-int.h"
132 #include "print-rtl.h"
133
134 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
135 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 reload insns. */
137 static int bb_reload_num;
138
139 /* The current insn being processed and corresponding its single set
140 (NULL otherwise), its data (basic block, the insn data, the insn
141 static data, and the mode of each operand). */
142 static rtx_insn *curr_insn;
143 static rtx curr_insn_set;
144 static basic_block curr_bb;
145 static lra_insn_recog_data_t curr_id;
146 static struct lra_static_insn_data *curr_static_id;
147 static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
148 /* Mode of the register substituted by its equivalence with VOIDmode
149 (e.g. constant) and whose subreg is given operand of the current
150 insn. VOIDmode in all other cases. */
151 static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS];
152
153
154
155 /* Start numbers for new registers and insns at the current constraints
156 pass start. */
157 static int new_regno_start;
158 static int new_insn_uid_start;
159
160 /* If LOC is nonnull, strip any outer subreg from it. */
161 static inline rtx *
strip_subreg(rtx * loc)162 strip_subreg (rtx *loc)
163 {
164 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
165 }
166
167 /* Return hard regno of REGNO or if it is was not assigned to a hard
168 register, use a hard register from its allocno class. */
169 static int
get_try_hard_regno(int regno)170 get_try_hard_regno (int regno)
171 {
172 int hard_regno;
173 enum reg_class rclass;
174
175 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
176 hard_regno = lra_get_regno_hard_regno (regno);
177 if (hard_regno >= 0)
178 return hard_regno;
179 rclass = lra_get_allocno_class (regno);
180 if (rclass == NO_REGS)
181 return -1;
182 return ira_class_hard_regs[rclass][0];
183 }
184
185 /* Return final hard regno (plus offset) which will be after
186 elimination. We do this for matching constraints because the final
187 hard regno could have a different class. */
188 static int
get_final_hard_regno(int hard_regno,int offset)189 get_final_hard_regno (int hard_regno, int offset)
190 {
191 if (hard_regno < 0)
192 return hard_regno;
193 hard_regno = lra_get_elimination_hard_regno (hard_regno);
194 return hard_regno + offset;
195 }
196
197 /* Return hard regno of X after removing subreg and making
198 elimination. If X is not a register or subreg of register, return
199 -1. For pseudo use its assignment. */
200 static int
get_hard_regno(rtx x)201 get_hard_regno (rtx x)
202 {
203 rtx reg;
204 int offset, hard_regno;
205
206 reg = x;
207 if (GET_CODE (x) == SUBREG)
208 reg = SUBREG_REG (x);
209 if (! REG_P (reg))
210 return -1;
211 if ((hard_regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
212 hard_regno = lra_get_regno_hard_regno (hard_regno);
213 if (hard_regno < 0)
214 return -1;
215 offset = 0;
216 if (GET_CODE (x) == SUBREG)
217 offset += subreg_regno_offset (hard_regno, GET_MODE (reg),
218 SUBREG_BYTE (x), GET_MODE (x));
219 return get_final_hard_regno (hard_regno, offset);
220 }
221
222 /* If REGNO is a hard register or has been allocated a hard register,
223 return the class of that register. If REGNO is a reload pseudo
224 created by the current constraints pass, return its allocno class.
225 Return NO_REGS otherwise. */
226 static enum reg_class
get_reg_class(int regno)227 get_reg_class (int regno)
228 {
229 int hard_regno;
230
231 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
232 hard_regno = lra_get_regno_hard_regno (regno);
233 if (hard_regno >= 0)
234 {
235 hard_regno = get_final_hard_regno (hard_regno, 0);
236 return REGNO_REG_CLASS (hard_regno);
237 }
238 if (regno >= new_regno_start)
239 return lra_get_allocno_class (regno);
240 return NO_REGS;
241 }
242
243 /* Return true if REG satisfies (or will satisfy) reg class constraint
244 CL. Use elimination first if REG is a hard register. If REG is a
245 reload pseudo created by this constraints pass, assume that it will
246 be allocated a hard register from its allocno class, but allow that
247 class to be narrowed to CL if it is currently a superset of CL.
248
249 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
250 REGNO (reg), or NO_REGS if no change in its class was needed. */
251 static bool
in_class_p(rtx reg,enum reg_class cl,enum reg_class * new_class)252 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
253 {
254 enum reg_class rclass, common_class;
255 machine_mode reg_mode;
256 int class_size, hard_regno, nregs, i, j;
257 int regno = REGNO (reg);
258
259 if (new_class != NULL)
260 *new_class = NO_REGS;
261 if (regno < FIRST_PSEUDO_REGISTER)
262 {
263 rtx final_reg = reg;
264 rtx *final_loc = &final_reg;
265
266 lra_eliminate_reg_if_possible (final_loc);
267 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
268 }
269 reg_mode = GET_MODE (reg);
270 rclass = get_reg_class (regno);
271 if (regno < new_regno_start
272 /* Do not allow the constraints for reload instructions to
273 influence the classes of new pseudos. These reloads are
274 typically moves that have many alternatives, and restricting
275 reload pseudos for one alternative may lead to situations
276 where other reload pseudos are no longer allocatable. */
277 || (INSN_UID (curr_insn) >= new_insn_uid_start
278 && curr_insn_set != NULL
279 && ((OBJECT_P (SET_SRC (curr_insn_set))
280 && ! CONSTANT_P (SET_SRC (curr_insn_set)))
281 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
282 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
283 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
284 /* When we don't know what class will be used finally for reload
285 pseudos, we use ALL_REGS. */
286 return ((regno >= new_regno_start && rclass == ALL_REGS)
287 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
288 && ! hard_reg_set_subset_p (reg_class_contents[cl],
289 lra_no_alloc_regs)));
290 else
291 {
292 common_class = ira_reg_class_subset[rclass][cl];
293 if (new_class != NULL)
294 *new_class = common_class;
295 if (hard_reg_set_subset_p (reg_class_contents[common_class],
296 lra_no_alloc_regs))
297 return false;
298 /* Check that there are enough allocatable regs. */
299 class_size = ira_class_hard_regs_num[common_class];
300 for (i = 0; i < class_size; i++)
301 {
302 hard_regno = ira_class_hard_regs[common_class][i];
303 nregs = hard_regno_nregs[hard_regno][reg_mode];
304 if (nregs == 1)
305 return true;
306 for (j = 0; j < nregs; j++)
307 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
308 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class],
309 hard_regno + j))
310 break;
311 if (j >= nregs)
312 return true;
313 }
314 return false;
315 }
316 }
317
318 /* Return true if REGNO satisfies a memory constraint. */
319 static bool
in_mem_p(int regno)320 in_mem_p (int regno)
321 {
322 return get_reg_class (regno) == NO_REGS;
323 }
324
325 /* Return 1 if ADDR is a valid memory address for mode MODE in address
326 space AS, and check that each pseudo has the proper kind of hard
327 reg. */
328 static int
valid_address_p(machine_mode mode ATTRIBUTE_UNUSED,rtx addr,addr_space_t as)329 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED,
330 rtx addr, addr_space_t as)
331 {
332 #ifdef GO_IF_LEGITIMATE_ADDRESS
333 lra_assert (ADDR_SPACE_GENERIC_P (as));
334 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
335 return 0;
336
337 win:
338 return 1;
339 #else
340 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
341 #endif
342 }
343
344 namespace {
345 /* Temporarily eliminates registers in an address (for the lifetime of
346 the object). */
347 class address_eliminator {
348 public:
349 address_eliminator (struct address_info *ad);
350 ~address_eliminator ();
351
352 private:
353 struct address_info *m_ad;
354 rtx *m_base_loc;
355 rtx m_base_reg;
356 rtx *m_index_loc;
357 rtx m_index_reg;
358 };
359 }
360
address_eliminator(struct address_info * ad)361 address_eliminator::address_eliminator (struct address_info *ad)
362 : m_ad (ad),
363 m_base_loc (strip_subreg (ad->base_term)),
364 m_base_reg (NULL_RTX),
365 m_index_loc (strip_subreg (ad->index_term)),
366 m_index_reg (NULL_RTX)
367 {
368 if (m_base_loc != NULL)
369 {
370 m_base_reg = *m_base_loc;
371 lra_eliminate_reg_if_possible (m_base_loc);
372 if (m_ad->base_term2 != NULL)
373 *m_ad->base_term2 = *m_ad->base_term;
374 }
375 if (m_index_loc != NULL)
376 {
377 m_index_reg = *m_index_loc;
378 lra_eliminate_reg_if_possible (m_index_loc);
379 }
380 }
381
~address_eliminator()382 address_eliminator::~address_eliminator ()
383 {
384 if (m_base_loc && *m_base_loc != m_base_reg)
385 {
386 *m_base_loc = m_base_reg;
387 if (m_ad->base_term2 != NULL)
388 *m_ad->base_term2 = *m_ad->base_term;
389 }
390 if (m_index_loc && *m_index_loc != m_index_reg)
391 *m_index_loc = m_index_reg;
392 }
393
394 /* Return true if the eliminated form of AD is a legitimate target address. */
395 static bool
valid_address_p(struct address_info * ad)396 valid_address_p (struct address_info *ad)
397 {
398 address_eliminator eliminator (ad);
399 return valid_address_p (ad->mode, *ad->outer, ad->as);
400 }
401
402 /* Return true if the eliminated form of memory reference OP satisfies
403 extra (special) memory constraint CONSTRAINT. */
404 static bool
satisfies_memory_constraint_p(rtx op,enum constraint_num constraint)405 satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
406 {
407 struct address_info ad;
408
409 decompose_mem_address (&ad, op);
410 address_eliminator eliminator (&ad);
411 return constraint_satisfied_p (op, constraint);
412 }
413
414 /* Return true if the eliminated form of address AD satisfies extra
415 address constraint CONSTRAINT. */
416 static bool
satisfies_address_constraint_p(struct address_info * ad,enum constraint_num constraint)417 satisfies_address_constraint_p (struct address_info *ad,
418 enum constraint_num constraint)
419 {
420 address_eliminator eliminator (ad);
421 return constraint_satisfied_p (*ad->outer, constraint);
422 }
423
424 /* Return true if the eliminated form of address OP satisfies extra
425 address constraint CONSTRAINT. */
426 static bool
satisfies_address_constraint_p(rtx op,enum constraint_num constraint)427 satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
428 {
429 struct address_info ad;
430
431 decompose_lea_address (&ad, &op);
432 return satisfies_address_constraint_p (&ad, constraint);
433 }
434
435 /* Initiate equivalences for LRA. As we keep original equivalences
436 before any elimination, we need to make copies otherwise any change
437 in insns might change the equivalences. */
438 void
lra_init_equiv(void)439 lra_init_equiv (void)
440 {
441 ira_expand_reg_equiv ();
442 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
443 {
444 rtx res;
445
446 if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
447 ira_reg_equiv[i].memory = copy_rtx (res);
448 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
449 ira_reg_equiv[i].invariant = copy_rtx (res);
450 }
451 }
452
453 static rtx loc_equivalence_callback (rtx, const_rtx, void *);
454
455 /* Update equivalence for REGNO. We need to this as the equivalence
456 might contain other pseudos which are changed by their
457 equivalences. */
458 static void
update_equiv(int regno)459 update_equiv (int regno)
460 {
461 rtx x;
462
463 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
464 ira_reg_equiv[regno].memory
465 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
466 NULL_RTX);
467 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
468 ira_reg_equiv[regno].invariant
469 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
470 NULL_RTX);
471 }
472
473 /* If we have decided to substitute X with another value, return that
474 value, otherwise return X. */
475 static rtx
get_equiv(rtx x)476 get_equiv (rtx x)
477 {
478 int regno;
479 rtx res;
480
481 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
482 || ! ira_reg_equiv[regno].defined_p
483 || ! ira_reg_equiv[regno].profitable_p
484 || lra_get_regno_hard_regno (regno) >= 0)
485 return x;
486 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
487 {
488 if (targetm.cannot_substitute_mem_equiv_p (res))
489 return x;
490 return res;
491 }
492 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
493 return res;
494 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
495 return res;
496 gcc_unreachable ();
497 }
498
499 /* If we have decided to substitute X with the equivalent value,
500 return that value after elimination for INSN, otherwise return
501 X. */
502 static rtx
get_equiv_with_elimination(rtx x,rtx_insn * insn)503 get_equiv_with_elimination (rtx x, rtx_insn *insn)
504 {
505 rtx res = get_equiv (x);
506
507 if (x == res || CONSTANT_P (res))
508 return res;
509 return lra_eliminate_regs_1 (insn, res, GET_MODE (res),
510 false, false, 0, true);
511 }
512
513 /* Set up curr_operand_mode. */
514 static void
init_curr_operand_mode(void)515 init_curr_operand_mode (void)
516 {
517 int nop = curr_static_id->n_operands;
518 for (int i = 0; i < nop; i++)
519 {
520 machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
521 if (mode == VOIDmode)
522 {
523 /* The .md mode for address operands is the mode of the
524 addressed value rather than the mode of the address itself. */
525 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
526 mode = Pmode;
527 else
528 mode = curr_static_id->operand[i].mode;
529 }
530 curr_operand_mode[i] = mode;
531 }
532 }
533
534
535
536 /* The page contains code to reuse input reloads. */
537
538 /* Structure describes input reload of the current insns. */
539 struct input_reload
540 {
541 /* Reloaded value. */
542 rtx input;
543 /* Reload pseudo used. */
544 rtx reg;
545 };
546
547 /* The number of elements in the following array. */
548 static int curr_insn_input_reloads_num;
549 /* Array containing info about input reloads. It is used to find the
550 same input reload and reuse the reload pseudo in this case. */
551 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
552
553 /* Initiate data concerning reuse of input reloads for the current
554 insn. */
555 static void
init_curr_insn_input_reloads(void)556 init_curr_insn_input_reloads (void)
557 {
558 curr_insn_input_reloads_num = 0;
559 }
560
561 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
562 created input reload pseudo (only if TYPE is not OP_OUT). Don't
563 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
564 wrapped up in SUBREG. The result pseudo is returned through
565 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
566 reused the already created input reload pseudo. Use TITLE to
567 describe new registers for debug purposes. */
568 static bool
get_reload_reg(enum op_type type,machine_mode mode,rtx original,enum reg_class rclass,bool in_subreg_p,const char * title,rtx * result_reg)569 get_reload_reg (enum op_type type, machine_mode mode, rtx original,
570 enum reg_class rclass, bool in_subreg_p,
571 const char *title, rtx *result_reg)
572 {
573 int i, regno;
574 enum reg_class new_class;
575
576 if (type == OP_OUT)
577 {
578 *result_reg
579 = lra_create_new_reg_with_unique_value (mode, original, rclass, title);
580 return true;
581 }
582 /* Prevent reuse value of expression with side effects,
583 e.g. volatile memory. */
584 if (! side_effects_p (original))
585 for (i = 0; i < curr_insn_input_reloads_num; i++)
586 if (rtx_equal_p (curr_insn_input_reloads[i].input, original)
587 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
588 {
589 rtx reg = curr_insn_input_reloads[i].reg;
590 regno = REGNO (reg);
591 /* If input is equal to original and both are VOIDmode,
592 GET_MODE (reg) might be still different from mode.
593 Ensure we don't return *result_reg with wrong mode. */
594 if (GET_MODE (reg) != mode)
595 {
596 if (in_subreg_p)
597 continue;
598 if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode))
599 continue;
600 reg = lowpart_subreg (mode, reg, GET_MODE (reg));
601 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
602 continue;
603 }
604 *result_reg = reg;
605 if (lra_dump_file != NULL)
606 {
607 fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
608 dump_value_slim (lra_dump_file, original, 1);
609 }
610 if (new_class != lra_get_allocno_class (regno))
611 lra_change_class (regno, new_class, ", change to", false);
612 if (lra_dump_file != NULL)
613 fprintf (lra_dump_file, "\n");
614 return false;
615 }
616 *result_reg = lra_create_new_reg (mode, original, rclass, title);
617 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
618 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
619 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
620 return true;
621 }
622
623
624
625 /* The page contains code to extract memory address parts. */
626
627 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
628 static inline bool
ok_for_index_p_nonstrict(rtx reg)629 ok_for_index_p_nonstrict (rtx reg)
630 {
631 unsigned regno = REGNO (reg);
632
633 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
634 }
635
636 /* A version of regno_ok_for_base_p for use here, when all pseudos
637 should count as OK. Arguments as for regno_ok_for_base_p. */
638 static inline bool
ok_for_base_p_nonstrict(rtx reg,machine_mode mode,addr_space_t as,enum rtx_code outer_code,enum rtx_code index_code)639 ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
640 enum rtx_code outer_code, enum rtx_code index_code)
641 {
642 unsigned regno = REGNO (reg);
643
644 if (regno >= FIRST_PSEUDO_REGISTER)
645 return true;
646 return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
647 }
648
649
650
651 /* The page contains major code to choose the current insn alternative
652 and generate reloads for it. */
653
654 /* Return the offset from REGNO of the least significant register
655 in (reg:MODE REGNO).
656
657 This function is used to tell whether two registers satisfy
658 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
659
660 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
661 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
662 int
lra_constraint_offset(int regno,machine_mode mode)663 lra_constraint_offset (int regno, machine_mode mode)
664 {
665 lra_assert (regno < FIRST_PSEUDO_REGISTER);
666 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (mode) > UNITS_PER_WORD
667 && SCALAR_INT_MODE_P (mode))
668 return hard_regno_nregs[regno][mode] - 1;
669 return 0;
670 }
671
672 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
673 if they are the same hard reg, and has special hacks for
674 auto-increment and auto-decrement. This is specifically intended for
675 process_alt_operands to use in determining whether two operands
676 match. X is the operand whose number is the lower of the two.
677
678 It is supposed that X is the output operand and Y is the input
679 operand. Y_HARD_REGNO is the final hard regno of register Y or
680 register in subreg Y as we know it now. Otherwise, it is a
681 negative value. */
682 static bool
operands_match_p(rtx x,rtx y,int y_hard_regno)683 operands_match_p (rtx x, rtx y, int y_hard_regno)
684 {
685 int i;
686 RTX_CODE code = GET_CODE (x);
687 const char *fmt;
688
689 if (x == y)
690 return true;
691 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
692 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
693 {
694 int j;
695
696 i = get_hard_regno (x);
697 if (i < 0)
698 goto slow;
699
700 if ((j = y_hard_regno) < 0)
701 goto slow;
702
703 i += lra_constraint_offset (i, GET_MODE (x));
704 j += lra_constraint_offset (j, GET_MODE (y));
705
706 return i == j;
707 }
708
709 /* If two operands must match, because they are really a single
710 operand of an assembler insn, then two post-increments are invalid
711 because the assembler insn would increment only once. On the
712 other hand, a post-increment matches ordinary indexing if the
713 post-increment is the output operand. */
714 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
715 return operands_match_p (XEXP (x, 0), y, y_hard_regno);
716
717 /* Two pre-increments are invalid because the assembler insn would
718 increment only once. On the other hand, a pre-increment matches
719 ordinary indexing if the pre-increment is the input operand. */
720 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
721 || GET_CODE (y) == PRE_MODIFY)
722 return operands_match_p (x, XEXP (y, 0), -1);
723
724 slow:
725
726 if (code == REG && REG_P (y))
727 return REGNO (x) == REGNO (y);
728
729 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
730 && x == SUBREG_REG (y))
731 return true;
732 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
733 && SUBREG_REG (x) == y)
734 return true;
735
736 /* Now we have disposed of all the cases in which different rtx
737 codes can match. */
738 if (code != GET_CODE (y))
739 return false;
740
741 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
742 if (GET_MODE (x) != GET_MODE (y))
743 return false;
744
745 switch (code)
746 {
747 CASE_CONST_UNIQUE:
748 return false;
749
750 case LABEL_REF:
751 return LABEL_REF_LABEL (x) == LABEL_REF_LABEL (y);
752 case SYMBOL_REF:
753 return XSTR (x, 0) == XSTR (y, 0);
754
755 default:
756 break;
757 }
758
759 /* Compare the elements. If any pair of corresponding elements fail
760 to match, return false for the whole things. */
761
762 fmt = GET_RTX_FORMAT (code);
763 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
764 {
765 int val, j;
766 switch (fmt[i])
767 {
768 case 'w':
769 if (XWINT (x, i) != XWINT (y, i))
770 return false;
771 break;
772
773 case 'i':
774 if (XINT (x, i) != XINT (y, i))
775 return false;
776 break;
777
778 case 'e':
779 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
780 if (val == 0)
781 return false;
782 break;
783
784 case '0':
785 break;
786
787 case 'E':
788 if (XVECLEN (x, i) != XVECLEN (y, i))
789 return false;
790 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
791 {
792 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
793 if (val == 0)
794 return false;
795 }
796 break;
797
798 /* It is believed that rtx's at this level will never
799 contain anything but integers and other rtx's, except for
800 within LABEL_REFs and SYMBOL_REFs. */
801 default:
802 gcc_unreachable ();
803 }
804 }
805 return true;
806 }
807
808 /* True if X is a constant that can be forced into the constant pool.
809 MODE is the mode of the operand, or VOIDmode if not known. */
810 #define CONST_POOL_OK_P(MODE, X) \
811 ((MODE) != VOIDmode \
812 && CONSTANT_P (X) \
813 && GET_CODE (X) != HIGH \
814 && !targetm.cannot_force_const_mem (MODE, X))
815
816 /* True if C is a non-empty register class that has too few registers
817 to be safely used as a reload target class. */
818 #define SMALL_REGISTER_CLASS_P(C) \
819 (ira_class_hard_regs_num [(C)] == 1 \
820 || (ira_class_hard_regs_num [(C)] >= 1 \
821 && targetm.class_likely_spilled_p (C)))
822
823 /* If REG is a reload pseudo, try to make its class satisfying CL. */
824 static void
narrow_reload_pseudo_class(rtx reg,enum reg_class cl)825 narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
826 {
827 enum reg_class rclass;
828
829 /* Do not make more accurate class from reloads generated. They are
830 mostly moves with a lot of constraints. Making more accurate
831 class may results in very narrow class and impossibility of find
832 registers for several reloads of one insn. */
833 if (INSN_UID (curr_insn) >= new_insn_uid_start)
834 return;
835 if (GET_CODE (reg) == SUBREG)
836 reg = SUBREG_REG (reg);
837 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
838 return;
839 if (in_class_p (reg, cl, &rclass) && rclass != cl)
840 lra_change_class (REGNO (reg), rclass, " Change to", true);
841 }
842
843 /* Searches X for any reference to a reg with the same value as REGNO,
844 returning the rtx of the reference found if any. Otherwise,
845 returns NULL_RTX. */
846 static rtx
regno_val_use_in(unsigned int regno,rtx x)847 regno_val_use_in (unsigned int regno, rtx x)
848 {
849 const char *fmt;
850 int i, j;
851 rtx tem;
852
853 if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val)
854 return x;
855
856 fmt = GET_RTX_FORMAT (GET_CODE (x));
857 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
858 {
859 if (fmt[i] == 'e')
860 {
861 if ((tem = regno_val_use_in (regno, XEXP (x, i))))
862 return tem;
863 }
864 else if (fmt[i] == 'E')
865 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
866 if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j))))
867 return tem;
868 }
869
870 return NULL_RTX;
871 }
872
873 /* Generate reloads for matching OUT and INS (array of input operand
874 numbers with end marker -1) with reg class GOAL_CLASS, considering
875 output operands OUTS (similar array to INS) needing to be in different
876 registers. Add input and output reloads correspondingly to the lists
877 *BEFORE and *AFTER. OUT might be negative. In this case we generate
878 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
879 that the output operand is early clobbered for chosen alternative. */
880 static void
match_reload(signed char out,signed char * ins,signed char * outs,enum reg_class goal_class,rtx_insn ** before,rtx_insn ** after,bool early_clobber_p)881 match_reload (signed char out, signed char *ins, signed char *outs,
882 enum reg_class goal_class, rtx_insn **before,
883 rtx_insn **after, bool early_clobber_p)
884 {
885 bool out_conflict;
886 int i, in;
887 rtx new_in_reg, new_out_reg, reg;
888 machine_mode inmode, outmode;
889 rtx in_rtx = *curr_id->operand_loc[ins[0]];
890 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
891
892 inmode = curr_operand_mode[ins[0]];
893 outmode = out < 0 ? inmode : curr_operand_mode[out];
894 push_to_sequence (*before);
895 if (inmode != outmode)
896 {
897 if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
898 {
899 reg = new_in_reg
900 = lra_create_new_reg_with_unique_value (inmode, in_rtx,
901 goal_class, "");
902 if (SCALAR_INT_MODE_P (inmode))
903 new_out_reg = gen_lowpart_SUBREG (outmode, reg);
904 else
905 new_out_reg = gen_rtx_SUBREG (outmode, reg, 0);
906 LRA_SUBREG_P (new_out_reg) = 1;
907 /* If the input reg is dying here, we can use the same hard
908 register for REG and IN_RTX. We do it only for original
909 pseudos as reload pseudos can die although original
910 pseudos still live where reload pseudos dies. */
911 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
912 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)))
913 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
914 }
915 else
916 {
917 reg = new_out_reg
918 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
919 goal_class, "");
920 if (SCALAR_INT_MODE_P (outmode))
921 new_in_reg = gen_lowpart_SUBREG (inmode, reg);
922 else
923 new_in_reg = gen_rtx_SUBREG (inmode, reg, 0);
924 /* NEW_IN_REG is non-paradoxical subreg. We don't want
925 NEW_OUT_REG living above. We add clobber clause for
926 this. This is just a temporary clobber. We can remove
927 it at the end of LRA work. */
928 rtx_insn *clobber = emit_clobber (new_out_reg);
929 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
930 LRA_SUBREG_P (new_in_reg) = 1;
931 if (GET_CODE (in_rtx) == SUBREG)
932 {
933 rtx subreg_reg = SUBREG_REG (in_rtx);
934
935 /* If SUBREG_REG is dying here and sub-registers IN_RTX
936 and NEW_IN_REG are similar, we can use the same hard
937 register for REG and SUBREG_REG. */
938 if (REG_P (subreg_reg)
939 && (int) REGNO (subreg_reg) < lra_new_regno_start
940 && GET_MODE (subreg_reg) == outmode
941 && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg)
942 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)))
943 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
944 }
945 }
946 }
947 else
948 {
949 /* Pseudos have values -- see comments for lra_reg_info.
950 Different pseudos with the same value do not conflict even if
951 they live in the same place. When we create a pseudo we
952 assign value of original pseudo (if any) from which we
953 created the new pseudo. If we create the pseudo from the
954 input pseudo, the new pseudo will have no conflict with the
955 input pseudo which is wrong when the input pseudo lives after
956 the insn and as the new pseudo value is changed by the insn
957 output. Therefore we create the new pseudo from the output
958 except the case when we have single matched dying input
959 pseudo.
960
961 We cannot reuse the current output register because we might
962 have a situation like "a <- a op b", where the constraints
963 force the second input operand ("b") to match the output
964 operand ("a"). "b" must then be copied into a new register
965 so that it doesn't clobber the current value of "a".
966
967 We can not use the same value if the output pseudo is
968 early clobbered or the input pseudo is mentioned in the
969 output, e.g. as an address part in memory, because
970 output reload will actually extend the pseudo liveness.
971 We don't care about eliminable hard regs here as we are
972 interesting only in pseudos. */
973
974 /* Matching input's register value is the same as one of the other
975 output operand. Output operands in a parallel insn must be in
976 different registers. */
977 out_conflict = false;
978 if (REG_P (in_rtx))
979 {
980 for (i = 0; outs[i] >= 0; i++)
981 {
982 rtx other_out_rtx = *curr_id->operand_loc[outs[i]];
983 if (REG_P (other_out_rtx)
984 && (regno_val_use_in (REGNO (in_rtx), other_out_rtx)
985 != NULL_RTX))
986 {
987 out_conflict = true;
988 break;
989 }
990 }
991 }
992
993 new_in_reg = new_out_reg
994 = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx)
995 && (int) REGNO (in_rtx) < lra_new_regno_start
996 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
997 && (out < 0
998 || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX)
999 && !out_conflict
1000 ? lra_create_new_reg (inmode, in_rtx, goal_class, "")
1001 : lra_create_new_reg_with_unique_value (outmode, out_rtx,
1002 goal_class, ""));
1003 }
1004 /* In operand can be got from transformations before processing insn
1005 constraints. One example of such transformations is subreg
1006 reloading (see function simplify_operand_subreg). The new
1007 pseudos created by the transformations might have inaccurate
1008 class (ALL_REGS) and we should make their classes more
1009 accurate. */
1010 narrow_reload_pseudo_class (in_rtx, goal_class);
1011 lra_emit_move (copy_rtx (new_in_reg), in_rtx);
1012 *before = get_insns ();
1013 end_sequence ();
1014 for (i = 0; (in = ins[i]) >= 0; i++)
1015 {
1016 lra_assert
1017 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
1018 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]));
1019 *curr_id->operand_loc[in] = new_in_reg;
1020 }
1021 lra_update_dups (curr_id, ins);
1022 if (out < 0)
1023 return;
1024 /* See a comment for the input operand above. */
1025 narrow_reload_pseudo_class (out_rtx, goal_class);
1026 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
1027 {
1028 start_sequence ();
1029 lra_emit_move (out_rtx, copy_rtx (new_out_reg));
1030 emit_insn (*after);
1031 *after = get_insns ();
1032 end_sequence ();
1033 }
1034 *curr_id->operand_loc[out] = new_out_reg;
1035 lra_update_dup (curr_id, out);
1036 }
1037
1038 /* Return register class which is union of all reg classes in insn
1039 constraint alternative string starting with P. */
1040 static enum reg_class
reg_class_from_constraints(const char * p)1041 reg_class_from_constraints (const char *p)
1042 {
1043 int c, len;
1044 enum reg_class op_class = NO_REGS;
1045
1046 do
1047 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1048 {
1049 case '#':
1050 case ',':
1051 return op_class;
1052
1053 case 'g':
1054 op_class = reg_class_subunion[op_class][GENERAL_REGS];
1055 break;
1056
1057 default:
1058 enum constraint_num cn = lookup_constraint (p);
1059 enum reg_class cl = reg_class_for_constraint (cn);
1060 if (cl == NO_REGS)
1061 {
1062 if (insn_extra_address_constraint (cn))
1063 op_class
1064 = (reg_class_subunion
1065 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1066 ADDRESS, SCRATCH)]);
1067 break;
1068 }
1069
1070 op_class = reg_class_subunion[op_class][cl];
1071 break;
1072 }
1073 while ((p += len), c);
1074 return op_class;
1075 }
1076
1077 /* If OP is a register, return the class of the register as per
1078 get_reg_class, otherwise return NO_REGS. */
1079 static inline enum reg_class
get_op_class(rtx op)1080 get_op_class (rtx op)
1081 {
1082 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
1083 }
1084
1085 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1086 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1087 SUBREG for VAL to make them equal. */
1088 static rtx_insn *
emit_spill_move(bool to_p,rtx mem_pseudo,rtx val)1089 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1090 {
1091 if (GET_MODE (mem_pseudo) != GET_MODE (val))
1092 {
1093 /* Usually size of mem_pseudo is greater than val size but in
1094 rare cases it can be less as it can be defined by target
1095 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1096 if (! MEM_P (val))
1097 {
1098 val = gen_rtx_SUBREG (GET_MODE (mem_pseudo),
1099 GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val,
1100 0);
1101 LRA_SUBREG_P (val) = 1;
1102 }
1103 else
1104 {
1105 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
1106 LRA_SUBREG_P (mem_pseudo) = 1;
1107 }
1108 }
1109 return to_p ? gen_move_insn (mem_pseudo, val)
1110 : gen_move_insn (val, mem_pseudo);
1111 }
1112
1113 /* Process a special case insn (register move), return true if we
1114 don't need to process it anymore. INSN should be a single set
1115 insn. Set up that RTL was changed through CHANGE_P and macro
1116 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1117 SEC_MEM_P. */
1118 static bool
check_and_process_move(bool * change_p,bool * sec_mem_p ATTRIBUTE_UNUSED)1119 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
1120 {
1121 int sregno, dregno;
1122 rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1123 rtx_insn *before;
1124 enum reg_class dclass, sclass, secondary_class;
1125 secondary_reload_info sri;
1126
1127 lra_assert (curr_insn_set != NULL_RTX);
1128 dreg = dest = SET_DEST (curr_insn_set);
1129 sreg = src = SET_SRC (curr_insn_set);
1130 if (GET_CODE (dest) == SUBREG)
1131 dreg = SUBREG_REG (dest);
1132 if (GET_CODE (src) == SUBREG)
1133 sreg = SUBREG_REG (src);
1134 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
1135 return false;
1136 sclass = dclass = NO_REGS;
1137 if (REG_P (dreg))
1138 dclass = get_reg_class (REGNO (dreg));
1139 if (dclass == ALL_REGS)
1140 /* ALL_REGS is used for new pseudos created by transformations
1141 like reload of SUBREG_REG (see function
1142 simplify_operand_subreg). We don't know their class yet. We
1143 should figure out the class from processing the insn
1144 constraints not in this fast path function. Even if ALL_REGS
1145 were a right class for the pseudo, secondary_... hooks usually
1146 are not define for ALL_REGS. */
1147 return false;
1148 if (REG_P (sreg))
1149 sclass = get_reg_class (REGNO (sreg));
1150 if (sclass == ALL_REGS)
1151 /* See comments above. */
1152 return false;
1153 if (sclass == NO_REGS && dclass == NO_REGS)
1154 return false;
1155 #ifdef SECONDARY_MEMORY_NEEDED
1156 if (SECONDARY_MEMORY_NEEDED (sclass, dclass, GET_MODE (src))
1157 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1158 && ((sclass != NO_REGS && dclass != NO_REGS)
1159 || GET_MODE (src) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src)))
1160 #endif
1161 )
1162 {
1163 *sec_mem_p = true;
1164 return false;
1165 }
1166 #endif
1167 if (! REG_P (dreg) || ! REG_P (sreg))
1168 return false;
1169 sri.prev_sri = NULL;
1170 sri.icode = CODE_FOR_nothing;
1171 sri.extra_cost = 0;
1172 secondary_class = NO_REGS;
1173 /* Set up hard register for a reload pseudo for hook
1174 secondary_reload because some targets just ignore unassigned
1175 pseudos in the hook. */
1176 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
1177 {
1178 dregno = REGNO (dreg);
1179 reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
1180 }
1181 else
1182 dregno = -1;
1183 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1184 {
1185 sregno = REGNO (sreg);
1186 reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1187 }
1188 else
1189 sregno = -1;
1190 if (sclass != NO_REGS)
1191 secondary_class
1192 = (enum reg_class) targetm.secondary_reload (false, dest,
1193 (reg_class_t) sclass,
1194 GET_MODE (src), &sri);
1195 if (sclass == NO_REGS
1196 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1197 && dclass != NO_REGS))
1198 {
1199 enum reg_class old_sclass = secondary_class;
1200 secondary_reload_info old_sri = sri;
1201
1202 sri.prev_sri = NULL;
1203 sri.icode = CODE_FOR_nothing;
1204 sri.extra_cost = 0;
1205 secondary_class
1206 = (enum reg_class) targetm.secondary_reload (true, src,
1207 (reg_class_t) dclass,
1208 GET_MODE (src), &sri);
1209 /* Check the target hook consistency. */
1210 lra_assert
1211 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1212 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1213 || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1214 }
1215 if (sregno >= 0)
1216 reg_renumber [sregno] = -1;
1217 if (dregno >= 0)
1218 reg_renumber [dregno] = -1;
1219 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1220 return false;
1221 *change_p = true;
1222 new_reg = NULL_RTX;
1223 if (secondary_class != NO_REGS)
1224 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX,
1225 secondary_class,
1226 "secondary");
1227 start_sequence ();
1228 if (sri.icode == CODE_FOR_nothing)
1229 lra_emit_move (new_reg, src);
1230 else
1231 {
1232 enum reg_class scratch_class;
1233
1234 scratch_class = (reg_class_from_constraints
1235 (insn_data[sri.icode].operand[2].constraint));
1236 scratch_reg = (lra_create_new_reg_with_unique_value
1237 (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1238 scratch_class, "scratch"));
1239 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1240 src, scratch_reg));
1241 }
1242 before = get_insns ();
1243 end_sequence ();
1244 lra_process_new_insns (curr_insn, before, NULL, "Inserting the move");
1245 if (new_reg != NULL_RTX)
1246 SET_SRC (curr_insn_set) = new_reg;
1247 else
1248 {
1249 if (lra_dump_file != NULL)
1250 {
1251 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1252 dump_insn_slim (lra_dump_file, curr_insn);
1253 }
1254 lra_set_insn_deleted (curr_insn);
1255 return true;
1256 }
1257 return false;
1258 }
1259
1260 /* The following data describe the result of process_alt_operands.
1261 The data are used in curr_insn_transform to generate reloads. */
1262
1263 /* The chosen reg classes which should be used for the corresponding
1264 operands. */
1265 static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1266 /* True if the operand should be the same as another operand and that
1267 other operand does not need a reload. */
1268 static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1269 /* True if the operand does not need a reload. */
1270 static bool goal_alt_win[MAX_RECOG_OPERANDS];
1271 /* True if the operand can be offsetable memory. */
1272 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1273 /* The number of an operand to which given operand can be matched to. */
1274 static int goal_alt_matches[MAX_RECOG_OPERANDS];
1275 /* The number of elements in the following array. */
1276 static int goal_alt_dont_inherit_ops_num;
1277 /* Numbers of operands whose reload pseudos should not be inherited. */
1278 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1279 /* True if the insn commutative operands should be swapped. */
1280 static bool goal_alt_swapped;
1281 /* The chosen insn alternative. */
1282 static int goal_alt_number;
1283
1284 /* The following five variables are used to choose the best insn
1285 alternative. They reflect final characteristics of the best
1286 alternative. */
1287
1288 /* Number of necessary reloads and overall cost reflecting the
1289 previous value and other unpleasantness of the best alternative. */
1290 static int best_losers, best_overall;
1291 /* Overall number hard registers used for reloads. For example, on
1292 some targets we need 2 general registers to reload DFmode and only
1293 one floating point register. */
1294 static int best_reload_nregs;
1295 /* Overall number reflecting distances of previous reloading the same
1296 value. The distances are counted from the current BB start. It is
1297 used to improve inheritance chances. */
1298 static int best_reload_sum;
1299
1300 /* True if the current insn should have no correspondingly input or
1301 output reloads. */
1302 static bool no_input_reloads_p, no_output_reloads_p;
1303
1304 /* True if we swapped the commutative operands in the current
1305 insn. */
1306 static int curr_swapped;
1307
1308 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1309 register of class CL. Add any input reloads to list BEFORE. AFTER
1310 is nonnull if *LOC is an automodified value; handle that case by
1311 adding the required output reloads to list AFTER. Return true if
1312 the RTL was changed.
1313
1314 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1315 register. Return false if the address register is correct. */
1316 static bool
process_addr_reg(rtx * loc,bool check_only_p,rtx_insn ** before,rtx_insn ** after,enum reg_class cl)1317 process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1318 enum reg_class cl)
1319 {
1320 int regno;
1321 enum reg_class rclass, new_class;
1322 rtx reg;
1323 rtx new_reg;
1324 machine_mode mode;
1325 bool subreg_p, before_p = false;
1326
1327 subreg_p = GET_CODE (*loc) == SUBREG;
1328 if (subreg_p)
1329 loc = &SUBREG_REG (*loc);
1330 reg = *loc;
1331 mode = GET_MODE (reg);
1332 if (! REG_P (reg))
1333 {
1334 if (check_only_p)
1335 return true;
1336 /* Always reload memory in an address even if the target supports
1337 such addresses. */
1338 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1339 before_p = true;
1340 }
1341 else
1342 {
1343 regno = REGNO (reg);
1344 rclass = get_reg_class (regno);
1345 if (! check_only_p
1346 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1347 {
1348 if (lra_dump_file != NULL)
1349 {
1350 fprintf (lra_dump_file,
1351 "Changing pseudo %d in address of insn %u on equiv ",
1352 REGNO (reg), INSN_UID (curr_insn));
1353 dump_value_slim (lra_dump_file, *loc, 1);
1354 fprintf (lra_dump_file, "\n");
1355 }
1356 *loc = copy_rtx (*loc);
1357 }
1358 if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1359 {
1360 if (check_only_p)
1361 return true;
1362 reg = *loc;
1363 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1364 mode, reg, cl, subreg_p, "address", &new_reg))
1365 before_p = true;
1366 }
1367 else if (new_class != NO_REGS && rclass != new_class)
1368 {
1369 if (check_only_p)
1370 return true;
1371 lra_change_class (regno, new_class, " Change to", true);
1372 return false;
1373 }
1374 else
1375 return false;
1376 }
1377 if (before_p)
1378 {
1379 push_to_sequence (*before);
1380 lra_emit_move (new_reg, reg);
1381 *before = get_insns ();
1382 end_sequence ();
1383 }
1384 *loc = new_reg;
1385 if (after != NULL)
1386 {
1387 start_sequence ();
1388 lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
1389 emit_insn (*after);
1390 *after = get_insns ();
1391 end_sequence ();
1392 }
1393 return true;
1394 }
1395
1396 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1397 the insn to be inserted before curr insn. AFTER returns the
1398 the insn to be inserted after curr insn. ORIGREG and NEWREG
1399 are the original reg and new reg for reload. */
1400 static void
insert_move_for_subreg(rtx_insn ** before,rtx_insn ** after,rtx origreg,rtx newreg)1401 insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1402 rtx newreg)
1403 {
1404 if (before)
1405 {
1406 push_to_sequence (*before);
1407 lra_emit_move (newreg, origreg);
1408 *before = get_insns ();
1409 end_sequence ();
1410 }
1411 if (after)
1412 {
1413 start_sequence ();
1414 lra_emit_move (origreg, newreg);
1415 emit_insn (*after);
1416 *after = get_insns ();
1417 end_sequence ();
1418 }
1419 }
1420
1421 static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1422
1423 /* Make reloads for subreg in operand NOP with internal subreg mode
1424 REG_MODE, add new reloads for further processing. Return true if
1425 any change was done. */
1426 static bool
simplify_operand_subreg(int nop,machine_mode reg_mode)1427 simplify_operand_subreg (int nop, machine_mode reg_mode)
1428 {
1429 int hard_regno;
1430 rtx_insn *before, *after;
1431 machine_mode mode, innermode;
1432 rtx reg, new_reg;
1433 rtx operand = *curr_id->operand_loc[nop];
1434 enum reg_class regclass;
1435 enum op_type type;
1436
1437 before = after = NULL;
1438
1439 if (GET_CODE (operand) != SUBREG)
1440 return false;
1441
1442 mode = GET_MODE (operand);
1443 reg = SUBREG_REG (operand);
1444 innermode = GET_MODE (reg);
1445 type = curr_static_id->operand[nop].type;
1446 /* If we change address for paradoxical subreg of memory, the
1447 address might violate the necessary alignment or the access might
1448 be slow. So take this into consideration. We should not worry
1449 about access beyond allocated memory for paradoxical memory
1450 subregs as we don't substitute such equiv memory (see processing
1451 equivalences in function lra_constraints) and because for spilled
1452 pseudos we allocate stack memory enough for the biggest
1453 corresponding paradoxical subreg. */
1454 if (MEM_P (reg)
1455 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (reg))
1456 || MEM_ALIGN (reg) >= GET_MODE_ALIGNMENT (mode)))
1457 {
1458 rtx subst, old = *curr_id->operand_loc[nop];
1459
1460 alter_subreg (curr_id->operand_loc[nop], false);
1461 subst = *curr_id->operand_loc[nop];
1462 lra_assert (MEM_P (subst));
1463 if (! valid_address_p (innermode, XEXP (reg, 0),
1464 MEM_ADDR_SPACE (reg))
1465 || valid_address_p (GET_MODE (subst), XEXP (subst, 0),
1466 MEM_ADDR_SPACE (subst)))
1467 return true;
1468 else if ((get_constraint_type (lookup_constraint
1469 (curr_static_id->operand[nop].constraint))
1470 != CT_SPECIAL_MEMORY)
1471 /* We still can reload address and if the address is
1472 valid, we can remove subreg without reloading its
1473 inner memory. */
1474 && valid_address_p (GET_MODE (subst),
1475 regno_reg_rtx
1476 [ira_class_hard_regs
1477 [base_reg_class (GET_MODE (subst),
1478 MEM_ADDR_SPACE (subst),
1479 ADDRESS, SCRATCH)][0]],
1480 MEM_ADDR_SPACE (subst)))
1481 return true;
1482
1483 /* If the address was valid and became invalid, prefer to reload
1484 the memory. Typical case is when the index scale should
1485 correspond the memory. */
1486 *curr_id->operand_loc[nop] = old;
1487 }
1488 else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
1489 {
1490 alter_subreg (curr_id->operand_loc[nop], false);
1491 return true;
1492 }
1493 else if (CONSTANT_P (reg))
1494 {
1495 /* Try to simplify subreg of constant. It is usually result of
1496 equivalence substitution. */
1497 if (innermode == VOIDmode
1498 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode)
1499 innermode = curr_static_id->operand[nop].mode;
1500 if ((new_reg = simplify_subreg (mode, reg, innermode,
1501 SUBREG_BYTE (operand))) != NULL_RTX)
1502 {
1503 *curr_id->operand_loc[nop] = new_reg;
1504 return true;
1505 }
1506 }
1507 /* Put constant into memory when we have mixed modes. It generates
1508 a better code in most cases as it does not need a secondary
1509 reload memory. It also prevents LRA looping when LRA is using
1510 secondary reload memory again and again. */
1511 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1512 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1513 {
1514 SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1515 alter_subreg (curr_id->operand_loc[nop], false);
1516 return true;
1517 }
1518 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1519 if there may be a problem accessing OPERAND in the outer
1520 mode. */
1521 if ((REG_P (reg)
1522 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1523 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1524 /* Don't reload paradoxical subregs because we could be looping
1525 having repeatedly final regno out of hard regs range. */
1526 && (hard_regno_nregs[hard_regno][innermode]
1527 >= hard_regno_nregs[hard_regno][mode])
1528 && simplify_subreg_regno (hard_regno, innermode,
1529 SUBREG_BYTE (operand), mode) < 0
1530 /* Don't reload subreg for matching reload. It is actually
1531 valid subreg in LRA. */
1532 && ! LRA_SUBREG_P (operand))
1533 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1534 {
1535 enum reg_class rclass;
1536
1537 if (REG_P (reg))
1538 /* There is a big probability that we will get the same class
1539 for the new pseudo and we will get the same insn which
1540 means infinite looping. So spill the new pseudo. */
1541 rclass = NO_REGS;
1542 else
1543 /* The class will be defined later in curr_insn_transform. */
1544 rclass
1545 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1546
1547 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1548 rclass, TRUE, "subreg reg", &new_reg))
1549 {
1550 bool insert_before, insert_after;
1551 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1552
1553 insert_before = (type != OP_OUT
1554 || GET_MODE_SIZE (innermode) > GET_MODE_SIZE (mode));
1555 insert_after = (type != OP_IN);
1556 insert_move_for_subreg (insert_before ? &before : NULL,
1557 insert_after ? &after : NULL,
1558 reg, new_reg);
1559 }
1560 SUBREG_REG (operand) = new_reg;
1561 lra_process_new_insns (curr_insn, before, after,
1562 "Inserting subreg reload");
1563 return true;
1564 }
1565 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1566 IRA allocates hardreg to the inner pseudo reg according to its mode
1567 instead of the outermode, so the size of the hardreg may not be enough
1568 to contain the outermode operand, in that case we may need to insert
1569 reload for the reg. For the following two types of paradoxical subreg,
1570 we need to insert reload:
1571 1. If the op_type is OP_IN, and the hardreg could not be paired with
1572 other hardreg to contain the outermode operand
1573 (checked by in_hard_reg_set_p), we need to insert the reload.
1574 2. If the op_type is OP_OUT or OP_INOUT.
1575
1576 Here is a paradoxical subreg example showing how the reload is generated:
1577
1578 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1579 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1580
1581 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1582 here, if reg107 is assigned to hardreg R15, because R15 is the last
1583 hardreg, compiler cannot find another hardreg to pair with R15 to
1584 contain TImode data. So we insert a TImode reload reg180 for it.
1585 After reload is inserted:
1586
1587 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1588 (reg:DI 107 [ __comp ])) -1
1589 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1590 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1591
1592 Two reload hard registers will be allocated to reg180 to save TImode data
1593 in LRA_assign. */
1594 else if (REG_P (reg)
1595 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1596 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1597 && (hard_regno_nregs[hard_regno][innermode]
1598 < hard_regno_nregs[hard_regno][mode])
1599 && (regclass = lra_get_allocno_class (REGNO (reg)))
1600 && (type != OP_IN
1601 || !in_hard_reg_set_p (reg_class_contents[regclass],
1602 mode, hard_regno)))
1603 {
1604 /* The class will be defined later in curr_insn_transform. */
1605 enum reg_class rclass
1606 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1607
1608 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1609 rclass, TRUE, "paradoxical subreg", &new_reg))
1610 {
1611 rtx subreg;
1612 bool insert_before, insert_after;
1613
1614 PUT_MODE (new_reg, mode);
1615 subreg = gen_lowpart_SUBREG (innermode, new_reg);
1616 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1617
1618 insert_before = (type != OP_OUT);
1619 insert_after = (type != OP_IN);
1620 insert_move_for_subreg (insert_before ? &before : NULL,
1621 insert_after ? &after : NULL,
1622 reg, subreg);
1623 }
1624 SUBREG_REG (operand) = new_reg;
1625 lra_process_new_insns (curr_insn, before, after,
1626 "Inserting paradoxical subreg reload");
1627 return true;
1628 }
1629 return false;
1630 }
1631
1632 /* Return TRUE if X refers for a hard register from SET. */
1633 static bool
uses_hard_regs_p(rtx x,HARD_REG_SET set)1634 uses_hard_regs_p (rtx x, HARD_REG_SET set)
1635 {
1636 int i, j, x_hard_regno;
1637 machine_mode mode;
1638 const char *fmt;
1639 enum rtx_code code;
1640
1641 if (x == NULL_RTX)
1642 return false;
1643 code = GET_CODE (x);
1644 mode = GET_MODE (x);
1645 if (code == SUBREG)
1646 {
1647 x = SUBREG_REG (x);
1648 code = GET_CODE (x);
1649 if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode))
1650 mode = GET_MODE (x);
1651 }
1652
1653 if (REG_P (x))
1654 {
1655 x_hard_regno = get_hard_regno (x);
1656 return (x_hard_regno >= 0
1657 && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1658 }
1659 if (MEM_P (x))
1660 {
1661 struct address_info ad;
1662
1663 decompose_mem_address (&ad, x);
1664 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set))
1665 return true;
1666 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set))
1667 return true;
1668 }
1669 fmt = GET_RTX_FORMAT (code);
1670 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1671 {
1672 if (fmt[i] == 'e')
1673 {
1674 if (uses_hard_regs_p (XEXP (x, i), set))
1675 return true;
1676 }
1677 else if (fmt[i] == 'E')
1678 {
1679 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1680 if (uses_hard_regs_p (XVECEXP (x, i, j), set))
1681 return true;
1682 }
1683 }
1684 return false;
1685 }
1686
1687 /* Return true if OP is a spilled pseudo. */
1688 static inline bool
spilled_pseudo_p(rtx op)1689 spilled_pseudo_p (rtx op)
1690 {
1691 return (REG_P (op)
1692 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
1693 }
1694
1695 /* Return true if X is a general constant. */
1696 static inline bool
general_constant_p(rtx x)1697 general_constant_p (rtx x)
1698 {
1699 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
1700 }
1701
1702 static bool
reg_in_class_p(rtx reg,enum reg_class cl)1703 reg_in_class_p (rtx reg, enum reg_class cl)
1704 {
1705 if (cl == NO_REGS)
1706 return get_reg_class (REGNO (reg)) == NO_REGS;
1707 return in_class_p (reg, cl, NULL);
1708 }
1709
1710 /* Return true if SET of RCLASS contains no hard regs which can be
1711 used in MODE. */
1712 static bool
prohibited_class_reg_set_mode_p(enum reg_class rclass,HARD_REG_SET & set,enum machine_mode mode)1713 prohibited_class_reg_set_mode_p (enum reg_class rclass,
1714 HARD_REG_SET &set,
1715 enum machine_mode mode)
1716 {
1717 HARD_REG_SET temp;
1718
1719 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
1720 COPY_HARD_REG_SET (temp, set);
1721 AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs);
1722 return (hard_reg_set_subset_p
1723 (temp, ira_prohibited_class_mode_regs[rclass][mode]));
1724 }
1725
1726 /* Major function to choose the current insn alternative and what
1727 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1728 negative we should consider only this alternative. Return false if
1729 we can not choose the alternative or find how to reload the
1730 operands. */
1731 static bool
process_alt_operands(int only_alternative)1732 process_alt_operands (int only_alternative)
1733 {
1734 bool ok_p = false;
1735 int nop, overall, nalt;
1736 int n_alternatives = curr_static_id->n_alternatives;
1737 int n_operands = curr_static_id->n_operands;
1738 /* LOSERS counts the operands that don't fit this alternative and
1739 would require loading. */
1740 int losers;
1741 /* REJECT is a count of how undesirable this alternative says it is
1742 if any reloading is required. If the alternative matches exactly
1743 then REJECT is ignored, but otherwise it gets this much counted
1744 against it in addition to the reloading needed. */
1745 int reject;
1746 int op_reject;
1747 /* The number of elements in the following array. */
1748 int early_clobbered_regs_num;
1749 /* Numbers of operands which are early clobber registers. */
1750 int early_clobbered_nops[MAX_RECOG_OPERANDS];
1751 enum reg_class curr_alt[MAX_RECOG_OPERANDS];
1752 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
1753 bool curr_alt_match_win[MAX_RECOG_OPERANDS];
1754 bool curr_alt_win[MAX_RECOG_OPERANDS];
1755 bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
1756 int curr_alt_matches[MAX_RECOG_OPERANDS];
1757 /* The number of elements in the following array. */
1758 int curr_alt_dont_inherit_ops_num;
1759 /* Numbers of operands whose reload pseudos should not be inherited. */
1760 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1761 rtx op;
1762 /* The register when the operand is a subreg of register, otherwise the
1763 operand itself. */
1764 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
1765 /* The register if the operand is a register or subreg of register,
1766 otherwise NULL. */
1767 rtx operand_reg[MAX_RECOG_OPERANDS];
1768 int hard_regno[MAX_RECOG_OPERANDS];
1769 machine_mode biggest_mode[MAX_RECOG_OPERANDS];
1770 int reload_nregs, reload_sum;
1771 bool costly_p;
1772 enum reg_class cl;
1773
1774 /* Calculate some data common for all alternatives to speed up the
1775 function. */
1776 for (nop = 0; nop < n_operands; nop++)
1777 {
1778 rtx reg;
1779
1780 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
1781 /* The real hard regno of the operand after the allocation. */
1782 hard_regno[nop] = get_hard_regno (op);
1783
1784 operand_reg[nop] = reg = op;
1785 biggest_mode[nop] = GET_MODE (op);
1786 if (GET_CODE (op) == SUBREG)
1787 {
1788 operand_reg[nop] = reg = SUBREG_REG (op);
1789 if (GET_MODE_SIZE (biggest_mode[nop])
1790 < GET_MODE_SIZE (GET_MODE (reg)))
1791 biggest_mode[nop] = GET_MODE (reg);
1792 }
1793 if (! REG_P (reg))
1794 operand_reg[nop] = NULL_RTX;
1795 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1796 || ((int) REGNO (reg)
1797 == lra_get_elimination_hard_regno (REGNO (reg))))
1798 no_subreg_reg_operand[nop] = reg;
1799 else
1800 operand_reg[nop] = no_subreg_reg_operand[nop]
1801 /* Just use natural mode for elimination result. It should
1802 be enough for extra constraints hooks. */
1803 = regno_reg_rtx[hard_regno[nop]];
1804 }
1805
1806 /* The constraints are made of several alternatives. Each operand's
1807 constraint looks like foo,bar,... with commas separating the
1808 alternatives. The first alternatives for all operands go
1809 together, the second alternatives go together, etc.
1810
1811 First loop over alternatives. */
1812 alternative_mask preferred = curr_id->preferred_alternatives;
1813 if (only_alternative >= 0)
1814 preferred &= ALTERNATIVE_BIT (only_alternative);
1815
1816 for (nalt = 0; nalt < n_alternatives; nalt++)
1817 {
1818 /* Loop over operands for one constraint alternative. */
1819 if (!TEST_BIT (preferred, nalt))
1820 continue;
1821
1822 overall = losers = reject = reload_nregs = reload_sum = 0;
1823 for (nop = 0; nop < n_operands; nop++)
1824 {
1825 int inc = (curr_static_id
1826 ->operand_alternative[nalt * n_operands + nop].reject);
1827 if (lra_dump_file != NULL && inc != 0)
1828 fprintf (lra_dump_file,
1829 " Staticly defined alt reject+=%d\n", inc);
1830 reject += inc;
1831 }
1832 early_clobbered_regs_num = 0;
1833
1834 for (nop = 0; nop < n_operands; nop++)
1835 {
1836 const char *p;
1837 char *end;
1838 int len, c, m, i, opalt_num, this_alternative_matches;
1839 bool win, did_match, offmemok, early_clobber_p;
1840 /* false => this operand can be reloaded somehow for this
1841 alternative. */
1842 bool badop;
1843 /* true => this operand can be reloaded if the alternative
1844 allows regs. */
1845 bool winreg;
1846 /* True if a constant forced into memory would be OK for
1847 this operand. */
1848 bool constmemok;
1849 enum reg_class this_alternative, this_costly_alternative;
1850 HARD_REG_SET this_alternative_set, this_costly_alternative_set;
1851 bool this_alternative_match_win, this_alternative_win;
1852 bool this_alternative_offmemok;
1853 bool scratch_p;
1854 machine_mode mode;
1855 enum constraint_num cn;
1856
1857 opalt_num = nalt * n_operands + nop;
1858 if (curr_static_id->operand_alternative[opalt_num].anything_ok)
1859 {
1860 /* Fast track for no constraints at all. */
1861 curr_alt[nop] = NO_REGS;
1862 CLEAR_HARD_REG_SET (curr_alt_set[nop]);
1863 curr_alt_win[nop] = true;
1864 curr_alt_match_win[nop] = false;
1865 curr_alt_offmemok[nop] = false;
1866 curr_alt_matches[nop] = -1;
1867 continue;
1868 }
1869
1870 op = no_subreg_reg_operand[nop];
1871 mode = curr_operand_mode[nop];
1872
1873 win = did_match = winreg = offmemok = constmemok = false;
1874 badop = true;
1875
1876 early_clobber_p = false;
1877 p = curr_static_id->operand_alternative[opalt_num].constraint;
1878
1879 this_costly_alternative = this_alternative = NO_REGS;
1880 /* We update set of possible hard regs besides its class
1881 because reg class might be inaccurate. For example,
1882 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1883 is translated in HI_REGS because classes are merged by
1884 pairs and there is no accurate intermediate class. */
1885 CLEAR_HARD_REG_SET (this_alternative_set);
1886 CLEAR_HARD_REG_SET (this_costly_alternative_set);
1887 this_alternative_win = false;
1888 this_alternative_match_win = false;
1889 this_alternative_offmemok = false;
1890 this_alternative_matches = -1;
1891
1892 /* An empty constraint should be excluded by the fast
1893 track. */
1894 lra_assert (*p != 0 && *p != ',');
1895
1896 op_reject = 0;
1897 /* Scan this alternative's specs for this operand; set WIN
1898 if the operand fits any letter in this alternative.
1899 Otherwise, clear BADOP if this operand could fit some
1900 letter after reloads, or set WINREG if this operand could
1901 fit after reloads provided the constraint allows some
1902 registers. */
1903 costly_p = false;
1904 do
1905 {
1906 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1907 {
1908 case '\0':
1909 len = 0;
1910 break;
1911 case ',':
1912 c = '\0';
1913 break;
1914
1915 case '&':
1916 early_clobber_p = true;
1917 break;
1918
1919 case '$':
1920 op_reject += LRA_MAX_REJECT;
1921 break;
1922 case '^':
1923 op_reject += LRA_LOSER_COST_FACTOR;
1924 break;
1925
1926 case '#':
1927 /* Ignore rest of this alternative. */
1928 c = '\0';
1929 break;
1930
1931 case '0': case '1': case '2': case '3': case '4':
1932 case '5': case '6': case '7': case '8': case '9':
1933 {
1934 int m_hregno;
1935 bool match_p;
1936
1937 m = strtoul (p, &end, 10);
1938 p = end;
1939 len = 0;
1940 lra_assert (nop > m);
1941
1942 this_alternative_matches = m;
1943 m_hregno = get_hard_regno (*curr_id->operand_loc[m]);
1944 /* We are supposed to match a previous operand.
1945 If we do, we win if that one did. If we do
1946 not, count both of the operands as losers.
1947 (This is too conservative, since most of the
1948 time only a single reload insn will be needed
1949 to make the two operands win. As a result,
1950 this alternative may be rejected when it is
1951 actually desirable.) */
1952 match_p = false;
1953 if (operands_match_p (*curr_id->operand_loc[nop],
1954 *curr_id->operand_loc[m], m_hregno))
1955 {
1956 /* We should reject matching of an early
1957 clobber operand if the matching operand is
1958 not dying in the insn. */
1959 if (! curr_static_id->operand[m].early_clobber
1960 || operand_reg[nop] == NULL_RTX
1961 || (find_regno_note (curr_insn, REG_DEAD,
1962 REGNO (op))
1963 || REGNO (op) == REGNO (operand_reg[m])))
1964 match_p = true;
1965 }
1966 if (match_p)
1967 {
1968 /* If we are matching a non-offsettable
1969 address where an offsettable address was
1970 expected, then we must reject this
1971 combination, because we can't reload
1972 it. */
1973 if (curr_alt_offmemok[m]
1974 && MEM_P (*curr_id->operand_loc[m])
1975 && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
1976 continue;
1977 }
1978 else
1979 {
1980 /* Operands don't match. Both operands must
1981 allow a reload register, otherwise we
1982 cannot make them match. */
1983 if (curr_alt[m] == NO_REGS)
1984 break;
1985 /* Retroactively mark the operand we had to
1986 match as a loser, if it wasn't already and
1987 it wasn't matched to a register constraint
1988 (e.g it might be matched by memory). */
1989 if (curr_alt_win[m]
1990 && (operand_reg[m] == NULL_RTX
1991 || hard_regno[m] < 0))
1992 {
1993 losers++;
1994 reload_nregs
1995 += (ira_reg_class_max_nregs[curr_alt[m]]
1996 [GET_MODE (*curr_id->operand_loc[m])]);
1997 }
1998
1999 /* Prefer matching earlyclobber alternative as
2000 it results in less hard regs required for
2001 the insn than a non-matching earlyclobber
2002 alternative. */
2003 if (curr_static_id->operand[m].early_clobber)
2004 {
2005 if (lra_dump_file != NULL)
2006 fprintf
2007 (lra_dump_file,
2008 " %d Matching earlyclobber alt:"
2009 " reject--\n",
2010 nop);
2011 reject--;
2012 }
2013 /* Otherwise we prefer no matching
2014 alternatives because it gives more freedom
2015 in RA. */
2016 else if (operand_reg[nop] == NULL_RTX
2017 || (find_regno_note (curr_insn, REG_DEAD,
2018 REGNO (operand_reg[nop]))
2019 == NULL_RTX))
2020 {
2021 if (lra_dump_file != NULL)
2022 fprintf
2023 (lra_dump_file,
2024 " %d Matching alt: reject+=2\n",
2025 nop);
2026 reject += 2;
2027 }
2028 }
2029 /* If we have to reload this operand and some
2030 previous operand also had to match the same
2031 thing as this operand, we don't know how to do
2032 that. */
2033 if (!match_p || !curr_alt_win[m])
2034 {
2035 for (i = 0; i < nop; i++)
2036 if (curr_alt_matches[i] == m)
2037 break;
2038 if (i < nop)
2039 break;
2040 }
2041 else
2042 did_match = true;
2043
2044 /* This can be fixed with reloads if the operand
2045 we are supposed to match can be fixed with
2046 reloads. */
2047 badop = false;
2048 this_alternative = curr_alt[m];
2049 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]);
2050 winreg = this_alternative != NO_REGS;
2051 break;
2052 }
2053
2054 case 'g':
2055 if (MEM_P (op)
2056 || general_constant_p (op)
2057 || spilled_pseudo_p (op))
2058 win = true;
2059 cl = GENERAL_REGS;
2060 goto reg;
2061
2062 default:
2063 cn = lookup_constraint (p);
2064 switch (get_constraint_type (cn))
2065 {
2066 case CT_REGISTER:
2067 cl = reg_class_for_constraint (cn);
2068 if (cl != NO_REGS)
2069 goto reg;
2070 break;
2071
2072 case CT_CONST_INT:
2073 if (CONST_INT_P (op)
2074 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
2075 win = true;
2076 break;
2077
2078 case CT_MEMORY:
2079 if (MEM_P (op)
2080 && satisfies_memory_constraint_p (op, cn))
2081 win = true;
2082 else if (spilled_pseudo_p (op))
2083 win = true;
2084
2085 /* If we didn't already win, we can reload constants
2086 via force_const_mem or put the pseudo value into
2087 memory, or make other memory by reloading the
2088 address like for 'o'. */
2089 if (CONST_POOL_OK_P (mode, op)
2090 || MEM_P (op) || REG_P (op))
2091 badop = false;
2092 constmemok = true;
2093 offmemok = true;
2094 break;
2095
2096 case CT_ADDRESS:
2097 /* If we didn't already win, we can reload the address
2098 into a base register. */
2099 if (satisfies_address_constraint_p (op, cn))
2100 win = true;
2101 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2102 ADDRESS, SCRATCH);
2103 badop = false;
2104 goto reg;
2105
2106 case CT_FIXED_FORM:
2107 if (constraint_satisfied_p (op, cn))
2108 win = true;
2109 break;
2110
2111 case CT_SPECIAL_MEMORY:
2112 if (MEM_P (op)
2113 && satisfies_memory_constraint_p (op, cn))
2114 win = true;
2115 else if (spilled_pseudo_p (op))
2116 win = true;
2117 break;
2118 }
2119 break;
2120
2121 reg:
2122 this_alternative = reg_class_subunion[this_alternative][cl];
2123 IOR_HARD_REG_SET (this_alternative_set,
2124 reg_class_contents[cl]);
2125 if (costly_p)
2126 {
2127 this_costly_alternative
2128 = reg_class_subunion[this_costly_alternative][cl];
2129 IOR_HARD_REG_SET (this_costly_alternative_set,
2130 reg_class_contents[cl]);
2131 }
2132 if (mode == BLKmode)
2133 break;
2134 winreg = true;
2135 if (REG_P (op))
2136 {
2137 if (hard_regno[nop] >= 0
2138 && in_hard_reg_set_p (this_alternative_set,
2139 mode, hard_regno[nop]))
2140 win = true;
2141 else if (hard_regno[nop] < 0
2142 && in_class_p (op, this_alternative, NULL))
2143 win = true;
2144 }
2145 break;
2146 }
2147 if (c != ' ' && c != '\t')
2148 costly_p = c == '*';
2149 }
2150 while ((p += len), c);
2151
2152 scratch_p = (operand_reg[nop] != NULL_RTX
2153 && lra_former_scratch_p (REGNO (operand_reg[nop])));
2154 /* Record which operands fit this alternative. */
2155 if (win)
2156 {
2157 this_alternative_win = true;
2158 if (operand_reg[nop] != NULL_RTX)
2159 {
2160 if (hard_regno[nop] >= 0)
2161 {
2162 if (in_hard_reg_set_p (this_costly_alternative_set,
2163 mode, hard_regno[nop]))
2164 {
2165 if (lra_dump_file != NULL)
2166 fprintf (lra_dump_file,
2167 " %d Costly set: reject++\n",
2168 nop);
2169 reject++;
2170 }
2171 }
2172 else
2173 {
2174 /* Prefer won reg to spilled pseudo under other
2175 equal conditions for possibe inheritance. */
2176 if (! scratch_p)
2177 {
2178 if (lra_dump_file != NULL)
2179 fprintf
2180 (lra_dump_file,
2181 " %d Non pseudo reload: reject++\n",
2182 nop);
2183 reject++;
2184 }
2185 if (in_class_p (operand_reg[nop],
2186 this_costly_alternative, NULL))
2187 {
2188 if (lra_dump_file != NULL)
2189 fprintf
2190 (lra_dump_file,
2191 " %d Non pseudo costly reload:"
2192 " reject++\n",
2193 nop);
2194 reject++;
2195 }
2196 }
2197 /* We simulate the behavior of old reload here.
2198 Although scratches need hard registers and it
2199 might result in spilling other pseudos, no reload
2200 insns are generated for the scratches. So it
2201 might cost something but probably less than old
2202 reload pass believes. */
2203 if (scratch_p)
2204 {
2205 if (lra_dump_file != NULL)
2206 fprintf (lra_dump_file,
2207 " %d Scratch win: reject+=2\n",
2208 nop);
2209 reject += 2;
2210 }
2211 }
2212 }
2213 else if (did_match)
2214 this_alternative_match_win = true;
2215 else
2216 {
2217 int const_to_mem = 0;
2218 bool no_regs_p;
2219
2220 reject += op_reject;
2221 /* Never do output reload of stack pointer. It makes
2222 impossible to do elimination when SP is changed in
2223 RTL. */
2224 if (op == stack_pointer_rtx && ! frame_pointer_needed
2225 && curr_static_id->operand[nop].type != OP_IN)
2226 goto fail;
2227
2228 /* If this alternative asks for a specific reg class, see if there
2229 is at least one allocatable register in that class. */
2230 no_regs_p
2231 = (this_alternative == NO_REGS
2232 || (hard_reg_set_subset_p
2233 (reg_class_contents[this_alternative],
2234 lra_no_alloc_regs)));
2235
2236 /* For asms, verify that the class for this alternative is possible
2237 for the mode that is specified. */
2238 if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2239 {
2240 int i;
2241 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2242 if (HARD_REGNO_MODE_OK (i, mode)
2243 && in_hard_reg_set_p (reg_class_contents[this_alternative],
2244 mode, i))
2245 break;
2246 if (i == FIRST_PSEUDO_REGISTER)
2247 winreg = false;
2248 }
2249
2250 /* If this operand accepts a register, and if the
2251 register class has at least one allocatable register,
2252 then this operand can be reloaded. */
2253 if (winreg && !no_regs_p)
2254 badop = false;
2255
2256 if (badop)
2257 {
2258 if (lra_dump_file != NULL)
2259 fprintf (lra_dump_file,
2260 " alt=%d: Bad operand -- refuse\n",
2261 nalt);
2262 goto fail;
2263 }
2264
2265 /* If not assigned pseudo has a class which a subset of
2266 required reg class, it is a less costly alternative
2267 as the pseudo still can get a hard reg of necessary
2268 class. */
2269 if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
2270 && (cl = get_reg_class (REGNO (op))) != NO_REGS
2271 && ira_class_subset_p[this_alternative][cl])
2272 {
2273 if (lra_dump_file != NULL)
2274 fprintf
2275 (lra_dump_file,
2276 " %d Super set class reg: reject-=3\n", nop);
2277 reject -= 3;
2278 }
2279
2280 this_alternative_offmemok = offmemok;
2281 if (this_costly_alternative != NO_REGS)
2282 {
2283 if (lra_dump_file != NULL)
2284 fprintf (lra_dump_file,
2285 " %d Costly loser: reject++\n", nop);
2286 reject++;
2287 }
2288 /* If the operand is dying, has a matching constraint,
2289 and satisfies constraints of the matched operand
2290 which failed to satisfy the own constraints, most probably
2291 the reload for this operand will be gone. */
2292 if (this_alternative_matches >= 0
2293 && !curr_alt_win[this_alternative_matches]
2294 && REG_P (op)
2295 && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2296 && (hard_regno[nop] >= 0
2297 ? in_hard_reg_set_p (this_alternative_set,
2298 mode, hard_regno[nop])
2299 : in_class_p (op, this_alternative, NULL)))
2300 {
2301 if (lra_dump_file != NULL)
2302 fprintf
2303 (lra_dump_file,
2304 " %d Dying matched operand reload: reject++\n",
2305 nop);
2306 reject++;
2307 }
2308 else
2309 {
2310 /* Strict_low_part requires to reload the register
2311 not the sub-register. In this case we should
2312 check that a final reload hard reg can hold the
2313 value mode. */
2314 if (curr_static_id->operand[nop].strict_low
2315 && REG_P (op)
2316 && hard_regno[nop] < 0
2317 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2318 && ira_class_hard_regs_num[this_alternative] > 0
2319 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2320 [this_alternative][0],
2321 GET_MODE
2322 (*curr_id->operand_loc[nop])))
2323 {
2324 if (lra_dump_file != NULL)
2325 fprintf
2326 (lra_dump_file,
2327 " alt=%d: Strict low subreg reload -- refuse\n",
2328 nalt);
2329 goto fail;
2330 }
2331 losers++;
2332 }
2333 if (operand_reg[nop] != NULL_RTX
2334 /* Output operands and matched input operands are
2335 not inherited. The following conditions do not
2336 exactly describe the previous statement but they
2337 are pretty close. */
2338 && curr_static_id->operand[nop].type != OP_OUT
2339 && (this_alternative_matches < 0
2340 || curr_static_id->operand[nop].type != OP_IN))
2341 {
2342 int last_reload = (lra_reg_info[ORIGINAL_REGNO
2343 (operand_reg[nop])]
2344 .last_reload);
2345
2346 /* The value of reload_sum has sense only if we
2347 process insns in their order. It happens only on
2348 the first constraints sub-pass when we do most of
2349 reload work. */
2350 if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2351 reload_sum += last_reload - bb_reload_num;
2352 }
2353 /* If this is a constant that is reloaded into the
2354 desired class by copying it to memory first, count
2355 that as another reload. This is consistent with
2356 other code and is required to avoid choosing another
2357 alternative when the constant is moved into memory.
2358 Note that the test here is precisely the same as in
2359 the code below that calls force_const_mem. */
2360 if (CONST_POOL_OK_P (mode, op)
2361 && ((targetm.preferred_reload_class
2362 (op, this_alternative) == NO_REGS)
2363 || no_input_reloads_p))
2364 {
2365 const_to_mem = 1;
2366 if (! no_regs_p)
2367 losers++;
2368 }
2369
2370 /* Alternative loses if it requires a type of reload not
2371 permitted for this insn. We can always reload
2372 objects with a REG_UNUSED note. */
2373 if ((curr_static_id->operand[nop].type != OP_IN
2374 && no_output_reloads_p
2375 && ! find_reg_note (curr_insn, REG_UNUSED, op))
2376 || (curr_static_id->operand[nop].type != OP_OUT
2377 && no_input_reloads_p && ! const_to_mem)
2378 || (this_alternative_matches >= 0
2379 && (no_input_reloads_p
2380 || (no_output_reloads_p
2381 && (curr_static_id->operand
2382 [this_alternative_matches].type != OP_IN)
2383 && ! find_reg_note (curr_insn, REG_UNUSED,
2384 no_subreg_reg_operand
2385 [this_alternative_matches])))))
2386 {
2387 if (lra_dump_file != NULL)
2388 fprintf
2389 (lra_dump_file,
2390 " alt=%d: No input/otput reload -- refuse\n",
2391 nalt);
2392 goto fail;
2393 }
2394
2395 /* Alternative loses if it required class pseudo can not
2396 hold value of required mode. Such insns can be
2397 described by insn definitions with mode iterators. */
2398 if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
2399 && ! hard_reg_set_empty_p (this_alternative_set)
2400 /* It is common practice for constraints to use a
2401 class which does not have actually enough regs to
2402 hold the value (e.g. x86 AREG for mode requiring
2403 more one general reg). Therefore we have 2
2404 conditions to check that the reload pseudo can
2405 not hold the mode value. */
2406 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2407 [this_alternative][0],
2408 GET_MODE (*curr_id->operand_loc[nop]))
2409 /* The above condition is not enough as the first
2410 reg in ira_class_hard_regs can be not aligned for
2411 multi-words mode values. */
2412 && (prohibited_class_reg_set_mode_p
2413 (this_alternative, this_alternative_set,
2414 GET_MODE (*curr_id->operand_loc[nop]))))
2415 {
2416 if (lra_dump_file != NULL)
2417 fprintf (lra_dump_file,
2418 " alt=%d: reload pseudo for op %d "
2419 " can not hold the mode value -- refuse\n",
2420 nalt, nop);
2421 goto fail;
2422 }
2423
2424 /* Check strong discouragement of reload of non-constant
2425 into class THIS_ALTERNATIVE. */
2426 if (! CONSTANT_P (op) && ! no_regs_p
2427 && (targetm.preferred_reload_class
2428 (op, this_alternative) == NO_REGS
2429 || (curr_static_id->operand[nop].type == OP_OUT
2430 && (targetm.preferred_output_reload_class
2431 (op, this_alternative) == NO_REGS))))
2432 {
2433 if (lra_dump_file != NULL)
2434 fprintf (lra_dump_file,
2435 " %d Non-prefered reload: reject+=%d\n",
2436 nop, LRA_MAX_REJECT);
2437 reject += LRA_MAX_REJECT;
2438 }
2439
2440 if (! (MEM_P (op) && offmemok)
2441 && ! (const_to_mem && constmemok))
2442 {
2443 /* We prefer to reload pseudos over reloading other
2444 things, since such reloads may be able to be
2445 eliminated later. So bump REJECT in other cases.
2446 Don't do this in the case where we are forcing a
2447 constant into memory and it will then win since
2448 we don't want to have a different alternative
2449 match then. */
2450 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2451 {
2452 if (lra_dump_file != NULL)
2453 fprintf
2454 (lra_dump_file,
2455 " %d Non-pseudo reload: reject+=2\n",
2456 nop);
2457 reject += 2;
2458 }
2459
2460 if (! no_regs_p)
2461 reload_nregs
2462 += ira_reg_class_max_nregs[this_alternative][mode];
2463
2464 if (SMALL_REGISTER_CLASS_P (this_alternative))
2465 {
2466 if (lra_dump_file != NULL)
2467 fprintf
2468 (lra_dump_file,
2469 " %d Small class reload: reject+=%d\n",
2470 nop, LRA_LOSER_COST_FACTOR / 2);
2471 reject += LRA_LOSER_COST_FACTOR / 2;
2472 }
2473 }
2474
2475 /* We are trying to spill pseudo into memory. It is
2476 usually more costly than moving to a hard register
2477 although it might takes the same number of
2478 reloads. */
2479 if (no_regs_p && REG_P (op) && hard_regno[nop] >= 0)
2480 {
2481 if (lra_dump_file != NULL)
2482 fprintf
2483 (lra_dump_file,
2484 " %d Spill pseudo into memory: reject+=3\n",
2485 nop);
2486 reject += 3;
2487 if (VECTOR_MODE_P (mode))
2488 {
2489 /* Spilling vectors into memory is usually more
2490 costly as they contain big values. */
2491 if (lra_dump_file != NULL)
2492 fprintf
2493 (lra_dump_file,
2494 " %d Spill vector pseudo: reject+=2\n",
2495 nop);
2496 reject += 2;
2497 }
2498 }
2499
2500 #ifdef SECONDARY_MEMORY_NEEDED
2501 /* If reload requires moving value through secondary
2502 memory, it will need one more insn at least. */
2503 if (this_alternative != NO_REGS
2504 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
2505 && ((curr_static_id->operand[nop].type != OP_OUT
2506 && SECONDARY_MEMORY_NEEDED (cl, this_alternative,
2507 GET_MODE (op)))
2508 || (curr_static_id->operand[nop].type != OP_IN
2509 && SECONDARY_MEMORY_NEEDED (this_alternative, cl,
2510 GET_MODE (op)))))
2511 losers++;
2512 #endif
2513 /* Input reloads can be inherited more often than output
2514 reloads can be removed, so penalize output
2515 reloads. */
2516 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
2517 {
2518 if (lra_dump_file != NULL)
2519 fprintf
2520 (lra_dump_file,
2521 " %d Non input pseudo reload: reject++\n",
2522 nop);
2523 reject++;
2524 }
2525 }
2526
2527 if (early_clobber_p && ! scratch_p)
2528 {
2529 if (lra_dump_file != NULL)
2530 fprintf (lra_dump_file,
2531 " %d Early clobber: reject++\n", nop);
2532 reject++;
2533 }
2534 /* ??? We check early clobbers after processing all operands
2535 (see loop below) and there we update the costs more.
2536 Should we update the cost (may be approximately) here
2537 because of early clobber register reloads or it is a rare
2538 or non-important thing to be worth to do it. */
2539 overall = losers * LRA_LOSER_COST_FACTOR + reject;
2540 if ((best_losers == 0 || losers != 0) && best_overall < overall)
2541 {
2542 if (lra_dump_file != NULL)
2543 fprintf (lra_dump_file,
2544 " alt=%d,overall=%d,losers=%d -- refuse\n",
2545 nalt, overall, losers);
2546 goto fail;
2547 }
2548
2549 curr_alt[nop] = this_alternative;
2550 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set);
2551 curr_alt_win[nop] = this_alternative_win;
2552 curr_alt_match_win[nop] = this_alternative_match_win;
2553 curr_alt_offmemok[nop] = this_alternative_offmemok;
2554 curr_alt_matches[nop] = this_alternative_matches;
2555
2556 if (this_alternative_matches >= 0
2557 && !did_match && !this_alternative_win)
2558 curr_alt_win[this_alternative_matches] = false;
2559
2560 if (early_clobber_p && operand_reg[nop] != NULL_RTX)
2561 early_clobbered_nops[early_clobbered_regs_num++] = nop;
2562 }
2563 if (curr_insn_set != NULL_RTX && n_operands == 2
2564 /* Prevent processing non-move insns. */
2565 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
2566 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
2567 && ((! curr_alt_win[0] && ! curr_alt_win[1]
2568 && REG_P (no_subreg_reg_operand[0])
2569 && REG_P (no_subreg_reg_operand[1])
2570 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2571 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
2572 || (! curr_alt_win[0] && curr_alt_win[1]
2573 && REG_P (no_subreg_reg_operand[1])
2574 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
2575 || (curr_alt_win[0] && ! curr_alt_win[1]
2576 && REG_P (no_subreg_reg_operand[0])
2577 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2578 && (! CONST_POOL_OK_P (curr_operand_mode[1],
2579 no_subreg_reg_operand[1])
2580 || (targetm.preferred_reload_class
2581 (no_subreg_reg_operand[1],
2582 (enum reg_class) curr_alt[1]) != NO_REGS))
2583 /* If it is a result of recent elimination in move
2584 insn we can transform it into an add still by
2585 using this alternative. */
2586 && GET_CODE (no_subreg_reg_operand[1]) != PLUS)))
2587 {
2588 /* We have a move insn and a new reload insn will be similar
2589 to the current insn. We should avoid such situation as it
2590 results in LRA cycling. */
2591 overall += LRA_MAX_REJECT;
2592 }
2593 ok_p = true;
2594 curr_alt_dont_inherit_ops_num = 0;
2595 for (nop = 0; nop < early_clobbered_regs_num; nop++)
2596 {
2597 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
2598 HARD_REG_SET temp_set;
2599
2600 i = early_clobbered_nops[nop];
2601 if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
2602 || hard_regno[i] < 0)
2603 continue;
2604 lra_assert (operand_reg[i] != NULL_RTX);
2605 clobbered_hard_regno = hard_regno[i];
2606 CLEAR_HARD_REG_SET (temp_set);
2607 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
2608 first_conflict_j = last_conflict_j = -1;
2609 for (j = 0; j < n_operands; j++)
2610 if (j == i
2611 /* We don't want process insides of match_operator and
2612 match_parallel because otherwise we would process
2613 their operands once again generating a wrong
2614 code. */
2615 || curr_static_id->operand[j].is_operator)
2616 continue;
2617 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
2618 || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
2619 continue;
2620 /* If we don't reload j-th operand, check conflicts. */
2621 else if ((curr_alt_win[j] || curr_alt_match_win[j])
2622 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
2623 {
2624 if (first_conflict_j < 0)
2625 first_conflict_j = j;
2626 last_conflict_j = j;
2627 }
2628 if (last_conflict_j < 0)
2629 continue;
2630 /* If earlyclobber operand conflicts with another
2631 non-matching operand which is actually the same register
2632 as the earlyclobber operand, it is better to reload the
2633 another operand as an operand matching the earlyclobber
2634 operand can be also the same. */
2635 if (first_conflict_j == last_conflict_j
2636 && operand_reg[last_conflict_j] != NULL_RTX
2637 && ! curr_alt_match_win[last_conflict_j]
2638 && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j]))
2639 {
2640 curr_alt_win[last_conflict_j] = false;
2641 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
2642 = last_conflict_j;
2643 losers++;
2644 /* Early clobber was already reflected in REJECT. */
2645 lra_assert (reject > 0);
2646 if (lra_dump_file != NULL)
2647 fprintf
2648 (lra_dump_file,
2649 " %d Conflict early clobber reload: reject--\n",
2650 i);
2651 reject--;
2652 overall += LRA_LOSER_COST_FACTOR - 1;
2653 }
2654 else
2655 {
2656 /* We need to reload early clobbered register and the
2657 matched registers. */
2658 for (j = 0; j < n_operands; j++)
2659 if (curr_alt_matches[j] == i)
2660 {
2661 curr_alt_match_win[j] = false;
2662 losers++;
2663 overall += LRA_LOSER_COST_FACTOR;
2664 }
2665 if (! curr_alt_match_win[i])
2666 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
2667 else
2668 {
2669 /* Remember pseudos used for match reloads are never
2670 inherited. */
2671 lra_assert (curr_alt_matches[i] >= 0);
2672 curr_alt_win[curr_alt_matches[i]] = false;
2673 }
2674 curr_alt_win[i] = curr_alt_match_win[i] = false;
2675 losers++;
2676 /* Early clobber was already reflected in REJECT. */
2677 lra_assert (reject > 0);
2678 if (lra_dump_file != NULL)
2679 fprintf
2680 (lra_dump_file,
2681 " %d Matched conflict early clobber reloads:"
2682 "reject--\n",
2683 i);
2684 reject--;
2685 overall += LRA_LOSER_COST_FACTOR - 1;
2686 }
2687 }
2688 if (lra_dump_file != NULL)
2689 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2690 nalt, overall, losers, reload_nregs);
2691
2692 /* If this alternative can be made to work by reloading, and it
2693 needs less reloading than the others checked so far, record
2694 it as the chosen goal for reloading. */
2695 if ((best_losers != 0 && losers == 0)
2696 || (((best_losers == 0 && losers == 0)
2697 || (best_losers != 0 && losers != 0))
2698 && (best_overall > overall
2699 || (best_overall == overall
2700 /* If the cost of the reloads is the same,
2701 prefer alternative which requires minimal
2702 number of reload regs. */
2703 && (reload_nregs < best_reload_nregs
2704 || (reload_nregs == best_reload_nregs
2705 && (best_reload_sum < reload_sum
2706 || (best_reload_sum == reload_sum
2707 && nalt < goal_alt_number))))))))
2708 {
2709 for (nop = 0; nop < n_operands; nop++)
2710 {
2711 goal_alt_win[nop] = curr_alt_win[nop];
2712 goal_alt_match_win[nop] = curr_alt_match_win[nop];
2713 goal_alt_matches[nop] = curr_alt_matches[nop];
2714 goal_alt[nop] = curr_alt[nop];
2715 goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
2716 }
2717 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
2718 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
2719 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
2720 goal_alt_swapped = curr_swapped;
2721 best_overall = overall;
2722 best_losers = losers;
2723 best_reload_nregs = reload_nregs;
2724 best_reload_sum = reload_sum;
2725 goal_alt_number = nalt;
2726 }
2727 if (losers == 0)
2728 /* Everything is satisfied. Do not process alternatives
2729 anymore. */
2730 break;
2731 fail:
2732 ;
2733 }
2734 return ok_p;
2735 }
2736
2737 /* Make reload base reg from address AD. */
2738 static rtx
base_to_reg(struct address_info * ad)2739 base_to_reg (struct address_info *ad)
2740 {
2741 enum reg_class cl;
2742 int code = -1;
2743 rtx new_inner = NULL_RTX;
2744 rtx new_reg = NULL_RTX;
2745 rtx_insn *insn;
2746 rtx_insn *last_insn = get_last_insn();
2747
2748 lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term);
2749 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
2750 get_index_code (ad));
2751 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
2752 cl, "base");
2753 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
2754 ad->disp_term == NULL
2755 ? gen_int_mode (0, ad->mode)
2756 : *ad->disp_term);
2757 if (!valid_address_p (ad->mode, new_inner, ad->as))
2758 return NULL_RTX;
2759 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base_term));
2760 code = recog_memoized (insn);
2761 if (code < 0)
2762 {
2763 delete_insns_since (last_insn);
2764 return NULL_RTX;
2765 }
2766
2767 return new_inner;
2768 }
2769
2770 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2771 static rtx
base_plus_disp_to_reg(struct address_info * ad)2772 base_plus_disp_to_reg (struct address_info *ad)
2773 {
2774 enum reg_class cl;
2775 rtx new_reg;
2776
2777 lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term);
2778 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
2779 get_index_code (ad));
2780 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
2781 cl, "base + disp");
2782 lra_emit_add (new_reg, *ad->base_term, *ad->disp_term);
2783 return new_reg;
2784 }
2785
2786 /* Make reload of index part of address AD. Return the new
2787 pseudo. */
2788 static rtx
index_part_to_reg(struct address_info * ad)2789 index_part_to_reg (struct address_info *ad)
2790 {
2791 rtx new_reg;
2792
2793 new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
2794 INDEX_REG_CLASS, "index term");
2795 expand_mult (GET_MODE (*ad->index), *ad->index_term,
2796 GEN_INT (get_index_scale (ad)), new_reg, 1);
2797 return new_reg;
2798 }
2799
2800 /* Return true if we can add a displacement to address AD, even if that
2801 makes the address invalid. The fix-up code requires any new address
2802 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2803 static bool
can_add_disp_p(struct address_info * ad)2804 can_add_disp_p (struct address_info *ad)
2805 {
2806 return (!ad->autoinc_p
2807 && ad->segment == NULL
2808 && ad->base == ad->base_term
2809 && ad->disp == ad->disp_term);
2810 }
2811
2812 /* Make equiv substitution in address AD. Return true if a substitution
2813 was made. */
2814 static bool
equiv_address_substitution(struct address_info * ad)2815 equiv_address_substitution (struct address_info *ad)
2816 {
2817 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
2818 HOST_WIDE_INT disp, scale;
2819 bool change_p;
2820
2821 base_term = strip_subreg (ad->base_term);
2822 if (base_term == NULL)
2823 base_reg = new_base_reg = NULL_RTX;
2824 else
2825 {
2826 base_reg = *base_term;
2827 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
2828 }
2829 index_term = strip_subreg (ad->index_term);
2830 if (index_term == NULL)
2831 index_reg = new_index_reg = NULL_RTX;
2832 else
2833 {
2834 index_reg = *index_term;
2835 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
2836 }
2837 if (base_reg == new_base_reg && index_reg == new_index_reg)
2838 return false;
2839 disp = 0;
2840 change_p = false;
2841 if (lra_dump_file != NULL)
2842 {
2843 fprintf (lra_dump_file, "Changing address in insn %d ",
2844 INSN_UID (curr_insn));
2845 dump_value_slim (lra_dump_file, *ad->outer, 1);
2846 }
2847 if (base_reg != new_base_reg)
2848 {
2849 if (REG_P (new_base_reg))
2850 {
2851 *base_term = new_base_reg;
2852 change_p = true;
2853 }
2854 else if (GET_CODE (new_base_reg) == PLUS
2855 && REG_P (XEXP (new_base_reg, 0))
2856 && CONST_INT_P (XEXP (new_base_reg, 1))
2857 && can_add_disp_p (ad))
2858 {
2859 disp += INTVAL (XEXP (new_base_reg, 1));
2860 *base_term = XEXP (new_base_reg, 0);
2861 change_p = true;
2862 }
2863 if (ad->base_term2 != NULL)
2864 *ad->base_term2 = *ad->base_term;
2865 }
2866 if (index_reg != new_index_reg)
2867 {
2868 if (REG_P (new_index_reg))
2869 {
2870 *index_term = new_index_reg;
2871 change_p = true;
2872 }
2873 else if (GET_CODE (new_index_reg) == PLUS
2874 && REG_P (XEXP (new_index_reg, 0))
2875 && CONST_INT_P (XEXP (new_index_reg, 1))
2876 && can_add_disp_p (ad)
2877 && (scale = get_index_scale (ad)))
2878 {
2879 disp += INTVAL (XEXP (new_index_reg, 1)) * scale;
2880 *index_term = XEXP (new_index_reg, 0);
2881 change_p = true;
2882 }
2883 }
2884 if (disp != 0)
2885 {
2886 if (ad->disp != NULL)
2887 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
2888 else
2889 {
2890 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
2891 update_address (ad);
2892 }
2893 change_p = true;
2894 }
2895 if (lra_dump_file != NULL)
2896 {
2897 if (! change_p)
2898 fprintf (lra_dump_file, " -- no change\n");
2899 else
2900 {
2901 fprintf (lra_dump_file, " on equiv ");
2902 dump_value_slim (lra_dump_file, *ad->outer, 1);
2903 fprintf (lra_dump_file, "\n");
2904 }
2905 }
2906 return change_p;
2907 }
2908
2909 /* Major function to make reloads for an address in operand NOP or
2910 check its correctness (If CHECK_ONLY_P is true). The supported
2911 cases are:
2912
2913 1) an address that existed before LRA started, at which point it
2914 must have been valid. These addresses are subject to elimination
2915 and may have become invalid due to the elimination offset being out
2916 of range.
2917
2918 2) an address created by forcing a constant to memory
2919 (force_const_to_mem). The initial form of these addresses might
2920 not be valid, and it is this function's job to make them valid.
2921
2922 3) a frame address formed from a register and a (possibly zero)
2923 constant offset. As above, these addresses might not be valid and
2924 this function must make them so.
2925
2926 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2927 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2928 address. Return true for any RTL change.
2929
2930 The function is a helper function which does not produce all
2931 transformations (when CHECK_ONLY_P is false) which can be
2932 necessary. It does just basic steps. To do all necessary
2933 transformations use function process_address. */
2934 static bool
process_address_1(int nop,bool check_only_p,rtx_insn ** before,rtx_insn ** after)2935 process_address_1 (int nop, bool check_only_p,
2936 rtx_insn **before, rtx_insn **after)
2937 {
2938 struct address_info ad;
2939 rtx new_reg;
2940 HOST_WIDE_INT scale;
2941 rtx op = *curr_id->operand_loc[nop];
2942 const char *constraint = curr_static_id->operand[nop].constraint;
2943 enum constraint_num cn = lookup_constraint (constraint);
2944 bool change_p = false;
2945
2946 if (MEM_P (op)
2947 && GET_MODE (op) == BLKmode
2948 && GET_CODE (XEXP (op, 0)) == SCRATCH)
2949 return false;
2950
2951 if (insn_extra_address_constraint (cn))
2952 decompose_lea_address (&ad, curr_id->operand_loc[nop]);
2953 else if (MEM_P (op))
2954 decompose_mem_address (&ad, op);
2955 else if (GET_CODE (op) == SUBREG
2956 && MEM_P (SUBREG_REG (op)))
2957 decompose_mem_address (&ad, SUBREG_REG (op));
2958 else
2959 return false;
2960 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
2961 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
2962 when INDEX_REG_CLASS is a single register class. */
2963 if (ad.base_term != NULL
2964 && ad.index_term != NULL
2965 && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1
2966 && REG_P (*ad.base_term)
2967 && REG_P (*ad.index_term)
2968 && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL)
2969 && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL))
2970 {
2971 std::swap (ad.base, ad.index);
2972 std::swap (ad.base_term, ad.index_term);
2973 }
2974 if (! check_only_p)
2975 change_p = equiv_address_substitution (&ad);
2976 if (ad.base_term != NULL
2977 && (process_addr_reg
2978 (ad.base_term, check_only_p, before,
2979 (ad.autoinc_p
2980 && !(REG_P (*ad.base_term)
2981 && find_regno_note (curr_insn, REG_DEAD,
2982 REGNO (*ad.base_term)) != NULL_RTX)
2983 ? after : NULL),
2984 base_reg_class (ad.mode, ad.as, ad.base_outer_code,
2985 get_index_code (&ad)))))
2986 {
2987 change_p = true;
2988 if (ad.base_term2 != NULL)
2989 *ad.base_term2 = *ad.base_term;
2990 }
2991 if (ad.index_term != NULL
2992 && process_addr_reg (ad.index_term, check_only_p,
2993 before, NULL, INDEX_REG_CLASS))
2994 change_p = true;
2995
2996 /* Target hooks sometimes don't treat extra-constraint addresses as
2997 legitimate address_operands, so handle them specially. */
2998 if (insn_extra_address_constraint (cn)
2999 && satisfies_address_constraint_p (&ad, cn))
3000 return change_p;
3001
3002 if (check_only_p)
3003 return change_p;
3004
3005 /* There are three cases where the shape of *AD.INNER may now be invalid:
3006
3007 1) the original address was valid, but either elimination or
3008 equiv_address_substitution was applied and that made
3009 the address invalid.
3010
3011 2) the address is an invalid symbolic address created by
3012 force_const_to_mem.
3013
3014 3) the address is a frame address with an invalid offset.
3015
3016 4) the address is a frame address with an invalid base.
3017
3018 All these cases involve a non-autoinc address, so there is no
3019 point revalidating other types. */
3020 if (ad.autoinc_p || valid_address_p (&ad))
3021 return change_p;
3022
3023 /* Any index existed before LRA started, so we can assume that the
3024 presence and shape of the index is valid. */
3025 push_to_sequence (*before);
3026 lra_assert (ad.disp == ad.disp_term);
3027 if (ad.base == NULL)
3028 {
3029 if (ad.index == NULL)
3030 {
3031 rtx_insn *insn;
3032 rtx_insn *last = get_last_insn ();
3033 int code = -1;
3034 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3035 SCRATCH, SCRATCH);
3036 rtx addr = *ad.inner;
3037
3038 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3039 if (HAVE_lo_sum)
3040 {
3041 /* addr => lo_sum (new_base, addr), case (2) above. */
3042 insn = emit_insn (gen_rtx_SET
3043 (new_reg,
3044 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
3045 code = recog_memoized (insn);
3046 if (code >= 0)
3047 {
3048 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
3049 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3050 {
3051 /* Try to put lo_sum into register. */
3052 insn = emit_insn (gen_rtx_SET
3053 (new_reg,
3054 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
3055 code = recog_memoized (insn);
3056 if (code >= 0)
3057 {
3058 *ad.inner = new_reg;
3059 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3060 {
3061 *ad.inner = addr;
3062 code = -1;
3063 }
3064 }
3065
3066 }
3067 }
3068 if (code < 0)
3069 delete_insns_since (last);
3070 }
3071
3072 if (code < 0)
3073 {
3074 /* addr => new_base, case (2) above. */
3075 lra_emit_move (new_reg, addr);
3076
3077 for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last);
3078 insn != NULL_RTX;
3079 insn = NEXT_INSN (insn))
3080 if (recog_memoized (insn) < 0)
3081 break;
3082 if (insn != NULL_RTX)
3083 {
3084 /* Do nothing if we cannot generate right insns.
3085 This is analogous to reload pass behavior. */
3086 delete_insns_since (last);
3087 end_sequence ();
3088 return false;
3089 }
3090 *ad.inner = new_reg;
3091 }
3092 }
3093 else
3094 {
3095 /* index * scale + disp => new base + index * scale,
3096 case (1) above. */
3097 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3098 GET_CODE (*ad.index));
3099
3100 lra_assert (INDEX_REG_CLASS != NO_REGS);
3101 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
3102 lra_emit_move (new_reg, *ad.disp);
3103 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3104 new_reg, *ad.index);
3105 }
3106 }
3107 else if (ad.index == NULL)
3108 {
3109 int regno;
3110 enum reg_class cl;
3111 rtx set;
3112 rtx_insn *insns, *last_insn;
3113 /* Try to reload base into register only if the base is invalid
3114 for the address but with valid offset, case (4) above. */
3115 start_sequence ();
3116 new_reg = base_to_reg (&ad);
3117
3118 /* base + disp => new base, cases (1) and (3) above. */
3119 /* Another option would be to reload the displacement into an
3120 index register. However, postreload has code to optimize
3121 address reloads that have the same base and different
3122 displacements, so reloading into an index register would
3123 not necessarily be a win. */
3124 if (new_reg == NULL_RTX)
3125 new_reg = base_plus_disp_to_reg (&ad);
3126 insns = get_insns ();
3127 last_insn = get_last_insn ();
3128 /* If we generated at least two insns, try last insn source as
3129 an address. If we succeed, we generate one less insn. */
3130 if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX
3131 && GET_CODE (SET_SRC (set)) == PLUS
3132 && REG_P (XEXP (SET_SRC (set), 0))
3133 && CONSTANT_P (XEXP (SET_SRC (set), 1)))
3134 {
3135 *ad.inner = SET_SRC (set);
3136 if (valid_address_p (ad.mode, *ad.outer, ad.as))
3137 {
3138 *ad.base_term = XEXP (SET_SRC (set), 0);
3139 *ad.disp_term = XEXP (SET_SRC (set), 1);
3140 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3141 get_index_code (&ad));
3142 regno = REGNO (*ad.base_term);
3143 if (regno >= FIRST_PSEUDO_REGISTER
3144 && cl != lra_get_allocno_class (regno))
3145 lra_change_class (regno, cl, " Change to", true);
3146 new_reg = SET_SRC (set);
3147 delete_insns_since (PREV_INSN (last_insn));
3148 }
3149 }
3150 /* Try if target can split displacement into legitimite new disp
3151 and offset. If it's the case, we replace the last insn with
3152 insns for base + offset => new_reg and set new_reg + new disp
3153 to *ad.inner. */
3154 last_insn = get_last_insn ();
3155 if ((set = single_set (last_insn)) != NULL_RTX
3156 && GET_CODE (SET_SRC (set)) == PLUS
3157 && REG_P (XEXP (SET_SRC (set), 0))
3158 && REGNO (XEXP (SET_SRC (set), 0)) < FIRST_PSEUDO_REGISTER
3159 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
3160 {
3161 rtx addend, disp = XEXP (SET_SRC (set), 1);
3162 if (targetm.legitimize_address_displacement (&disp, &addend,
3163 ad.mode))
3164 {
3165 rtx_insn *new_insns;
3166 start_sequence ();
3167 lra_emit_add (new_reg, XEXP (SET_SRC (set), 0), addend);
3168 new_insns = get_insns ();
3169 end_sequence ();
3170 new_reg = gen_rtx_PLUS (Pmode, new_reg, disp);
3171 delete_insns_since (PREV_INSN (last_insn));
3172 add_insn (new_insns);
3173 insns = get_insns ();
3174 }
3175 }
3176 end_sequence ();
3177 emit_insn (insns);
3178 *ad.inner = new_reg;
3179 }
3180 else if (ad.disp_term != NULL)
3181 {
3182 /* base + scale * index + disp => new base + scale * index,
3183 case (1) above. */
3184 new_reg = base_plus_disp_to_reg (&ad);
3185 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3186 new_reg, *ad.index);
3187 }
3188 else if ((scale = get_index_scale (&ad)) == 1)
3189 {
3190 /* The last transformation to one reg will be made in
3191 curr_insn_transform function. */
3192 end_sequence ();
3193 return false;
3194 }
3195 else if (scale != 0)
3196 {
3197 /* base + scale * index => base + new_reg,
3198 case (1) above.
3199 Index part of address may become invalid. For example, we
3200 changed pseudo on the equivalent memory and a subreg of the
3201 pseudo onto the memory of different mode for which the scale is
3202 prohibitted. */
3203 new_reg = index_part_to_reg (&ad);
3204 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3205 *ad.base_term, new_reg);
3206 }
3207 else
3208 {
3209 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3210 SCRATCH, SCRATCH);
3211 rtx addr = *ad.inner;
3212
3213 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3214 /* addr => new_base. */
3215 lra_emit_move (new_reg, addr);
3216 *ad.inner = new_reg;
3217 }
3218 *before = get_insns ();
3219 end_sequence ();
3220 return true;
3221 }
3222
3223 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3224 Use process_address_1 as a helper function. Return true for any
3225 RTL changes.
3226
3227 If CHECK_ONLY_P is true, just check address correctness. Return
3228 false if the address correct. */
3229 static bool
process_address(int nop,bool check_only_p,rtx_insn ** before,rtx_insn ** after)3230 process_address (int nop, bool check_only_p,
3231 rtx_insn **before, rtx_insn **after)
3232 {
3233 bool res = false;
3234
3235 while (process_address_1 (nop, check_only_p, before, after))
3236 {
3237 if (check_only_p)
3238 return true;
3239 res = true;
3240 }
3241 return res;
3242 }
3243
3244 /* Emit insns to reload VALUE into a new register. VALUE is an
3245 auto-increment or auto-decrement RTX whose operand is a register or
3246 memory location; so reloading involves incrementing that location.
3247 IN is either identical to VALUE, or some cheaper place to reload
3248 value being incremented/decremented from.
3249
3250 INC_AMOUNT is the number to increment or decrement by (always
3251 positive and ignored for POST_MODIFY/PRE_MODIFY).
3252
3253 Return pseudo containing the result. */
3254 static rtx
emit_inc(enum reg_class new_rclass,rtx in,rtx value,int inc_amount)3255 emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount)
3256 {
3257 /* REG or MEM to be copied and incremented. */
3258 rtx incloc = XEXP (value, 0);
3259 /* Nonzero if increment after copying. */
3260 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
3261 || GET_CODE (value) == POST_MODIFY);
3262 rtx_insn *last;
3263 rtx inc;
3264 rtx_insn *add_insn;
3265 int code;
3266 rtx real_in = in == value ? incloc : in;
3267 rtx result;
3268 bool plus_p = true;
3269
3270 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
3271 {
3272 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS
3273 || GET_CODE (XEXP (value, 1)) == MINUS);
3274 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)));
3275 plus_p = GET_CODE (XEXP (value, 1)) == PLUS;
3276 inc = XEXP (XEXP (value, 1), 1);
3277 }
3278 else
3279 {
3280 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
3281 inc_amount = -inc_amount;
3282
3283 inc = GEN_INT (inc_amount);
3284 }
3285
3286 if (! post && REG_P (incloc))
3287 result = incloc;
3288 else
3289 result = lra_create_new_reg (GET_MODE (value), value, new_rclass,
3290 "INC/DEC result");
3291
3292 if (real_in != result)
3293 {
3294 /* First copy the location to the result register. */
3295 lra_assert (REG_P (result));
3296 emit_insn (gen_move_insn (result, real_in));
3297 }
3298
3299 /* We suppose that there are insns to add/sub with the constant
3300 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3301 old reload worked with this assumption. If the assumption
3302 becomes wrong, we should use approach in function
3303 base_plus_disp_to_reg. */
3304 if (in == value)
3305 {
3306 /* See if we can directly increment INCLOC. */
3307 last = get_last_insn ();
3308 add_insn = emit_insn (plus_p
3309 ? gen_add2_insn (incloc, inc)
3310 : gen_sub2_insn (incloc, inc));
3311
3312 code = recog_memoized (add_insn);
3313 if (code >= 0)
3314 {
3315 if (! post && result != incloc)
3316 emit_insn (gen_move_insn (result, incloc));
3317 return result;
3318 }
3319 delete_insns_since (last);
3320 }
3321
3322 /* If couldn't do the increment directly, must increment in RESULT.
3323 The way we do this depends on whether this is pre- or
3324 post-increment. For pre-increment, copy INCLOC to the reload
3325 register, increment it there, then save back. */
3326 if (! post)
3327 {
3328 if (real_in != result)
3329 emit_insn (gen_move_insn (result, real_in));
3330 if (plus_p)
3331 emit_insn (gen_add2_insn (result, inc));
3332 else
3333 emit_insn (gen_sub2_insn (result, inc));
3334 if (result != incloc)
3335 emit_insn (gen_move_insn (incloc, result));
3336 }
3337 else
3338 {
3339 /* Post-increment.
3340
3341 Because this might be a jump insn or a compare, and because
3342 RESULT may not be available after the insn in an input
3343 reload, we must do the incrementing before the insn being
3344 reloaded for.
3345
3346 We have already copied IN to RESULT. Increment the copy in
3347 RESULT, save that back, then decrement RESULT so it has
3348 the original value. */
3349 if (plus_p)
3350 emit_insn (gen_add2_insn (result, inc));
3351 else
3352 emit_insn (gen_sub2_insn (result, inc));
3353 emit_insn (gen_move_insn (incloc, result));
3354 /* Restore non-modified value for the result. We prefer this
3355 way because it does not require an additional hard
3356 register. */
3357 if (plus_p)
3358 {
3359 if (CONST_INT_P (inc))
3360 emit_insn (gen_add2_insn (result,
3361 gen_int_mode (-INTVAL (inc),
3362 GET_MODE (result))));
3363 else
3364 emit_insn (gen_sub2_insn (result, inc));
3365 }
3366 else
3367 emit_insn (gen_add2_insn (result, inc));
3368 }
3369 return result;
3370 }
3371
3372 /* Return true if the current move insn does not need processing as we
3373 already know that it satisfies its constraints. */
3374 static bool
simple_move_p(void)3375 simple_move_p (void)
3376 {
3377 rtx dest, src;
3378 enum reg_class dclass, sclass;
3379
3380 lra_assert (curr_insn_set != NULL_RTX);
3381 dest = SET_DEST (curr_insn_set);
3382 src = SET_SRC (curr_insn_set);
3383
3384 /* If the instruction has multiple sets we need to process it even if it
3385 is single_set. This can happen if one or more of the SETs are dead.
3386 See PR73650. */
3387 if (multiple_sets (curr_insn))
3388 return false;
3389
3390 return ((dclass = get_op_class (dest)) != NO_REGS
3391 && (sclass = get_op_class (src)) != NO_REGS
3392 /* The backend guarantees that register moves of cost 2
3393 never need reloads. */
3394 && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2);
3395 }
3396
3397 /* Swap operands NOP and NOP + 1. */
3398 static inline void
swap_operands(int nop)3399 swap_operands (int nop)
3400 {
3401 std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]);
3402 std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]);
3403 std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]);
3404 /* Swap the duplicates too. */
3405 lra_update_dup (curr_id, nop);
3406 lra_update_dup (curr_id, nop + 1);
3407 }
3408
3409 /* Main entry point of the constraint code: search the body of the
3410 current insn to choose the best alternative. It is mimicking insn
3411 alternative cost calculation model of former reload pass. That is
3412 because machine descriptions were written to use this model. This
3413 model can be changed in future. Make commutative operand exchange
3414 if it is chosen.
3415
3416 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3417 constraints. Return true if any change happened during function
3418 call.
3419
3420 If CHECK_ONLY_P is true then don't do any transformation. Just
3421 check that the insn satisfies all constraints. If the insn does
3422 not satisfy any constraint, return true. */
3423 static bool
curr_insn_transform(bool check_only_p)3424 curr_insn_transform (bool check_only_p)
3425 {
3426 int i, j, k;
3427 int n_operands;
3428 int n_alternatives;
3429 int n_outputs;
3430 int commutative;
3431 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
3432 signed char match_inputs[MAX_RECOG_OPERANDS + 1];
3433 signed char outputs[MAX_RECOG_OPERANDS + 1];
3434 rtx_insn *before, *after;
3435 bool alt_p = false;
3436 /* Flag that the insn has been changed through a transformation. */
3437 bool change_p;
3438 bool sec_mem_p;
3439 #ifdef SECONDARY_MEMORY_NEEDED
3440 bool use_sec_mem_p;
3441 #endif
3442 int max_regno_before;
3443 int reused_alternative_num;
3444
3445 curr_insn_set = single_set (curr_insn);
3446 if (curr_insn_set != NULL_RTX && simple_move_p ())
3447 return false;
3448
3449 no_input_reloads_p = no_output_reloads_p = false;
3450 goal_alt_number = -1;
3451 change_p = sec_mem_p = false;
3452 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3453 reloads; neither are insns that SET cc0. Insns that use CC0 are
3454 not allowed to have any input reloads. */
3455 if (JUMP_P (curr_insn) || CALL_P (curr_insn))
3456 no_output_reloads_p = true;
3457
3458 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn)))
3459 no_input_reloads_p = true;
3460 if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn)))
3461 no_output_reloads_p = true;
3462
3463 n_operands = curr_static_id->n_operands;
3464 n_alternatives = curr_static_id->n_alternatives;
3465
3466 /* Just return "no reloads" if insn has no operands with
3467 constraints. */
3468 if (n_operands == 0 || n_alternatives == 0)
3469 return false;
3470
3471 max_regno_before = max_reg_num ();
3472
3473 for (i = 0; i < n_operands; i++)
3474 {
3475 goal_alt_matched[i][0] = -1;
3476 goal_alt_matches[i] = -1;
3477 }
3478
3479 commutative = curr_static_id->commutative;
3480
3481 /* Now see what we need for pseudos that didn't get hard regs or got
3482 the wrong kind of hard reg. For this, we must consider all the
3483 operands together against the register constraints. */
3484
3485 best_losers = best_overall = INT_MAX;
3486 best_reload_sum = 0;
3487
3488 curr_swapped = false;
3489 goal_alt_swapped = false;
3490
3491 if (! check_only_p)
3492 /* Make equivalence substitution and memory subreg elimination
3493 before address processing because an address legitimacy can
3494 depend on memory mode. */
3495 for (i = 0; i < n_operands; i++)
3496 {
3497 rtx op, subst, old;
3498 bool op_change_p = false;
3499
3500 if (curr_static_id->operand[i].is_operator)
3501 continue;
3502
3503 old = op = *curr_id->operand_loc[i];
3504 if (GET_CODE (old) == SUBREG)
3505 old = SUBREG_REG (old);
3506 subst = get_equiv_with_elimination (old, curr_insn);
3507 original_subreg_reg_mode[i] = VOIDmode;
3508 if (subst != old)
3509 {
3510 subst = copy_rtx (subst);
3511 lra_assert (REG_P (old));
3512 if (GET_CODE (op) != SUBREG)
3513 *curr_id->operand_loc[i] = subst;
3514 else
3515 {
3516 SUBREG_REG (op) = subst;
3517 if (GET_MODE (subst) == VOIDmode)
3518 original_subreg_reg_mode[i] = GET_MODE (old);
3519 }
3520 if (lra_dump_file != NULL)
3521 {
3522 fprintf (lra_dump_file,
3523 "Changing pseudo %d in operand %i of insn %u on equiv ",
3524 REGNO (old), i, INSN_UID (curr_insn));
3525 dump_value_slim (lra_dump_file, subst, 1);
3526 fprintf (lra_dump_file, "\n");
3527 }
3528 op_change_p = change_p = true;
3529 }
3530 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
3531 {
3532 change_p = true;
3533 lra_update_dup (curr_id, i);
3534 }
3535 }
3536
3537 /* Reload address registers and displacements. We do it before
3538 finding an alternative because of memory constraints. */
3539 before = after = NULL;
3540 for (i = 0; i < n_operands; i++)
3541 if (! curr_static_id->operand[i].is_operator
3542 && process_address (i, check_only_p, &before, &after))
3543 {
3544 if (check_only_p)
3545 return true;
3546 change_p = true;
3547 lra_update_dup (curr_id, i);
3548 }
3549
3550 if (change_p)
3551 /* If we've changed the instruction then any alternative that
3552 we chose previously may no longer be valid. */
3553 lra_set_used_insn_alternative (curr_insn, -1);
3554
3555 if (! check_only_p && curr_insn_set != NULL_RTX
3556 && check_and_process_move (&change_p, &sec_mem_p))
3557 return change_p;
3558
3559 try_swapped:
3560
3561 reused_alternative_num = check_only_p ? -1 : curr_id->used_insn_alternative;
3562 if (lra_dump_file != NULL && reused_alternative_num >= 0)
3563 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
3564 reused_alternative_num, INSN_UID (curr_insn));
3565
3566 if (process_alt_operands (reused_alternative_num))
3567 alt_p = true;
3568
3569 if (check_only_p)
3570 return ! alt_p || best_losers != 0;
3571
3572 /* If insn is commutative (it's safe to exchange a certain pair of
3573 operands) then we need to try each alternative twice, the second
3574 time matching those two operands as if we had exchanged them. To
3575 do this, really exchange them in operands.
3576
3577 If we have just tried the alternatives the second time, return
3578 operands to normal and drop through. */
3579
3580 if (reused_alternative_num < 0 && commutative >= 0)
3581 {
3582 curr_swapped = !curr_swapped;
3583 if (curr_swapped)
3584 {
3585 swap_operands (commutative);
3586 goto try_swapped;
3587 }
3588 else
3589 swap_operands (commutative);
3590 }
3591
3592 if (! alt_p && ! sec_mem_p)
3593 {
3594 /* No alternative works with reloads?? */
3595 if (INSN_CODE (curr_insn) >= 0)
3596 fatal_insn ("unable to generate reloads for:", curr_insn);
3597 error_for_asm (curr_insn,
3598 "inconsistent operand constraints in an %<asm%>");
3599 /* Avoid further trouble with this insn. */
3600 PATTERN (curr_insn) = gen_rtx_USE (VOIDmode, const0_rtx);
3601 lra_invalidate_insn_data (curr_insn);
3602 return true;
3603 }
3604
3605 /* If the best alternative is with operands 1 and 2 swapped, swap
3606 them. Update the operand numbers of any reloads already
3607 pushed. */
3608
3609 if (goal_alt_swapped)
3610 {
3611 if (lra_dump_file != NULL)
3612 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
3613 INSN_UID (curr_insn));
3614
3615 /* Swap the duplicates too. */
3616 swap_operands (commutative);
3617 change_p = true;
3618 }
3619
3620 #ifdef SECONDARY_MEMORY_NEEDED
3621 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3622 too conservatively. So we use the secondary memory only if there
3623 is no any alternative without reloads. */
3624 use_sec_mem_p = false;
3625 if (! alt_p)
3626 use_sec_mem_p = true;
3627 else if (sec_mem_p)
3628 {
3629 for (i = 0; i < n_operands; i++)
3630 if (! goal_alt_win[i] && ! goal_alt_match_win[i])
3631 break;
3632 use_sec_mem_p = i < n_operands;
3633 }
3634
3635 if (use_sec_mem_p)
3636 {
3637 int in = -1, out = -1;
3638 rtx new_reg, src, dest, rld;
3639 machine_mode sec_mode, rld_mode;
3640
3641 lra_assert (curr_insn_set != NULL_RTX && sec_mem_p);
3642 dest = SET_DEST (curr_insn_set);
3643 src = SET_SRC (curr_insn_set);
3644 for (i = 0; i < n_operands; i++)
3645 if (*curr_id->operand_loc[i] == dest)
3646 out = i;
3647 else if (*curr_id->operand_loc[i] == src)
3648 in = i;
3649 for (i = 0; i < curr_static_id->n_dups; i++)
3650 if (out < 0 && *curr_id->dup_loc[i] == dest)
3651 out = curr_static_id->dup_num[i];
3652 else if (in < 0 && *curr_id->dup_loc[i] == src)
3653 in = curr_static_id->dup_num[i];
3654 lra_assert (out >= 0 && in >= 0
3655 && curr_static_id->operand[out].type == OP_OUT
3656 && curr_static_id->operand[in].type == OP_IN);
3657 rld = (GET_MODE_SIZE (GET_MODE (dest)) <= GET_MODE_SIZE (GET_MODE (src))
3658 ? dest : src);
3659 rld_mode = GET_MODE (rld);
3660 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3661 sec_mode = SECONDARY_MEMORY_NEEDED_MODE (rld_mode);
3662 #else
3663 sec_mode = rld_mode;
3664 #endif
3665 new_reg = lra_create_new_reg (sec_mode, NULL_RTX,
3666 NO_REGS, "secondary");
3667 /* If the mode is changed, it should be wider. */
3668 lra_assert (GET_MODE_SIZE (sec_mode) >= GET_MODE_SIZE (rld_mode));
3669 if (sec_mode != rld_mode)
3670 {
3671 /* If the target says specifically to use another mode for
3672 secondary memory moves we can not reuse the original
3673 insn. */
3674 after = emit_spill_move (false, new_reg, dest);
3675 lra_process_new_insns (curr_insn, NULL, after,
3676 "Inserting the sec. move");
3677 /* We may have non null BEFORE here (e.g. after address
3678 processing. */
3679 push_to_sequence (before);
3680 before = emit_spill_move (true, new_reg, src);
3681 emit_insn (before);
3682 before = get_insns ();
3683 end_sequence ();
3684 lra_process_new_insns (curr_insn, before, NULL, "Changing on");
3685 lra_set_insn_deleted (curr_insn);
3686 }
3687 else if (dest == rld)
3688 {
3689 *curr_id->operand_loc[out] = new_reg;
3690 lra_update_dup (curr_id, out);
3691 after = emit_spill_move (false, new_reg, dest);
3692 lra_process_new_insns (curr_insn, NULL, after,
3693 "Inserting the sec. move");
3694 }
3695 else
3696 {
3697 *curr_id->operand_loc[in] = new_reg;
3698 lra_update_dup (curr_id, in);
3699 /* See comments above. */
3700 push_to_sequence (before);
3701 before = emit_spill_move (true, new_reg, src);
3702 emit_insn (before);
3703 before = get_insns ();
3704 end_sequence ();
3705 lra_process_new_insns (curr_insn, before, NULL,
3706 "Inserting the sec. move");
3707 }
3708 lra_update_insn_regno_info (curr_insn);
3709 return true;
3710 }
3711 #endif
3712
3713 lra_assert (goal_alt_number >= 0);
3714 lra_set_used_insn_alternative (curr_insn, goal_alt_number);
3715
3716 if (lra_dump_file != NULL)
3717 {
3718 const char *p;
3719
3720 fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
3721 goal_alt_number, INSN_UID (curr_insn));
3722 for (i = 0; i < n_operands; i++)
3723 {
3724 p = (curr_static_id->operand_alternative
3725 [goal_alt_number * n_operands + i].constraint);
3726 if (*p == '\0')
3727 continue;
3728 fprintf (lra_dump_file, " (%d) ", i);
3729 for (; *p != '\0' && *p != ',' && *p != '#'; p++)
3730 fputc (*p, lra_dump_file);
3731 }
3732 if (INSN_CODE (curr_insn) >= 0
3733 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
3734 fprintf (lra_dump_file, " {%s}", p);
3735 if (curr_id->sp_offset != 0)
3736 fprintf (lra_dump_file, " (sp_off=%" HOST_WIDE_INT_PRINT "d)",
3737 curr_id->sp_offset);
3738 fprintf (lra_dump_file, "\n");
3739 }
3740
3741 /* Right now, for any pair of operands I and J that are required to
3742 match, with J < I, goal_alt_matches[I] is J. Add I to
3743 goal_alt_matched[J]. */
3744
3745 for (i = 0; i < n_operands; i++)
3746 if ((j = goal_alt_matches[i]) >= 0)
3747 {
3748 for (k = 0; goal_alt_matched[j][k] >= 0; k++)
3749 ;
3750 /* We allow matching one output operand and several input
3751 operands. */
3752 lra_assert (k == 0
3753 || (curr_static_id->operand[j].type == OP_OUT
3754 && curr_static_id->operand[i].type == OP_IN
3755 && (curr_static_id->operand
3756 [goal_alt_matched[j][0]].type == OP_IN)));
3757 goal_alt_matched[j][k] = i;
3758 goal_alt_matched[j][k + 1] = -1;
3759 }
3760
3761 for (i = 0; i < n_operands; i++)
3762 goal_alt_win[i] |= goal_alt_match_win[i];
3763
3764 /* Any constants that aren't allowed and can't be reloaded into
3765 registers are here changed into memory references. */
3766 for (i = 0; i < n_operands; i++)
3767 if (goal_alt_win[i])
3768 {
3769 int regno;
3770 enum reg_class new_class;
3771 rtx reg = *curr_id->operand_loc[i];
3772
3773 if (GET_CODE (reg) == SUBREG)
3774 reg = SUBREG_REG (reg);
3775
3776 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
3777 {
3778 bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
3779
3780 if (new_class != NO_REGS && get_reg_class (regno) != new_class)
3781 {
3782 lra_assert (ok_p);
3783 lra_change_class (regno, new_class, " Change to", true);
3784 }
3785 }
3786 }
3787 else
3788 {
3789 const char *constraint;
3790 char c;
3791 rtx op = *curr_id->operand_loc[i];
3792 rtx subreg = NULL_RTX;
3793 machine_mode mode = curr_operand_mode[i];
3794
3795 if (GET_CODE (op) == SUBREG)
3796 {
3797 subreg = op;
3798 op = SUBREG_REG (op);
3799 mode = GET_MODE (op);
3800 }
3801
3802 if (CONST_POOL_OK_P (mode, op)
3803 && ((targetm.preferred_reload_class
3804 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
3805 || no_input_reloads_p))
3806 {
3807 rtx tem = force_const_mem (mode, op);
3808
3809 change_p = true;
3810 if (subreg != NULL_RTX)
3811 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
3812
3813 *curr_id->operand_loc[i] = tem;
3814 lra_update_dup (curr_id, i);
3815 process_address (i, false, &before, &after);
3816
3817 /* If the alternative accepts constant pool refs directly
3818 there will be no reload needed at all. */
3819 if (subreg != NULL_RTX)
3820 continue;
3821 /* Skip alternatives before the one requested. */
3822 constraint = (curr_static_id->operand_alternative
3823 [goal_alt_number * n_operands + i].constraint);
3824 for (;
3825 (c = *constraint) && c != ',' && c != '#';
3826 constraint += CONSTRAINT_LEN (c, constraint))
3827 {
3828 enum constraint_num cn = lookup_constraint (constraint);
3829 if ((insn_extra_memory_constraint (cn)
3830 || insn_extra_special_memory_constraint (cn))
3831 && satisfies_memory_constraint_p (tem, cn))
3832 break;
3833 }
3834 if (c == '\0' || c == ',' || c == '#')
3835 continue;
3836
3837 goal_alt_win[i] = true;
3838 }
3839 }
3840
3841 n_outputs = 0;
3842 outputs[0] = -1;
3843 for (i = 0; i < n_operands; i++)
3844 {
3845 int regno;
3846 bool optional_p = false;
3847 rtx old, new_reg;
3848 rtx op = *curr_id->operand_loc[i];
3849
3850 if (goal_alt_win[i])
3851 {
3852 if (goal_alt[i] == NO_REGS
3853 && REG_P (op)
3854 /* When we assign NO_REGS it means that we will not
3855 assign a hard register to the scratch pseudo by
3856 assigment pass and the scratch pseudo will be
3857 spilled. Spilled scratch pseudos are transformed
3858 back to scratches at the LRA end. */
3859 && lra_former_scratch_operand_p (curr_insn, i)
3860 && lra_former_scratch_p (REGNO (op)))
3861 {
3862 int regno = REGNO (op);
3863 lra_change_class (regno, NO_REGS, " Change to", true);
3864 if (lra_get_regno_hard_regno (regno) >= 0)
3865 /* We don't have to mark all insn affected by the
3866 spilled pseudo as there is only one such insn, the
3867 current one. */
3868 reg_renumber[regno] = -1;
3869 lra_assert (bitmap_single_bit_set_p
3870 (&lra_reg_info[REGNO (op)].insn_bitmap));
3871 }
3872 /* We can do an optional reload. If the pseudo got a hard
3873 reg, we might improve the code through inheritance. If
3874 it does not get a hard register we coalesce memory/memory
3875 moves later. Ignore move insns to avoid cycling. */
3876 if (! lra_simple_p
3877 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
3878 && goal_alt[i] != NO_REGS && REG_P (op)
3879 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
3880 && regno < new_regno_start
3881 && ! lra_former_scratch_p (regno)
3882 && reg_renumber[regno] < 0
3883 /* Check that the optional reload pseudo will be able to
3884 hold given mode value. */
3885 && ! (prohibited_class_reg_set_mode_p
3886 (goal_alt[i], reg_class_contents[goal_alt[i]],
3887 PSEUDO_REGNO_MODE (regno)))
3888 && (curr_insn_set == NULL_RTX
3889 || !((REG_P (SET_SRC (curr_insn_set))
3890 || MEM_P (SET_SRC (curr_insn_set))
3891 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
3892 && (REG_P (SET_DEST (curr_insn_set))
3893 || MEM_P (SET_DEST (curr_insn_set))
3894 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
3895 optional_p = true;
3896 else
3897 continue;
3898 }
3899
3900 /* Operands that match previous ones have already been handled. */
3901 if (goal_alt_matches[i] >= 0)
3902 continue;
3903
3904 /* We should not have an operand with a non-offsettable address
3905 appearing where an offsettable address will do. It also may
3906 be a case when the address should be special in other words
3907 not a general one (e.g. it needs no index reg). */
3908 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
3909 {
3910 enum reg_class rclass;
3911 rtx *loc = &XEXP (op, 0);
3912 enum rtx_code code = GET_CODE (*loc);
3913
3914 push_to_sequence (before);
3915 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
3916 MEM, SCRATCH);
3917 if (GET_RTX_CLASS (code) == RTX_AUTOINC)
3918 new_reg = emit_inc (rclass, *loc, *loc,
3919 /* This value does not matter for MODIFY. */
3920 GET_MODE_SIZE (GET_MODE (op)));
3921 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE,
3922 "offsetable address", &new_reg))
3923 lra_emit_move (new_reg, *loc);
3924 before = get_insns ();
3925 end_sequence ();
3926 *loc = new_reg;
3927 lra_update_dup (curr_id, i);
3928 }
3929 else if (goal_alt_matched[i][0] == -1)
3930 {
3931 machine_mode mode;
3932 rtx reg, *loc;
3933 int hard_regno, byte;
3934 enum op_type type = curr_static_id->operand[i].type;
3935
3936 loc = curr_id->operand_loc[i];
3937 mode = curr_operand_mode[i];
3938 if (GET_CODE (*loc) == SUBREG)
3939 {
3940 reg = SUBREG_REG (*loc);
3941 byte = SUBREG_BYTE (*loc);
3942 if (REG_P (reg)
3943 /* Strict_low_part requires reload the register not
3944 the sub-register. */
3945 && (curr_static_id->operand[i].strict_low
3946 || (GET_MODE_SIZE (mode)
3947 <= GET_MODE_SIZE (GET_MODE (reg))
3948 && (hard_regno
3949 = get_try_hard_regno (REGNO (reg))) >= 0
3950 && (simplify_subreg_regno
3951 (hard_regno,
3952 GET_MODE (reg), byte, mode) < 0)
3953 && (goal_alt[i] == NO_REGS
3954 || (simplify_subreg_regno
3955 (ira_class_hard_regs[goal_alt[i]][0],
3956 GET_MODE (reg), byte, mode) >= 0)))))
3957 {
3958 if (type == OP_OUT)
3959 type = OP_INOUT;
3960 loc = &SUBREG_REG (*loc);
3961 mode = GET_MODE (*loc);
3962 }
3963 }
3964 old = *loc;
3965 if (get_reload_reg (type, mode, old, goal_alt[i],
3966 loc != curr_id->operand_loc[i], "", &new_reg)
3967 && type != OP_OUT)
3968 {
3969 push_to_sequence (before);
3970 lra_emit_move (new_reg, old);
3971 before = get_insns ();
3972 end_sequence ();
3973 }
3974 *loc = new_reg;
3975 if (type != OP_IN
3976 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
3977 {
3978 start_sequence ();
3979 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
3980 emit_insn (after);
3981 after = get_insns ();
3982 end_sequence ();
3983 *loc = new_reg;
3984 }
3985 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
3986 if (goal_alt_dont_inherit_ops[j] == i)
3987 {
3988 lra_set_regno_unique_value (REGNO (new_reg));
3989 break;
3990 }
3991 lra_update_dup (curr_id, i);
3992 }
3993 else if (curr_static_id->operand[i].type == OP_IN
3994 && (curr_static_id->operand[goal_alt_matched[i][0]].type
3995 == OP_OUT))
3996 {
3997 /* generate reloads for input and matched outputs. */
3998 match_inputs[0] = i;
3999 match_inputs[1] = -1;
4000 match_reload (goal_alt_matched[i][0], match_inputs, outputs,
4001 goal_alt[i], &before, &after,
4002 curr_static_id->operand_alternative
4003 [goal_alt_number * n_operands + goal_alt_matched[i][0]]
4004 .earlyclobber);
4005 }
4006 else if (curr_static_id->operand[i].type == OP_OUT
4007 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4008 == OP_IN))
4009 /* Generate reloads for output and matched inputs. */
4010 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4011 &after, curr_static_id->operand_alternative
4012 [goal_alt_number * n_operands + i].earlyclobber);
4013 else if (curr_static_id->operand[i].type == OP_IN
4014 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4015 == OP_IN))
4016 {
4017 /* Generate reloads for matched inputs. */
4018 match_inputs[0] = i;
4019 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
4020 match_inputs[j + 1] = k;
4021 match_inputs[j + 1] = -1;
4022 match_reload (-1, match_inputs, outputs, goal_alt[i], &before,
4023 &after, false);
4024 }
4025 else
4026 /* We must generate code in any case when function
4027 process_alt_operands decides that it is possible. */
4028 gcc_unreachable ();
4029
4030 /* Memorise processed outputs so that output remaining to be processed
4031 can avoid using the same register value (see match_reload). */
4032 if (curr_static_id->operand[i].type == OP_OUT)
4033 {
4034 outputs[n_outputs++] = i;
4035 outputs[n_outputs] = -1;
4036 }
4037
4038 if (optional_p)
4039 {
4040 lra_assert (REG_P (op));
4041 regno = REGNO (op);
4042 op = *curr_id->operand_loc[i]; /* Substitution. */
4043 if (GET_CODE (op) == SUBREG)
4044 op = SUBREG_REG (op);
4045 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
4046 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
4047 lra_reg_info[REGNO (op)].restore_regno = regno;
4048 if (lra_dump_file != NULL)
4049 fprintf (lra_dump_file,
4050 " Making reload reg %d for reg %d optional\n",
4051 REGNO (op), regno);
4052 }
4053 }
4054 if (before != NULL_RTX || after != NULL_RTX
4055 || max_regno_before != max_reg_num ())
4056 change_p = true;
4057 if (change_p)
4058 {
4059 lra_update_operator_dups (curr_id);
4060 /* Something changes -- process the insn. */
4061 lra_update_insn_regno_info (curr_insn);
4062 }
4063 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
4064 return change_p;
4065 }
4066
4067 /* Return true if INSN satisfies all constraints. In other words, no
4068 reload insns are needed. */
4069 bool
lra_constrain_insn(rtx_insn * insn)4070 lra_constrain_insn (rtx_insn *insn)
4071 {
4072 int saved_new_regno_start = new_regno_start;
4073 int saved_new_insn_uid_start = new_insn_uid_start;
4074 bool change_p;
4075
4076 curr_insn = insn;
4077 curr_id = lra_get_insn_recog_data (curr_insn);
4078 curr_static_id = curr_id->insn_static_data;
4079 new_insn_uid_start = get_max_uid ();
4080 new_regno_start = max_reg_num ();
4081 change_p = curr_insn_transform (true);
4082 new_regno_start = saved_new_regno_start;
4083 new_insn_uid_start = saved_new_insn_uid_start;
4084 return ! change_p;
4085 }
4086
4087 /* Return true if X is in LIST. */
4088 static bool
in_list_p(rtx x,rtx list)4089 in_list_p (rtx x, rtx list)
4090 {
4091 for (; list != NULL_RTX; list = XEXP (list, 1))
4092 if (XEXP (list, 0) == x)
4093 return true;
4094 return false;
4095 }
4096
4097 /* Return true if X contains an allocatable hard register (if
4098 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4099 static bool
contains_reg_p(rtx x,bool hard_reg_p,bool spilled_p)4100 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
4101 {
4102 int i, j;
4103 const char *fmt;
4104 enum rtx_code code;
4105
4106 code = GET_CODE (x);
4107 if (REG_P (x))
4108 {
4109 int regno = REGNO (x);
4110 HARD_REG_SET alloc_regs;
4111
4112 if (hard_reg_p)
4113 {
4114 if (regno >= FIRST_PSEUDO_REGISTER)
4115 regno = lra_get_regno_hard_regno (regno);
4116 if (regno < 0)
4117 return false;
4118 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs);
4119 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
4120 }
4121 else
4122 {
4123 if (regno < FIRST_PSEUDO_REGISTER)
4124 return false;
4125 if (! spilled_p)
4126 return true;
4127 return lra_get_regno_hard_regno (regno) < 0;
4128 }
4129 }
4130 fmt = GET_RTX_FORMAT (code);
4131 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4132 {
4133 if (fmt[i] == 'e')
4134 {
4135 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
4136 return true;
4137 }
4138 else if (fmt[i] == 'E')
4139 {
4140 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4141 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
4142 return true;
4143 }
4144 }
4145 return false;
4146 }
4147
4148 /* Process all regs in location *LOC and change them on equivalent
4149 substitution. Return true if any change was done. */
4150 static bool
loc_equivalence_change_p(rtx * loc)4151 loc_equivalence_change_p (rtx *loc)
4152 {
4153 rtx subst, reg, x = *loc;
4154 bool result = false;
4155 enum rtx_code code = GET_CODE (x);
4156 const char *fmt;
4157 int i, j;
4158
4159 if (code == SUBREG)
4160 {
4161 reg = SUBREG_REG (x);
4162 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4163 && GET_MODE (subst) == VOIDmode)
4164 {
4165 /* We cannot reload debug location. Simplify subreg here
4166 while we know the inner mode. */
4167 *loc = simplify_gen_subreg (GET_MODE (x), subst,
4168 GET_MODE (reg), SUBREG_BYTE (x));
4169 return true;
4170 }
4171 }
4172 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
4173 {
4174 *loc = subst;
4175 return true;
4176 }
4177
4178 /* Scan all the operand sub-expressions. */
4179 fmt = GET_RTX_FORMAT (code);
4180 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4181 {
4182 if (fmt[i] == 'e')
4183 result = loc_equivalence_change_p (&XEXP (x, i)) || result;
4184 else if (fmt[i] == 'E')
4185 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4186 result
4187 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result;
4188 }
4189 return result;
4190 }
4191
4192 /* Similar to loc_equivalence_change_p, but for use as
4193 simplify_replace_fn_rtx callback. DATA is insn for which the
4194 elimination is done. If it null we don't do the elimination. */
4195 static rtx
loc_equivalence_callback(rtx loc,const_rtx,void * data)4196 loc_equivalence_callback (rtx loc, const_rtx, void *data)
4197 {
4198 if (!REG_P (loc))
4199 return NULL_RTX;
4200
4201 rtx subst = (data == NULL
4202 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data));
4203 if (subst != loc)
4204 return subst;
4205
4206 return NULL_RTX;
4207 }
4208
4209 /* Maximum number of generated reload insns per an insn. It is for
4210 preventing this pass cycling in a bug case. */
4211 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4212
4213 /* The current iteration number of this LRA pass. */
4214 int lra_constraint_iter;
4215
4216 /* True if we substituted equiv which needs checking register
4217 allocation correctness because the equivalent value contains
4218 allocatable hard registers or when we restore multi-register
4219 pseudo. */
4220 bool lra_risky_transformations_p;
4221
4222 /* Return true if REGNO is referenced in more than one block. */
4223 static bool
multi_block_pseudo_p(int regno)4224 multi_block_pseudo_p (int regno)
4225 {
4226 basic_block bb = NULL;
4227 unsigned int uid;
4228 bitmap_iterator bi;
4229
4230 if (regno < FIRST_PSEUDO_REGISTER)
4231 return false;
4232
4233 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
4234 if (bb == NULL)
4235 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
4236 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
4237 return true;
4238 return false;
4239 }
4240
4241 /* Return true if LIST contains a deleted insn. */
4242 static bool
contains_deleted_insn_p(rtx_insn_list * list)4243 contains_deleted_insn_p (rtx_insn_list *list)
4244 {
4245 for (; list != NULL_RTX; list = list->next ())
4246 if (NOTE_P (list->insn ())
4247 && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED)
4248 return true;
4249 return false;
4250 }
4251
4252 /* Return true if X contains a pseudo dying in INSN. */
4253 static bool
dead_pseudo_p(rtx x,rtx_insn * insn)4254 dead_pseudo_p (rtx x, rtx_insn *insn)
4255 {
4256 int i, j;
4257 const char *fmt;
4258 enum rtx_code code;
4259
4260 if (REG_P (x))
4261 return (insn != NULL_RTX
4262 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX);
4263 code = GET_CODE (x);
4264 fmt = GET_RTX_FORMAT (code);
4265 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4266 {
4267 if (fmt[i] == 'e')
4268 {
4269 if (dead_pseudo_p (XEXP (x, i), insn))
4270 return true;
4271 }
4272 else if (fmt[i] == 'E')
4273 {
4274 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4275 if (dead_pseudo_p (XVECEXP (x, i, j), insn))
4276 return true;
4277 }
4278 }
4279 return false;
4280 }
4281
4282 /* Return true if INSN contains a dying pseudo in INSN right hand
4283 side. */
4284 static bool
insn_rhs_dead_pseudo_p(rtx_insn * insn)4285 insn_rhs_dead_pseudo_p (rtx_insn *insn)
4286 {
4287 rtx set = single_set (insn);
4288
4289 gcc_assert (set != NULL);
4290 return dead_pseudo_p (SET_SRC (set), insn);
4291 }
4292
4293 /* Return true if any init insn of REGNO contains a dying pseudo in
4294 insn right hand side. */
4295 static bool
init_insn_rhs_dead_pseudo_p(int regno)4296 init_insn_rhs_dead_pseudo_p (int regno)
4297 {
4298 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4299
4300 if (insns == NULL)
4301 return false;
4302 for (; insns != NULL_RTX; insns = insns->next ())
4303 if (insn_rhs_dead_pseudo_p (insns->insn ()))
4304 return true;
4305 return false;
4306 }
4307
4308 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4309 reverse only if we have one init insn with given REGNO as a
4310 source. */
4311 static bool
reverse_equiv_p(int regno)4312 reverse_equiv_p (int regno)
4313 {
4314 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4315 rtx set;
4316
4317 if (insns == NULL)
4318 return false;
4319 if (! INSN_P (insns->insn ())
4320 || insns->next () != NULL)
4321 return false;
4322 if ((set = single_set (insns->insn ())) == NULL_RTX)
4323 return false;
4324 return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno;
4325 }
4326
4327 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4328 call this function only for non-reverse equivalence. */
4329 static bool
contains_reloaded_insn_p(int regno)4330 contains_reloaded_insn_p (int regno)
4331 {
4332 rtx set;
4333 rtx_insn_list *list = ira_reg_equiv[regno].init_insns;
4334
4335 for (; list != NULL; list = list->next ())
4336 if ((set = single_set (list->insn ())) == NULL_RTX
4337 || ! REG_P (SET_DEST (set))
4338 || (int) REGNO (SET_DEST (set)) != regno)
4339 return true;
4340 return false;
4341 }
4342
4343 /* Entry function of LRA constraint pass. Return true if the
4344 constraint pass did change the code. */
4345 bool
lra_constraints(bool first_p)4346 lra_constraints (bool first_p)
4347 {
4348 bool changed_p;
4349 int i, hard_regno, new_insns_num;
4350 unsigned int min_len, new_min_len, uid;
4351 rtx set, x, reg, dest_reg;
4352 basic_block last_bb;
4353 bitmap_head equiv_insn_bitmap;
4354 bitmap_iterator bi;
4355
4356 lra_constraint_iter++;
4357 if (lra_dump_file != NULL)
4358 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
4359 lra_constraint_iter);
4360 changed_p = false;
4361 if (pic_offset_table_rtx
4362 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
4363 lra_risky_transformations_p = true;
4364 else
4365 lra_risky_transformations_p = false;
4366 new_insn_uid_start = get_max_uid ();
4367 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
4368 /* Mark used hard regs for target stack size calulations. */
4369 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4370 if (lra_reg_info[i].nrefs != 0
4371 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4372 {
4373 int j, nregs;
4374
4375 nregs = hard_regno_nregs[hard_regno][lra_reg_info[i].biggest_mode];
4376 for (j = 0; j < nregs; j++)
4377 df_set_regs_ever_live (hard_regno + j, true);
4378 }
4379 /* Do elimination before the equivalence processing as we can spill
4380 some pseudos during elimination. */
4381 lra_eliminate (false, first_p);
4382 bitmap_initialize (&equiv_insn_bitmap, ®_obstack);
4383 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4384 if (lra_reg_info[i].nrefs != 0)
4385 {
4386 ira_reg_equiv[i].profitable_p = true;
4387 reg = regno_reg_rtx[i];
4388 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
4389 {
4390 bool pseudo_p = contains_reg_p (x, false, false);
4391
4392 /* After RTL transformation, we can not guarantee that
4393 pseudo in the substitution was not reloaded which might
4394 make equivalence invalid. For example, in reverse
4395 equiv of p0
4396
4397 p0 <- ...
4398 ...
4399 equiv_mem <- p0
4400
4401 the memory address register was reloaded before the 2nd
4402 insn. */
4403 if ((! first_p && pseudo_p)
4404 /* We don't use DF for compilation speed sake. So it
4405 is problematic to update live info when we use an
4406 equivalence containing pseudos in more than one
4407 BB. */
4408 || (pseudo_p && multi_block_pseudo_p (i))
4409 /* If an init insn was deleted for some reason, cancel
4410 the equiv. We could update the equiv insns after
4411 transformations including an equiv insn deletion
4412 but it is not worthy as such cases are extremely
4413 rare. */
4414 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
4415 /* If it is not a reverse equivalence, we check that a
4416 pseudo in rhs of the init insn is not dying in the
4417 insn. Otherwise, the live info at the beginning of
4418 the corresponding BB might be wrong after we
4419 removed the insn. When the equiv can be a
4420 constant, the right hand side of the init insn can
4421 be a pseudo. */
4422 || (! reverse_equiv_p (i)
4423 && (init_insn_rhs_dead_pseudo_p (i)
4424 /* If we reloaded the pseudo in an equivalence
4425 init insn, we can not remove the equiv init
4426 insns and the init insns might write into
4427 const memory in this case. */
4428 || contains_reloaded_insn_p (i)))
4429 /* Prevent access beyond equivalent memory for
4430 paradoxical subregs. */
4431 || (MEM_P (x)
4432 && (GET_MODE_SIZE (lra_reg_info[i].biggest_mode)
4433 > GET_MODE_SIZE (GET_MODE (x))))
4434 || (pic_offset_table_rtx
4435 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x)
4436 && (targetm.preferred_reload_class
4437 (x, lra_get_allocno_class (i)) == NO_REGS))
4438 || contains_symbol_ref_p (x))))
4439 ira_reg_equiv[i].defined_p = false;
4440 if (contains_reg_p (x, false, true))
4441 ira_reg_equiv[i].profitable_p = false;
4442 if (get_equiv (reg) != reg)
4443 bitmap_ior_into (&equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
4444 }
4445 }
4446 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4447 update_equiv (i);
4448 /* We should add all insns containing pseudos which should be
4449 substituted by their equivalences. */
4450 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap, 0, uid, bi)
4451 lra_push_insn_by_uid (uid);
4452 min_len = lra_insn_stack_length ();
4453 new_insns_num = 0;
4454 last_bb = NULL;
4455 changed_p = false;
4456 while ((new_min_len = lra_insn_stack_length ()) != 0)
4457 {
4458 curr_insn = lra_pop_insn ();
4459 --new_min_len;
4460 curr_bb = BLOCK_FOR_INSN (curr_insn);
4461 if (curr_bb != last_bb)
4462 {
4463 last_bb = curr_bb;
4464 bb_reload_num = lra_curr_reload_num;
4465 }
4466 if (min_len > new_min_len)
4467 {
4468 min_len = new_min_len;
4469 new_insns_num = 0;
4470 }
4471 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
4472 internal_error
4473 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4474 MAX_RELOAD_INSNS_NUMBER);
4475 new_insns_num++;
4476 if (DEBUG_INSN_P (curr_insn))
4477 {
4478 /* We need to check equivalence in debug insn and change
4479 pseudo to the equivalent value if necessary. */
4480 curr_id = lra_get_insn_recog_data (curr_insn);
4481 if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn)))
4482 {
4483 rtx old = *curr_id->operand_loc[0];
4484 *curr_id->operand_loc[0]
4485 = simplify_replace_fn_rtx (old, NULL_RTX,
4486 loc_equivalence_callback, curr_insn);
4487 if (old != *curr_id->operand_loc[0])
4488 {
4489 lra_update_insn_regno_info (curr_insn);
4490 changed_p = true;
4491 }
4492 }
4493 }
4494 else if (INSN_P (curr_insn))
4495 {
4496 if ((set = single_set (curr_insn)) != NULL_RTX)
4497 {
4498 dest_reg = SET_DEST (set);
4499 /* The equivalence pseudo could be set up as SUBREG in a
4500 case when it is a call restore insn in a mode
4501 different from the pseudo mode. */
4502 if (GET_CODE (dest_reg) == SUBREG)
4503 dest_reg = SUBREG_REG (dest_reg);
4504 if ((REG_P (dest_reg)
4505 && (x = get_equiv (dest_reg)) != dest_reg
4506 /* Remove insns which set up a pseudo whose value
4507 can not be changed. Such insns might be not in
4508 init_insns because we don't update equiv data
4509 during insn transformations.
4510
4511 As an example, let suppose that a pseudo got
4512 hard register and on the 1st pass was not
4513 changed to equivalent constant. We generate an
4514 additional insn setting up the pseudo because of
4515 secondary memory movement. Then the pseudo is
4516 spilled and we use the equiv constant. In this
4517 case we should remove the additional insn and
4518 this insn is not init_insns list. */
4519 && (! MEM_P (x) || MEM_READONLY_P (x)
4520 /* Check that this is actually an insn setting
4521 up the equivalence. */
4522 || in_list_p (curr_insn,
4523 ira_reg_equiv
4524 [REGNO (dest_reg)].init_insns)))
4525 || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
4526 && in_list_p (curr_insn,
4527 ira_reg_equiv
4528 [REGNO (SET_SRC (set))].init_insns)))
4529 {
4530 /* This is equiv init insn of pseudo which did not get a
4531 hard register -- remove the insn. */
4532 if (lra_dump_file != NULL)
4533 {
4534 fprintf (lra_dump_file,
4535 " Removing equiv init insn %i (freq=%d)\n",
4536 INSN_UID (curr_insn),
4537 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
4538 dump_insn_slim (lra_dump_file, curr_insn);
4539 }
4540 if (contains_reg_p (x, true, false))
4541 lra_risky_transformations_p = true;
4542 lra_set_insn_deleted (curr_insn);
4543 continue;
4544 }
4545 }
4546 curr_id = lra_get_insn_recog_data (curr_insn);
4547 curr_static_id = curr_id->insn_static_data;
4548 init_curr_insn_input_reloads ();
4549 init_curr_operand_mode ();
4550 if (curr_insn_transform (false))
4551 changed_p = true;
4552 /* Check non-transformed insns too for equiv change as USE
4553 or CLOBBER don't need reloads but can contain pseudos
4554 being changed on their equivalences. */
4555 else if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn))
4556 && loc_equivalence_change_p (&PATTERN (curr_insn)))
4557 {
4558 lra_update_insn_regno_info (curr_insn);
4559 changed_p = true;
4560 }
4561 }
4562 }
4563 bitmap_clear (&equiv_insn_bitmap);
4564 /* If we used a new hard regno, changed_p should be true because the
4565 hard reg is assigned to a new pseudo. */
4566 if (flag_checking && !changed_p)
4567 {
4568 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4569 if (lra_reg_info[i].nrefs != 0
4570 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4571 {
4572 int j, nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (i)];
4573
4574 for (j = 0; j < nregs; j++)
4575 lra_assert (df_regs_ever_live_p (hard_regno + j));
4576 }
4577 }
4578 return changed_p;
4579 }
4580
4581 /* Initiate the LRA constraint pass. It is done once per
4582 function. */
4583 void
lra_constraints_init(void)4584 lra_constraints_init (void)
4585 {
4586 }
4587
4588 /* Finalize the LRA constraint pass. It is done once per
4589 function. */
4590 void
lra_constraints_finish(void)4591 lra_constraints_finish (void)
4592 {
4593 }
4594
4595
4596
4597 /* This page contains code to do inheritance/split
4598 transformations. */
4599
4600 /* Number of reloads passed so far in current EBB. */
4601 static int reloads_num;
4602
4603 /* Number of calls passed so far in current EBB. */
4604 static int calls_num;
4605
4606 /* Current reload pseudo check for validity of elements in
4607 USAGE_INSNS. */
4608 static int curr_usage_insns_check;
4609
4610 /* Info about last usage of registers in EBB to do inheritance/split
4611 transformation. Inheritance transformation is done from a spilled
4612 pseudo and split transformations from a hard register or a pseudo
4613 assigned to a hard register. */
4614 struct usage_insns
4615 {
4616 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4617 value INSNS is valid. The insns is chain of optional debug insns
4618 and a finishing non-debug insn using the corresponding reg. The
4619 value is also used to mark the registers which are set up in the
4620 current insn. The negated insn uid is used for this. */
4621 int check;
4622 /* Value of global reloads_num at the last insn in INSNS. */
4623 int reloads_num;
4624 /* Value of global reloads_nums at the last insn in INSNS. */
4625 int calls_num;
4626 /* It can be true only for splitting. And it means that the restore
4627 insn should be put after insn given by the following member. */
4628 bool after_p;
4629 /* Next insns in the current EBB which use the original reg and the
4630 original reg value is not changed between the current insn and
4631 the next insns. In order words, e.g. for inheritance, if we need
4632 to use the original reg value again in the next insns we can try
4633 to use the value in a hard register from a reload insn of the
4634 current insn. */
4635 rtx insns;
4636 };
4637
4638 /* Map: regno -> corresponding pseudo usage insns. */
4639 static struct usage_insns *usage_insns;
4640
4641 static void
setup_next_usage_insn(int regno,rtx insn,int reloads_num,bool after_p)4642 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p)
4643 {
4644 usage_insns[regno].check = curr_usage_insns_check;
4645 usage_insns[regno].insns = insn;
4646 usage_insns[regno].reloads_num = reloads_num;
4647 usage_insns[regno].calls_num = calls_num;
4648 usage_insns[regno].after_p = after_p;
4649 }
4650
4651 /* The function is used to form list REGNO usages which consists of
4652 optional debug insns finished by a non-debug insn using REGNO.
4653 RELOADS_NUM is current number of reload insns processed so far. */
4654 static void
add_next_usage_insn(int regno,rtx_insn * insn,int reloads_num)4655 add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num)
4656 {
4657 rtx next_usage_insns;
4658
4659 if (usage_insns[regno].check == curr_usage_insns_check
4660 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX
4661 && DEBUG_INSN_P (insn))
4662 {
4663 /* Check that we did not add the debug insn yet. */
4664 if (next_usage_insns != insn
4665 && (GET_CODE (next_usage_insns) != INSN_LIST
4666 || XEXP (next_usage_insns, 0) != insn))
4667 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn,
4668 next_usage_insns);
4669 }
4670 else if (NONDEBUG_INSN_P (insn))
4671 setup_next_usage_insn (regno, insn, reloads_num, false);
4672 else
4673 usage_insns[regno].check = 0;
4674 }
4675
4676 /* Return first non-debug insn in list USAGE_INSNS. */
4677 static rtx_insn *
skip_usage_debug_insns(rtx usage_insns)4678 skip_usage_debug_insns (rtx usage_insns)
4679 {
4680 rtx insn;
4681
4682 /* Skip debug insns. */
4683 for (insn = usage_insns;
4684 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST;
4685 insn = XEXP (insn, 1))
4686 ;
4687 return safe_as_a <rtx_insn *> (insn);
4688 }
4689
4690 /* Return true if we need secondary memory moves for insn in
4691 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4692 into the insn. */
4693 static bool
check_secondary_memory_needed_p(enum reg_class inher_cl ATTRIBUTE_UNUSED,rtx usage_insns ATTRIBUTE_UNUSED)4694 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED,
4695 rtx usage_insns ATTRIBUTE_UNUSED)
4696 {
4697 #ifndef SECONDARY_MEMORY_NEEDED
4698 return false;
4699 #else
4700 rtx_insn *insn;
4701 rtx set, dest;
4702 enum reg_class cl;
4703
4704 if (inher_cl == ALL_REGS
4705 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX)
4706 return false;
4707 lra_assert (INSN_P (insn));
4708 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set)))
4709 return false;
4710 dest = SET_DEST (set);
4711 if (! REG_P (dest))
4712 return false;
4713 lra_assert (inher_cl != NO_REGS);
4714 cl = get_reg_class (REGNO (dest));
4715 return (cl != NO_REGS && cl != ALL_REGS
4716 && SECONDARY_MEMORY_NEEDED (inher_cl, cl, GET_MODE (dest)));
4717 #endif
4718 }
4719
4720 /* Registers involved in inheritance/split in the current EBB
4721 (inheritance/split pseudos and original registers). */
4722 static bitmap_head check_only_regs;
4723
4724 /* Do inheritance transformations for insn INSN, which defines (if
4725 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4726 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4727 form as the "insns" field of usage_insns. Return true if we
4728 succeed in such transformation.
4729
4730 The transformations look like:
4731
4732 p <- ... i <- ...
4733 ... p <- i (new insn)
4734 ... =>
4735 <- ... p ... <- ... i ...
4736 or
4737 ... i <- p (new insn)
4738 <- ... p ... <- ... i ...
4739 ... =>
4740 <- ... p ... <- ... i ...
4741 where p is a spilled original pseudo and i is a new inheritance pseudo.
4742
4743
4744 The inheritance pseudo has the smallest class of two classes CL and
4745 class of ORIGINAL REGNO. */
4746 static bool
inherit_reload_reg(bool def_p,int original_regno,enum reg_class cl,rtx_insn * insn,rtx next_usage_insns)4747 inherit_reload_reg (bool def_p, int original_regno,
4748 enum reg_class cl, rtx_insn *insn, rtx next_usage_insns)
4749 {
4750 if (optimize_function_for_size_p (cfun))
4751 return false;
4752
4753 enum reg_class rclass = lra_get_allocno_class (original_regno);
4754 rtx original_reg = regno_reg_rtx[original_regno];
4755 rtx new_reg, usage_insn;
4756 rtx_insn *new_insns;
4757
4758 lra_assert (! usage_insns[original_regno].after_p);
4759 if (lra_dump_file != NULL)
4760 fprintf (lra_dump_file,
4761 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4762 if (! ira_reg_classes_intersect_p[cl][rclass])
4763 {
4764 if (lra_dump_file != NULL)
4765 {
4766 fprintf (lra_dump_file,
4767 " Rejecting inheritance for %d "
4768 "because of disjoint classes %s and %s\n",
4769 original_regno, reg_class_names[cl],
4770 reg_class_names[rclass]);
4771 fprintf (lra_dump_file,
4772 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4773 }
4774 return false;
4775 }
4776 if ((ira_class_subset_p[cl][rclass] && cl != rclass)
4777 /* We don't use a subset of two classes because it can be
4778 NO_REGS. This transformation is still profitable in most
4779 cases even if the classes are not intersected as register
4780 move is probably cheaper than a memory load. */
4781 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass])
4782 {
4783 if (lra_dump_file != NULL)
4784 fprintf (lra_dump_file, " Use smallest class of %s and %s\n",
4785 reg_class_names[cl], reg_class_names[rclass]);
4786
4787 rclass = cl;
4788 }
4789 if (check_secondary_memory_needed_p (rclass, next_usage_insns))
4790 {
4791 /* Reject inheritance resulting in secondary memory moves.
4792 Otherwise, there is a danger in LRA cycling. Also such
4793 transformation will be unprofitable. */
4794 if (lra_dump_file != NULL)
4795 {
4796 rtx_insn *insn = skip_usage_debug_insns (next_usage_insns);
4797 rtx set = single_set (insn);
4798
4799 lra_assert (set != NULL_RTX);
4800
4801 rtx dest = SET_DEST (set);
4802
4803 lra_assert (REG_P (dest));
4804 fprintf (lra_dump_file,
4805 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4806 "as secondary mem is needed\n",
4807 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))],
4808 original_regno, reg_class_names[rclass]);
4809 fprintf (lra_dump_file,
4810 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4811 }
4812 return false;
4813 }
4814 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
4815 rclass, "inheritance");
4816 start_sequence ();
4817 if (def_p)
4818 lra_emit_move (original_reg, new_reg);
4819 else
4820 lra_emit_move (new_reg, original_reg);
4821 new_insns = get_insns ();
4822 end_sequence ();
4823 if (NEXT_INSN (new_insns) != NULL_RTX)
4824 {
4825 if (lra_dump_file != NULL)
4826 {
4827 fprintf (lra_dump_file,
4828 " Rejecting inheritance %d->%d "
4829 "as it results in 2 or more insns:\n",
4830 original_regno, REGNO (new_reg));
4831 dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0);
4832 fprintf (lra_dump_file,
4833 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4834 }
4835 return false;
4836 }
4837 lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false);
4838 lra_update_insn_regno_info (insn);
4839 if (! def_p)
4840 /* We now have a new usage insn for original regno. */
4841 setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
4842 if (lra_dump_file != NULL)
4843 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n",
4844 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
4845 lra_reg_info[REGNO (new_reg)].restore_regno = original_regno;
4846 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
4847 bitmap_set_bit (&check_only_regs, original_regno);
4848 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
4849 if (def_p)
4850 lra_process_new_insns (insn, NULL, new_insns,
4851 "Add original<-inheritance");
4852 else
4853 lra_process_new_insns (insn, new_insns, NULL,
4854 "Add inheritance<-original");
4855 while (next_usage_insns != NULL_RTX)
4856 {
4857 if (GET_CODE (next_usage_insns) != INSN_LIST)
4858 {
4859 usage_insn = next_usage_insns;
4860 lra_assert (NONDEBUG_INSN_P (usage_insn));
4861 next_usage_insns = NULL;
4862 }
4863 else
4864 {
4865 usage_insn = XEXP (next_usage_insns, 0);
4866 lra_assert (DEBUG_INSN_P (usage_insn));
4867 next_usage_insns = XEXP (next_usage_insns, 1);
4868 }
4869 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false);
4870 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
4871 if (lra_dump_file != NULL)
4872 {
4873 fprintf (lra_dump_file,
4874 " Inheritance reuse change %d->%d (bb%d):\n",
4875 original_regno, REGNO (new_reg),
4876 BLOCK_FOR_INSN (usage_insn)->index);
4877 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
4878 }
4879 }
4880 if (lra_dump_file != NULL)
4881 fprintf (lra_dump_file,
4882 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4883 return true;
4884 }
4885
4886 /* Return true if we need a caller save/restore for pseudo REGNO which
4887 was assigned to a hard register. */
4888 static inline bool
need_for_call_save_p(int regno)4889 need_for_call_save_p (int regno)
4890 {
4891 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
4892 return (usage_insns[regno].calls_num < calls_num
4893 && (overlaps_hard_reg_set_p
4894 ((flag_ipa_ra &&
4895 ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set))
4896 ? lra_reg_info[regno].actual_call_used_reg_set
4897 : call_used_reg_set,
4898 PSEUDO_REGNO_MODE (regno), reg_renumber[regno])
4899 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber[regno],
4900 PSEUDO_REGNO_MODE (regno))));
4901 }
4902
4903 /* Global registers occurring in the current EBB. */
4904 static bitmap_head ebb_global_regs;
4905
4906 /* Return true if we need a split for hard register REGNO or pseudo
4907 REGNO which was assigned to a hard register.
4908 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4909 used for reloads since the EBB end. It is an approximation of the
4910 used hard registers in the split range. The exact value would
4911 require expensive calculations. If we were aggressive with
4912 splitting because of the approximation, the split pseudo will save
4913 the same hard register assignment and will be removed in the undo
4914 pass. We still need the approximation because too aggressive
4915 splitting would result in too inaccurate cost calculation in the
4916 assignment pass because of too many generated moves which will be
4917 probably removed in the undo pass. */
4918 static inline bool
need_for_split_p(HARD_REG_SET potential_reload_hard_regs,int regno)4919 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
4920 {
4921 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno];
4922
4923 lra_assert (hard_regno >= 0);
4924 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
4925 /* Don't split eliminable hard registers, otherwise we can
4926 split hard registers like hard frame pointer, which
4927 lives on BB start/end according to DF-infrastructure,
4928 when there is a pseudo assigned to the register and
4929 living in the same BB. */
4930 && (regno >= FIRST_PSEUDO_REGISTER
4931 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
4932 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
4933 /* Don't split call clobbered hard regs living through
4934 calls, otherwise we might have a check problem in the
4935 assign sub-pass as in the most cases (exception is a
4936 situation when lra_risky_transformations_p value is
4937 true) the assign pass assumes that all pseudos living
4938 through calls are assigned to call saved hard regs. */
4939 && (regno >= FIRST_PSEUDO_REGISTER
4940 || ! TEST_HARD_REG_BIT (call_used_reg_set, regno)
4941 || usage_insns[regno].calls_num == calls_num)
4942 /* We need at least 2 reloads to make pseudo splitting
4943 profitable. We should provide hard regno splitting in
4944 any case to solve 1st insn scheduling problem when
4945 moving hard register definition up might result in
4946 impossibility to find hard register for reload pseudo of
4947 small register class. */
4948 && (usage_insns[regno].reloads_num
4949 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num)
4950 && (regno < FIRST_PSEUDO_REGISTER
4951 /* For short living pseudos, spilling + inheritance can
4952 be considered a substitution for splitting.
4953 Therefore we do not splitting for local pseudos. It
4954 decreases also aggressiveness of splitting. The
4955 minimal number of references is chosen taking into
4956 account that for 2 references splitting has no sense
4957 as we can just spill the pseudo. */
4958 || (regno >= FIRST_PSEUDO_REGISTER
4959 && lra_reg_info[regno].nrefs > 3
4960 && bitmap_bit_p (&ebb_global_regs, regno))))
4961 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno)));
4962 }
4963
4964 /* Return class for the split pseudo created from original pseudo with
4965 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4966 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4967 results in no secondary memory movements. */
4968 static enum reg_class
choose_split_class(enum reg_class allocno_class,int hard_regno ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED)4969 choose_split_class (enum reg_class allocno_class,
4970 int hard_regno ATTRIBUTE_UNUSED,
4971 machine_mode mode ATTRIBUTE_UNUSED)
4972 {
4973 #ifndef SECONDARY_MEMORY_NEEDED
4974 return allocno_class;
4975 #else
4976 int i;
4977 enum reg_class cl, best_cl = NO_REGS;
4978 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4979 = REGNO_REG_CLASS (hard_regno);
4980
4981 if (! SECONDARY_MEMORY_NEEDED (allocno_class, allocno_class, mode)
4982 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno))
4983 return allocno_class;
4984 for (i = 0;
4985 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES;
4986 i++)
4987 if (! SECONDARY_MEMORY_NEEDED (cl, hard_reg_class, mode)
4988 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class, cl, mode)
4989 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno)
4990 && (best_cl == NO_REGS
4991 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl]))
4992 best_cl = cl;
4993 return best_cl;
4994 #endif
4995 }
4996
4997 /* Do split transformations for insn INSN, which defines or uses
4998 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4999 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5000 "insns" field of usage_insns.
5001
5002 The transformations look like:
5003
5004 p <- ... p <- ...
5005 ... s <- p (new insn -- save)
5006 ... =>
5007 ... p <- s (new insn -- restore)
5008 <- ... p ... <- ... p ...
5009 or
5010 <- ... p ... <- ... p ...
5011 ... s <- p (new insn -- save)
5012 ... =>
5013 ... p <- s (new insn -- restore)
5014 <- ... p ... <- ... p ...
5015
5016 where p is an original pseudo got a hard register or a hard
5017 register and s is a new split pseudo. The save is put before INSN
5018 if BEFORE_P is true. Return true if we succeed in such
5019 transformation. */
5020 static bool
split_reg(bool before_p,int original_regno,rtx_insn * insn,rtx next_usage_insns)5021 split_reg (bool before_p, int original_regno, rtx_insn *insn,
5022 rtx next_usage_insns)
5023 {
5024 enum reg_class rclass;
5025 rtx original_reg;
5026 int hard_regno, nregs;
5027 rtx new_reg, usage_insn;
5028 rtx_insn *restore, *save;
5029 bool after_p;
5030 bool call_save_p;
5031 machine_mode mode;
5032
5033 if (original_regno < FIRST_PSEUDO_REGISTER)
5034 {
5035 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)];
5036 hard_regno = original_regno;
5037 call_save_p = false;
5038 nregs = 1;
5039 mode = lra_reg_info[hard_regno].biggest_mode;
5040 machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]);
5041 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5042 as part of a multi-word register. In that case, or if the biggest
5043 mode was larger than a register, just use the reg_rtx. Otherwise,
5044 limit the size to that of the biggest access in the function. */
5045 if (mode == VOIDmode
5046 || GET_MODE_SIZE (mode) > GET_MODE_SIZE (reg_rtx_mode))
5047 {
5048 original_reg = regno_reg_rtx[hard_regno];
5049 mode = reg_rtx_mode;
5050 }
5051 else
5052 original_reg = gen_rtx_REG (mode, hard_regno);
5053 }
5054 else
5055 {
5056 mode = PSEUDO_REGNO_MODE (original_regno);
5057 hard_regno = reg_renumber[original_regno];
5058 nregs = hard_regno_nregs[hard_regno][mode];
5059 rclass = lra_get_allocno_class (original_regno);
5060 original_reg = regno_reg_rtx[original_regno];
5061 call_save_p = need_for_call_save_p (original_regno);
5062 }
5063 lra_assert (hard_regno >= 0);
5064 if (lra_dump_file != NULL)
5065 fprintf (lra_dump_file,
5066 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5067
5068 if (call_save_p)
5069 {
5070 mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno,
5071 hard_regno_nregs[hard_regno][mode],
5072 mode);
5073 new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save");
5074 }
5075 else
5076 {
5077 rclass = choose_split_class (rclass, hard_regno, mode);
5078 if (rclass == NO_REGS)
5079 {
5080 if (lra_dump_file != NULL)
5081 {
5082 fprintf (lra_dump_file,
5083 " Rejecting split of %d(%s): "
5084 "no good reg class for %d(%s)\n",
5085 original_regno,
5086 reg_class_names[lra_get_allocno_class (original_regno)],
5087 hard_regno,
5088 reg_class_names[REGNO_REG_CLASS (hard_regno)]);
5089 fprintf
5090 (lra_dump_file,
5091 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5092 }
5093 return false;
5094 }
5095 new_reg = lra_create_new_reg (mode, original_reg, rclass, "split");
5096 reg_renumber[REGNO (new_reg)] = hard_regno;
5097 }
5098 save = emit_spill_move (true, new_reg, original_reg);
5099 if (NEXT_INSN (save) != NULL_RTX && !call_save_p)
5100 {
5101 if (lra_dump_file != NULL)
5102 {
5103 fprintf
5104 (lra_dump_file,
5105 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5106 original_regno, REGNO (new_reg));
5107 dump_rtl_slim (lra_dump_file, save, NULL, -1, 0);
5108 fprintf (lra_dump_file,
5109 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5110 }
5111 return false;
5112 }
5113 restore = emit_spill_move (false, new_reg, original_reg);
5114 if (NEXT_INSN (restore) != NULL_RTX && !call_save_p)
5115 {
5116 if (lra_dump_file != NULL)
5117 {
5118 fprintf (lra_dump_file,
5119 " Rejecting split %d->%d "
5120 "resulting in > 2 restore insns:\n",
5121 original_regno, REGNO (new_reg));
5122 dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0);
5123 fprintf (lra_dump_file,
5124 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5125 }
5126 return false;
5127 }
5128 after_p = usage_insns[original_regno].after_p;
5129 lra_reg_info[REGNO (new_reg)].restore_regno = original_regno;
5130 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5131 bitmap_set_bit (&check_only_regs, original_regno);
5132 bitmap_set_bit (&lra_split_regs, REGNO (new_reg));
5133 for (;;)
5134 {
5135 if (GET_CODE (next_usage_insns) != INSN_LIST)
5136 {
5137 usage_insn = next_usage_insns;
5138 break;
5139 }
5140 usage_insn = XEXP (next_usage_insns, 0);
5141 lra_assert (DEBUG_INSN_P (usage_insn));
5142 next_usage_insns = XEXP (next_usage_insns, 1);
5143 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false);
5144 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5145 if (lra_dump_file != NULL)
5146 {
5147 fprintf (lra_dump_file, " Split reuse change %d->%d:\n",
5148 original_regno, REGNO (new_reg));
5149 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5150 }
5151 }
5152 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn));
5153 lra_assert (usage_insn != insn || (after_p && before_p));
5154 lra_process_new_insns (as_a <rtx_insn *> (usage_insn),
5155 after_p ? NULL : restore,
5156 after_p ? restore : NULL,
5157 call_save_p
5158 ? "Add reg<-save" : "Add reg<-split");
5159 lra_process_new_insns (insn, before_p ? save : NULL,
5160 before_p ? NULL : save,
5161 call_save_p
5162 ? "Add save<-reg" : "Add split<-reg");
5163 if (nregs > 1)
5164 /* If we are trying to split multi-register. We should check
5165 conflicts on the next assignment sub-pass. IRA can allocate on
5166 sub-register levels, LRA do this on pseudos level right now and
5167 this discrepancy may create allocation conflicts after
5168 splitting. */
5169 lra_risky_transformations_p = true;
5170 if (lra_dump_file != NULL)
5171 fprintf (lra_dump_file,
5172 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5173 return true;
5174 }
5175
5176 /* Recognize that we need a split transformation for insn INSN, which
5177 defines or uses REGNO in its insn biggest MODE (we use it only if
5178 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5179 hard registers which might be used for reloads since the EBB end.
5180 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5181 uid before starting INSN processing. Return true if we succeed in
5182 such transformation. */
5183 static bool
split_if_necessary(int regno,machine_mode mode,HARD_REG_SET potential_reload_hard_regs,bool before_p,rtx_insn * insn,int max_uid)5184 split_if_necessary (int regno, machine_mode mode,
5185 HARD_REG_SET potential_reload_hard_regs,
5186 bool before_p, rtx_insn *insn, int max_uid)
5187 {
5188 bool res = false;
5189 int i, nregs = 1;
5190 rtx next_usage_insns;
5191
5192 if (regno < FIRST_PSEUDO_REGISTER)
5193 nregs = hard_regno_nregs[regno][mode];
5194 for (i = 0; i < nregs; i++)
5195 if (usage_insns[regno + i].check == curr_usage_insns_check
5196 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX
5197 /* To avoid processing the register twice or more. */
5198 && ((GET_CODE (next_usage_insns) != INSN_LIST
5199 && INSN_UID (next_usage_insns) < max_uid)
5200 || (GET_CODE (next_usage_insns) == INSN_LIST
5201 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid)))
5202 && need_for_split_p (potential_reload_hard_regs, regno + i)
5203 && split_reg (before_p, regno + i, insn, next_usage_insns))
5204 res = true;
5205 return res;
5206 }
5207
5208 /* Check only registers living at the current program point in the
5209 current EBB. */
5210 static bitmap_head live_regs;
5211
5212 /* Update live info in EBB given by its HEAD and TAIL insns after
5213 inheritance/split transformation. The function removes dead moves
5214 too. */
5215 static void
update_ebb_live_info(rtx_insn * head,rtx_insn * tail)5216 update_ebb_live_info (rtx_insn *head, rtx_insn *tail)
5217 {
5218 unsigned int j;
5219 int i, regno;
5220 bool live_p;
5221 rtx_insn *prev_insn;
5222 rtx set;
5223 bool remove_p;
5224 basic_block last_bb, prev_bb, curr_bb;
5225 bitmap_iterator bi;
5226 struct lra_insn_reg *reg;
5227 edge e;
5228 edge_iterator ei;
5229
5230 last_bb = BLOCK_FOR_INSN (tail);
5231 prev_bb = NULL;
5232 for (curr_insn = tail;
5233 curr_insn != PREV_INSN (head);
5234 curr_insn = prev_insn)
5235 {
5236 prev_insn = PREV_INSN (curr_insn);
5237 /* We need to process empty blocks too. They contain
5238 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5239 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK)
5240 continue;
5241 curr_bb = BLOCK_FOR_INSN (curr_insn);
5242 if (curr_bb != prev_bb)
5243 {
5244 if (prev_bb != NULL)
5245 {
5246 /* Update df_get_live_in (prev_bb): */
5247 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5248 if (bitmap_bit_p (&live_regs, j))
5249 bitmap_set_bit (df_get_live_in (prev_bb), j);
5250 else
5251 bitmap_clear_bit (df_get_live_in (prev_bb), j);
5252 }
5253 if (curr_bb != last_bb)
5254 {
5255 /* Update df_get_live_out (curr_bb): */
5256 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5257 {
5258 live_p = bitmap_bit_p (&live_regs, j);
5259 if (! live_p)
5260 FOR_EACH_EDGE (e, ei, curr_bb->succs)
5261 if (bitmap_bit_p (df_get_live_in (e->dest), j))
5262 {
5263 live_p = true;
5264 break;
5265 }
5266 if (live_p)
5267 bitmap_set_bit (df_get_live_out (curr_bb), j);
5268 else
5269 bitmap_clear_bit (df_get_live_out (curr_bb), j);
5270 }
5271 }
5272 prev_bb = curr_bb;
5273 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb));
5274 }
5275 if (! NONDEBUG_INSN_P (curr_insn))
5276 continue;
5277 curr_id = lra_get_insn_recog_data (curr_insn);
5278 curr_static_id = curr_id->insn_static_data;
5279 remove_p = false;
5280 if ((set = single_set (curr_insn)) != NULL_RTX
5281 && REG_P (SET_DEST (set))
5282 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
5283 && SET_DEST (set) != pic_offset_table_rtx
5284 && bitmap_bit_p (&check_only_regs, regno)
5285 && ! bitmap_bit_p (&live_regs, regno))
5286 remove_p = true;
5287 /* See which defined values die here. */
5288 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5289 if (reg->type == OP_OUT && ! reg->subreg_p)
5290 bitmap_clear_bit (&live_regs, reg->regno);
5291 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5292 if (reg->type == OP_OUT && ! reg->subreg_p)
5293 bitmap_clear_bit (&live_regs, reg->regno);
5294 if (curr_id->arg_hard_regs != NULL)
5295 /* Make clobbered argument hard registers die. */
5296 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5297 if (regno >= FIRST_PSEUDO_REGISTER)
5298 bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER);
5299 /* Mark each used value as live. */
5300 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5301 if (reg->type != OP_OUT
5302 && bitmap_bit_p (&check_only_regs, reg->regno))
5303 bitmap_set_bit (&live_regs, reg->regno);
5304 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5305 if (reg->type != OP_OUT
5306 && bitmap_bit_p (&check_only_regs, reg->regno))
5307 bitmap_set_bit (&live_regs, reg->regno);
5308 if (curr_id->arg_hard_regs != NULL)
5309 /* Make used argument hard registers live. */
5310 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5311 if (regno < FIRST_PSEUDO_REGISTER
5312 && bitmap_bit_p (&check_only_regs, regno))
5313 bitmap_set_bit (&live_regs, regno);
5314 /* It is quite important to remove dead move insns because it
5315 means removing dead store. We don't need to process them for
5316 constraints. */
5317 if (remove_p)
5318 {
5319 if (lra_dump_file != NULL)
5320 {
5321 fprintf (lra_dump_file, " Removing dead insn:\n ");
5322 dump_insn_slim (lra_dump_file, curr_insn);
5323 }
5324 lra_set_insn_deleted (curr_insn);
5325 }
5326 }
5327 }
5328
5329 /* The structure describes info to do an inheritance for the current
5330 insn. We need to collect such info first before doing the
5331 transformations because the transformations change the insn
5332 internal representation. */
5333 struct to_inherit
5334 {
5335 /* Original regno. */
5336 int regno;
5337 /* Subsequent insns which can inherit original reg value. */
5338 rtx insns;
5339 };
5340
5341 /* Array containing all info for doing inheritance from the current
5342 insn. */
5343 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS];
5344
5345 /* Number elements in the previous array. */
5346 static int to_inherit_num;
5347
5348 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5349 structure to_inherit. */
5350 static void
add_to_inherit(int regno,rtx insns)5351 add_to_inherit (int regno, rtx insns)
5352 {
5353 int i;
5354
5355 for (i = 0; i < to_inherit_num; i++)
5356 if (to_inherit[i].regno == regno)
5357 return;
5358 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS);
5359 to_inherit[to_inherit_num].regno = regno;
5360 to_inherit[to_inherit_num++].insns = insns;
5361 }
5362
5363 /* Return the last non-debug insn in basic block BB, or the block begin
5364 note if none. */
5365 static rtx_insn *
get_last_insertion_point(basic_block bb)5366 get_last_insertion_point (basic_block bb)
5367 {
5368 rtx_insn *insn;
5369
5370 FOR_BB_INSNS_REVERSE (bb, insn)
5371 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn))
5372 return insn;
5373 gcc_unreachable ();
5374 }
5375
5376 /* Set up RES by registers living on edges FROM except the edge (FROM,
5377 TO) or by registers set up in a jump insn in BB FROM. */
5378 static void
get_live_on_other_edges(basic_block from,basic_block to,bitmap res)5379 get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
5380 {
5381 rtx_insn *last;
5382 struct lra_insn_reg *reg;
5383 edge e;
5384 edge_iterator ei;
5385
5386 lra_assert (to != NULL);
5387 bitmap_clear (res);
5388 FOR_EACH_EDGE (e, ei, from->succs)
5389 if (e->dest != to)
5390 bitmap_ior_into (res, df_get_live_in (e->dest));
5391 last = get_last_insertion_point (from);
5392 if (! JUMP_P (last))
5393 return;
5394 curr_id = lra_get_insn_recog_data (last);
5395 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5396 if (reg->type != OP_IN)
5397 bitmap_set_bit (res, reg->regno);
5398 }
5399
5400 /* Used as a temporary results of some bitmap calculations. */
5401 static bitmap_head temp_bitmap;
5402
5403 /* We split for reloads of small class of hard regs. The following
5404 defines how many hard regs the class should have to be qualified as
5405 small. The code is mostly oriented to x86/x86-64 architecture
5406 where some insns need to use only specific register or pair of
5407 registers and these register can live in RTL explicitly, e.g. for
5408 parameter passing. */
5409 static const int max_small_class_regs_num = 2;
5410
5411 /* Do inheritance/split transformations in EBB starting with HEAD and
5412 finishing on TAIL. We process EBB insns in the reverse order.
5413 Return true if we did any inheritance/split transformation in the
5414 EBB.
5415
5416 We should avoid excessive splitting which results in worse code
5417 because of inaccurate cost calculations for spilling new split
5418 pseudos in such case. To achieve this we do splitting only if
5419 register pressure is high in given basic block and there are reload
5420 pseudos requiring hard registers. We could do more register
5421 pressure calculations at any given program point to avoid necessary
5422 splitting even more but it is to expensive and the current approach
5423 works well enough. */
5424 static bool
inherit_in_ebb(rtx_insn * head,rtx_insn * tail)5425 inherit_in_ebb (rtx_insn *head, rtx_insn *tail)
5426 {
5427 int i, src_regno, dst_regno, nregs;
5428 bool change_p, succ_p, update_reloads_num_p;
5429 rtx_insn *prev_insn, *last_insn;
5430 rtx next_usage_insns, set;
5431 enum reg_class cl;
5432 struct lra_insn_reg *reg;
5433 basic_block last_processed_bb, curr_bb = NULL;
5434 HARD_REG_SET potential_reload_hard_regs, live_hard_regs;
5435 bitmap to_process;
5436 unsigned int j;
5437 bitmap_iterator bi;
5438 bool head_p, after_p;
5439
5440 change_p = false;
5441 curr_usage_insns_check++;
5442 reloads_num = calls_num = 0;
5443 bitmap_clear (&check_only_regs);
5444 last_processed_bb = NULL;
5445 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
5446 COPY_HARD_REG_SET (live_hard_regs, eliminable_regset);
5447 IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
5448 /* We don't process new insns generated in the loop. */
5449 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
5450 {
5451 prev_insn = PREV_INSN (curr_insn);
5452 if (BLOCK_FOR_INSN (curr_insn) != NULL)
5453 curr_bb = BLOCK_FOR_INSN (curr_insn);
5454 if (last_processed_bb != curr_bb)
5455 {
5456 /* We are at the end of BB. Add qualified living
5457 pseudos for potential splitting. */
5458 to_process = df_get_live_out (curr_bb);
5459 if (last_processed_bb != NULL)
5460 {
5461 /* We are somewhere in the middle of EBB. */
5462 get_live_on_other_edges (curr_bb, last_processed_bb,
5463 &temp_bitmap);
5464 to_process = &temp_bitmap;
5465 }
5466 last_processed_bb = curr_bb;
5467 last_insn = get_last_insertion_point (curr_bb);
5468 after_p = (! JUMP_P (last_insn)
5469 && (! CALL_P (last_insn)
5470 || (find_reg_note (last_insn,
5471 REG_NORETURN, NULL_RTX) == NULL_RTX
5472 && ! SIBLING_CALL_P (last_insn))));
5473 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
5474 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
5475 {
5476 if ((int) j >= lra_constraint_new_regno_start)
5477 break;
5478 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
5479 {
5480 if (j < FIRST_PSEUDO_REGISTER)
5481 SET_HARD_REG_BIT (live_hard_regs, j);
5482 else
5483 add_to_hard_reg_set (&live_hard_regs,
5484 PSEUDO_REGNO_MODE (j),
5485 reg_renumber[j]);
5486 setup_next_usage_insn (j, last_insn, reloads_num, after_p);
5487 }
5488 }
5489 }
5490 src_regno = dst_regno = -1;
5491 if (NONDEBUG_INSN_P (curr_insn)
5492 && (set = single_set (curr_insn)) != NULL_RTX
5493 && REG_P (SET_DEST (set)) && REG_P (SET_SRC (set)))
5494 {
5495 src_regno = REGNO (SET_SRC (set));
5496 dst_regno = REGNO (SET_DEST (set));
5497 }
5498 update_reloads_num_p = true;
5499 if (src_regno < lra_constraint_new_regno_start
5500 && src_regno >= FIRST_PSEUDO_REGISTER
5501 && reg_renumber[src_regno] < 0
5502 && dst_regno >= lra_constraint_new_regno_start
5503 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
5504 {
5505 /* 'reload_pseudo <- original_pseudo'. */
5506 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
5507 reloads_num++;
5508 update_reloads_num_p = false;
5509 succ_p = false;
5510 if (usage_insns[src_regno].check == curr_usage_insns_check
5511 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX)
5512 succ_p = inherit_reload_reg (false, src_regno, cl,
5513 curr_insn, next_usage_insns);
5514 if (succ_p)
5515 change_p = true;
5516 else
5517 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
5518 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
5519 IOR_HARD_REG_SET (potential_reload_hard_regs,
5520 reg_class_contents[cl]);
5521 }
5522 else if (src_regno >= lra_constraint_new_regno_start
5523 && dst_regno < lra_constraint_new_regno_start
5524 && dst_regno >= FIRST_PSEUDO_REGISTER
5525 && reg_renumber[dst_regno] < 0
5526 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS
5527 && usage_insns[dst_regno].check == curr_usage_insns_check
5528 && (next_usage_insns
5529 = usage_insns[dst_regno].insns) != NULL_RTX)
5530 {
5531 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
5532 reloads_num++;
5533 update_reloads_num_p = false;
5534 /* 'original_pseudo <- reload_pseudo'. */
5535 if (! JUMP_P (curr_insn)
5536 && inherit_reload_reg (true, dst_regno, cl,
5537 curr_insn, next_usage_insns))
5538 change_p = true;
5539 /* Invalidate. */
5540 usage_insns[dst_regno].check = 0;
5541 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
5542 IOR_HARD_REG_SET (potential_reload_hard_regs,
5543 reg_class_contents[cl]);
5544 }
5545 else if (INSN_P (curr_insn))
5546 {
5547 int iter;
5548 int max_uid = get_max_uid ();
5549
5550 curr_id = lra_get_insn_recog_data (curr_insn);
5551 curr_static_id = curr_id->insn_static_data;
5552 to_inherit_num = 0;
5553 /* Process insn definitions. */
5554 for (iter = 0; iter < 2; iter++)
5555 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
5556 reg != NULL;
5557 reg = reg->next)
5558 if (reg->type != OP_IN
5559 && (dst_regno = reg->regno) < lra_constraint_new_regno_start)
5560 {
5561 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT
5562 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p
5563 && usage_insns[dst_regno].check == curr_usage_insns_check
5564 && (next_usage_insns
5565 = usage_insns[dst_regno].insns) != NULL_RTX)
5566 {
5567 struct lra_insn_reg *r;
5568
5569 for (r = curr_id->regs; r != NULL; r = r->next)
5570 if (r->type != OP_OUT && r->regno == dst_regno)
5571 break;
5572 /* Don't do inheritance if the pseudo is also
5573 used in the insn. */
5574 if (r == NULL)
5575 /* We can not do inheritance right now
5576 because the current insn reg info (chain
5577 regs) can change after that. */
5578 add_to_inherit (dst_regno, next_usage_insns);
5579 }
5580 /* We can not process one reg twice here because of
5581 usage_insns invalidation. */
5582 if ((dst_regno < FIRST_PSEUDO_REGISTER
5583 || reg_renumber[dst_regno] >= 0)
5584 && ! reg->subreg_p && reg->type != OP_IN)
5585 {
5586 HARD_REG_SET s;
5587
5588 if (split_if_necessary (dst_regno, reg->biggest_mode,
5589 potential_reload_hard_regs,
5590 false, curr_insn, max_uid))
5591 change_p = true;
5592 CLEAR_HARD_REG_SET (s);
5593 if (dst_regno < FIRST_PSEUDO_REGISTER)
5594 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
5595 else
5596 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
5597 reg_renumber[dst_regno]);
5598 AND_COMPL_HARD_REG_SET (live_hard_regs, s);
5599 }
5600 /* We should invalidate potential inheritance or
5601 splitting for the current insn usages to the next
5602 usage insns (see code below) as the output pseudo
5603 prevents this. */
5604 if ((dst_regno >= FIRST_PSEUDO_REGISTER
5605 && reg_renumber[dst_regno] < 0)
5606 || (reg->type == OP_OUT && ! reg->subreg_p
5607 && (dst_regno < FIRST_PSEUDO_REGISTER
5608 || reg_renumber[dst_regno] >= 0)))
5609 {
5610 /* Invalidate and mark definitions. */
5611 if (dst_regno >= FIRST_PSEUDO_REGISTER)
5612 usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn);
5613 else
5614 {
5615 nregs = hard_regno_nregs[dst_regno][reg->biggest_mode];
5616 for (i = 0; i < nregs; i++)
5617 usage_insns[dst_regno + i].check
5618 = -(int) INSN_UID (curr_insn);
5619 }
5620 }
5621 }
5622 /* Process clobbered call regs. */
5623 if (curr_id->arg_hard_regs != NULL)
5624 for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5625 if (dst_regno >= FIRST_PSEUDO_REGISTER)
5626 usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check
5627 = -(int) INSN_UID (curr_insn);
5628 if (! JUMP_P (curr_insn))
5629 for (i = 0; i < to_inherit_num; i++)
5630 if (inherit_reload_reg (true, to_inherit[i].regno,
5631 ALL_REGS, curr_insn,
5632 to_inherit[i].insns))
5633 change_p = true;
5634 if (CALL_P (curr_insn))
5635 {
5636 rtx cheap, pat, dest;
5637 rtx_insn *restore;
5638 int regno, hard_regno;
5639
5640 calls_num++;
5641 if ((cheap = find_reg_note (curr_insn,
5642 REG_RETURNED, NULL_RTX)) != NULL_RTX
5643 && ((cheap = XEXP (cheap, 0)), true)
5644 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
5645 && (hard_regno = reg_renumber[regno]) >= 0
5646 /* If there are pending saves/restores, the
5647 optimization is not worth. */
5648 && usage_insns[regno].calls_num == calls_num - 1
5649 && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno))
5650 {
5651 /* Restore the pseudo from the call result as
5652 REG_RETURNED note says that the pseudo value is
5653 in the call result and the pseudo is an argument
5654 of the call. */
5655 pat = PATTERN (curr_insn);
5656 if (GET_CODE (pat) == PARALLEL)
5657 pat = XVECEXP (pat, 0, 0);
5658 dest = SET_DEST (pat);
5659 /* For multiple return values dest is PARALLEL.
5660 Currently we handle only single return value case. */
5661 if (REG_P (dest))
5662 {
5663 start_sequence ();
5664 emit_move_insn (cheap, copy_rtx (dest));
5665 restore = get_insns ();
5666 end_sequence ();
5667 lra_process_new_insns (curr_insn, NULL, restore,
5668 "Inserting call parameter restore");
5669 /* We don't need to save/restore of the pseudo from
5670 this call. */
5671 usage_insns[regno].calls_num = calls_num;
5672 bitmap_set_bit (&check_only_regs, regno);
5673 }
5674 }
5675 }
5676 to_inherit_num = 0;
5677 /* Process insn usages. */
5678 for (iter = 0; iter < 2; iter++)
5679 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
5680 reg != NULL;
5681 reg = reg->next)
5682 if ((reg->type != OP_OUT
5683 || (reg->type == OP_OUT && reg->subreg_p))
5684 && (src_regno = reg->regno) < lra_constraint_new_regno_start)
5685 {
5686 if (src_regno >= FIRST_PSEUDO_REGISTER
5687 && reg_renumber[src_regno] < 0 && reg->type == OP_IN)
5688 {
5689 if (usage_insns[src_regno].check == curr_usage_insns_check
5690 && (next_usage_insns
5691 = usage_insns[src_regno].insns) != NULL_RTX
5692 && NONDEBUG_INSN_P (curr_insn))
5693 add_to_inherit (src_regno, next_usage_insns);
5694 else if (usage_insns[src_regno].check
5695 != -(int) INSN_UID (curr_insn))
5696 /* Add usages but only if the reg is not set up
5697 in the same insn. */
5698 add_next_usage_insn (src_regno, curr_insn, reloads_num);
5699 }
5700 else if (src_regno < FIRST_PSEUDO_REGISTER
5701 || reg_renumber[src_regno] >= 0)
5702 {
5703 bool before_p;
5704 rtx_insn *use_insn = curr_insn;
5705
5706 before_p = (JUMP_P (curr_insn)
5707 || (CALL_P (curr_insn) && reg->type == OP_IN));
5708 if (NONDEBUG_INSN_P (curr_insn)
5709 && (! JUMP_P (curr_insn) || reg->type == OP_IN)
5710 && split_if_necessary (src_regno, reg->biggest_mode,
5711 potential_reload_hard_regs,
5712 before_p, curr_insn, max_uid))
5713 {
5714 if (reg->subreg_p)
5715 lra_risky_transformations_p = true;
5716 change_p = true;
5717 /* Invalidate. */
5718 usage_insns[src_regno].check = 0;
5719 if (before_p)
5720 use_insn = PREV_INSN (curr_insn);
5721 }
5722 if (NONDEBUG_INSN_P (curr_insn))
5723 {
5724 if (src_regno < FIRST_PSEUDO_REGISTER)
5725 add_to_hard_reg_set (&live_hard_regs,
5726 reg->biggest_mode, src_regno);
5727 else
5728 add_to_hard_reg_set (&live_hard_regs,
5729 PSEUDO_REGNO_MODE (src_regno),
5730 reg_renumber[src_regno]);
5731 }
5732 add_next_usage_insn (src_regno, use_insn, reloads_num);
5733 }
5734 }
5735 /* Process used call regs. */
5736 if (curr_id->arg_hard_regs != NULL)
5737 for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5738 if (src_regno < FIRST_PSEUDO_REGISTER)
5739 {
5740 SET_HARD_REG_BIT (live_hard_regs, src_regno);
5741 add_next_usage_insn (src_regno, curr_insn, reloads_num);
5742 }
5743 for (i = 0; i < to_inherit_num; i++)
5744 {
5745 src_regno = to_inherit[i].regno;
5746 if (inherit_reload_reg (false, src_regno, ALL_REGS,
5747 curr_insn, to_inherit[i].insns))
5748 change_p = true;
5749 else
5750 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
5751 }
5752 }
5753 if (update_reloads_num_p
5754 && NONDEBUG_INSN_P (curr_insn)
5755 && (set = single_set (curr_insn)) != NULL_RTX)
5756 {
5757 int regno = -1;
5758 if ((REG_P (SET_DEST (set))
5759 && (regno = REGNO (SET_DEST (set))) >= lra_constraint_new_regno_start
5760 && reg_renumber[regno] < 0
5761 && (cl = lra_get_allocno_class (regno)) != NO_REGS)
5762 || (REG_P (SET_SRC (set))
5763 && (regno = REGNO (SET_SRC (set))) >= lra_constraint_new_regno_start
5764 && reg_renumber[regno] < 0
5765 && (cl = lra_get_allocno_class (regno)) != NO_REGS))
5766 {
5767 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
5768 reloads_num++;
5769 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
5770 IOR_HARD_REG_SET (potential_reload_hard_regs,
5771 reg_class_contents[cl]);
5772 }
5773 }
5774 /* We reached the start of the current basic block. */
5775 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head)
5776 || BLOCK_FOR_INSN (prev_insn) != curr_bb)
5777 {
5778 /* We reached the beginning of the current block -- do
5779 rest of spliting in the current BB. */
5780 to_process = df_get_live_in (curr_bb);
5781 if (BLOCK_FOR_INSN (head) != curr_bb)
5782 {
5783 /* We are somewhere in the middle of EBB. */
5784 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src,
5785 curr_bb, &temp_bitmap);
5786 to_process = &temp_bitmap;
5787 }
5788 head_p = true;
5789 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
5790 {
5791 if ((int) j >= lra_constraint_new_regno_start)
5792 break;
5793 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
5794 && usage_insns[j].check == curr_usage_insns_check
5795 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX)
5796 {
5797 if (need_for_split_p (potential_reload_hard_regs, j))
5798 {
5799 if (lra_dump_file != NULL && head_p)
5800 {
5801 fprintf (lra_dump_file,
5802 " ----------------------------------\n");
5803 head_p = false;
5804 }
5805 if (split_reg (false, j, bb_note (curr_bb),
5806 next_usage_insns))
5807 change_p = true;
5808 }
5809 usage_insns[j].check = 0;
5810 }
5811 }
5812 }
5813 }
5814 return change_p;
5815 }
5816
5817 /* This value affects EBB forming. If probability of edge from EBB to
5818 a BB is not greater than the following value, we don't add the BB
5819 to EBB. */
5820 #define EBB_PROBABILITY_CUTOFF \
5821 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
5822
5823 /* Current number of inheritance/split iteration. */
5824 int lra_inheritance_iter;
5825
5826 /* Entry function for inheritance/split pass. */
5827 void
lra_inheritance(void)5828 lra_inheritance (void)
5829 {
5830 int i;
5831 basic_block bb, start_bb;
5832 edge e;
5833
5834 lra_inheritance_iter++;
5835 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
5836 return;
5837 timevar_push (TV_LRA_INHERITANCE);
5838 if (lra_dump_file != NULL)
5839 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n",
5840 lra_inheritance_iter);
5841 curr_usage_insns_check = 0;
5842 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start);
5843 for (i = 0; i < lra_constraint_new_regno_start; i++)
5844 usage_insns[i].check = 0;
5845 bitmap_initialize (&check_only_regs, ®_obstack);
5846 bitmap_initialize (&live_regs, ®_obstack);
5847 bitmap_initialize (&temp_bitmap, ®_obstack);
5848 bitmap_initialize (&ebb_global_regs, ®_obstack);
5849 FOR_EACH_BB_FN (bb, cfun)
5850 {
5851 start_bb = bb;
5852 if (lra_dump_file != NULL)
5853 fprintf (lra_dump_file, "EBB");
5854 /* Form a EBB starting with BB. */
5855 bitmap_clear (&ebb_global_regs);
5856 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb));
5857 for (;;)
5858 {
5859 if (lra_dump_file != NULL)
5860 fprintf (lra_dump_file, " %d", bb->index);
5861 if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
5862 || LABEL_P (BB_HEAD (bb->next_bb)))
5863 break;
5864 e = find_fallthru_edge (bb->succs);
5865 if (! e)
5866 break;
5867 if (e->probability < EBB_PROBABILITY_CUTOFF)
5868 break;
5869 bb = bb->next_bb;
5870 }
5871 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb));
5872 if (lra_dump_file != NULL)
5873 fprintf (lra_dump_file, "\n");
5874 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
5875 /* Remember that the EBB head and tail can change in
5876 inherit_in_ebb. */
5877 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
5878 }
5879 bitmap_clear (&ebb_global_regs);
5880 bitmap_clear (&temp_bitmap);
5881 bitmap_clear (&live_regs);
5882 bitmap_clear (&check_only_regs);
5883 free (usage_insns);
5884
5885 timevar_pop (TV_LRA_INHERITANCE);
5886 }
5887
5888
5889
5890 /* This page contains code to undo failed inheritance/split
5891 transformations. */
5892
5893 /* Current number of iteration undoing inheritance/split. */
5894 int lra_undo_inheritance_iter;
5895
5896 /* Fix BB live info LIVE after removing pseudos created on pass doing
5897 inheritance/split which are REMOVED_PSEUDOS. */
5898 static void
fix_bb_live_info(bitmap live,bitmap removed_pseudos)5899 fix_bb_live_info (bitmap live, bitmap removed_pseudos)
5900 {
5901 unsigned int regno;
5902 bitmap_iterator bi;
5903
5904 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi)
5905 if (bitmap_clear_bit (live, regno))
5906 bitmap_set_bit (live, lra_reg_info[regno].restore_regno);
5907 }
5908
5909 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5910 number. */
5911 static int
get_regno(rtx reg)5912 get_regno (rtx reg)
5913 {
5914 if (GET_CODE (reg) == SUBREG)
5915 reg = SUBREG_REG (reg);
5916 if (REG_P (reg))
5917 return REGNO (reg);
5918 return -1;
5919 }
5920
5921 /* Delete a move INSN with destination reg DREGNO and a previous
5922 clobber insn with the same regno. The inheritance/split code can
5923 generate moves with preceding clobber and when we delete such moves
5924 we should delete the clobber insn too to keep the correct life
5925 info. */
5926 static void
delete_move_and_clobber(rtx_insn * insn,int dregno)5927 delete_move_and_clobber (rtx_insn *insn, int dregno)
5928 {
5929 rtx_insn *prev_insn = PREV_INSN (insn);
5930
5931 lra_set_insn_deleted (insn);
5932 lra_assert (dregno >= 0);
5933 if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn)
5934 && GET_CODE (PATTERN (prev_insn)) == CLOBBER
5935 && dregno == get_regno (XEXP (PATTERN (prev_insn), 0)))
5936 lra_set_insn_deleted (prev_insn);
5937 }
5938
5939 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5940 return true if we did any change. The undo transformations for
5941 inheritance looks like
5942 i <- i2
5943 p <- i => p <- i2
5944 or removing
5945 p <- i, i <- p, and i <- i3
5946 where p is original pseudo from which inheritance pseudo i was
5947 created, i and i3 are removed inheritance pseudos, i2 is another
5948 not removed inheritance pseudo. All split pseudos or other
5949 occurrences of removed inheritance pseudos are changed on the
5950 corresponding original pseudos.
5951
5952 The function also schedules insns changed and created during
5953 inheritance/split pass for processing by the subsequent constraint
5954 pass. */
5955 static bool
remove_inheritance_pseudos(bitmap remove_pseudos)5956 remove_inheritance_pseudos (bitmap remove_pseudos)
5957 {
5958 basic_block bb;
5959 int regno, sregno, prev_sregno, dregno, restore_regno;
5960 rtx set, prev_set;
5961 rtx_insn *prev_insn;
5962 bool change_p, done_p;
5963
5964 change_p = ! bitmap_empty_p (remove_pseudos);
5965 /* We can not finish the function right away if CHANGE_P is true
5966 because we need to marks insns affected by previous
5967 inheritance/split pass for processing by the subsequent
5968 constraint pass. */
5969 FOR_EACH_BB_FN (bb, cfun)
5970 {
5971 fix_bb_live_info (df_get_live_in (bb), remove_pseudos);
5972 fix_bb_live_info (df_get_live_out (bb), remove_pseudos);
5973 FOR_BB_INSNS_REVERSE (bb, curr_insn)
5974 {
5975 if (! INSN_P (curr_insn))
5976 continue;
5977 done_p = false;
5978 sregno = dregno = -1;
5979 if (change_p && NONDEBUG_INSN_P (curr_insn)
5980 && (set = single_set (curr_insn)) != NULL_RTX)
5981 {
5982 dregno = get_regno (SET_DEST (set));
5983 sregno = get_regno (SET_SRC (set));
5984 }
5985
5986 if (sregno >= 0 && dregno >= 0)
5987 {
5988 if ((bitmap_bit_p (remove_pseudos, sregno)
5989 && (lra_reg_info[sregno].restore_regno == dregno
5990 || (bitmap_bit_p (remove_pseudos, dregno)
5991 && (lra_reg_info[sregno].restore_regno
5992 == lra_reg_info[dregno].restore_regno))))
5993 || (bitmap_bit_p (remove_pseudos, dregno)
5994 && lra_reg_info[dregno].restore_regno == sregno))
5995 /* One of the following cases:
5996 original <- removed inheritance pseudo
5997 removed inherit pseudo <- another removed inherit pseudo
5998 removed inherit pseudo <- original pseudo
5999 Or
6000 removed_split_pseudo <- original_reg
6001 original_reg <- removed_split_pseudo */
6002 {
6003 if (lra_dump_file != NULL)
6004 {
6005 fprintf (lra_dump_file, " Removing %s:\n",
6006 bitmap_bit_p (&lra_split_regs, sregno)
6007 || bitmap_bit_p (&lra_split_regs, dregno)
6008 ? "split" : "inheritance");
6009 dump_insn_slim (lra_dump_file, curr_insn);
6010 }
6011 delete_move_and_clobber (curr_insn, dregno);
6012 done_p = true;
6013 }
6014 else if (bitmap_bit_p (remove_pseudos, sregno)
6015 && bitmap_bit_p (&lra_inheritance_pseudos, sregno))
6016 {
6017 /* Search the following pattern:
6018 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6019 original_pseudo <- inherit_or_split_pseudo1
6020 where the 2nd insn is the current insn and
6021 inherit_or_split_pseudo2 is not removed. If it is found,
6022 change the current insn onto:
6023 original_pseudo <- inherit_or_split_pseudo2. */
6024 for (prev_insn = PREV_INSN (curr_insn);
6025 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn);
6026 prev_insn = PREV_INSN (prev_insn))
6027 ;
6028 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb
6029 && (prev_set = single_set (prev_insn)) != NULL_RTX
6030 /* There should be no subregs in insn we are
6031 searching because only the original reg might
6032 be in subreg when we changed the mode of
6033 load/store for splitting. */
6034 && REG_P (SET_DEST (prev_set))
6035 && REG_P (SET_SRC (prev_set))
6036 && (int) REGNO (SET_DEST (prev_set)) == sregno
6037 && ((prev_sregno = REGNO (SET_SRC (prev_set)))
6038 >= FIRST_PSEUDO_REGISTER)
6039 /* As we consider chain of inheritance or
6040 splitting described in above comment we should
6041 check that sregno and prev_sregno were
6042 inheritance/split pseudos created from the
6043 same original regno. */
6044 && (lra_reg_info[sregno].restore_regno
6045 == lra_reg_info[prev_sregno].restore_regno)
6046 && ! bitmap_bit_p (remove_pseudos, prev_sregno))
6047 {
6048 lra_assert (GET_MODE (SET_SRC (prev_set))
6049 == GET_MODE (regno_reg_rtx[sregno]));
6050 if (GET_CODE (SET_SRC (set)) == SUBREG)
6051 SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set);
6052 else
6053 SET_SRC (set) = SET_SRC (prev_set);
6054 /* As we are finishing with processing the insn
6055 here, check the destination too as it might
6056 inheritance pseudo for another pseudo. */
6057 if (bitmap_bit_p (remove_pseudos, dregno)
6058 && bitmap_bit_p (&lra_inheritance_pseudos, dregno)
6059 && (restore_regno
6060 = lra_reg_info[dregno].restore_regno) >= 0)
6061 {
6062 if (GET_CODE (SET_DEST (set)) == SUBREG)
6063 SUBREG_REG (SET_DEST (set))
6064 = regno_reg_rtx[restore_regno];
6065 else
6066 SET_DEST (set) = regno_reg_rtx[restore_regno];
6067 }
6068 lra_push_insn_and_update_insn_regno_info (curr_insn);
6069 lra_set_used_insn_alternative_by_uid
6070 (INSN_UID (curr_insn), -1);
6071 done_p = true;
6072 if (lra_dump_file != NULL)
6073 {
6074 fprintf (lra_dump_file, " Change reload insn:\n");
6075 dump_insn_slim (lra_dump_file, curr_insn);
6076 }
6077 }
6078 }
6079 }
6080 if (! done_p)
6081 {
6082 struct lra_insn_reg *reg;
6083 bool restored_regs_p = false;
6084 bool kept_regs_p = false;
6085
6086 curr_id = lra_get_insn_recog_data (curr_insn);
6087 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6088 {
6089 regno = reg->regno;
6090 restore_regno = lra_reg_info[regno].restore_regno;
6091 if (restore_regno >= 0)
6092 {
6093 if (change_p && bitmap_bit_p (remove_pseudos, regno))
6094 {
6095 lra_substitute_pseudo_within_insn
6096 (curr_insn, regno, regno_reg_rtx[restore_regno],
6097 false);
6098 restored_regs_p = true;
6099 }
6100 else
6101 kept_regs_p = true;
6102 }
6103 }
6104 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p)
6105 {
6106 /* The instruction has changed since the previous
6107 constraints pass. */
6108 lra_push_insn_and_update_insn_regno_info (curr_insn);
6109 lra_set_used_insn_alternative_by_uid
6110 (INSN_UID (curr_insn), -1);
6111 }
6112 else if (restored_regs_p)
6113 /* The instruction has been restored to the form that
6114 it had during the previous constraints pass. */
6115 lra_update_insn_regno_info (curr_insn);
6116 if (restored_regs_p && lra_dump_file != NULL)
6117 {
6118 fprintf (lra_dump_file, " Insn after restoring regs:\n");
6119 dump_insn_slim (lra_dump_file, curr_insn);
6120 }
6121 }
6122 }
6123 }
6124 return change_p;
6125 }
6126
6127 /* If optional reload pseudos failed to get a hard register or was not
6128 inherited, it is better to remove optional reloads. We do this
6129 transformation after undoing inheritance to figure out necessity to
6130 remove optional reloads easier. Return true if we do any
6131 change. */
6132 static bool
undo_optional_reloads(void)6133 undo_optional_reloads (void)
6134 {
6135 bool change_p, keep_p;
6136 unsigned int regno, uid;
6137 bitmap_iterator bi, bi2;
6138 rtx_insn *insn;
6139 rtx set, src, dest;
6140 bitmap_head removed_optional_reload_pseudos, insn_bitmap;
6141
6142 bitmap_initialize (&removed_optional_reload_pseudos, ®_obstack);
6143 bitmap_copy (&removed_optional_reload_pseudos, &lra_optional_reload_pseudos);
6144 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
6145 {
6146 keep_p = false;
6147 /* Keep optional reloads from previous subpasses. */
6148 if (lra_reg_info[regno].restore_regno < 0
6149 /* If the original pseudo changed its allocation, just
6150 removing the optional pseudo is dangerous as the original
6151 pseudo will have longer live range. */
6152 || reg_renumber[lra_reg_info[regno].restore_regno] >= 0)
6153 keep_p = true;
6154 else if (reg_renumber[regno] >= 0)
6155 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2)
6156 {
6157 insn = lra_insn_recog_data[uid]->insn;
6158 if ((set = single_set (insn)) == NULL_RTX)
6159 continue;
6160 src = SET_SRC (set);
6161 dest = SET_DEST (set);
6162 if (! REG_P (src) || ! REG_P (dest))
6163 continue;
6164 if (REGNO (dest) == regno
6165 /* Ignore insn for optional reloads itself. */
6166 && lra_reg_info[regno].restore_regno != (int) REGNO (src)
6167 /* Check only inheritance on last inheritance pass. */
6168 && (int) REGNO (src) >= new_regno_start
6169 /* Check that the optional reload was inherited. */
6170 && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src)))
6171 {
6172 keep_p = true;
6173 break;
6174 }
6175 }
6176 if (keep_p)
6177 {
6178 bitmap_clear_bit (&removed_optional_reload_pseudos, regno);
6179 if (lra_dump_file != NULL)
6180 fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno);
6181 }
6182 }
6183 change_p = ! bitmap_empty_p (&removed_optional_reload_pseudos);
6184 bitmap_initialize (&insn_bitmap, ®_obstack);
6185 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos, 0, regno, bi)
6186 {
6187 if (lra_dump_file != NULL)
6188 fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno);
6189 bitmap_copy (&insn_bitmap, &lra_reg_info[regno].insn_bitmap);
6190 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap, 0, uid, bi2)
6191 {
6192 insn = lra_insn_recog_data[uid]->insn;
6193 if ((set = single_set (insn)) != NULL_RTX)
6194 {
6195 src = SET_SRC (set);
6196 dest = SET_DEST (set);
6197 if (REG_P (src) && REG_P (dest)
6198 && ((REGNO (src) == regno
6199 && (lra_reg_info[regno].restore_regno
6200 == (int) REGNO (dest)))
6201 || (REGNO (dest) == regno
6202 && (lra_reg_info[regno].restore_regno
6203 == (int) REGNO (src)))))
6204 {
6205 if (lra_dump_file != NULL)
6206 {
6207 fprintf (lra_dump_file, " Deleting move %u\n",
6208 INSN_UID (insn));
6209 dump_insn_slim (lra_dump_file, insn);
6210 }
6211 delete_move_and_clobber (insn, REGNO (dest));
6212 continue;
6213 }
6214 /* We should not worry about generation memory-memory
6215 moves here as if the corresponding inheritance did
6216 not work (inheritance pseudo did not get a hard reg),
6217 we remove the inheritance pseudo and the optional
6218 reload. */
6219 }
6220 lra_substitute_pseudo_within_insn
6221 (insn, regno, regno_reg_rtx[lra_reg_info[regno].restore_regno],
6222 false);
6223 lra_update_insn_regno_info (insn);
6224 if (lra_dump_file != NULL)
6225 {
6226 fprintf (lra_dump_file,
6227 " Restoring original insn:\n");
6228 dump_insn_slim (lra_dump_file, insn);
6229 }
6230 }
6231 }
6232 /* Clear restore_regnos. */
6233 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
6234 lra_reg_info[regno].restore_regno = -1;
6235 bitmap_clear (&insn_bitmap);
6236 bitmap_clear (&removed_optional_reload_pseudos);
6237 return change_p;
6238 }
6239
6240 /* Entry function for undoing inheritance/split transformation. Return true
6241 if we did any RTL change in this pass. */
6242 bool
lra_undo_inheritance(void)6243 lra_undo_inheritance (void)
6244 {
6245 unsigned int regno;
6246 int restore_regno, hard_regno;
6247 int n_all_inherit, n_inherit, n_all_split, n_split;
6248 bitmap_head remove_pseudos;
6249 bitmap_iterator bi;
6250 bool change_p;
6251
6252 lra_undo_inheritance_iter++;
6253 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
6254 return false;
6255 if (lra_dump_file != NULL)
6256 fprintf (lra_dump_file,
6257 "\n********** Undoing inheritance #%d: **********\n\n",
6258 lra_undo_inheritance_iter);
6259 bitmap_initialize (&remove_pseudos, ®_obstack);
6260 n_inherit = n_all_inherit = 0;
6261 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
6262 if (lra_reg_info[regno].restore_regno >= 0)
6263 {
6264 n_all_inherit++;
6265 if (reg_renumber[regno] < 0
6266 /* If the original pseudo changed its allocation, just
6267 removing inheritance is dangerous as for changing
6268 allocation we used shorter live-ranges. */
6269 && reg_renumber[lra_reg_info[regno].restore_regno] < 0)
6270 bitmap_set_bit (&remove_pseudos, regno);
6271 else
6272 n_inherit++;
6273 }
6274 if (lra_dump_file != NULL && n_all_inherit != 0)
6275 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n",
6276 n_inherit, n_all_inherit,
6277 (double) n_inherit / n_all_inherit * 100);
6278 n_split = n_all_split = 0;
6279 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
6280 if ((restore_regno = lra_reg_info[regno].restore_regno) >= 0)
6281 {
6282 n_all_split++;
6283 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER
6284 ? reg_renumber[restore_regno] : restore_regno);
6285 if (hard_regno < 0 || reg_renumber[regno] == hard_regno)
6286 bitmap_set_bit (&remove_pseudos, regno);
6287 else
6288 {
6289 n_split++;
6290 if (lra_dump_file != NULL)
6291 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n",
6292 regno, restore_regno);
6293 }
6294 }
6295 if (lra_dump_file != NULL && n_all_split != 0)
6296 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n",
6297 n_split, n_all_split,
6298 (double) n_split / n_all_split * 100);
6299 change_p = remove_inheritance_pseudos (&remove_pseudos);
6300 bitmap_clear (&remove_pseudos);
6301 /* Clear restore_regnos. */
6302 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
6303 lra_reg_info[regno].restore_regno = -1;
6304 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
6305 lra_reg_info[regno].restore_regno = -1;
6306 change_p = undo_optional_reloads () || change_p;
6307 return change_p;
6308 }
6309