1 /* Check that no unnecessary sign or zero extension insn is generated after 2 a negc or movrt insn that stores the inverted T bit in a reg. */ 3 /* { dg-do compile { target { any_fpu } } } */ 4 /* { dg-options "-O1" } */ 5 /* { dg-final { scan-assembler-not "extu|exts" } } */ 6 7 float test_00(float q[4],float m[9])8test_00 (float q[4], float m[9]) 9 { 10 float s0 = m[0] + m[1]; 11 float s1 = m[0] - m[1]; 12 13 return q[s0 > s1 ? 0 : 1]; 14 } 15