1 /* { dg-do run { target aarch64_sve_hw } } */
2 /* { dg-options "-O3 -fopenmp-simd -fno-omit-frame-pointer" } */
3
4 /* Invoke X (P##n) for n in [0, 7]. */
5 #define REPEAT8(X, P) \
6 X (P##0) X (P##1) X (P##2) X (P##3) X (P##4) X (P##5) X (P##6) X (P##7)
7
8 /* Invoke X (n) for all octal n in [0, 39]. */
9 #define REPEAT40(X) \
10 REPEAT8 (X, 0) REPEAT8 (X, 1) REPEAT8 (X, 2) REPEAT8 (X, 3) REPEAT8 (X, 4)
11
12 volatile int testi;
13
14 /* Throw to f3. */
15 void __attribute__ ((weak))
f1(int x[40][100],int * y)16 f1 (int x[40][100], int *y)
17 {
18 /* A wild write to x and y. */
19 asm volatile ("" ::: "memory");
20 if (y[testi] == x[testi][testi])
21 throw 100;
22 }
23
24 /* Expect vector work to be done, with spilling of vector registers. */
25 void __attribute__ ((weak))
f2(int x[40][100],int * y)26 f2 (int x[40][100], int *y)
27 {
28 /* Try to force some spilling. */
29 #define DECLARE(N) int y##N = y[N];
30 REPEAT40 (DECLARE);
31 for (int j = 0; j < 20; ++j)
32 {
33 f1 (x, y);
34 #pragma omp simd
35 for (int i = 0; i < 100; ++i)
36 {
37 #define INC(N) x[N][i] += y##N;
38 REPEAT40 (INC);
39 }
40 }
41 }
42
43 /* Catch an exception thrown from f1, via f2. */
44 void __attribute__ ((weak))
f3(int x[40][100],int * y,int * z)45 f3 (int x[40][100], int *y, int *z)
46 {
47 volatile int extra = 111;
48 try
49 {
50 f2 (x, y);
51 }
52 catch (int val)
53 {
54 *z = val + extra;
55 }
56 }
57
58 static int x[40][100];
59 static int y[40];
60 static int z;
61
62 int
main(void)63 main (void)
64 {
65 f3 (x, y, &z);
66 if (z != 211)
67 __builtin_abort ();
68 return 0;
69 }
70