1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996-2016 Free Software Foundation, Inc.
3 Contributed by Jeff Law (law@cygnus.com).
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "backend.h"
25 #include "target.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "cfghooks.h"
29 #include "cfgloop.h"
30 #include "df.h"
31 #include "tm_p.h"
32 #include "optabs.h"
33 #include "regs.h"
34 #include "emit-rtl.h"
35 #include "recog.h"
36 #include "diagnostic-core.h"
37 #include "alias.h"
38 #include "stor-layout.h"
39 #include "varasm.h"
40 #include "calls.h"
41 #include "output.h"
42 #include "insn-attr.h"
43 #include "reload.h"
44 #include "explow.h"
45 #include "expr.h"
46 #include "tm-constrs.h"
47 #include "cfgrtl.h"
48 #include "dumpfile.h"
49 #include "builtins.h"
50
51 /* This file should be included last. */
52 #include "target-def.h"
53
54 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
55 names are not prefixed by underscores, to tell whether to prefix a
56 label with a plus sign or not, so that the assembler can tell
57 symbol names from register names. */
58 int mn10300_protect_label;
59
60 /* Selected processor type for tuning. */
61 enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT;
62
63 #define CC_FLAG_Z 1
64 #define CC_FLAG_N 2
65 #define CC_FLAG_C 4
66 #define CC_FLAG_V 8
67
68 static int cc_flags_for_mode(machine_mode);
69 static int cc_flags_for_code(enum rtx_code);
70
71 /* Implement TARGET_OPTION_OVERRIDE. */
72 static void
mn10300_option_override(void)73 mn10300_option_override (void)
74 {
75 if (TARGET_AM33)
76 target_flags &= ~MASK_MULT_BUG;
77 else
78 {
79 /* Disable scheduling for the MN10300 as we do
80 not have timing information available for it. */
81 flag_schedule_insns = 0;
82 flag_schedule_insns_after_reload = 0;
83
84 /* Force enable splitting of wide types, as otherwise it is trivial
85 to run out of registers. Indeed, this works so well that register
86 allocation problems are now more common *without* optimization,
87 when this flag is not enabled by default. */
88 flag_split_wide_types = 1;
89 }
90
91 if (mn10300_tune_string)
92 {
93 if (strcasecmp (mn10300_tune_string, "mn10300") == 0)
94 mn10300_tune_cpu = PROCESSOR_MN10300;
95 else if (strcasecmp (mn10300_tune_string, "am33") == 0)
96 mn10300_tune_cpu = PROCESSOR_AM33;
97 else if (strcasecmp (mn10300_tune_string, "am33-2") == 0)
98 mn10300_tune_cpu = PROCESSOR_AM33_2;
99 else if (strcasecmp (mn10300_tune_string, "am34") == 0)
100 mn10300_tune_cpu = PROCESSOR_AM34;
101 else
102 error ("-mtune= expects mn10300, am33, am33-2, or am34");
103 }
104 }
105
106 static void
mn10300_file_start(void)107 mn10300_file_start (void)
108 {
109 default_file_start ();
110
111 if (TARGET_AM33_2)
112 fprintf (asm_out_file, "\t.am33_2\n");
113 else if (TARGET_AM33)
114 fprintf (asm_out_file, "\t.am33\n");
115 }
116
117 /* Note: This list must match the liw_op attribute in mn10300.md. */
118
119 static const char *liw_op_names[] =
120 {
121 "add", "cmp", "sub", "mov",
122 "and", "or", "xor",
123 "asr", "lsr", "asl",
124 "none", "max"
125 };
126
127 /* Print operand X using operand code CODE to assembly language output file
128 FILE. */
129
130 void
mn10300_print_operand(FILE * file,rtx x,int code)131 mn10300_print_operand (FILE *file, rtx x, int code)
132 {
133 switch (code)
134 {
135 case 'W':
136 {
137 unsigned int liw_op = UINTVAL (x);
138
139 gcc_assert (TARGET_ALLOW_LIW);
140 gcc_assert (liw_op < LIW_OP_MAX);
141 fputs (liw_op_names[liw_op], file);
142 break;
143 }
144
145 case 'b':
146 case 'B':
147 {
148 enum rtx_code cmp = GET_CODE (x);
149 machine_mode mode = GET_MODE (XEXP (x, 0));
150 const char *str;
151 int have_flags;
152
153 if (code == 'B')
154 cmp = reverse_condition (cmp);
155 have_flags = cc_flags_for_mode (mode);
156
157 switch (cmp)
158 {
159 case NE:
160 str = "ne";
161 break;
162 case EQ:
163 str = "eq";
164 break;
165 case GE:
166 /* bge is smaller than bnc. */
167 str = (have_flags & CC_FLAG_V ? "ge" : "nc");
168 break;
169 case LT:
170 str = (have_flags & CC_FLAG_V ? "lt" : "ns");
171 break;
172 case GT:
173 str = "gt";
174 break;
175 case LE:
176 str = "le";
177 break;
178 case GEU:
179 str = "cc";
180 break;
181 case GTU:
182 str = "hi";
183 break;
184 case LEU:
185 str = "ls";
186 break;
187 case LTU:
188 str = "cs";
189 break;
190 case ORDERED:
191 str = "lge";
192 break;
193 case UNORDERED:
194 str = "uo";
195 break;
196 case LTGT:
197 str = "lg";
198 break;
199 case UNEQ:
200 str = "ue";
201 break;
202 case UNGE:
203 str = "uge";
204 break;
205 case UNGT:
206 str = "ug";
207 break;
208 case UNLE:
209 str = "ule";
210 break;
211 case UNLT:
212 str = "ul";
213 break;
214 default:
215 gcc_unreachable ();
216 }
217
218 gcc_checking_assert ((cc_flags_for_code (cmp) & ~have_flags) == 0);
219 fputs (str, file);
220 }
221 break;
222
223 case 'C':
224 /* This is used for the operand to a call instruction;
225 if it's a REG, enclose it in parens, else output
226 the operand normally. */
227 if (REG_P (x))
228 {
229 fputc ('(', file);
230 mn10300_print_operand (file, x, 0);
231 fputc (')', file);
232 }
233 else
234 mn10300_print_operand (file, x, 0);
235 break;
236
237 case 'D':
238 switch (GET_CODE (x))
239 {
240 case MEM:
241 fputc ('(', file);
242 output_address (GET_MODE (x), XEXP (x, 0));
243 fputc (')', file);
244 break;
245
246 case REG:
247 fprintf (file, "fd%d", REGNO (x) - 18);
248 break;
249
250 default:
251 gcc_unreachable ();
252 }
253 break;
254
255 /* These are the least significant word in a 64bit value. */
256 case 'L':
257 switch (GET_CODE (x))
258 {
259 case MEM:
260 fputc ('(', file);
261 output_address (GET_MODE (x), XEXP (x, 0));
262 fputc (')', file);
263 break;
264
265 case REG:
266 fprintf (file, "%s", reg_names[REGNO (x)]);
267 break;
268
269 case SUBREG:
270 fprintf (file, "%s", reg_names[subreg_regno (x)]);
271 break;
272
273 case CONST_DOUBLE:
274 {
275 long val[2];
276
277 switch (GET_MODE (x))
278 {
279 case DFmode:
280 REAL_VALUE_TO_TARGET_DOUBLE
281 (*CONST_DOUBLE_REAL_VALUE (x), val);
282 fprintf (file, "0x%lx", val[0]);
283 break;;
284 case SFmode:
285 REAL_VALUE_TO_TARGET_SINGLE
286 (*CONST_DOUBLE_REAL_VALUE (x), val[0]);
287 fprintf (file, "0x%lx", val[0]);
288 break;;
289 case VOIDmode:
290 case DImode:
291 mn10300_print_operand_address (file,
292 GEN_INT (CONST_DOUBLE_LOW (x)));
293 break;
294 default:
295 break;
296 }
297 break;
298 }
299
300 case CONST_INT:
301 {
302 rtx low, high;
303 split_double (x, &low, &high);
304 fprintf (file, "%ld", (long)INTVAL (low));
305 break;
306 }
307
308 default:
309 gcc_unreachable ();
310 }
311 break;
312
313 /* Similarly, but for the most significant word. */
314 case 'H':
315 switch (GET_CODE (x))
316 {
317 case MEM:
318 fputc ('(', file);
319 x = adjust_address (x, SImode, 4);
320 output_address (GET_MODE (x), XEXP (x, 0));
321 fputc (')', file);
322 break;
323
324 case REG:
325 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
326 break;
327
328 case SUBREG:
329 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
330 break;
331
332 case CONST_DOUBLE:
333 {
334 long val[2];
335
336 switch (GET_MODE (x))
337 {
338 case DFmode:
339 REAL_VALUE_TO_TARGET_DOUBLE
340 (*CONST_DOUBLE_REAL_VALUE (x), val);
341 fprintf (file, "0x%lx", val[1]);
342 break;;
343 case SFmode:
344 gcc_unreachable ();
345 case VOIDmode:
346 case DImode:
347 mn10300_print_operand_address (file,
348 GEN_INT (CONST_DOUBLE_HIGH (x)));
349 break;
350 default:
351 break;
352 }
353 break;
354 }
355
356 case CONST_INT:
357 {
358 rtx low, high;
359 split_double (x, &low, &high);
360 fprintf (file, "%ld", (long)INTVAL (high));
361 break;
362 }
363
364 default:
365 gcc_unreachable ();
366 }
367 break;
368
369 case 'A':
370 fputc ('(', file);
371 if (REG_P (XEXP (x, 0)))
372 output_address (VOIDmode, gen_rtx_PLUS (SImode,
373 XEXP (x, 0), const0_rtx));
374 else
375 output_address (VOIDmode, XEXP (x, 0));
376 fputc (')', file);
377 break;
378
379 case 'N':
380 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
381 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
382 break;
383
384 case 'U':
385 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
386 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
387 break;
388
389 /* For shift counts. The hardware ignores the upper bits of
390 any immediate, but the assembler will flag an out of range
391 shift count as an error. So we mask off the high bits
392 of the immediate here. */
393 case 'S':
394 if (CONST_INT_P (x))
395 {
396 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
397 break;
398 }
399 /* FALL THROUGH */
400
401 default:
402 switch (GET_CODE (x))
403 {
404 case MEM:
405 fputc ('(', file);
406 output_address (GET_MODE (x), XEXP (x, 0));
407 fputc (')', file);
408 break;
409
410 case PLUS:
411 output_address (VOIDmode, x);
412 break;
413
414 case REG:
415 fprintf (file, "%s", reg_names[REGNO (x)]);
416 break;
417
418 case SUBREG:
419 fprintf (file, "%s", reg_names[subreg_regno (x)]);
420 break;
421
422 /* This will only be single precision.... */
423 case CONST_DOUBLE:
424 {
425 unsigned long val;
426
427 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
428 fprintf (file, "0x%lx", val);
429 break;
430 }
431
432 case CONST_INT:
433 case SYMBOL_REF:
434 case CONST:
435 case LABEL_REF:
436 case CODE_LABEL:
437 case UNSPEC:
438 mn10300_print_operand_address (file, x);
439 break;
440 default:
441 gcc_unreachable ();
442 }
443 break;
444 }
445 }
446
447 /* Output assembly language output for the address ADDR to FILE. */
448
449 void
mn10300_print_operand_address(FILE * file,rtx addr)450 mn10300_print_operand_address (FILE *file, rtx addr)
451 {
452 switch (GET_CODE (addr))
453 {
454 case POST_INC:
455 mn10300_print_operand (file, XEXP (addr, 0), 0);
456 fputc ('+', file);
457 break;
458
459 case POST_MODIFY:
460 mn10300_print_operand (file, XEXP (addr, 0), 0);
461 fputc ('+', file);
462 fputc (',', file);
463 mn10300_print_operand (file, XEXP (addr, 1), 0);
464 break;
465
466 case REG:
467 mn10300_print_operand (file, addr, 0);
468 break;
469 case PLUS:
470 {
471 rtx base = XEXP (addr, 0);
472 rtx index = XEXP (addr, 1);
473
474 if (REG_P (index) && !REG_OK_FOR_INDEX_P (index))
475 {
476 rtx x = base;
477 base = index;
478 index = x;
479
480 gcc_assert (REG_P (index) && REG_OK_FOR_INDEX_P (index));
481 }
482 gcc_assert (REG_OK_FOR_BASE_P (base));
483
484 mn10300_print_operand (file, index, 0);
485 fputc (',', file);
486 mn10300_print_operand (file, base, 0);
487 break;
488 }
489 case SYMBOL_REF:
490 output_addr_const (file, addr);
491 break;
492 default:
493 output_addr_const (file, addr);
494 break;
495 }
496 }
497
498 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA.
499
500 Used for PIC-specific UNSPECs. */
501
502 static bool
mn10300_asm_output_addr_const_extra(FILE * file,rtx x)503 mn10300_asm_output_addr_const_extra (FILE *file, rtx x)
504 {
505 if (GET_CODE (x) == UNSPEC)
506 {
507 switch (XINT (x, 1))
508 {
509 case UNSPEC_PIC:
510 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
511 output_addr_const (file, XVECEXP (x, 0, 0));
512 break;
513 case UNSPEC_GOT:
514 output_addr_const (file, XVECEXP (x, 0, 0));
515 fputs ("@GOT", file);
516 break;
517 case UNSPEC_GOTOFF:
518 output_addr_const (file, XVECEXP (x, 0, 0));
519 fputs ("@GOTOFF", file);
520 break;
521 case UNSPEC_PLT:
522 output_addr_const (file, XVECEXP (x, 0, 0));
523 fputs ("@PLT", file);
524 break;
525 case UNSPEC_GOTSYM_OFF:
526 assemble_name (file, GOT_SYMBOL_NAME);
527 fputs ("-(", file);
528 output_addr_const (file, XVECEXP (x, 0, 0));
529 fputs ("-.)", file);
530 break;
531 default:
532 return false;
533 }
534 return true;
535 }
536 else
537 return false;
538 }
539
540 /* Count the number of FP registers that have to be saved. */
541 static int
fp_regs_to_save(void)542 fp_regs_to_save (void)
543 {
544 int i, n = 0;
545
546 if (! TARGET_AM33_2)
547 return 0;
548
549 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
550 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
551 ++n;
552
553 return n;
554 }
555
556 /* Print a set of registers in the format required by "movm" and "ret".
557 Register K is saved if bit K of MASK is set. The data and address
558 registers can be stored individually, but the extended registers cannot.
559 We assume that the mask already takes that into account. For instance,
560 bits 14 to 17 must have the same value. */
561
562 void
mn10300_print_reg_list(FILE * file,int mask)563 mn10300_print_reg_list (FILE *file, int mask)
564 {
565 int need_comma;
566 int i;
567
568 need_comma = 0;
569 fputc ('[', file);
570
571 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
572 if ((mask & (1 << i)) != 0)
573 {
574 if (need_comma)
575 fputc (',', file);
576 fputs (reg_names [i], file);
577 need_comma = 1;
578 }
579
580 if ((mask & 0x3c000) != 0)
581 {
582 gcc_assert ((mask & 0x3c000) == 0x3c000);
583 if (need_comma)
584 fputc (',', file);
585 fputs ("exreg1", file);
586 need_comma = 1;
587 }
588
589 fputc (']', file);
590 }
591
592 /* If the MDR register is never clobbered, we can use the RETF instruction
593 which takes the address from the MDR register. This is 3 cycles faster
594 than having to load the address from the stack. */
595
596 bool
mn10300_can_use_retf_insn(void)597 mn10300_can_use_retf_insn (void)
598 {
599 /* Don't bother if we're not optimizing. In this case we won't
600 have proper access to df_regs_ever_live_p. */
601 if (!optimize)
602 return false;
603
604 /* EH returns alter the saved return address; MDR is not current. */
605 if (crtl->calls_eh_return)
606 return false;
607
608 /* Obviously not if MDR is ever clobbered. */
609 if (df_regs_ever_live_p (MDR_REG))
610 return false;
611
612 /* ??? Careful not to use this during expand_epilogue etc. */
613 gcc_assert (!in_sequence_p ());
614 return leaf_function_p ();
615 }
616
617 bool
mn10300_can_use_rets_insn(void)618 mn10300_can_use_rets_insn (void)
619 {
620 return !mn10300_initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM);
621 }
622
623 /* Returns the set of live, callee-saved registers as a bitmask. The
624 callee-saved extended registers cannot be stored individually, so
625 all of them will be included in the mask if any one of them is used.
626 Also returns the number of bytes in the registers in the mask if
627 BYTES_SAVED is not NULL. */
628
629 unsigned int
mn10300_get_live_callee_saved_regs(unsigned int * bytes_saved)630 mn10300_get_live_callee_saved_regs (unsigned int * bytes_saved)
631 {
632 int mask;
633 int i;
634 unsigned int count;
635
636 count = mask = 0;
637 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
638 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
639 {
640 mask |= (1 << i);
641 ++ count;
642 }
643
644 if ((mask & 0x3c000) != 0)
645 {
646 for (i = 0x04000; i < 0x40000; i <<= 1)
647 if ((mask & i) == 0)
648 ++ count;
649
650 mask |= 0x3c000;
651 }
652
653 if (bytes_saved)
654 * bytes_saved = count * UNITS_PER_WORD;
655
656 return mask;
657 }
658
659 static rtx
F(rtx r)660 F (rtx r)
661 {
662 RTX_FRAME_RELATED_P (r) = 1;
663 return r;
664 }
665
666 /* Generate an instruction that pushes several registers onto the stack.
667 Register K will be saved if bit K in MASK is set. The function does
668 nothing if MASK is zero.
669
670 To be compatible with the "movm" instruction, the lowest-numbered
671 register must be stored in the lowest slot. If MASK is the set
672 { R1,...,RN }, where R1...RN are ordered least first, the generated
673 instruction will have the form:
674
675 (parallel
676 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
677 (set (mem:SI (plus:SI (reg:SI 9)
678 (const_int -1*4)))
679 (reg:SI RN))
680 ...
681 (set (mem:SI (plus:SI (reg:SI 9)
682 (const_int -N*4)))
683 (reg:SI R1))) */
684
685 static void
mn10300_gen_multiple_store(unsigned int mask)686 mn10300_gen_multiple_store (unsigned int mask)
687 {
688 /* The order in which registers are stored, from SP-4 through SP-N*4. */
689 static const unsigned int store_order[8] = {
690 /* e2, e3: never saved */
691 FIRST_EXTENDED_REGNUM + 4,
692 FIRST_EXTENDED_REGNUM + 5,
693 FIRST_EXTENDED_REGNUM + 6,
694 FIRST_EXTENDED_REGNUM + 7,
695 /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */
696 FIRST_DATA_REGNUM + 2,
697 FIRST_DATA_REGNUM + 3,
698 FIRST_ADDRESS_REGNUM + 2,
699 FIRST_ADDRESS_REGNUM + 3,
700 /* d0, d1, a0, a1, mdr, lir, lar: never saved. */
701 };
702
703 rtx x, elts[9];
704 unsigned int i;
705 int count;
706
707 if (mask == 0)
708 return;
709
710 for (i = count = 0; i < ARRAY_SIZE(store_order); ++i)
711 {
712 unsigned regno = store_order[i];
713
714 if (((mask >> regno) & 1) == 0)
715 continue;
716
717 ++count;
718 x = plus_constant (Pmode, stack_pointer_rtx, count * -4);
719 x = gen_frame_mem (SImode, x);
720 x = gen_rtx_SET (x, gen_rtx_REG (SImode, regno));
721 elts[count] = F(x);
722
723 /* Remove the register from the mask so that... */
724 mask &= ~(1u << regno);
725 }
726
727 /* ... we can make sure that we didn't try to use a register
728 not listed in the store order. */
729 gcc_assert (mask == 0);
730
731 /* Create the instruction that updates the stack pointer. */
732 x = plus_constant (Pmode, stack_pointer_rtx, count * -4);
733 x = gen_rtx_SET (stack_pointer_rtx, x);
734 elts[0] = F(x);
735
736 /* We need one PARALLEL element to update the stack pointer and
737 an additional element for each register that is stored. */
738 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (count + 1, elts));
739 F (emit_insn (x));
740 }
741
742 static inline unsigned int
popcount(unsigned int mask)743 popcount (unsigned int mask)
744 {
745 unsigned int count = 0;
746
747 while (mask)
748 {
749 ++ count;
750 mask &= ~ (mask & - mask);
751 }
752 return count;
753 }
754
755 void
mn10300_expand_prologue(void)756 mn10300_expand_prologue (void)
757 {
758 HOST_WIDE_INT size = mn10300_frame_size ();
759 unsigned int mask;
760
761 mask = mn10300_get_live_callee_saved_regs (NULL);
762 /* If we use any of the callee-saved registers, save them now. */
763 mn10300_gen_multiple_store (mask);
764
765 if (flag_stack_usage_info)
766 current_function_static_stack_size = size + popcount (mask) * 4;
767
768 if (TARGET_AM33_2 && fp_regs_to_save ())
769 {
770 int num_regs_to_save = fp_regs_to_save (), i;
771 HOST_WIDE_INT xsize;
772 enum
773 {
774 save_sp_merge,
775 save_sp_no_merge,
776 save_sp_partial_merge,
777 save_a0_merge,
778 save_a0_no_merge
779 } strategy;
780 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
781 rtx reg;
782
783 if (flag_stack_usage_info)
784 current_function_static_stack_size += num_regs_to_save * 4;
785
786 /* We have several different strategies to save FP registers.
787 We can store them using SP offsets, which is beneficial if
788 there are just a few registers to save, or we can use `a0' in
789 post-increment mode (`a0' is the only call-clobbered address
790 register that is never used to pass information to a
791 function). Furthermore, if we don't need a frame pointer, we
792 can merge the two SP adds into a single one, but this isn't
793 always beneficial; sometimes we can just split the two adds
794 so that we don't exceed a 16-bit constant size. The code
795 below will select which strategy to use, so as to generate
796 smallest code. Ties are broken in favor or shorter sequences
797 (in terms of number of instructions). */
798
799 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
800 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
801 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
802 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
803
804 /* We add 0 * (S) in two places to promote to the type of S,
805 so that all arms of the conditional have the same type. */
806 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
807 (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \
808 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
809 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
810 : 0 * (S) + (ELSE))
811 #define SIZE_FMOV_SP_(S,N) \
812 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
813 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
814 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
815 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
816
817 /* Consider alternative save_sp_merge only if we don't need the
818 frame pointer and size is nonzero. */
819 if (! frame_pointer_needed && size)
820 {
821 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
822 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
823 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
824 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
825
826 if (this_strategy_size < strategy_size)
827 {
828 strategy = save_sp_merge;
829 strategy_size = this_strategy_size;
830 }
831 }
832
833 /* Consider alternative save_sp_no_merge unconditionally. */
834 /* Insn: add -4 * num_regs_to_save, sp. */
835 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
836 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
837 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
838 if (size)
839 {
840 /* Insn: add -size, sp. */
841 this_strategy_size += SIZE_ADD_SP (-size);
842 }
843
844 if (this_strategy_size < strategy_size)
845 {
846 strategy = save_sp_no_merge;
847 strategy_size = this_strategy_size;
848 }
849
850 /* Consider alternative save_sp_partial_merge only if we don't
851 need a frame pointer and size is reasonably large. */
852 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
853 {
854 /* Insn: add -128, sp. */
855 this_strategy_size = SIZE_ADD_SP (-128);
856 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
857 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
858 num_regs_to_save);
859 if (size)
860 {
861 /* Insn: add 128-size, sp. */
862 this_strategy_size += SIZE_ADD_SP (128 - size);
863 }
864
865 if (this_strategy_size < strategy_size)
866 {
867 strategy = save_sp_partial_merge;
868 strategy_size = this_strategy_size;
869 }
870 }
871
872 /* Consider alternative save_a0_merge only if we don't need a
873 frame pointer, size is nonzero and the user hasn't
874 changed the calling conventions of a0. */
875 if (! frame_pointer_needed && size
876 && call_really_used_regs [FIRST_ADDRESS_REGNUM]
877 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
878 {
879 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
880 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
881 /* Insn: mov sp, a0. */
882 this_strategy_size++;
883 if (size)
884 {
885 /* Insn: add size, a0. */
886 this_strategy_size += SIZE_ADD_AX (size);
887 }
888 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
889 this_strategy_size += 3 * num_regs_to_save;
890
891 if (this_strategy_size < strategy_size)
892 {
893 strategy = save_a0_merge;
894 strategy_size = this_strategy_size;
895 }
896 }
897
898 /* Consider alternative save_a0_no_merge if the user hasn't
899 changed the calling conventions of a0. */
900 if (call_really_used_regs [FIRST_ADDRESS_REGNUM]
901 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
902 {
903 /* Insn: add -4 * num_regs_to_save, sp. */
904 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
905 /* Insn: mov sp, a0. */
906 this_strategy_size++;
907 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
908 this_strategy_size += 3 * num_regs_to_save;
909 if (size)
910 {
911 /* Insn: add -size, sp. */
912 this_strategy_size += SIZE_ADD_SP (-size);
913 }
914
915 if (this_strategy_size < strategy_size)
916 {
917 strategy = save_a0_no_merge;
918 strategy_size = this_strategy_size;
919 }
920 }
921
922 /* Emit the initial SP add, common to all strategies. */
923 switch (strategy)
924 {
925 case save_sp_no_merge:
926 case save_a0_no_merge:
927 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
928 stack_pointer_rtx,
929 GEN_INT (-4 * num_regs_to_save))));
930 xsize = 0;
931 break;
932
933 case save_sp_partial_merge:
934 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
935 stack_pointer_rtx,
936 GEN_INT (-128))));
937 xsize = 128 - 4 * num_regs_to_save;
938 size -= xsize;
939 break;
940
941 case save_sp_merge:
942 case save_a0_merge:
943 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
944 stack_pointer_rtx,
945 GEN_INT (-(size + 4 * num_regs_to_save)))));
946 /* We'll have to adjust FP register saves according to the
947 frame size. */
948 xsize = size;
949 /* Since we've already created the stack frame, don't do it
950 again at the end of the function. */
951 size = 0;
952 break;
953
954 default:
955 gcc_unreachable ();
956 }
957
958 /* Now prepare register a0, if we have decided to use it. */
959 switch (strategy)
960 {
961 case save_sp_merge:
962 case save_sp_no_merge:
963 case save_sp_partial_merge:
964 reg = 0;
965 break;
966
967 case save_a0_merge:
968 case save_a0_no_merge:
969 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
970 F (emit_insn (gen_movsi (reg, stack_pointer_rtx)));
971 if (xsize)
972 F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))));
973 reg = gen_rtx_POST_INC (SImode, reg);
974 break;
975
976 default:
977 gcc_unreachable ();
978 }
979
980 /* Now actually save the FP registers. */
981 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
982 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
983 {
984 rtx addr;
985
986 if (reg)
987 addr = reg;
988 else
989 {
990 /* If we aren't using `a0', use an SP offset. */
991 if (xsize)
992 {
993 addr = gen_rtx_PLUS (SImode,
994 stack_pointer_rtx,
995 GEN_INT (xsize));
996 }
997 else
998 addr = stack_pointer_rtx;
999
1000 xsize += 4;
1001 }
1002
1003 F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr),
1004 gen_rtx_REG (SFmode, i))));
1005 }
1006 }
1007
1008 /* Now put the frame pointer into the frame pointer register. */
1009 if (frame_pointer_needed)
1010 F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
1011
1012 /* Allocate stack for this frame. */
1013 if (size)
1014 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
1015 stack_pointer_rtx,
1016 GEN_INT (-size))));
1017
1018 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
1019 emit_insn (gen_load_pic ());
1020 }
1021
1022 void
mn10300_expand_epilogue(void)1023 mn10300_expand_epilogue (void)
1024 {
1025 HOST_WIDE_INT size = mn10300_frame_size ();
1026 unsigned int reg_save_bytes;
1027
1028 mn10300_get_live_callee_saved_regs (& reg_save_bytes);
1029
1030 if (TARGET_AM33_2 && fp_regs_to_save ())
1031 {
1032 int num_regs_to_save = fp_regs_to_save (), i;
1033 rtx reg = 0;
1034
1035 /* We have several options to restore FP registers. We could
1036 load them from SP offsets, but, if there are enough FP
1037 registers to restore, we win if we use a post-increment
1038 addressing mode. */
1039
1040 /* If we have a frame pointer, it's the best option, because we
1041 already know it has the value we want. */
1042 if (frame_pointer_needed)
1043 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
1044 /* Otherwise, we may use `a1', since it's call-clobbered and
1045 it's never used for return values. But only do so if it's
1046 smaller than using SP offsets. */
1047 else
1048 {
1049 enum { restore_sp_post_adjust,
1050 restore_sp_pre_adjust,
1051 restore_sp_partial_adjust,
1052 restore_a1 } strategy;
1053 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
1054
1055 /* Consider using sp offsets before adjusting sp. */
1056 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1057 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
1058 /* If size is too large, we'll have to adjust SP with an
1059 add. */
1060 if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
1061 {
1062 /* Insn: add size + 4 * num_regs_to_save, sp. */
1063 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
1064 }
1065 /* If we don't have to restore any non-FP registers,
1066 we'll be able to save one byte by using rets. */
1067 if (! reg_save_bytes)
1068 this_strategy_size--;
1069
1070 if (this_strategy_size < strategy_size)
1071 {
1072 strategy = restore_sp_post_adjust;
1073 strategy_size = this_strategy_size;
1074 }
1075
1076 /* Consider using sp offsets after adjusting sp. */
1077 /* Insn: add size, sp. */
1078 this_strategy_size = SIZE_ADD_SP (size);
1079 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1080 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
1081 /* We're going to use ret to release the FP registers
1082 save area, so, no savings. */
1083
1084 if (this_strategy_size < strategy_size)
1085 {
1086 strategy = restore_sp_pre_adjust;
1087 strategy_size = this_strategy_size;
1088 }
1089
1090 /* Consider using sp offsets after partially adjusting sp.
1091 When size is close to 32Kb, we may be able to adjust SP
1092 with an imm16 add instruction while still using fmov
1093 (d8,sp). */
1094 if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
1095 {
1096 /* Insn: add size + 4 * num_regs_to_save
1097 + reg_save_bytes - 252,sp. */
1098 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
1099 + (int) reg_save_bytes - 252);
1100 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1101 this_strategy_size += SIZE_FMOV_SP (252 - reg_save_bytes
1102 - 4 * num_regs_to_save,
1103 num_regs_to_save);
1104 /* We're going to use ret to release the FP registers
1105 save area, so, no savings. */
1106
1107 if (this_strategy_size < strategy_size)
1108 {
1109 strategy = restore_sp_partial_adjust;
1110 strategy_size = this_strategy_size;
1111 }
1112 }
1113
1114 /* Consider using a1 in post-increment mode, as long as the
1115 user hasn't changed the calling conventions of a1. */
1116 if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1]
1117 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1118 {
1119 /* Insn: mov sp,a1. */
1120 this_strategy_size = 1;
1121 if (size)
1122 {
1123 /* Insn: add size,a1. */
1124 this_strategy_size += SIZE_ADD_AX (size);
1125 }
1126 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1127 this_strategy_size += 3 * num_regs_to_save;
1128 /* If size is large enough, we may be able to save a
1129 couple of bytes. */
1130 if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
1131 {
1132 /* Insn: mov a1,sp. */
1133 this_strategy_size += 2;
1134 }
1135 /* If we don't have to restore any non-FP registers,
1136 we'll be able to save one byte by using rets. */
1137 if (! reg_save_bytes)
1138 this_strategy_size--;
1139
1140 if (this_strategy_size < strategy_size)
1141 {
1142 strategy = restore_a1;
1143 strategy_size = this_strategy_size;
1144 }
1145 }
1146
1147 switch (strategy)
1148 {
1149 case restore_sp_post_adjust:
1150 break;
1151
1152 case restore_sp_pre_adjust:
1153 emit_insn (gen_addsi3 (stack_pointer_rtx,
1154 stack_pointer_rtx,
1155 GEN_INT (size)));
1156 size = 0;
1157 break;
1158
1159 case restore_sp_partial_adjust:
1160 emit_insn (gen_addsi3 (stack_pointer_rtx,
1161 stack_pointer_rtx,
1162 GEN_INT (size + 4 * num_regs_to_save
1163 + reg_save_bytes - 252)));
1164 size = 252 - reg_save_bytes - 4 * num_regs_to_save;
1165 break;
1166
1167 case restore_a1:
1168 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1169 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1170 if (size)
1171 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1172 break;
1173
1174 default:
1175 gcc_unreachable ();
1176 }
1177 }
1178
1179 /* Adjust the selected register, if any, for post-increment. */
1180 if (reg)
1181 reg = gen_rtx_POST_INC (SImode, reg);
1182
1183 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1184 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
1185 {
1186 rtx addr;
1187
1188 if (reg)
1189 addr = reg;
1190 else if (size)
1191 {
1192 /* If we aren't using a post-increment register, use an
1193 SP offset. */
1194 addr = gen_rtx_PLUS (SImode,
1195 stack_pointer_rtx,
1196 GEN_INT (size));
1197 }
1198 else
1199 addr = stack_pointer_rtx;
1200
1201 size += 4;
1202
1203 emit_insn (gen_movsf (gen_rtx_REG (SFmode, i),
1204 gen_rtx_MEM (SFmode, addr)));
1205 }
1206
1207 /* If we were using the restore_a1 strategy and the number of
1208 bytes to be released won't fit in the `ret' byte, copy `a1'
1209 to `sp', to avoid having to use `add' to adjust it. */
1210 if (! frame_pointer_needed && reg && size + reg_save_bytes > 255)
1211 {
1212 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1213 size = 0;
1214 }
1215 }
1216
1217 /* Maybe cut back the stack, except for the register save area.
1218
1219 If the frame pointer exists, then use the frame pointer to
1220 cut back the stack.
1221
1222 If the stack size + register save area is more than 255 bytes,
1223 then the stack must be cut back here since the size + register
1224 save size is too big for a ret/retf instruction.
1225
1226 Else leave it alone, it will be cut back as part of the
1227 ret/retf instruction, or there wasn't any stack to begin with.
1228
1229 Under no circumstances should the register save area be
1230 deallocated here, that would leave a window where an interrupt
1231 could occur and trash the register save area. */
1232 if (frame_pointer_needed)
1233 {
1234 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1235 size = 0;
1236 }
1237 else if (size + reg_save_bytes > 255)
1238 {
1239 emit_insn (gen_addsi3 (stack_pointer_rtx,
1240 stack_pointer_rtx,
1241 GEN_INT (size)));
1242 size = 0;
1243 }
1244
1245 /* Adjust the stack and restore callee-saved registers, if any. */
1246 if (mn10300_can_use_rets_insn ())
1247 emit_jump_insn (ret_rtx);
1248 else
1249 emit_jump_insn (gen_return_ret (GEN_INT (size + reg_save_bytes)));
1250 }
1251
1252 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1253 This function is for MATCH_PARALLEL and so assumes OP is known to be
1254 parallel. If OP is a multiple store, return a mask indicating which
1255 registers it saves. Return 0 otherwise. */
1256
1257 unsigned int
mn10300_store_multiple_regs(rtx op)1258 mn10300_store_multiple_regs (rtx op)
1259 {
1260 int count;
1261 int mask;
1262 int i;
1263 unsigned int last;
1264 rtx elt;
1265
1266 count = XVECLEN (op, 0);
1267 if (count < 2)
1268 return 0;
1269
1270 /* Check that first instruction has the form (set (sp) (plus A B)) */
1271 elt = XVECEXP (op, 0, 0);
1272 if (GET_CODE (elt) != SET
1273 || (! REG_P (SET_DEST (elt)))
1274 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1275 || GET_CODE (SET_SRC (elt)) != PLUS)
1276 return 0;
1277
1278 /* Check that A is the stack pointer and B is the expected stack size.
1279 For OP to match, each subsequent instruction should push a word onto
1280 the stack. We therefore expect the first instruction to create
1281 COUNT-1 stack slots. */
1282 elt = SET_SRC (elt);
1283 if ((! REG_P (XEXP (elt, 0)))
1284 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1285 || (! CONST_INT_P (XEXP (elt, 1)))
1286 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1287 return 0;
1288
1289 mask = 0;
1290 for (i = 1; i < count; i++)
1291 {
1292 /* Check that element i is a (set (mem M) R). */
1293 /* ??? Validate the register order a-la mn10300_gen_multiple_store.
1294 Remember: the ordering is *not* monotonic. */
1295 elt = XVECEXP (op, 0, i);
1296 if (GET_CODE (elt) != SET
1297 || (! MEM_P (SET_DEST (elt)))
1298 || (! REG_P (SET_SRC (elt))))
1299 return 0;
1300
1301 /* Remember which registers are to be saved. */
1302 last = REGNO (SET_SRC (elt));
1303 mask |= (1 << last);
1304
1305 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1306 elt = XEXP (SET_DEST (elt), 0);
1307 if (GET_CODE (elt) != PLUS
1308 || (! REG_P (XEXP (elt, 0)))
1309 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1310 || (! CONST_INT_P (XEXP (elt, 1)))
1311 || INTVAL (XEXP (elt, 1)) != -i * 4)
1312 return 0;
1313 }
1314
1315 /* All or none of the callee-saved extended registers must be in the set. */
1316 if ((mask & 0x3c000) != 0
1317 && (mask & 0x3c000) != 0x3c000)
1318 return 0;
1319
1320 return mask;
1321 }
1322
1323 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
1324
1325 static reg_class_t
mn10300_preferred_reload_class(rtx x,reg_class_t rclass)1326 mn10300_preferred_reload_class (rtx x, reg_class_t rclass)
1327 {
1328 if (x == stack_pointer_rtx && rclass != SP_REGS)
1329 return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
1330 else if (MEM_P (x)
1331 || (REG_P (x)
1332 && !HARD_REGISTER_P (x))
1333 || (GET_CODE (x) == SUBREG
1334 && REG_P (SUBREG_REG (x))
1335 && !HARD_REGISTER_P (SUBREG_REG (x))))
1336 return LIMIT_RELOAD_CLASS (GET_MODE (x), rclass);
1337 else
1338 return rclass;
1339 }
1340
1341 /* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
1342
1343 static reg_class_t
mn10300_preferred_output_reload_class(rtx x,reg_class_t rclass)1344 mn10300_preferred_output_reload_class (rtx x, reg_class_t rclass)
1345 {
1346 if (x == stack_pointer_rtx && rclass != SP_REGS)
1347 return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
1348 return rclass;
1349 }
1350
1351 /* Implement TARGET_SECONDARY_RELOAD. */
1352
1353 static reg_class_t
mn10300_secondary_reload(bool in_p,rtx x,reg_class_t rclass_i,machine_mode mode,secondary_reload_info * sri)1354 mn10300_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
1355 machine_mode mode, secondary_reload_info *sri)
1356 {
1357 enum reg_class rclass = (enum reg_class) rclass_i;
1358 enum reg_class xclass = NO_REGS;
1359 unsigned int xregno = INVALID_REGNUM;
1360
1361 if (REG_P (x))
1362 {
1363 xregno = REGNO (x);
1364 if (xregno >= FIRST_PSEUDO_REGISTER)
1365 xregno = true_regnum (x);
1366 if (xregno != INVALID_REGNUM)
1367 xclass = REGNO_REG_CLASS (xregno);
1368 }
1369
1370 if (!TARGET_AM33)
1371 {
1372 /* Memory load/stores less than a full word wide can't have an
1373 address or stack pointer destination. They must use a data
1374 register as an intermediate register. */
1375 if (rclass != DATA_REGS
1376 && (mode == QImode || mode == HImode)
1377 && xclass == NO_REGS)
1378 return DATA_REGS;
1379
1380 /* We can only move SP to/from an address register. */
1381 if (in_p
1382 && rclass == SP_REGS
1383 && xclass != ADDRESS_REGS)
1384 return ADDRESS_REGS;
1385 if (!in_p
1386 && xclass == SP_REGS
1387 && rclass != ADDRESS_REGS
1388 && rclass != SP_OR_ADDRESS_REGS)
1389 return ADDRESS_REGS;
1390 }
1391
1392 /* We can't directly load sp + const_int into a register;
1393 we must use an address register as an scratch. */
1394 if (in_p
1395 && rclass != SP_REGS
1396 && rclass != SP_OR_ADDRESS_REGS
1397 && rclass != SP_OR_GENERAL_REGS
1398 && GET_CODE (x) == PLUS
1399 && (XEXP (x, 0) == stack_pointer_rtx
1400 || XEXP (x, 1) == stack_pointer_rtx))
1401 {
1402 sri->icode = CODE_FOR_reload_plus_sp_const;
1403 return NO_REGS;
1404 }
1405
1406 /* We can only move MDR to/from a data register. */
1407 if (rclass == MDR_REGS && xclass != DATA_REGS)
1408 return DATA_REGS;
1409 if (xclass == MDR_REGS && rclass != DATA_REGS)
1410 return DATA_REGS;
1411
1412 /* We can't load/store an FP register from a constant address. */
1413 if (TARGET_AM33_2
1414 && (rclass == FP_REGS || xclass == FP_REGS)
1415 && (xclass == NO_REGS || rclass == NO_REGS))
1416 {
1417 rtx addr = NULL;
1418
1419 if (xregno >= FIRST_PSEUDO_REGISTER && xregno != INVALID_REGNUM)
1420 {
1421 addr = reg_equiv_mem (xregno);
1422 if (addr)
1423 addr = XEXP (addr, 0);
1424 }
1425 else if (MEM_P (x))
1426 addr = XEXP (x, 0);
1427
1428 if (addr && CONSTANT_ADDRESS_P (addr))
1429 return GENERAL_REGS;
1430 }
1431 /* Otherwise assume no secondary reloads are needed. */
1432 return NO_REGS;
1433 }
1434
1435 int
mn10300_frame_size(void)1436 mn10300_frame_size (void)
1437 {
1438 /* size includes the fixed stack space needed for function calls. */
1439 int size = get_frame_size () + crtl->outgoing_args_size;
1440
1441 /* And space for the return pointer. */
1442 size += crtl->outgoing_args_size ? 4 : 0;
1443
1444 return size;
1445 }
1446
1447 int
mn10300_initial_offset(int from,int to)1448 mn10300_initial_offset (int from, int to)
1449 {
1450 int diff = 0;
1451
1452 gcc_assert (from == ARG_POINTER_REGNUM || from == FRAME_POINTER_REGNUM);
1453 gcc_assert (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
1454
1455 if (to == STACK_POINTER_REGNUM)
1456 diff = mn10300_frame_size ();
1457
1458 /* The difference between the argument pointer and the frame pointer
1459 is the size of the callee register save area. */
1460 if (from == ARG_POINTER_REGNUM)
1461 {
1462 unsigned int reg_save_bytes;
1463
1464 mn10300_get_live_callee_saved_regs (& reg_save_bytes);
1465 diff += reg_save_bytes;
1466 diff += 4 * fp_regs_to_save ();
1467 }
1468
1469 return diff;
1470 }
1471
1472 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1473
1474 static bool
mn10300_return_in_memory(const_tree type,const_tree fntype ATTRIBUTE_UNUSED)1475 mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1476 {
1477 /* Return values > 8 bytes in length in memory. */
1478 return (int_size_in_bytes (type) > 8
1479 || int_size_in_bytes (type) == 0
1480 || TYPE_MODE (type) == BLKmode);
1481 }
1482
1483 /* Flush the argument registers to the stack for a stdarg function;
1484 return the new argument pointer. */
1485 static rtx
mn10300_builtin_saveregs(void)1486 mn10300_builtin_saveregs (void)
1487 {
1488 rtx offset, mem;
1489 tree fntype = TREE_TYPE (current_function_decl);
1490 int argadj = ((!stdarg_p (fntype))
1491 ? UNITS_PER_WORD : 0);
1492 alias_set_type set = get_varargs_alias_set ();
1493
1494 if (argadj)
1495 offset = plus_constant (Pmode, crtl->args.arg_offset_rtx, argadj);
1496 else
1497 offset = crtl->args.arg_offset_rtx;
1498
1499 mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer);
1500 set_mem_alias_set (mem, set);
1501 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1502
1503 mem = gen_rtx_MEM (SImode,
1504 plus_constant (Pmode,
1505 crtl->args.internal_arg_pointer, 4));
1506 set_mem_alias_set (mem, set);
1507 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1508
1509 return copy_to_reg (expand_binop (Pmode, add_optab,
1510 crtl->args.internal_arg_pointer,
1511 offset, 0, 0, OPTAB_LIB_WIDEN));
1512 }
1513
1514 static void
mn10300_va_start(tree valist,rtx nextarg)1515 mn10300_va_start (tree valist, rtx nextarg)
1516 {
1517 nextarg = expand_builtin_saveregs ();
1518 std_expand_builtin_va_start (valist, nextarg);
1519 }
1520
1521 /* Return true when a parameter should be passed by reference. */
1522
1523 static bool
mn10300_pass_by_reference(cumulative_args_t cum ATTRIBUTE_UNUSED,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)1524 mn10300_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
1525 machine_mode mode, const_tree type,
1526 bool named ATTRIBUTE_UNUSED)
1527 {
1528 unsigned HOST_WIDE_INT size;
1529
1530 if (type)
1531 size = int_size_in_bytes (type);
1532 else
1533 size = GET_MODE_SIZE (mode);
1534
1535 return (size > 8 || size == 0);
1536 }
1537
1538 /* Return an RTX to represent where a value with mode MODE will be returned
1539 from a function. If the result is NULL_RTX, the argument is pushed. */
1540
1541 static rtx
mn10300_function_arg(cumulative_args_t cum_v,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)1542 mn10300_function_arg (cumulative_args_t cum_v, machine_mode mode,
1543 const_tree type, bool named ATTRIBUTE_UNUSED)
1544 {
1545 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1546 rtx result = NULL_RTX;
1547 int size;
1548
1549 /* We only support using 2 data registers as argument registers. */
1550 int nregs = 2;
1551
1552 /* Figure out the size of the object to be passed. */
1553 if (mode == BLKmode)
1554 size = int_size_in_bytes (type);
1555 else
1556 size = GET_MODE_SIZE (mode);
1557
1558 cum->nbytes = (cum->nbytes + 3) & ~3;
1559
1560 /* Don't pass this arg via a register if all the argument registers
1561 are used up. */
1562 if (cum->nbytes > nregs * UNITS_PER_WORD)
1563 return result;
1564
1565 /* Don't pass this arg via a register if it would be split between
1566 registers and memory. */
1567 if (type == NULL_TREE
1568 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1569 return result;
1570
1571 switch (cum->nbytes / UNITS_PER_WORD)
1572 {
1573 case 0:
1574 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM);
1575 break;
1576 case 1:
1577 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1);
1578 break;
1579 default:
1580 break;
1581 }
1582
1583 return result;
1584 }
1585
1586 /* Update the data in CUM to advance over an argument
1587 of mode MODE and data type TYPE.
1588 (TYPE is null for libcalls where that information may not be available.) */
1589
1590 static void
mn10300_function_arg_advance(cumulative_args_t cum_v,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)1591 mn10300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
1592 const_tree type, bool named ATTRIBUTE_UNUSED)
1593 {
1594 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1595
1596 cum->nbytes += (mode != BLKmode
1597 ? (GET_MODE_SIZE (mode) + 3) & ~3
1598 : (int_size_in_bytes (type) + 3) & ~3);
1599 }
1600
1601 /* Return the number of bytes of registers to use for an argument passed
1602 partially in registers and partially in memory. */
1603
1604 static int
mn10300_arg_partial_bytes(cumulative_args_t cum_v,machine_mode mode,tree type,bool named ATTRIBUTE_UNUSED)1605 mn10300_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
1606 tree type, bool named ATTRIBUTE_UNUSED)
1607 {
1608 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1609 int size;
1610
1611 /* We only support using 2 data registers as argument registers. */
1612 int nregs = 2;
1613
1614 /* Figure out the size of the object to be passed. */
1615 if (mode == BLKmode)
1616 size = int_size_in_bytes (type);
1617 else
1618 size = GET_MODE_SIZE (mode);
1619
1620 cum->nbytes = (cum->nbytes + 3) & ~3;
1621
1622 /* Don't pass this arg via a register if all the argument registers
1623 are used up. */
1624 if (cum->nbytes > nregs * UNITS_PER_WORD)
1625 return 0;
1626
1627 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1628 return 0;
1629
1630 /* Don't pass this arg via a register if it would be split between
1631 registers and memory. */
1632 if (type == NULL_TREE
1633 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1634 return 0;
1635
1636 return nregs * UNITS_PER_WORD - cum->nbytes;
1637 }
1638
1639 /* Return the location of the function's value. This will be either
1640 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1641 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1642 we only return the PARALLEL for outgoing values; we do not want
1643 callers relying on this extra copy. */
1644
1645 static rtx
mn10300_function_value(const_tree valtype,const_tree fn_decl_or_type ATTRIBUTE_UNUSED,bool outgoing)1646 mn10300_function_value (const_tree valtype,
1647 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1648 bool outgoing)
1649 {
1650 rtx rv;
1651 machine_mode mode = TYPE_MODE (valtype);
1652
1653 if (! POINTER_TYPE_P (valtype))
1654 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1655 else if (! TARGET_PTR_A0D0 || ! outgoing
1656 || cfun->returns_struct)
1657 return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
1658
1659 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
1660 XVECEXP (rv, 0, 0)
1661 = gen_rtx_EXPR_LIST (VOIDmode,
1662 gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
1663 GEN_INT (0));
1664
1665 XVECEXP (rv, 0, 1)
1666 = gen_rtx_EXPR_LIST (VOIDmode,
1667 gen_rtx_REG (mode, FIRST_DATA_REGNUM),
1668 GEN_INT (0));
1669 return rv;
1670 }
1671
1672 /* Implements TARGET_LIBCALL_VALUE. */
1673
1674 static rtx
mn10300_libcall_value(machine_mode mode,const_rtx fun ATTRIBUTE_UNUSED)1675 mn10300_libcall_value (machine_mode mode,
1676 const_rtx fun ATTRIBUTE_UNUSED)
1677 {
1678 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1679 }
1680
1681 /* Implements FUNCTION_VALUE_REGNO_P. */
1682
1683 bool
mn10300_function_value_regno_p(const unsigned int regno)1684 mn10300_function_value_regno_p (const unsigned int regno)
1685 {
1686 return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM);
1687 }
1688
1689 /* Output an addition operation. */
1690
1691 const char *
mn10300_output_add(rtx operands[3],bool need_flags)1692 mn10300_output_add (rtx operands[3], bool need_flags)
1693 {
1694 rtx dest, src1, src2;
1695 unsigned int dest_regnum, src1_regnum, src2_regnum;
1696 enum reg_class src1_class, src2_class, dest_class;
1697
1698 dest = operands[0];
1699 src1 = operands[1];
1700 src2 = operands[2];
1701
1702 dest_regnum = true_regnum (dest);
1703 src1_regnum = true_regnum (src1);
1704
1705 dest_class = REGNO_REG_CLASS (dest_regnum);
1706 src1_class = REGNO_REG_CLASS (src1_regnum);
1707
1708 if (CONST_INT_P (src2))
1709 {
1710 gcc_assert (dest_regnum == src1_regnum);
1711
1712 if (src2 == const1_rtx && !need_flags)
1713 return "inc %0";
1714 if (INTVAL (src2) == 4 && !need_flags && dest_class != DATA_REGS)
1715 return "inc4 %0";
1716
1717 gcc_assert (!need_flags || dest_class != SP_REGS);
1718 return "add %2,%0";
1719 }
1720 else if (CONSTANT_P (src2))
1721 return "add %2,%0";
1722
1723 src2_regnum = true_regnum (src2);
1724 src2_class = REGNO_REG_CLASS (src2_regnum);
1725
1726 if (dest_regnum == src1_regnum)
1727 return "add %2,%0";
1728 if (dest_regnum == src2_regnum)
1729 return "add %1,%0";
1730
1731 /* The rest of the cases are reg = reg+reg. For AM33, we can implement
1732 this directly, as below, but when optimizing for space we can sometimes
1733 do better by using a mov+add. For MN103, we claimed that we could
1734 implement a three-operand add because the various move and add insns
1735 change sizes across register classes, and we can often do better than
1736 reload in choosing which operand to move. */
1737 if (TARGET_AM33 && optimize_insn_for_speed_p ())
1738 return "add %2,%1,%0";
1739
1740 /* Catch cases where no extended register was used. */
1741 if (src1_class != EXTENDED_REGS
1742 && src2_class != EXTENDED_REGS
1743 && dest_class != EXTENDED_REGS)
1744 {
1745 /* We have to copy one of the sources into the destination, then
1746 add the other source to the destination.
1747
1748 Carefully select which source to copy to the destination; a
1749 naive implementation will waste a byte when the source classes
1750 are different and the destination is an address register.
1751 Selecting the lowest cost register copy will optimize this
1752 sequence. */
1753 if (src1_class == dest_class)
1754 return "mov %1,%0\n\tadd %2,%0";
1755 else
1756 return "mov %2,%0\n\tadd %1,%0";
1757 }
1758
1759 /* At least one register is an extended register. */
1760
1761 /* The three operand add instruction on the am33 is a win iff the
1762 output register is an extended register, or if both source
1763 registers are extended registers. */
1764 if (dest_class == EXTENDED_REGS || src1_class == src2_class)
1765 return "add %2,%1,%0";
1766
1767 /* It is better to copy one of the sources to the destination, then
1768 perform a 2 address add. The destination in this case must be
1769 an address or data register and one of the sources must be an
1770 extended register and the remaining source must not be an extended
1771 register.
1772
1773 The best code for this case is to copy the extended reg to the
1774 destination, then emit a two address add. */
1775 if (src1_class == EXTENDED_REGS)
1776 return "mov %1,%0\n\tadd %2,%0";
1777 else
1778 return "mov %2,%0\n\tadd %1,%0";
1779 }
1780
1781 /* Return 1 if X contains a symbolic expression. We know these
1782 expressions will have one of a few well defined forms, so
1783 we need only check those forms. */
1784
1785 int
mn10300_symbolic_operand(rtx op,machine_mode mode ATTRIBUTE_UNUSED)1786 mn10300_symbolic_operand (rtx op,
1787 machine_mode mode ATTRIBUTE_UNUSED)
1788 {
1789 switch (GET_CODE (op))
1790 {
1791 case SYMBOL_REF:
1792 case LABEL_REF:
1793 return 1;
1794 case CONST:
1795 op = XEXP (op, 0);
1796 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1797 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1798 && CONST_INT_P (XEXP (op, 1)));
1799 default:
1800 return 0;
1801 }
1802 }
1803
1804 /* Try machine dependent ways of modifying an illegitimate address
1805 to be legitimate. If we find one, return the new valid address.
1806 This macro is used in only one place: `memory_address' in explow.c.
1807
1808 OLDX is the address as it was before break_out_memory_refs was called.
1809 In some cases it is useful to look at this to decide what needs to be done.
1810
1811 Normally it is always safe for this macro to do nothing. It exists to
1812 recognize opportunities to optimize the output.
1813
1814 But on a few ports with segmented architectures and indexed addressing
1815 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1816
1817 static rtx
mn10300_legitimize_address(rtx x,rtx oldx ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED)1818 mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1819 machine_mode mode ATTRIBUTE_UNUSED)
1820 {
1821 if (flag_pic && ! mn10300_legitimate_pic_operand_p (x))
1822 x = mn10300_legitimize_pic_address (oldx, NULL_RTX);
1823
1824 /* Uh-oh. We might have an address for x[n-100000]. This needs
1825 special handling to avoid creating an indexed memory address
1826 with x-100000 as the base. */
1827 if (GET_CODE (x) == PLUS
1828 && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode))
1829 {
1830 /* Ugly. We modify things here so that the address offset specified
1831 by the index expression is computed first, then added to x to form
1832 the entire address. */
1833
1834 rtx regx1, regy1, regy2, y;
1835
1836 /* Strip off any CONST. */
1837 y = XEXP (x, 1);
1838 if (GET_CODE (y) == CONST)
1839 y = XEXP (y, 0);
1840
1841 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1842 {
1843 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1844 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1845 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1846 regx1 = force_reg (Pmode,
1847 gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1,
1848 regy2));
1849 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1850 }
1851 }
1852 return x;
1853 }
1854
1855 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1856 @GOTOFF in `reg'. */
1857
1858 rtx
mn10300_legitimize_pic_address(rtx orig,rtx reg)1859 mn10300_legitimize_pic_address (rtx orig, rtx reg)
1860 {
1861 rtx x;
1862
1863 if (GET_CODE (orig) == LABEL_REF
1864 || (GET_CODE (orig) == SYMBOL_REF
1865 && (CONSTANT_POOL_ADDRESS_P (orig)
1866 || ! MN10300_GLOBAL_P (orig))))
1867 {
1868 if (reg == NULL)
1869 reg = gen_reg_rtx (Pmode);
1870
1871 x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOTOFF);
1872 x = gen_rtx_CONST (SImode, x);
1873 emit_move_insn (reg, x);
1874
1875 x = emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1876 }
1877 else if (GET_CODE (orig) == SYMBOL_REF)
1878 {
1879 if (reg == NULL)
1880 reg = gen_reg_rtx (Pmode);
1881
1882 x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOT);
1883 x = gen_rtx_CONST (SImode, x);
1884 x = gen_rtx_PLUS (SImode, pic_offset_table_rtx, x);
1885 x = gen_const_mem (SImode, x);
1886
1887 x = emit_move_insn (reg, x);
1888 }
1889 else
1890 return orig;
1891
1892 set_unique_reg_note (x, REG_EQUAL, orig);
1893 return reg;
1894 }
1895
1896 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1897 isn't protected by a PIC unspec; nonzero otherwise. */
1898
1899 int
mn10300_legitimate_pic_operand_p(rtx x)1900 mn10300_legitimate_pic_operand_p (rtx x)
1901 {
1902 const char *fmt;
1903 int i;
1904
1905 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1906 return 0;
1907
1908 if (GET_CODE (x) == UNSPEC
1909 && (XINT (x, 1) == UNSPEC_PIC
1910 || XINT (x, 1) == UNSPEC_GOT
1911 || XINT (x, 1) == UNSPEC_GOTOFF
1912 || XINT (x, 1) == UNSPEC_PLT
1913 || XINT (x, 1) == UNSPEC_GOTSYM_OFF))
1914 return 1;
1915
1916 fmt = GET_RTX_FORMAT (GET_CODE (x));
1917 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1918 {
1919 if (fmt[i] == 'E')
1920 {
1921 int j;
1922
1923 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1924 if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j)))
1925 return 0;
1926 }
1927 else if (fmt[i] == 'e'
1928 && ! mn10300_legitimate_pic_operand_p (XEXP (x, i)))
1929 return 0;
1930 }
1931
1932 return 1;
1933 }
1934
1935 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1936 legitimate, and FALSE otherwise.
1937
1938 On the mn10300, the value in the address register must be
1939 in the same memory space/segment as the effective address.
1940
1941 This is problematical for reload since it does not understand
1942 that base+index != index+base in a memory reference.
1943
1944 Note it is still possible to use reg+reg addressing modes,
1945 it's just much more difficult. For a discussion of a possible
1946 workaround and solution, see the comments in pa.c before the
1947 function record_unscaled_index_insn_codes. */
1948
1949 static bool
mn10300_legitimate_address_p(machine_mode mode,rtx x,bool strict)1950 mn10300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
1951 {
1952 rtx base, index;
1953
1954 if (CONSTANT_ADDRESS_P (x))
1955 return !flag_pic || mn10300_legitimate_pic_operand_p (x);
1956
1957 if (RTX_OK_FOR_BASE_P (x, strict))
1958 return true;
1959
1960 if (TARGET_AM33 && (mode == SImode || mode == SFmode || mode == HImode))
1961 {
1962 if (GET_CODE (x) == POST_INC)
1963 return RTX_OK_FOR_BASE_P (XEXP (x, 0), strict);
1964 if (GET_CODE (x) == POST_MODIFY)
1965 return (RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
1966 && CONSTANT_ADDRESS_P (XEXP (x, 1)));
1967 }
1968
1969 if (GET_CODE (x) != PLUS)
1970 return false;
1971
1972 base = XEXP (x, 0);
1973 index = XEXP (x, 1);
1974
1975 if (!REG_P (base))
1976 return false;
1977 if (REG_P (index))
1978 {
1979 /* ??? Without AM33 generalized (Ri,Rn) addressing, reg+reg
1980 addressing is hard to satisfy. */
1981 if (!TARGET_AM33)
1982 return false;
1983
1984 return (REGNO_GENERAL_P (REGNO (base), strict)
1985 && REGNO_GENERAL_P (REGNO (index), strict));
1986 }
1987
1988 if (!REGNO_STRICT_OK_FOR_BASE_P (REGNO (base), strict))
1989 return false;
1990
1991 if (CONST_INT_P (index))
1992 return IN_RANGE (INTVAL (index), -1 - 0x7fffffff, 0x7fffffff);
1993
1994 if (CONSTANT_ADDRESS_P (index))
1995 return !flag_pic || mn10300_legitimate_pic_operand_p (index);
1996
1997 return false;
1998 }
1999
2000 bool
mn10300_regno_in_class_p(unsigned regno,int rclass,bool strict)2001 mn10300_regno_in_class_p (unsigned regno, int rclass, bool strict)
2002 {
2003 if (regno >= FIRST_PSEUDO_REGISTER)
2004 {
2005 if (!strict)
2006 return true;
2007 if (!reg_renumber)
2008 return false;
2009 regno = reg_renumber[regno];
2010 if (regno == INVALID_REGNUM)
2011 return false;
2012 }
2013 return TEST_HARD_REG_BIT (reg_class_contents[rclass], regno);
2014 }
2015
2016 rtx
mn10300_legitimize_reload_address(rtx x,machine_mode mode ATTRIBUTE_UNUSED,int opnum,int type,int ind_levels ATTRIBUTE_UNUSED)2017 mn10300_legitimize_reload_address (rtx x,
2018 machine_mode mode ATTRIBUTE_UNUSED,
2019 int opnum, int type,
2020 int ind_levels ATTRIBUTE_UNUSED)
2021 {
2022 bool any_change = false;
2023
2024 /* See above re disabling reg+reg addressing for MN103. */
2025 if (!TARGET_AM33)
2026 return NULL_RTX;
2027
2028 if (GET_CODE (x) != PLUS)
2029 return NULL_RTX;
2030
2031 if (XEXP (x, 0) == stack_pointer_rtx)
2032 {
2033 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2034 GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0,
2035 opnum, (enum reload_type) type);
2036 any_change = true;
2037 }
2038 if (XEXP (x, 1) == stack_pointer_rtx)
2039 {
2040 push_reload (XEXP (x, 1), NULL_RTX, &XEXP (x, 1), NULL,
2041 GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0,
2042 opnum, (enum reload_type) type);
2043 any_change = true;
2044 }
2045
2046 return any_change ? x : NULL_RTX;
2047 }
2048
2049 /* Implement TARGET_LEGITIMATE_CONSTANT_P. Returns TRUE if X is a valid
2050 constant. Note that some "constants" aren't valid, such as TLS
2051 symbols and unconverted GOT-based references, so we eliminate
2052 those here. */
2053
2054 static bool
mn10300_legitimate_constant_p(machine_mode mode ATTRIBUTE_UNUSED,rtx x)2055 mn10300_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2056 {
2057 switch (GET_CODE (x))
2058 {
2059 case CONST:
2060 x = XEXP (x, 0);
2061
2062 if (GET_CODE (x) == PLUS)
2063 {
2064 if (! CONST_INT_P (XEXP (x, 1)))
2065 return false;
2066 x = XEXP (x, 0);
2067 }
2068
2069 /* Only some unspecs are valid as "constants". */
2070 if (GET_CODE (x) == UNSPEC)
2071 {
2072 switch (XINT (x, 1))
2073 {
2074 case UNSPEC_PIC:
2075 case UNSPEC_GOT:
2076 case UNSPEC_GOTOFF:
2077 case UNSPEC_PLT:
2078 return true;
2079 default:
2080 return false;
2081 }
2082 }
2083
2084 /* We must have drilled down to a symbol. */
2085 if (! mn10300_symbolic_operand (x, Pmode))
2086 return false;
2087 break;
2088
2089 default:
2090 break;
2091 }
2092
2093 return true;
2094 }
2095
2096 /* Undo pic address legitimization for the benefit of debug info. */
2097
2098 static rtx
mn10300_delegitimize_address(rtx orig_x)2099 mn10300_delegitimize_address (rtx orig_x)
2100 {
2101 rtx x = orig_x, ret, addend = NULL;
2102 bool need_mem;
2103
2104 if (MEM_P (x))
2105 x = XEXP (x, 0);
2106 if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode)
2107 return orig_x;
2108
2109 if (XEXP (x, 0) == pic_offset_table_rtx)
2110 ;
2111 /* With the REG+REG addressing of AM33, var-tracking can re-assemble
2112 some odd-looking "addresses" that were never valid in the first place.
2113 We need to look harder to avoid warnings being emitted. */
2114 else if (GET_CODE (XEXP (x, 0)) == PLUS)
2115 {
2116 rtx x0 = XEXP (x, 0);
2117 rtx x00 = XEXP (x0, 0);
2118 rtx x01 = XEXP (x0, 1);
2119
2120 if (x00 == pic_offset_table_rtx)
2121 addend = x01;
2122 else if (x01 == pic_offset_table_rtx)
2123 addend = x00;
2124 else
2125 return orig_x;
2126
2127 }
2128 else
2129 return orig_x;
2130 x = XEXP (x, 1);
2131
2132 if (GET_CODE (x) != CONST)
2133 return orig_x;
2134 x = XEXP (x, 0);
2135 if (GET_CODE (x) != UNSPEC)
2136 return orig_x;
2137
2138 ret = XVECEXP (x, 0, 0);
2139 if (XINT (x, 1) == UNSPEC_GOTOFF)
2140 need_mem = false;
2141 else if (XINT (x, 1) == UNSPEC_GOT)
2142 need_mem = true;
2143 else
2144 return orig_x;
2145
2146 gcc_assert (GET_CODE (ret) == SYMBOL_REF);
2147 if (need_mem != MEM_P (orig_x))
2148 return orig_x;
2149 if (need_mem && addend)
2150 return orig_x;
2151 if (addend)
2152 ret = gen_rtx_PLUS (Pmode, addend, ret);
2153 return ret;
2154 }
2155
2156 /* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is
2157 the 3-byte fully general instruction; for MN103 this is the 2-byte form
2158 with an address register. */
2159
2160 static int
mn10300_address_cost(rtx x,machine_mode mode ATTRIBUTE_UNUSED,addr_space_t as ATTRIBUTE_UNUSED,bool speed)2161 mn10300_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED,
2162 addr_space_t as ATTRIBUTE_UNUSED, bool speed)
2163 {
2164 HOST_WIDE_INT i;
2165 rtx base, index;
2166
2167 switch (GET_CODE (x))
2168 {
2169 case CONST:
2170 case SYMBOL_REF:
2171 case LABEL_REF:
2172 /* We assume all of these require a 32-bit constant, even though
2173 some symbol and label references can be relaxed. */
2174 return speed ? 1 : 4;
2175
2176 case REG:
2177 case SUBREG:
2178 case POST_INC:
2179 return 0;
2180
2181 case POST_MODIFY:
2182 /* Assume any symbolic offset is a 32-bit constant. */
2183 i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
2184 if (IN_RANGE (i, -128, 127))
2185 return speed ? 0 : 1;
2186 if (speed)
2187 return 1;
2188 if (IN_RANGE (i, -0x800000, 0x7fffff))
2189 return 3;
2190 return 4;
2191
2192 case PLUS:
2193 base = XEXP (x, 0);
2194 index = XEXP (x, 1);
2195 if (register_operand (index, SImode))
2196 {
2197 /* Attempt to minimize the number of registers in the address.
2198 This is similar to what other ports do. */
2199 if (register_operand (base, SImode))
2200 return 1;
2201
2202 base = XEXP (x, 1);
2203 index = XEXP (x, 0);
2204 }
2205
2206 /* Assume any symbolic offset is a 32-bit constant. */
2207 i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
2208 if (IN_RANGE (i, -128, 127))
2209 return speed ? 0 : 1;
2210 if (IN_RANGE (i, -32768, 32767))
2211 return speed ? 0 : 2;
2212 return speed ? 2 : 6;
2213
2214 default:
2215 return rtx_cost (x, Pmode, MEM, 0, speed);
2216 }
2217 }
2218
2219 /* Implement the TARGET_REGISTER_MOVE_COST hook.
2220
2221 Recall that the base value of 2 is required by assumptions elsewhere
2222 in the body of the compiler, and that cost 2 is special-cased as an
2223 early exit from reload meaning no work is required. */
2224
2225 static int
mn10300_register_move_cost(machine_mode mode ATTRIBUTE_UNUSED,reg_class_t ifrom,reg_class_t ito)2226 mn10300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
2227 reg_class_t ifrom, reg_class_t ito)
2228 {
2229 enum reg_class from = (enum reg_class) ifrom;
2230 enum reg_class to = (enum reg_class) ito;
2231 enum reg_class scratch, test;
2232
2233 /* Simplify the following code by unifying the fp register classes. */
2234 if (to == FP_ACC_REGS)
2235 to = FP_REGS;
2236 if (from == FP_ACC_REGS)
2237 from = FP_REGS;
2238
2239 /* Diagnose invalid moves by costing them as two moves. */
2240
2241 scratch = NO_REGS;
2242 test = from;
2243 if (to == SP_REGS)
2244 scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
2245 else if (to == MDR_REGS)
2246 scratch = DATA_REGS;
2247 else if (to == FP_REGS && to != from)
2248 scratch = GENERAL_REGS;
2249 else
2250 {
2251 test = to;
2252 if (from == SP_REGS)
2253 scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
2254 else if (from == MDR_REGS)
2255 scratch = DATA_REGS;
2256 else if (from == FP_REGS && to != from)
2257 scratch = GENERAL_REGS;
2258 }
2259 if (scratch != NO_REGS && !reg_class_subset_p (test, scratch))
2260 return (mn10300_register_move_cost (VOIDmode, from, scratch)
2261 + mn10300_register_move_cost (VOIDmode, scratch, to));
2262
2263 /* From here on, all we need consider are legal combinations. */
2264
2265 if (optimize_size)
2266 {
2267 /* The scale here is bytes * 2. */
2268
2269 if (from == to && (to == ADDRESS_REGS || to == DATA_REGS))
2270 return 2;
2271
2272 if (from == SP_REGS)
2273 return (to == ADDRESS_REGS ? 2 : 6);
2274
2275 /* For MN103, all remaining legal moves are two bytes. */
2276 if (TARGET_AM33)
2277 return 4;
2278
2279 if (to == SP_REGS)
2280 return (from == ADDRESS_REGS ? 4 : 6);
2281
2282 if ((from == ADDRESS_REGS || from == DATA_REGS)
2283 && (to == ADDRESS_REGS || to == DATA_REGS))
2284 return 4;
2285
2286 if (to == EXTENDED_REGS)
2287 return (to == from ? 6 : 4);
2288
2289 /* What's left are SP_REGS, FP_REGS, or combinations of the above. */
2290 return 6;
2291 }
2292 else
2293 {
2294 /* The scale here is cycles * 2. */
2295
2296 if (to == FP_REGS)
2297 return 8;
2298 if (from == FP_REGS)
2299 return 4;
2300
2301 /* All legal moves between integral registers are single cycle. */
2302 return 2;
2303 }
2304 }
2305
2306 /* Implement the TARGET_MEMORY_MOVE_COST hook.
2307
2308 Given lack of the form of the address, this must be speed-relative,
2309 though we should never be less expensive than a size-relative register
2310 move cost above. This is not a problem. */
2311
2312 static int
mn10300_memory_move_cost(machine_mode mode ATTRIBUTE_UNUSED,reg_class_t iclass,bool in ATTRIBUTE_UNUSED)2313 mn10300_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
2314 reg_class_t iclass, bool in ATTRIBUTE_UNUSED)
2315 {
2316 enum reg_class rclass = (enum reg_class) iclass;
2317
2318 if (rclass == FP_REGS)
2319 return 8;
2320 return 6;
2321 }
2322
2323 /* Implement the TARGET_RTX_COSTS hook.
2324
2325 Speed-relative costs are relative to COSTS_N_INSNS, which is intended
2326 to represent cycles. Size-relative costs are in bytes. */
2327
2328 static bool
mn10300_rtx_costs(rtx x,machine_mode mode,int outer_code,int opno ATTRIBUTE_UNUSED,int * ptotal,bool speed)2329 mn10300_rtx_costs (rtx x, machine_mode mode, int outer_code,
2330 int opno ATTRIBUTE_UNUSED, int *ptotal, bool speed)
2331 {
2332 /* This value is used for SYMBOL_REF etc where we want to pretend
2333 we have a full 32-bit constant. */
2334 HOST_WIDE_INT i = 0x12345678;
2335 int total;
2336 int code = GET_CODE (x);
2337
2338 switch (code)
2339 {
2340 case CONST_INT:
2341 i = INTVAL (x);
2342 do_int_costs:
2343 if (speed)
2344 {
2345 if (outer_code == SET)
2346 {
2347 /* 16-bit integer loads have latency 1, 32-bit loads 2. */
2348 if (IN_RANGE (i, -32768, 32767))
2349 total = COSTS_N_INSNS (1);
2350 else
2351 total = COSTS_N_INSNS (2);
2352 }
2353 else
2354 {
2355 /* 16-bit integer operands don't affect latency;
2356 24-bit and 32-bit operands add a cycle. */
2357 if (IN_RANGE (i, -32768, 32767))
2358 total = 0;
2359 else
2360 total = COSTS_N_INSNS (1);
2361 }
2362 }
2363 else
2364 {
2365 if (outer_code == SET)
2366 {
2367 if (i == 0)
2368 total = 1;
2369 else if (IN_RANGE (i, -128, 127))
2370 total = 2;
2371 else if (IN_RANGE (i, -32768, 32767))
2372 total = 3;
2373 else
2374 total = 6;
2375 }
2376 else
2377 {
2378 /* Reference here is ADD An,Dn, vs ADD imm,Dn. */
2379 if (IN_RANGE (i, -128, 127))
2380 total = 0;
2381 else if (IN_RANGE (i, -32768, 32767))
2382 total = 2;
2383 else if (TARGET_AM33 && IN_RANGE (i, -0x01000000, 0x00ffffff))
2384 total = 3;
2385 else
2386 total = 4;
2387 }
2388 }
2389 goto alldone;
2390
2391 case CONST:
2392 case LABEL_REF:
2393 case SYMBOL_REF:
2394 case CONST_DOUBLE:
2395 /* We assume all of these require a 32-bit constant, even though
2396 some symbol and label references can be relaxed. */
2397 goto do_int_costs;
2398
2399 case UNSPEC:
2400 switch (XINT (x, 1))
2401 {
2402 case UNSPEC_PIC:
2403 case UNSPEC_GOT:
2404 case UNSPEC_GOTOFF:
2405 case UNSPEC_PLT:
2406 case UNSPEC_GOTSYM_OFF:
2407 /* The PIC unspecs also resolve to a 32-bit constant. */
2408 goto do_int_costs;
2409
2410 default:
2411 /* Assume any non-listed unspec is some sort of arithmetic. */
2412 goto do_arith_costs;
2413 }
2414
2415 case PLUS:
2416 /* Notice the size difference of INC and INC4. */
2417 if (!speed && outer_code == SET && CONST_INT_P (XEXP (x, 1)))
2418 {
2419 i = INTVAL (XEXP (x, 1));
2420 if (i == 1 || i == 4)
2421 {
2422 total = 1 + rtx_cost (XEXP (x, 0), mode, PLUS, 0, speed);
2423 goto alldone;
2424 }
2425 }
2426 goto do_arith_costs;
2427
2428 case MINUS:
2429 case AND:
2430 case IOR:
2431 case XOR:
2432 case NOT:
2433 case NEG:
2434 case ZERO_EXTEND:
2435 case SIGN_EXTEND:
2436 case COMPARE:
2437 case BSWAP:
2438 case CLZ:
2439 do_arith_costs:
2440 total = (speed ? COSTS_N_INSNS (1) : 2);
2441 break;
2442
2443 case ASHIFT:
2444 /* Notice the size difference of ASL2 and variants. */
2445 if (!speed && CONST_INT_P (XEXP (x, 1)))
2446 switch (INTVAL (XEXP (x, 1)))
2447 {
2448 case 1:
2449 case 2:
2450 total = 1;
2451 goto alldone;
2452 case 3:
2453 case 4:
2454 total = 2;
2455 goto alldone;
2456 }
2457 /* FALLTHRU */
2458
2459 case ASHIFTRT:
2460 case LSHIFTRT:
2461 total = (speed ? COSTS_N_INSNS (1) : 3);
2462 goto alldone;
2463
2464 case MULT:
2465 total = (speed ? COSTS_N_INSNS (3) : 2);
2466 break;
2467
2468 case DIV:
2469 case UDIV:
2470 case MOD:
2471 case UMOD:
2472 total = (speed ? COSTS_N_INSNS (39)
2473 /* Include space to load+retrieve MDR. */
2474 : code == MOD || code == UMOD ? 6 : 4);
2475 break;
2476
2477 case MEM:
2478 total = mn10300_address_cost (XEXP (x, 0), mode,
2479 MEM_ADDR_SPACE (x), speed);
2480 if (speed)
2481 total = COSTS_N_INSNS (2 + total);
2482 goto alldone;
2483
2484 default:
2485 /* Probably not implemented. Assume external call. */
2486 total = (speed ? COSTS_N_INSNS (10) : 7);
2487 break;
2488 }
2489
2490 *ptotal = total;
2491 return false;
2492
2493 alldone:
2494 *ptotal = total;
2495 return true;
2496 }
2497
2498 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2499 may access it using GOTOFF instead of GOT. */
2500
2501 static void
mn10300_encode_section_info(tree decl,rtx rtl,int first)2502 mn10300_encode_section_info (tree decl, rtx rtl, int first)
2503 {
2504 rtx symbol;
2505
2506 default_encode_section_info (decl, rtl, first);
2507
2508 if (! MEM_P (rtl))
2509 return;
2510
2511 symbol = XEXP (rtl, 0);
2512 if (GET_CODE (symbol) != SYMBOL_REF)
2513 return;
2514
2515 if (flag_pic)
2516 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
2517 }
2518
2519 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2520 and readonly data size. So we crank up the case threshold value to
2521 encourage a series of if/else comparisons to implement many small switch
2522 statements. In theory, this value could be increased much more if we
2523 were solely optimizing for space, but we keep it "reasonable" to avoid
2524 serious code efficiency lossage. */
2525
2526 static unsigned int
mn10300_case_values_threshold(void)2527 mn10300_case_values_threshold (void)
2528 {
2529 return 6;
2530 }
2531
2532 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2533
2534 static void
mn10300_trampoline_init(rtx m_tramp,tree fndecl,rtx chain_value)2535 mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2536 {
2537 rtx mem, disp, fnaddr = XEXP (DECL_RTL (fndecl), 0);
2538
2539 /* This is a strict alignment target, which means that we play
2540 some games to make sure that the locations at which we need
2541 to store <chain> and <disp> wind up at aligned addresses.
2542
2543 0x28 0x00 add 0,d0
2544 0xfc 0xdd mov chain,a1
2545 <chain>
2546 0xf8 0xed 0x00 btst 0,d1
2547 0xdc jmp fnaddr
2548 <disp>
2549
2550 Note that the two extra insns are effectively nops; they
2551 clobber the flags but do not affect the contents of D0 or D1. */
2552
2553 disp = expand_binop (SImode, sub_optab, fnaddr,
2554 plus_constant (Pmode, XEXP (m_tramp, 0), 11),
2555 NULL_RTX, 1, OPTAB_DIRECT);
2556
2557 mem = adjust_address (m_tramp, SImode, 0);
2558 emit_move_insn (mem, gen_int_mode (0xddfc0028, SImode));
2559 mem = adjust_address (m_tramp, SImode, 4);
2560 emit_move_insn (mem, chain_value);
2561 mem = adjust_address (m_tramp, SImode, 8);
2562 emit_move_insn (mem, gen_int_mode (0xdc00edf8, SImode));
2563 mem = adjust_address (m_tramp, SImode, 12);
2564 emit_move_insn (mem, disp);
2565 }
2566
2567 /* Output the assembler code for a C++ thunk function.
2568 THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2569 is the decl for the target function. DELTA is an immediate constant
2570 offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
2571 the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2572 additionally added to THIS. Finally jump to the entry point of
2573 FUNCTION. */
2574
2575 static void
mn10300_asm_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset,tree function)2576 mn10300_asm_output_mi_thunk (FILE * file,
2577 tree thunk_fndecl ATTRIBUTE_UNUSED,
2578 HOST_WIDE_INT delta,
2579 HOST_WIDE_INT vcall_offset,
2580 tree function)
2581 {
2582 const char * _this;
2583
2584 /* Get the register holding the THIS parameter. Handle the case
2585 where there is a hidden first argument for a returned structure. */
2586 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
2587 _this = reg_names [FIRST_ARGUMENT_REGNUM + 1];
2588 else
2589 _this = reg_names [FIRST_ARGUMENT_REGNUM];
2590
2591 fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START);
2592
2593 if (delta)
2594 fprintf (file, "\tadd %d, %s\n", (int) delta, _this);
2595
2596 if (vcall_offset)
2597 {
2598 const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1];
2599
2600 fprintf (file, "\tmov %s, %s\n", _this, scratch);
2601 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2602 fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch);
2603 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2604 fprintf (file, "\tadd %s, %s\n", scratch, _this);
2605 }
2606
2607 fputs ("\tjmp ", file);
2608 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
2609 putc ('\n', file);
2610 }
2611
2612 /* Return true if mn10300_output_mi_thunk would be able to output the
2613 assembler code for the thunk function specified by the arguments
2614 it is passed, and false otherwise. */
2615
2616 static bool
mn10300_can_output_mi_thunk(const_tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta ATTRIBUTE_UNUSED,HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,const_tree function ATTRIBUTE_UNUSED)2617 mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
2618 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
2619 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2620 const_tree function ATTRIBUTE_UNUSED)
2621 {
2622 return true;
2623 }
2624
2625 bool
mn10300_hard_regno_mode_ok(unsigned int regno,machine_mode mode)2626 mn10300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2627 {
2628 if (REGNO_REG_CLASS (regno) == FP_REGS
2629 || REGNO_REG_CLASS (regno) == FP_ACC_REGS)
2630 /* Do not store integer values in FP registers. */
2631 return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0);
2632
2633 if (! TARGET_AM33 && REGNO_REG_CLASS (regno) == EXTENDED_REGS)
2634 return false;
2635
2636 if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4)
2637 return true;
2638
2639 if (REGNO_REG_CLASS (regno) == DATA_REGS
2640 || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS)
2641 || REGNO_REG_CLASS (regno) == EXTENDED_REGS)
2642 return GET_MODE_SIZE (mode) <= 4;
2643
2644 return false;
2645 }
2646
2647 bool
mn10300_modes_tieable(machine_mode mode1,machine_mode mode2)2648 mn10300_modes_tieable (machine_mode mode1, machine_mode mode2)
2649 {
2650 if (GET_MODE_CLASS (mode1) == MODE_FLOAT
2651 && GET_MODE_CLASS (mode2) != MODE_FLOAT)
2652 return false;
2653
2654 if (GET_MODE_CLASS (mode2) == MODE_FLOAT
2655 && GET_MODE_CLASS (mode1) != MODE_FLOAT)
2656 return false;
2657
2658 if (TARGET_AM33
2659 || mode1 == mode2
2660 || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4))
2661 return true;
2662
2663 return false;
2664 }
2665
2666 static int
cc_flags_for_mode(machine_mode mode)2667 cc_flags_for_mode (machine_mode mode)
2668 {
2669 switch (mode)
2670 {
2671 case CCmode:
2672 return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C | CC_FLAG_V;
2673 case CCZNCmode:
2674 return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C;
2675 case CCZNmode:
2676 return CC_FLAG_Z | CC_FLAG_N;
2677 case CC_FLOATmode:
2678 return -1;
2679 default:
2680 gcc_unreachable ();
2681 }
2682 }
2683
2684 static int
cc_flags_for_code(enum rtx_code code)2685 cc_flags_for_code (enum rtx_code code)
2686 {
2687 switch (code)
2688 {
2689 case EQ: /* Z */
2690 case NE: /* ~Z */
2691 return CC_FLAG_Z;
2692
2693 case LT: /* N */
2694 case GE: /* ~N */
2695 return CC_FLAG_N;
2696 break;
2697
2698 case GT: /* ~(Z|(N^V)) */
2699 case LE: /* Z|(N^V) */
2700 return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_V;
2701
2702 case GEU: /* ~C */
2703 case LTU: /* C */
2704 return CC_FLAG_C;
2705
2706 case GTU: /* ~(C | Z) */
2707 case LEU: /* C | Z */
2708 return CC_FLAG_Z | CC_FLAG_C;
2709
2710 case ORDERED:
2711 case UNORDERED:
2712 case LTGT:
2713 case UNEQ:
2714 case UNGE:
2715 case UNGT:
2716 case UNLE:
2717 case UNLT:
2718 return -1;
2719
2720 default:
2721 gcc_unreachable ();
2722 }
2723 }
2724
2725 machine_mode
mn10300_select_cc_mode(enum rtx_code code,rtx x,rtx y ATTRIBUTE_UNUSED)2726 mn10300_select_cc_mode (enum rtx_code code, rtx x, rtx y ATTRIBUTE_UNUSED)
2727 {
2728 int req;
2729
2730 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2731 return CC_FLOATmode;
2732
2733 req = cc_flags_for_code (code);
2734
2735 if (req & CC_FLAG_V)
2736 return CCmode;
2737 if (req & CC_FLAG_C)
2738 return CCZNCmode;
2739 return CCZNmode;
2740 }
2741
2742 static inline bool
set_is_load_p(rtx set)2743 set_is_load_p (rtx set)
2744 {
2745 return MEM_P (SET_SRC (set));
2746 }
2747
2748 static inline bool
set_is_store_p(rtx set)2749 set_is_store_p (rtx set)
2750 {
2751 return MEM_P (SET_DEST (set));
2752 }
2753
2754 /* Update scheduling costs for situations that cannot be
2755 described using the attributes and DFA machinery.
2756 DEP is the insn being scheduled.
2757 INSN is the previous insn.
2758 COST is the current cycle cost for DEP. */
2759
2760 static int
mn10300_adjust_sched_cost(rtx_insn * insn,rtx link,rtx_insn * dep,int cost)2761 mn10300_adjust_sched_cost (rtx_insn *insn, rtx link, rtx_insn *dep, int cost)
2762 {
2763 rtx insn_set;
2764 rtx dep_set;
2765 int timings;
2766
2767 if (!TARGET_AM33)
2768 return 1;
2769
2770 /* We are only interested in pairs of SET. */
2771 insn_set = single_set (insn);
2772 if (!insn_set)
2773 return cost;
2774
2775 dep_set = single_set (dep);
2776 if (!dep_set)
2777 return cost;
2778
2779 /* For the AM34 a load instruction that follows a
2780 store instruction incurs an extra cycle of delay. */
2781 if (mn10300_tune_cpu == PROCESSOR_AM34
2782 && set_is_load_p (dep_set)
2783 && set_is_store_p (insn_set))
2784 cost += 1;
2785
2786 /* For the AM34 a non-store, non-branch FPU insn that follows
2787 another FPU insn incurs a one cycle throughput increase. */
2788 else if (mn10300_tune_cpu == PROCESSOR_AM34
2789 && ! set_is_store_p (insn_set)
2790 && ! JUMP_P (insn)
2791 && GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set))) == MODE_FLOAT
2792 && GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set))) == MODE_FLOAT)
2793 cost += 1;
2794
2795 /* Resolve the conflict described in section 1-7-4 of
2796 Chapter 3 of the MN103E Series Instruction Manual
2797 where it says:
2798
2799 "When the preceding instruction is a CPU load or
2800 store instruction, a following FPU instruction
2801 cannot be executed until the CPU completes the
2802 latency period even though there are no register
2803 or flag dependencies between them." */
2804
2805 /* Only the AM33-2 (and later) CPUs have FPU instructions. */
2806 if (! TARGET_AM33_2)
2807 return cost;
2808
2809 /* If a data dependence already exists then the cost is correct. */
2810 if (REG_NOTE_KIND (link) == 0)
2811 return cost;
2812
2813 /* Check that the instruction about to scheduled is an FPU instruction. */
2814 if (GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set))) != MODE_FLOAT)
2815 return cost;
2816
2817 /* Now check to see if the previous instruction is a load or store. */
2818 if (! set_is_load_p (insn_set) && ! set_is_store_p (insn_set))
2819 return cost;
2820
2821 /* XXX: Verify: The text of 1-7-4 implies that the restriction
2822 only applies when an INTEGER load/store precedes an FPU
2823 instruction, but is this true ? For now we assume that it is. */
2824 if (GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set))) != MODE_INT)
2825 return cost;
2826
2827 /* Extract the latency value from the timings attribute. */
2828 timings = get_attr_timings (insn);
2829 return timings < 100 ? (timings % 10) : (timings % 100);
2830 }
2831
2832 static void
mn10300_conditional_register_usage(void)2833 mn10300_conditional_register_usage (void)
2834 {
2835 unsigned int i;
2836
2837 if (!TARGET_AM33)
2838 {
2839 for (i = FIRST_EXTENDED_REGNUM;
2840 i <= LAST_EXTENDED_REGNUM; i++)
2841 fixed_regs[i] = call_used_regs[i] = 1;
2842 }
2843 if (!TARGET_AM33_2)
2844 {
2845 for (i = FIRST_FP_REGNUM;
2846 i <= LAST_FP_REGNUM; i++)
2847 fixed_regs[i] = call_used_regs[i] = 1;
2848 }
2849 if (flag_pic)
2850 fixed_regs[PIC_OFFSET_TABLE_REGNUM] =
2851 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
2852 }
2853
2854 /* Worker function for TARGET_MD_ASM_ADJUST.
2855 We do this in the mn10300 backend to maintain source compatibility
2856 with the old cc0-based compiler. */
2857
2858 static rtx_insn *
mn10300_md_asm_adjust(vec<rtx> &,vec<rtx> &,vec<const char * > &,vec<rtx> & clobbers,HARD_REG_SET & clobbered_regs)2859 mn10300_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
2860 vec<const char *> &/*constraints*/,
2861 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
2862 {
2863 clobbers.safe_push (gen_rtx_REG (CCmode, CC_REG));
2864 SET_HARD_REG_BIT (clobbered_regs, CC_REG);
2865 return NULL;
2866 }
2867
2868 /* A helper function for splitting cbranch patterns after reload. */
2869
2870 void
mn10300_split_cbranch(machine_mode cmp_mode,rtx cmp_op,rtx label_ref)2871 mn10300_split_cbranch (machine_mode cmp_mode, rtx cmp_op, rtx label_ref)
2872 {
2873 rtx flags, x;
2874
2875 flags = gen_rtx_REG (cmp_mode, CC_REG);
2876 x = gen_rtx_COMPARE (cmp_mode, XEXP (cmp_op, 0), XEXP (cmp_op, 1));
2877 x = gen_rtx_SET (flags, x);
2878 emit_insn (x);
2879
2880 x = gen_rtx_fmt_ee (GET_CODE (cmp_op), VOIDmode, flags, const0_rtx);
2881 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label_ref, pc_rtx);
2882 x = gen_rtx_SET (pc_rtx, x);
2883 emit_jump_insn (x);
2884 }
2885
2886 /* A helper function for matching parallels that set the flags. */
2887
2888 bool
mn10300_match_ccmode(rtx insn,machine_mode cc_mode)2889 mn10300_match_ccmode (rtx insn, machine_mode cc_mode)
2890 {
2891 rtx op1, flags;
2892 machine_mode flags_mode;
2893
2894 gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2);
2895
2896 op1 = XVECEXP (PATTERN (insn), 0, 1);
2897 gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
2898
2899 flags = SET_DEST (op1);
2900 flags_mode = GET_MODE (flags);
2901
2902 if (GET_MODE (SET_SRC (op1)) != flags_mode)
2903 return false;
2904 if (GET_MODE_CLASS (flags_mode) != MODE_CC)
2905 return false;
2906
2907 /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
2908 if (cc_flags_for_mode (flags_mode) & ~cc_flags_for_mode (cc_mode))
2909 return false;
2910
2911 return true;
2912 }
2913
2914 /* This function is used to help split:
2915
2916 (set (reg) (and (reg) (int)))
2917
2918 into:
2919
2920 (set (reg) (shift (reg) (int))
2921 (set (reg) (shift (reg) (int))
2922
2923 where the shitfs will be shorter than the "and" insn.
2924
2925 It returns the number of bits that should be shifted. A positive
2926 values means that the low bits are to be cleared (and hence the
2927 shifts should be right followed by left) whereas a negative value
2928 means that the high bits are to be cleared (left followed by right).
2929 Zero is returned when it would not be economical to split the AND. */
2930
2931 int
mn10300_split_and_operand_count(rtx op)2932 mn10300_split_and_operand_count (rtx op)
2933 {
2934 HOST_WIDE_INT val = INTVAL (op);
2935 int count;
2936
2937 if (val < 0)
2938 {
2939 /* High bit is set, look for bits clear at the bottom. */
2940 count = exact_log2 (-val);
2941 if (count < 0)
2942 return 0;
2943 /* This is only size win if we can use the asl2 insn. Otherwise we
2944 would be replacing 1 6-byte insn with 2 3-byte insns. */
2945 if (count > (optimize_insn_for_speed_p () ? 2 : 4))
2946 return 0;
2947 return count;
2948 }
2949 else
2950 {
2951 /* High bit is clear, look for bits set at the bottom. */
2952 count = exact_log2 (val + 1);
2953 count = 32 - count;
2954 /* Again, this is only a size win with asl2. */
2955 if (count > (optimize_insn_for_speed_p () ? 2 : 4))
2956 return 0;
2957 return -count;
2958 }
2959 }
2960
2961 struct liw_data
2962 {
2963 enum attr_liw slot;
2964 enum attr_liw_op op;
2965 rtx dest;
2966 rtx src;
2967 };
2968
2969 /* Decide if the given insn is a candidate for LIW bundling. If it is then
2970 extract the operands and LIW attributes from the insn and use them to fill
2971 in the liw_data structure. Return true upon success or false if the insn
2972 cannot be bundled. */
2973
2974 static bool
extract_bundle(rtx_insn * insn,struct liw_data * pdata)2975 extract_bundle (rtx_insn *insn, struct liw_data * pdata)
2976 {
2977 bool allow_consts = true;
2978 rtx p;
2979
2980 gcc_assert (pdata != NULL);
2981
2982 if (insn == NULL)
2983 return false;
2984 /* Make sure that we are dealing with a simple SET insn. */
2985 p = single_set (insn);
2986 if (p == NULL_RTX)
2987 return false;
2988
2989 /* Make sure that it could go into one of the LIW pipelines. */
2990 pdata->slot = get_attr_liw (insn);
2991 if (pdata->slot == LIW_BOTH)
2992 return false;
2993
2994 pdata->op = get_attr_liw_op (insn);
2995
2996 switch (pdata->op)
2997 {
2998 case LIW_OP_MOV:
2999 pdata->dest = SET_DEST (p);
3000 pdata->src = SET_SRC (p);
3001 break;
3002 case LIW_OP_CMP:
3003 pdata->dest = XEXP (SET_SRC (p), 0);
3004 pdata->src = XEXP (SET_SRC (p), 1);
3005 break;
3006 case LIW_OP_NONE:
3007 return false;
3008 case LIW_OP_AND:
3009 case LIW_OP_OR:
3010 case LIW_OP_XOR:
3011 /* The AND, OR and XOR long instruction words only accept register arguments. */
3012 allow_consts = false;
3013 /* Fall through. */
3014 default:
3015 pdata->dest = SET_DEST (p);
3016 pdata->src = XEXP (SET_SRC (p), 1);
3017 break;
3018 }
3019
3020 if (! REG_P (pdata->dest))
3021 return false;
3022
3023 if (REG_P (pdata->src))
3024 return true;
3025
3026 return allow_consts && satisfies_constraint_O (pdata->src);
3027 }
3028
3029 /* Make sure that it is OK to execute LIW1 and LIW2 in parallel. GCC generated
3030 the instructions with the assumption that LIW1 would be executed before LIW2
3031 so we must check for overlaps between their sources and destinations. */
3032
3033 static bool
check_liw_constraints(struct liw_data * pliw1,struct liw_data * pliw2)3034 check_liw_constraints (struct liw_data * pliw1, struct liw_data * pliw2)
3035 {
3036 /* Check for slot conflicts. */
3037 if (pliw2->slot == pliw1->slot && pliw1->slot != LIW_EITHER)
3038 return false;
3039
3040 /* If either operation is a compare, then "dest" is really an input; the real
3041 destination is CC_REG. So these instructions need different checks. */
3042
3043 /* Changing "CMP ; OP" into "CMP | OP" is OK because the comparison will
3044 check its values prior to any changes made by OP. */
3045 if (pliw1->op == LIW_OP_CMP)
3046 {
3047 /* Two sequential comparisons means dead code, which ought to
3048 have been eliminated given that bundling only happens with
3049 optimization. We cannot bundle them in any case. */
3050 gcc_assert (pliw1->op != pliw2->op);
3051 return true;
3052 }
3053
3054 /* Changing "OP ; CMP" into "OP | CMP" does not work if the value being compared
3055 is the destination of OP, as the CMP will look at the old value, not the new
3056 one. */
3057 if (pliw2->op == LIW_OP_CMP)
3058 {
3059 if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
3060 return false;
3061
3062 if (REG_P (pliw2->src))
3063 return REGNO (pliw2->src) != REGNO (pliw1->dest);
3064
3065 return true;
3066 }
3067
3068 /* Changing "OP1 ; OP2" into "OP1 | OP2" does not work if they both write to the
3069 same destination register. */
3070 if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
3071 return false;
3072
3073 /* Changing "OP1 ; OP2" into "OP1 | OP2" generally does not work if the destination
3074 of OP1 is the source of OP2. The exception is when OP1 is a MOVE instruction when
3075 we can replace the source in OP2 with the source of OP1. */
3076 if (REG_P (pliw2->src) && REGNO (pliw2->src) == REGNO (pliw1->dest))
3077 {
3078 if (pliw1->op == LIW_OP_MOV && REG_P (pliw1->src))
3079 {
3080 if (! REG_P (pliw1->src)
3081 && (pliw2->op == LIW_OP_AND
3082 || pliw2->op == LIW_OP_OR
3083 || pliw2->op == LIW_OP_XOR))
3084 return false;
3085
3086 pliw2->src = pliw1->src;
3087 return true;
3088 }
3089 return false;
3090 }
3091
3092 /* Everything else is OK. */
3093 return true;
3094 }
3095
3096 /* Combine pairs of insns into LIW bundles. */
3097
3098 static void
mn10300_bundle_liw(void)3099 mn10300_bundle_liw (void)
3100 {
3101 rtx_insn *r;
3102
3103 for (r = get_insns (); r != NULL; r = next_nonnote_nondebug_insn (r))
3104 {
3105 rtx_insn *insn1, *insn2;
3106 struct liw_data liw1, liw2;
3107
3108 insn1 = r;
3109 if (! extract_bundle (insn1, & liw1))
3110 continue;
3111
3112 insn2 = next_nonnote_nondebug_insn (insn1);
3113 if (! extract_bundle (insn2, & liw2))
3114 continue;
3115
3116 /* Check for source/destination overlap. */
3117 if (! check_liw_constraints (& liw1, & liw2))
3118 continue;
3119
3120 if (liw1.slot == LIW_OP2 || liw2.slot == LIW_OP1)
3121 {
3122 struct liw_data temp;
3123
3124 temp = liw1;
3125 liw1 = liw2;
3126 liw2 = temp;
3127 }
3128
3129 delete_insn (insn2);
3130
3131 rtx insn2_pat;
3132 if (liw1.op == LIW_OP_CMP)
3133 insn2_pat = gen_cmp_liw (liw2.dest, liw2.src, liw1.dest, liw1.src,
3134 GEN_INT (liw2.op));
3135 else if (liw2.op == LIW_OP_CMP)
3136 insn2_pat = gen_liw_cmp (liw1.dest, liw1.src, liw2.dest, liw2.src,
3137 GEN_INT (liw1.op));
3138 else
3139 insn2_pat = gen_liw (liw1.dest, liw2.dest, liw1.src, liw2.src,
3140 GEN_INT (liw1.op), GEN_INT (liw2.op));
3141
3142 insn2 = emit_insn_after (insn2_pat, insn1);
3143 delete_insn (insn1);
3144 r = insn2;
3145 }
3146 }
3147
3148 #define DUMP(reason, insn) \
3149 do \
3150 { \
3151 if (dump_file) \
3152 { \
3153 fprintf (dump_file, reason "\n"); \
3154 if (insn != NULL_RTX) \
3155 print_rtl_single (dump_file, insn); \
3156 fprintf(dump_file, "\n"); \
3157 } \
3158 } \
3159 while (0)
3160
3161 /* Replace the BRANCH insn with a Lcc insn that goes to LABEL.
3162 Insert a SETLB insn just before LABEL. */
3163
3164 static void
mn10300_insert_setlb_lcc(rtx label,rtx branch)3165 mn10300_insert_setlb_lcc (rtx label, rtx branch)
3166 {
3167 rtx lcc, comparison, cmp_reg;
3168
3169 if (LABEL_NUSES (label) > 1)
3170 {
3171 rtx_insn *insn;
3172
3173 /* This label is used both as an entry point to the loop
3174 and as a loop-back point for the loop. We need to separate
3175 these two functions so that the SETLB happens upon entry,
3176 but the loop-back does not go to the SETLB instruction. */
3177 DUMP ("Inserting SETLB insn after:", label);
3178 insn = emit_insn_after (gen_setlb (), label);
3179 label = gen_label_rtx ();
3180 emit_label_after (label, insn);
3181 DUMP ("Created new loop-back label:", label);
3182 }
3183 else
3184 {
3185 DUMP ("Inserting SETLB insn before:", label);
3186 emit_insn_before (gen_setlb (), label);
3187 }
3188
3189 comparison = XEXP (SET_SRC (PATTERN (branch)), 0);
3190 cmp_reg = XEXP (comparison, 0);
3191 gcc_assert (REG_P (cmp_reg));
3192
3193 /* If the comparison has not already been split out of the branch
3194 then do so now. */
3195 gcc_assert (REGNO (cmp_reg) == CC_REG);
3196
3197 if (GET_MODE (cmp_reg) == CC_FLOATmode)
3198 lcc = gen_FLcc (comparison, label);
3199 else
3200 lcc = gen_Lcc (comparison, label);
3201
3202 rtx_insn *jump = emit_jump_insn_before (lcc, branch);
3203 mark_jump_label (XVECEXP (lcc, 0, 0), jump, 0);
3204 JUMP_LABEL (jump) = label;
3205 DUMP ("Replacing branch insn...", branch);
3206 DUMP ("... with Lcc insn:", jump);
3207 delete_insn (branch);
3208 }
3209
3210 static bool
mn10300_block_contains_call(basic_block block)3211 mn10300_block_contains_call (basic_block block)
3212 {
3213 rtx_insn *insn;
3214
3215 FOR_BB_INSNS (block, insn)
3216 if (CALL_P (insn))
3217 return true;
3218
3219 return false;
3220 }
3221
3222 static bool
mn10300_loop_contains_call_insn(loop_p loop)3223 mn10300_loop_contains_call_insn (loop_p loop)
3224 {
3225 basic_block * bbs;
3226 bool result = false;
3227 unsigned int i;
3228
3229 bbs = get_loop_body (loop);
3230
3231 for (i = 0; i < loop->num_nodes; i++)
3232 if (mn10300_block_contains_call (bbs[i]))
3233 {
3234 result = true;
3235 break;
3236 }
3237
3238 free (bbs);
3239 return result;
3240 }
3241
3242 static void
mn10300_scan_for_setlb_lcc(void)3243 mn10300_scan_for_setlb_lcc (void)
3244 {
3245 loop_p loop;
3246
3247 DUMP ("Looking for loops that can use the SETLB insn", NULL_RTX);
3248
3249 df_analyze ();
3250 compute_bb_for_insn ();
3251
3252 /* Find the loops. */
3253 loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
3254
3255 /* FIXME: For now we only investigate innermost loops. In practice however
3256 if an inner loop is not suitable for use with the SETLB/Lcc insns, it may
3257 be the case that its parent loop is suitable. Thus we should check all
3258 loops, but work from the innermost outwards. */
3259 FOR_EACH_LOOP (loop, LI_ONLY_INNERMOST)
3260 {
3261 const char * reason = NULL;
3262
3263 /* Check to see if we can modify this loop. If we cannot
3264 then set 'reason' to describe why it could not be done. */
3265 if (loop->latch == NULL)
3266 reason = "it contains multiple latches";
3267 else if (loop->header != loop->latch)
3268 /* FIXME: We could handle loops that span multiple blocks,
3269 but this requires a lot more work tracking down the branches
3270 that need altering, so for now keep things simple. */
3271 reason = "the loop spans multiple blocks";
3272 else if (mn10300_loop_contains_call_insn (loop))
3273 reason = "it contains CALL insns";
3274 else
3275 {
3276 rtx_insn *branch = BB_END (loop->latch);
3277
3278 gcc_assert (JUMP_P (branch));
3279 if (single_set (branch) == NULL_RTX || ! any_condjump_p (branch))
3280 /* We cannot optimize tablejumps and the like. */
3281 /* FIXME: We could handle unconditional jumps. */
3282 reason = "it is not a simple loop";
3283 else
3284 {
3285 rtx_insn *label;
3286
3287 if (dump_file)
3288 flow_loop_dump (loop, dump_file, NULL, 0);
3289
3290 label = BB_HEAD (loop->header);
3291 gcc_assert (LABEL_P (label));
3292
3293 mn10300_insert_setlb_lcc (label, branch);
3294 }
3295 }
3296
3297 if (dump_file && reason != NULL)
3298 fprintf (dump_file, "Loop starting with insn %d is not suitable because %s\n",
3299 INSN_UID (BB_HEAD (loop->header)),
3300 reason);
3301 }
3302
3303 loop_optimizer_finalize ();
3304
3305 df_finish_pass (false);
3306
3307 DUMP ("SETLB scan complete", NULL_RTX);
3308 }
3309
3310 static void
mn10300_reorg(void)3311 mn10300_reorg (void)
3312 {
3313 /* These are optimizations, so only run them if optimizing. */
3314 if (TARGET_AM33 && (optimize > 0 || optimize_size))
3315 {
3316 if (TARGET_ALLOW_SETLB)
3317 mn10300_scan_for_setlb_lcc ();
3318
3319 if (TARGET_ALLOW_LIW)
3320 mn10300_bundle_liw ();
3321 }
3322 }
3323
3324 /* Initialize the GCC target structure. */
3325
3326 #undef TARGET_MACHINE_DEPENDENT_REORG
3327 #define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg
3328
3329 #undef TARGET_ASM_ALIGNED_HI_OP
3330 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
3331
3332 #undef TARGET_LEGITIMIZE_ADDRESS
3333 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
3334
3335 #undef TARGET_ADDRESS_COST
3336 #define TARGET_ADDRESS_COST mn10300_address_cost
3337 #undef TARGET_REGISTER_MOVE_COST
3338 #define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost
3339 #undef TARGET_MEMORY_MOVE_COST
3340 #define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost
3341 #undef TARGET_RTX_COSTS
3342 #define TARGET_RTX_COSTS mn10300_rtx_costs
3343
3344 #undef TARGET_ASM_FILE_START
3345 #define TARGET_ASM_FILE_START mn10300_file_start
3346 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
3347 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
3348
3349 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
3350 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra
3351
3352 #undef TARGET_OPTION_OVERRIDE
3353 #define TARGET_OPTION_OVERRIDE mn10300_option_override
3354
3355 #undef TARGET_ENCODE_SECTION_INFO
3356 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
3357
3358 #undef TARGET_PROMOTE_PROTOTYPES
3359 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
3360 #undef TARGET_RETURN_IN_MEMORY
3361 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
3362 #undef TARGET_PASS_BY_REFERENCE
3363 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
3364 #undef TARGET_CALLEE_COPIES
3365 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
3366 #undef TARGET_ARG_PARTIAL_BYTES
3367 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
3368 #undef TARGET_FUNCTION_ARG
3369 #define TARGET_FUNCTION_ARG mn10300_function_arg
3370 #undef TARGET_FUNCTION_ARG_ADVANCE
3371 #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance
3372
3373 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
3374 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
3375 #undef TARGET_EXPAND_BUILTIN_VA_START
3376 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
3377
3378 #undef TARGET_CASE_VALUES_THRESHOLD
3379 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
3380
3381 #undef TARGET_LEGITIMATE_ADDRESS_P
3382 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
3383 #undef TARGET_DELEGITIMIZE_ADDRESS
3384 #define TARGET_DELEGITIMIZE_ADDRESS mn10300_delegitimize_address
3385 #undef TARGET_LEGITIMATE_CONSTANT_P
3386 #define TARGET_LEGITIMATE_CONSTANT_P mn10300_legitimate_constant_p
3387
3388 #undef TARGET_PREFERRED_RELOAD_CLASS
3389 #define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class
3390 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
3391 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS \
3392 mn10300_preferred_output_reload_class
3393 #undef TARGET_SECONDARY_RELOAD
3394 #define TARGET_SECONDARY_RELOAD mn10300_secondary_reload
3395
3396 #undef TARGET_TRAMPOLINE_INIT
3397 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
3398
3399 #undef TARGET_FUNCTION_VALUE
3400 #define TARGET_FUNCTION_VALUE mn10300_function_value
3401 #undef TARGET_LIBCALL_VALUE
3402 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
3403
3404 #undef TARGET_ASM_OUTPUT_MI_THUNK
3405 #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
3406 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3407 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
3408
3409 #undef TARGET_SCHED_ADJUST_COST
3410 #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost
3411
3412 #undef TARGET_CONDITIONAL_REGISTER_USAGE
3413 #define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage
3414
3415 #undef TARGET_MD_ASM_ADJUST
3416 #define TARGET_MD_ASM_ADJUST mn10300_md_asm_adjust
3417
3418 #undef TARGET_FLAGS_REGNUM
3419 #define TARGET_FLAGS_REGNUM CC_REG
3420
3421 struct gcc_target targetm = TARGET_INITIALIZER;
3422