1;; Machine Description for Renesas RL78 processors 2;; Copyright (C) 2011-2016 Free Software Foundation, Inc. 3;; Contributed by Red Hat. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; The insns in this file correspond to the actual opcodes the RL78 22;; can issue with real registers. All insns in here should be 23;; conditional on rl78_real_insns_ok() returning true, and should 24;; allow virtual registers in their predicates - the reorg pass that 25;; allocates physical registers uses the constraints to select 26;; registers, but insns with virtual registers MUST match one of these 27;; patterns - other than the constraints - so that the operand info is 28;; properly set up for the alloc pass. 29 30;; This attribute reflects how the insn alters the Z flag, 31;; based upon the value of the it's output. The default is NO 32;; for no change, but other possibilities are UPDATE_Z if it changes 33;; the Z flag and CLOBBER if the state of the flag is indeterminate. 34;; The CY and AC flags are not set in the same way as the Z flag, so 35;; their values are not tracked. 36(define_attr "update_Z" "no,update_Z,clobber" (const_string "no")) 37 38;;---------- Moving ------------------------ 39 40(define_insn "movqi_to_es" 41 [(set (reg:QI ES_REG) 42 (match_operand:QI 0 "register_operand" "a"))] 43 "" 44 "mov\tes, %0" 45) 46 47(define_insn "movqi_from_es" 48 [(set (match_operand:QI 0 "register_operand" "=a") 49 (reg:QI ES_REG))] 50 "" 51 "mov\t%0, es" 52) 53 54(define_insn "movqi_cs" 55 [(set (reg:QI CS_REG) 56 (match_operand:QI 0 "register_operand" "a"))] 57 "" 58 "mov\tcs, %0" 59) 60 61(define_insn "*movqi_real" 62 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=Rv,RaxbcWab,RaxbcWab,a, bcx,R, WabWd2WhlWh1WhbWbcWs1v, bcx,WsaWsf") 63 (match_operand 1 "rl78_general_operand" "0,K, M, RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a, R, i"))] 64 "rl78_real_insns_ok ()" 65 "@ 66 ; mov\t%0, %1 67 oneb\t%0 68 clrb\t%0 69 mov\t%0, %1 70 mov\t%0, %1 71 mov\t%0, %1 72 mov\t%0, %1 73 mov\t%0, %S1 74 mov\t%0, %1" 75) 76 77(define_insn "*movhi_real" 78 [(set (match_operand:HI 0 "rl78_nonimmediate_operand" "=Rv,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v") 79 (match_operand:HI 1 "rl78_general_operand" " 0,K, M, i, BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS, ABDT"))] 80 "rl78_real_insns_ok ()" 81 "@ 82 ; movw\t%0, %1 83 onew\t%0 84 clrw\t%0 85 movw\t%0, %1 86 movw\t%0, %1 87 movw\t%0, %1 88 movw\t%0, %S1 89 movw\t%0, %1 90 movw\t%0, %1" 91) 92 93;;---------- Conversions ------------------------ 94 95(define_insn "*zero_extendqihi2_real" 96 [(set (match_operand:HI 0 "nonimmediate_operand" "=Rv,A") 97 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))] 98 "rl78_real_insns_ok ()" 99 "@ 100 mov\t%Q0, #0 101 mov\tx, a \;mov\ta, #0" 102 ) 103 104(define_insn "*extendqihi2_real" 105 [(set (match_operand:HI 0 "nonimmediate_operand" "=A,A") 106 (sign_extend:HI (match_operand:QI 1 "general_operand" "x,a")))] 107 "rl78_real_insns_ok ()" 108 "@ 109 shlw\t%0, 8 \;sarw\t%0, 8 110 sarw\t%0, 8" 111 ) 112 113;;---------- Arithmetic ------------------------ 114 115(define_insn "*addqi3_real" 116 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=RvWabWhlWh1Wsa,RvWabWhlWh1Wsa,a,*bcdehl,Wsa") 117 (plus:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0,0") 118 (match_operand:QI 2 "rl78_general_operand" "K,L,RWhlWh1Wabi,a,i"))) 119 ] 120 "rl78_real_insns_ok ()" 121 "@ 122 inc\t%p0 123 dec\t%p0 124 add\t%0, %2 125 add\t%0, %2 126 add\t%0, %2" 127 [(set (attr "update_Z") (const_string "update_Z"))] 128) 129 130(define_insn "*addhi3_real" 131 [(set (match_operand:HI 0 "rl78_nonimmediate_operand" "=vABDTWhlWh1WabWsa,vABDTWhlWh1WabWsa,v,v,A,S,S,A") 132 (plus:HI (match_operand:HI 1 "rl78_general_operand" "%0,0,0,0,0,0,0,S") 133 (match_operand:HI 2 "" "K,L,N,O,RWh1WhlWabiv,Int8Qs8,J,Ri"))) 134 ] 135 "rl78_real_insns_ok ()" 136 "@ 137 incw\t%p0 138 decw\t%p0 139 incw\t%0 \;incw\t%0 140 decw\t%0 \;decw\t%0 141 addw\t%0, %p2 142 addw\t%0, %2 143 subw\t%0, %m2 144 movw\t%0, %1 \;addw\t%0, %2" 145 [(set_attr "update_Z" "*,*,*,*,update_Z,update_Z,update_Z,update_Z")] 146) 147 148(define_insn "*addqihi3a_real" 149 [(set (match_operand:HI 0 "register_operand" "=R") 150 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "R")) 151 (match_operand:HI 2 "register_operand" "0"))) 152 ] 153 "rl78_real_insns_ok ()" 154 "add\t%q0, %q1 \;addc\t%Q0, #0" 155 [(set (attr "update_Z") (const_string "update_Z"))] 156) 157 158(define_insn "*subqi3_real" 159 [(set (match_operand:QI 0 "nonimmediate_operand" "=a,R,v") 160 (minus:QI (match_operand:QI 1 "general_operand" "0,0,0") 161 (match_operand:QI 2 "rl78_general_operand" "RiWabWhbWh1Whl,a,i"))) 162 ] 163 "rl78_real_insns_ok ()" 164 "sub\t%0, %2" 165 [(set (attr "update_Z") (const_string "update_Z"))] 166) 167 168(define_insn "*subhi3_real" 169 [(set (match_operand:HI 0 "nonimmediate_operand" "=A,S") 170 (minus:HI (match_operand:HI 1 "general_operand" "0,0") 171 (match_operand:HI 2 "rl78_general_operand" "iBDTWabWh1v,i"))) 172 ] 173 "rl78_real_insns_ok ()" 174 "subw\t%0, %2" 175 [(set (attr "update_Z") (const_string "update_Z"))] 176) 177 178(define_insn "*umulhi3_shift_real" 179 [(set (match_operand:HI 0 "register_operand" "=A,A") 180 (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "0,0") 181 (match_operand:HI 2 "rl78_24_operand" "N,i")))] 182 "rl78_real_insns_ok ()" 183 "@ 184 shlw\t%0, 1 185 shlw\t%0, 2" 186) 187 188(define_insn "*umulqihi3_real" 189 [(set (match_operand:HI 0 "nonimmediate_operand" "=A") 190 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%a")) 191 (zero_extend:HI (match_operand:QI 2 "general_operand" "x"))))] 192 "rl78_real_insns_ok ()" 193 "mulu\t%2" 194) 195 196(define_insn "*andqi3_real" 197 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=WsfWsaWhlWab,A,R,vWsa") 198 (and:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0") 199 (match_operand:QI 2 "rl78_general_operand" "IBqi,iRvWabWhbWh1Whl,A,i"))) 200 ] 201 "rl78_real_insns_ok ()" 202 "@ 203 clr1\t%0.%B2 204 and\t%0, %2 205 and\t%0, %2 206 and\t%0, %2" 207 [(set_attr "update_Z" "*,update_Z,update_Z,update_Z")] 208) 209 210(define_insn "*iorqi3_real" 211 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=WsfWsaWhlWab,A,R,vWsa") 212 (ior:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0") 213 (match_operand:QI 2 "rl78_general_operand" "Ibqi,iRvWabWhbWh1Whl,A,i"))) 214 ] 215 "rl78_real_insns_ok ()" 216 "@ 217 set1\t%0.%B2 218 or\t%0, %2 219 or\t%0, %2 220 or\t%0, %2" 221 [(set_attr "update_Z" "*,update_Z,update_Z,update_Z")] 222) 223 224(define_insn "*xorqi3_real" 225 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=A,R,vWsa") 226 (xor:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0") 227 (match_operand 2 "rl78_general_operand" "iRvWabWhbWh1Whl,A,i"))) 228 ] 229 "rl78_real_insns_ok ()" 230 "xor\t%0, %2" 231 [(set (attr "update_Z") (const_string "update_Z"))] 232) 233 234;;---------- Shifts ------------------------ 235 236(define_insn "*ashlqi3_real" 237 [(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a") 238 (ashift:QI (match_operand:QI 1 "general_operand" "0,0,0") 239 (match_operand:QI 2 "general_operand" "Int3,bc,dehl"))) 240 ] 241 "rl78_real_insns_ok ()" 242 "@ 243 shl\t%0, %u2 244 cmp0 %2\; bz $2f\; 1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2: 245 inc %2\;dec %2\;bz $2f\;1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:" 246 [(set_attr "update_Z" "*,clobber,clobber")] 247) 248 249(define_insn "*ashlhi3_real" 250 [(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A") 251 (ashift:HI (match_operand:HI 1 "general_operand" "0,0,0") 252 (match_operand:QI 2 "general_operand" "P,bc,dehl"))) 253 ] 254 "rl78_real_insns_ok ()" 255 "@ 256 shlw\t%0, %u2 257 cmp0 %2\; bz $2f\; 1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2: 258 inc %2\;dec %2\;bz $2f\;1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:" 259 [(set_attr "update_Z" "*,clobber,clobber")] 260) 261 262;;---------- 263 264(define_insn "*ashrqi3_real" 265 [(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a") 266 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0") 267 (match_operand:QI 2 "general_operand" "Int3,bc,dehl"))) 268 ] 269 "rl78_real_insns_ok ()" 270 "@ 271 sar\t%0, %u2 272 cmp0 %2\; bz $2f\; 1: sar\t%0, 1 \;dec %2 \;bnz $1b\;2: 273 inc %2\;dec %2\;bz $2f\;1: sar\t%0, 1\;dec %2 \;bnz $1b\;2:" 274 [(set_attr "update_Z" "*,clobber,clobber")] 275) 276 277(define_insn "*ashrhi3_real" 278 [(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A") 279 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0") 280 (match_operand:QI 2 "general_operand" "P,bc,dehl"))) 281 ] 282 "rl78_real_insns_ok ()" 283 "@ 284 sarw\t%0, %u2 285 cmp0 %2\; bz $2f\; 1: sarw\t%0, 1 \;dec %2 \;bnz $1b\;2: 286 inc %2\;dec %2\;bz $2f\;1: sarw\t%0, 1\;dec %2\;bnz $1b\;2:" 287 [(set_attr "update_Z" "*,clobber,clobber")] 288) 289 290;;---------- 291 292(define_insn "*lshrqi3_real" 293 [(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a") 294 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0") 295 (match_operand:QI 2 "general_operand" "Int3,bc,dehl"))) 296 ] 297 "rl78_real_insns_ok ()" 298 "@ 299 shr\t%0, %u2 300 cmp0 %2\; bz $2f\; 1: shr\t%0, 1 \;dec %2 \;bnz $1b\;2: 301 inc %2\;dec %2\;bz $2f\;1: shr\t%0, 1\;dec %2\;bnz $1b\;2:" 302 [(set_attr "update_Z" "*,clobber,clobber")] 303) 304 305(define_insn "*lshrhi3_real" 306 [(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A") 307 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0") 308 (match_operand:QI 2 "general_operand" "P,bc,dehl"))) 309 ] 310 "rl78_real_insns_ok ()" 311 "@ 312 shrw\t%0, %u2 313 cmp0 %2\; bz $2f\; 1: shrw\t%0, 1 \;dec %2 \;bnz $1b\;2: 314 inc %2\;dec %2\;bz $2f\;1: shrw\t%0, 1\;dec %2\;bnz $1b\;2:" 315 [(set_attr "update_Z" "*,clobber,clobber")] 316) 317 318;;---------- Branching ------------------------ 319 320(define_insn "*indirect_jump_real" 321 [(set (pc) 322 (match_operand:HI 0 "nonimmediate_operand" "A"))] 323 "rl78_real_insns_ok ()" 324 "br\t%0" 325) 326 327(define_insn "jump" 328 [(set (pc) 329 (label_ref (match_operand 0 "" "")))] 330 "" 331 ;; $rel8, $!rel16, !abs16, !!abs20 332 "br\t!!%0" 333) 334 335(define_insn "*call_real" 336 [(call (match_operand:HI 0 "memory_operand" "Wab,Wca") 337 (match_operand 1 "" ""))] 338 "rl78_real_insns_ok ()" 339 "@ 340 call\t!!%A0 341 call\t%A0" 342 [(set (attr "update_Z") (const_string "clobber"))] 343 ) 344 345;; Peephole to match: 346;; 347;; (set (reg1) (reg2)) 348;; (call (mem (reg1))) 349;; 350;; and replace it with: 351;; 352;; (call (mem (reg2))) 353 354(define_peephole2 355 [(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand")) 356 (call (mem:HI (match_dup 0))(const_int 0)) 357 ] 358 "peep2_regno_dead_p (2, REGNO (operands[0])) 359 && REGNO (operands[1]) < 8" 360 [(call (mem:HI (match_dup 1))(const_int 0)) 361 ] 362) 363 364(define_insn "*call_value_real" 365 [(set (match_operand 0 "register_operand" "=v,v") 366 (call (match_operand:HI 1 "memory_operand" "Wab,Wca") 367 (match_operand 2 "" "")))] 368 "rl78_real_insns_ok ()" 369 "@ 370 call\t!!%A1 371 call\t%A1" 372 [(set (attr "update_Z") (const_string "clobber"))] 373 ) 374 375;; Peephole to match: 376;; 377;; (set (reg1) (reg2)) 378;; (set (reg3) (call (mem (reg1)))) 379;; 380;; and replace it with: 381;; 382;; (set (reg3) (call (mem (reg2)))) 383 384(define_peephole2 385 [(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand")) 386 (set (match_operand:HI 2 "register_operand") (call (mem:HI (match_dup 0))(const_int 0))) 387 ] 388 "peep2_regno_dead_p (2, REGNO (operands[0])) 389 && REGNO (operands[1]) < 8" 390 [(set (match_dup 2) (call (mem:HI (match_dup 1))(const_int 0))) 391 ] 392) 393 394(define_insn "*cbranchqi4_real_signed" 395 [(set (pc) (if_then_else 396 (match_operator 0 "rl78_cmp_operator_signed" 397 [(match_operand:QI 1 "general_operand" "A,A,A,A,Wsa") 398 (match_operand:QI 2 "general_operand" "M,ISqi,i,v,i")]) 399 (label_ref (match_operand 3 "" "")) 400 (pc)))] 401 "rl78_real_insns_ok ()" 402 { 403 gcc_assert (GET_CODE (operands[0]) != EQ && GET_CODE (operands[0]) != NE); 404 405 switch (which_alternative) 406 { 407 case 0: return "cmp0\t%1\; xor1\tCY, %1.7\; sk%C0\; br\t!!%3"; 408 case 1: return "cmp\t%1, %2\; xor1\tCY, %1.7\; not1\tCY\; sk%C0\; br\t!!%3"; 409 case 4: 410 case 2: return "cmp\t%1, %2\; xor1\tCY, %1.7\; sk%C0\; br\t!!%3"; 411 case 3: return "cmp\t%1, %2\; xor1\tCY, %1.7\; xor1\tCY, %2.7\; sk%C0\; br\t!!%3"; 412 default: gcc_unreachable (); 413 } 414 } 415 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: flags are set based on %1 vs %2 416 ) 417 418(define_insn "*cbranchqi4_real" 419 [(set (pc) (if_then_else 420 (match_operator 0 "rl78_cmp_operator_real" 421 [(match_operand:QI 1 "rl78_general_operand" "Wabvaxbc,a, vWsaWab,bcdehl") 422 (match_operand:QI 2 "rl78_general_operand" "M, iRvWabWhlWh1Whb,i,a")]) 423 (label_ref (match_operand 3 "" "")) 424 (pc)))] 425 "rl78_real_insns_ok ()" 426 { 427 if (which_alternative == 0) 428 { 429 if (rl78_flags_already_set (operands[0], operands[1])) 430 return "sk%C0\; br\t!!%3\; # zero-comparison eliminated"; 431 else 432 return "cmp0\t%1\; sk%C0\; br\t!!%3"; 433 } 434 return "cmp\t%1, %2\; sk%C0\; br\t!!%3"; 435 } 436 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: alt 0: flags are set based on %1 vs %2 437 ) 438 439(define_insn "*cbranchhi4_real_signed" 440 [(set (pc) (if_then_else 441 (match_operator 0 "rl78_cmp_operator_signed" 442 [(match_operand:HI 1 "general_operand" "A,A,A,vR") 443 (match_operand:HI 2 "general_operand" "IShi,i,v,1")]) 444 (label_ref (match_operand 3)) 445 (pc)))] 446 "rl78_real_insns_ok ()" 447 "@ 448 cmpw\t%1, %2\; xor1\tCY, %Q1.7\; not1\tCY\; sk%C0\; br\t!!%3 449 cmpw\t%1, %2\; xor1\tCY, %Q1.7\; sk%C0\; br\t!!%3 450 cmpw\t%1, %2\; xor1\tCY, %Q1.7\; xor1\tCY, %Q2.7\; sk%C0\; br\t!!%3 451 %z0\t!!%3" 452 [(set_attr "update_Z" "clobber,clobber,clobber,*")] 453 ) 454 455(define_insn "cbranchhi4_real" 456 [(set (pc) (if_then_else 457 (match_operator 0 "rl78_cmp_operator_real" 458 [(match_operand:HI 1 "general_operand" "A,A,vR") 459 (match_operand:HI 2 "rl78_general_operand" "M,iBDTvWabWhlWh1,1")]) 460 (label_ref (match_operand 3 "" "")) 461 (pc)))] 462 "rl78_real_insns_ok ()" 463 { 464 switch (which_alternative) 465 { 466 case 0: 467 if (rl78_flags_already_set (operands[0], operands[1])) 468 return "sk%C0\; br\t!!%3\; # cmpw eliminated"; 469 /* else fall through. */ 470 case 1: 471 return "cmpw\t%1, %2\; sk%C0\; br\t!!%3"; 472 case 2: 473 return "%z0\t!!%3"; 474 default: 475 gcc_unreachable (); 476 } 477 } 478 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: Z might be set based on %1 vs %2 479 ) 480 481(define_insn "cbranchhi4_real_inverted" 482 [(set (pc) (if_then_else 483 (match_operator 0 "rl78_cmp_operator_real" 484 [(match_operand:HI 1 "general_operand" "A,A") 485 (match_operand:HI 2 "rl78_general_operand" "M,iBDTvWabWhlWh1")]) 486 (pc) 487 (label_ref (match_operand 3 "" ""))))] 488 "rl78_real_insns_ok ()" 489 { 490 if (which_alternative == 0 && rl78_flags_already_set (operands[0], operands[1])) 491 return "sk%C0\; br\t!!%3\; # inverted cmpw eliminated"; 492 else 493 return "cmpw\t%1, %2\; sk%C0\; br\t!!%3"; 494 } 495 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: flags are set based on %1 vs %2 496 ) 497 498(define_insn "*cbranchsi4_real_lt" 499 [(set (pc) (if_then_else 500 (lt (match_operand:SI 0 "rl78_general_operand" "U,vWabWhlWh1") 501 (const_int 0)) 502 (label_ref (match_operand 1 "" "")) 503 (pc))) 504 (clobber (reg:HI AX_REG)) 505 ] 506 "rl78_real_insns_ok ()" 507 "@ 508 mov\ta, %E0\; mov1\tCY, a.7\; sknc\; br\t!!%1 509 mov1\tCY, %E0.7\; sknc\; br\t!!%1" 510 ) 511 512(define_insn "*cbranchsi4_real_ge" 513 [(set (pc) (if_then_else 514 (ge (match_operand:SI 0 "rl78_general_operand" "U,vWabWhlWh1") 515 (const_int 0)) 516 (label_ref (match_operand 1 "" "")) 517 (pc))) 518 (clobber (reg:HI AX_REG)) 519 ] 520 "rl78_real_insns_ok ()" 521 "@ 522 mov\ta, %E0\; mov1\tCY, a.7\; skc\; br\t!!%1 523 mov1\tCY, %E0.7\; skc\; br\t!!%1" 524 ) 525 526(define_insn "*cbranchsi4_real_signed" 527 [(set (pc) (if_then_else 528 (match_operator 0 "rl78_cmp_operator_signed" 529 [(match_operand:SI 1 "general_operand" "vU,vU,vU,i,i") 530 (match_operand:SI 2 "nonmemory_operand" "ISsi,i,v,S,v")]) 531 (label_ref (match_operand 3 "" "")) 532 (pc))) 533 (clobber (reg:HI AX_REG)) 534 ] 535 "rl78_real_insns_ok ()" 536 "@ 537 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; not1\tCY\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3 538 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3 539 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; xor1\tCY, %E2.7\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3 540 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; not1\tCY\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%0\; br\t!!%3 541 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%0\; br\t!!%3" 542 [(set (attr "update_Z") (const_string "clobber"))] 543 ) 544 545(define_insn "*cbranchsi4_real" 546 [(set (pc) (if_then_else 547 (match_operator 0 "rl78_cmp_operator_real" 548 [(match_operand:SI 1 "general_operand" "vUi") 549 (match_operand:SI 2 "general_operand" "iWhlWh1v")]) 550 (label_ref (match_operand 3 "" "")) 551 (pc))) 552 (clobber (reg:HI AX_REG)) 553 ] 554 "rl78_real_insns_ok ()" 555 "movw\tax, %H1\; cmpw\tax, %H2\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3" 556 [(set (attr "update_Z") (const_string "clobber"))] 557 ) 558 559;; Peephole to match: 560;; 561;; (set (mem (sp)) (ax)) 562;; (set (ax) (mem (sp))) 563;; or: 564;; (set (mem (plus (sp) (const)) (ax)) 565;; (set (ax) (mem (plus (sp) (const)))) 566;; 567;; which can be generated as the last instruction of the conversion 568;; of one virtual insn into a real insn and the first instruction of 569;; the conversion of the following virtual insn. 570 571(define_peephole2 572 [(set (match_operand:HI 0 "rl78_stack_based_mem") 573 (reg:HI AX_REG)) 574 (set (reg:HI AX_REG) 575 (match_dup 0))] 576 "" 577 [(set (match_dup 0) (reg:HI AX_REG))] 578 ) 579 580;; Bit test and branch insns. 581 582;; NOTE: These patterns will work for bits in other places, not just A. 583 584(define_insn "bf" 585 [(set (pc) 586 (if_then_else (eq (and (reg:QI A_REG) 587 (match_operand 0 "immediate_operand" "n")) 588 (const_int 0)) 589 (label_ref (match_operand 1 "" "")) 590 (pc)))] 591 "" 592 "bt\tA.%B0, $1f\n\tbr !!%1\n\t1:" 593 [(set (attr "update_Z") (const_string "clobber"))] 594) 595 596(define_insn "bt" 597 [(set (pc) 598 (if_then_else (ne (and (reg:QI A_REG) 599 (match_operand 0 "immediate_operand" "n")) 600 (const_int 0)) 601 (label_ref (match_operand 1 "" "")) 602 (pc)))] 603 "" 604 "bf\tA.%B0, $1f\n\tbr !!%1\n\t1:" 605 [(set (attr "update_Z") (const_string "clobber"))] 606) 607 608;; NOTE: These peepholes are fragile. They rely upon GCC generating 609;; a specific sequence on insns, based upon examination of test code. 610;; Improvements to GCC or using code other than the test code can result 611;; in the peephole not matching and the optimization being missed. 612 613(define_peephole2 614 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 615 (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 616 (set (pc) (if_then_else (eq (match_dup 0) (const_int 0)) 617 (label_ref (match_operand 2 "")) 618 (pc)))] 619 "peep2_regno_dead_p (3, REGNO (operands[0])) 620 && exact_log2 (INTVAL (operands[1])) >= 0" 621 [(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 1)) (const_int 0)) 622 (label_ref (match_dup 2)) 623 (pc)))] 624 ) 625 626(define_peephole2 627 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 628 (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 629 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0)) 630 (label_ref (match_operand 2 "")) 631 (pc)))] 632 "peep2_regno_dead_p (3, REGNO (operands[0])) 633 && exact_log2 (INTVAL (operands[1])) >= 0" 634 [(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 1)) (const_int 0)) 635 (label_ref (match_dup 2)) 636 (pc)))] 637 ) 638 639;; Eliminate needless register copies. 640(define_peephole2 641 [(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand")) 642 (set (match_operand:HI 2 "register_operand") (match_dup 0))] 643 "peep2_regno_dead_p (2, REGNO (operands[0])) 644 && (REGNO (operands[1]) < 8 || REGNO (operands[2]) < 8)" 645 [(set (match_dup 2) (match_dup 1))] 646 ) 647 648;; Eliminate needless register copying when performing bit manipulations. 649(define_peephole2 650 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 651 (set (match_dup 0) (ior:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 652 (set (reg:QI A_REG) (match_dup 0))] 653 "peep2_regno_dead_p (3, REGNO (operands[0]))" 654 [(set (reg:QI A_REG) (ior:QI (reg:QI A_REG) (match_dup 1)))] 655 ) 656 657(define_peephole2 658 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 659 (set (match_dup 0) (xor:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 660 (set (reg:QI A_REG) (match_dup 0))] 661 "peep2_regno_dead_p (3, REGNO (operands[0]))" 662 [(set (reg:QI A_REG) (xor:QI (reg:QI A_REG) (match_dup 1)))] 663 ) 664 665(define_peephole2 666 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 667 (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 668 (set (reg:QI A_REG) (match_dup 0))] 669 "peep2_regno_dead_p (3, REGNO (operands[0]))" 670 [(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))] 671 ) 672 673(define_insn "*negandhi3_real" 674 [(set (match_operand:HI 0 "register_operand" "=A") 675 (and:HI (neg:HI (match_operand:HI 1 "register_operand" "0")) 676 (match_operand:HI 2 "immediate_operand" "n"))) 677 ] 678 "rl78_real_insns_ok ()" 679 "xor a, #0xff @ xch a, x @ xor a, #0xff @ xch a, x @ addw ax, #1 @ and a, %Q2 @ xch a, x @ and a, %q2 @ xch a, x" 680 [(set (attr "update_Z") (const_string "clobber"))] 681) 682