1;; Predicate definitions for SPARC. 2;; Copyright (C) 2005-2016 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Predicates for numerical constants. 21 22;; Return true if OP is the zero constant for MODE. 23(define_predicate "const_zero_operand" 24 (and (match_code "const_int,const_wide_int,const_double,const_vector") 25 (match_test "op == CONST0_RTX (mode)"))) 26 27;; Return true if the integer representation of OP is all ones. 28(define_predicate "const_all_ones_operand" 29 (and (match_code "const_int,const_wide_int,const_double,const_vector") 30 (match_test "INTEGRAL_MODE_P (GET_MODE (op))") 31 (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) 32 33;; Return true if OP is the integer constant 4096. 34(define_predicate "const_4096_operand" 35 (and (match_code "const_int") 36 (match_test "INTVAL (op) == 4096"))) 37 38;; Return true if OP is a constant that is representable by a 13-bit 39;; signed field. This is an acceptable immediate operand for most 40;; 3-address instructions. 41(define_predicate "small_int_operand" 42 (and (match_code "const_int") 43 (match_test "SPARC_SIMM13_P (INTVAL (op))"))) 44 45;; Return true if OP is a constant operand for the umul instruction. That 46;; instruction sign-extends immediate values just like all other SPARC 47;; instructions, but interprets the extended result as an unsigned number. 48(define_predicate "uns_small_int_operand" 49 (and (match_code "const_int") 50 (match_test "((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) 51 || (INTVAL (op) >= 0xFFFFF000 52 && INTVAL (op) <= 0xFFFFFFFF))"))) 53 54;; Return true if OP is a constant that can be loaded by the sethi instruction. 55;; The first test avoids emitting sethi to load zero for example. 56(define_predicate "const_high_operand" 57 (and (match_code "const_int") 58 (and (not (match_operand 0 "small_int_operand")) 59 (match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))")))) 60 61;; Return true if OP is a constant whose 1's complement can be loaded by the 62;; sethi instruction. 63(define_predicate "const_compl_high_operand" 64 (and (match_code "const_int") 65 (and (not (match_operand 0 "small_int_operand")) 66 (match_test "SPARC_SETHI_P (~INTVAL (op) & GET_MODE_MASK (mode))")))) 67 68;; Return true if OP is a FP constant that needs to be loaded by the sethi/losum 69;; pair of instructions. 70(define_predicate "fp_const_high_losum_operand" 71 (match_operand 0 "const_double_operand") 72{ 73 gcc_assert (mode == SFmode); 74 return fp_high_losum_p (op); 75}) 76 77;; Return true if OP is a const_double or const_vector. 78(define_predicate "const_double_or_vector_operand" 79 (match_code "const_double,const_vector")) 80 81;; Return true if OP is Zero, or if the target is V7. 82(define_predicate "zero_or_v7_operand" 83 (and (match_code "const_int") 84 (ior (match_test "INTVAL (op) == 0") 85 (match_test "!TARGET_V8 && !TARGET_V9")))) 86 87;; Predicates for symbolic constants. 88 89;; Return true if OP is either a symbol reference or a sum of a symbol 90;; reference and a constant. 91(define_predicate "symbolic_operand" 92 (match_code "symbol_ref,label_ref,const") 93{ 94 machine_mode omode = GET_MODE (op); 95 96 if (omode != mode && omode != VOIDmode && mode != VOIDmode) 97 return false; 98 99 switch (GET_CODE (op)) 100 { 101 case SYMBOL_REF: 102 return !SYMBOL_REF_TLS_MODEL (op); 103 104 case LABEL_REF: 105 return true; 106 107 case CONST: 108 op = XEXP (op, 0); 109 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 110 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) 111 || GET_CODE (XEXP (op, 0)) == LABEL_REF) 112 && GET_CODE (XEXP (op, 1)) == CONST_INT); 113 114 default: 115 gcc_unreachable (); 116 } 117}) 118 119;; Return true if OP is a symbolic operand for the TLS Global Dynamic model. 120(define_predicate "tgd_symbolic_operand" 121 (and (match_code "symbol_ref") 122 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_GLOBAL_DYNAMIC"))) 123 124;; Return true if OP is a symbolic operand for the TLS Local Dynamic model. 125(define_predicate "tld_symbolic_operand" 126 (and (match_code "symbol_ref") 127 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_DYNAMIC"))) 128 129;; Return true if OP is a symbolic operand for the TLS Initial Exec model. 130(define_predicate "tie_symbolic_operand" 131 (and (match_code "symbol_ref") 132 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC"))) 133 134;; Return true if OP is a symbolic operand for the TLS Local Exec model. 135(define_predicate "tle_symbolic_operand" 136 (and (match_code "symbol_ref") 137 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC"))) 138 139;; Return true if the operand is an argument used in generating PIC references 140;; in either the medium/low or embedded medium/anywhere code models on V9. 141;; Check for (const (minus (symbol_ref:GOT) 142;; (const (minus (label) (pc))))) 143(define_predicate "medium_pic_operand" 144 (match_code "const") 145{ 146 /* Check for (const (minus (symbol_ref:GOT) 147 (const (minus (label) (pc))))). */ 148 op = XEXP (op, 0); 149 return GET_CODE (op) == MINUS 150 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF 151 && GET_CODE (XEXP (op, 1)) == CONST 152 && GET_CODE (XEXP (XEXP (op, 1), 0)) == MINUS; 153}) 154 155;; Return true if OP is a LABEL_REF of mode MODE. 156(define_predicate "label_ref_operand" 157 (and (match_code "label_ref") 158 (match_test "GET_MODE (op) == mode"))) 159 160;; Return true if OP is a data segment reference. This includes the readonly 161;; data segment or, in other words, anything but the text segment. 162;; This is needed in the embedded medium/anywhere code model on V9. These 163;; values are accessed with EMBMEDANY_BASE_REG. */ 164(define_predicate "data_segment_operand" 165 (match_code "symbol_ref,plus,const") 166{ 167 switch (GET_CODE (op)) 168 { 169 case SYMBOL_REF : 170 return ! SYMBOL_REF_FUNCTION_P (op); 171 case PLUS : 172 /* Assume canonical format of symbol + constant. 173 Fall through. */ 174 case CONST : 175 return data_segment_operand (XEXP (op, 0), VOIDmode); 176 default : 177 gcc_unreachable (); 178 } 179}) 180 181;; Return true if OP is a text segment reference. 182;; This is needed in the embedded medium/anywhere code model on V9. 183(define_predicate "text_segment_operand" 184 (match_code "label_ref,symbol_ref,plus,const") 185{ 186 switch (GET_CODE (op)) 187 { 188 case LABEL_REF : 189 return true; 190 case SYMBOL_REF : 191 return SYMBOL_REF_FUNCTION_P (op); 192 case PLUS : 193 /* Assume canonical format of symbol + constant. 194 Fall through. */ 195 case CONST : 196 return text_segment_operand (XEXP (op, 0), VOIDmode); 197 default : 198 gcc_unreachable (); 199 } 200}) 201 202 203;; Predicates for registers. 204 205;; Return true if OP is either the zero constant or a register. 206(define_predicate "register_or_zero_operand" 207 (ior (match_operand 0 "register_operand") 208 (match_operand 0 "const_zero_operand"))) 209 210(define_predicate "register_or_v9_zero_operand" 211 (ior (match_operand 0 "register_operand") 212 (and (match_test "TARGET_V9") 213 (match_operand 0 "const_zero_operand")))) 214 215;; Return true if OP is either the zero constant, the all-ones 216;; constant, or a register. 217(define_predicate "register_or_zero_or_all_ones_operand" 218 (ior (match_operand 0 "register_or_zero_operand") 219 (match_operand 0 "const_all_ones_operand"))) 220 221;; Return true if OP is a register operand in a floating point register. 222(define_predicate "fp_register_operand" 223 (match_operand 0 "register_operand") 224{ 225 if (GET_CODE (op) == SUBREG) 226 op = SUBREG_REG (op); /* Possibly a MEM */ 227 return REG_P (op) && SPARC_FP_REG_P (REGNO (op)); 228}) 229 230;; Return true if OP is an integer register of the appropriate mode 231;; for a cstore result. 232(define_special_predicate "cstore_result_operand" 233 (match_test "register_operand (op, TARGET_ARCH64 ? DImode : SImode)")) 234 235;; Return true if OP is a floating point condition code register. 236(define_predicate "fcc_register_operand" 237 (match_code "reg") 238{ 239 if (mode != VOIDmode && mode != GET_MODE (op)) 240 return false; 241 if (mode == VOIDmode 242 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 243 return false; 244 245#if 0 /* ??? 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ 246 if (reg_renumber == 0) 247 return REGNO (op) >= FIRST_PSEUDO_REGISTER; 248 return REGNO_OK_FOR_CCFP_P (REGNO (op)); 249#else 250 return ((unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG) < 4; 251#endif 252}) 253 254;; Return true if OP is the floating point condition code register fcc0. 255(define_predicate "fcc0_register_operand" 256 (match_code "reg") 257{ 258 if (mode != VOIDmode && mode != GET_MODE (op)) 259 return false; 260 if (mode == VOIDmode 261 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 262 return false; 263 264 return REGNO (op) == SPARC_FCC_REG; 265}) 266 267;; Return true if OP is an integer or floating point condition code register. 268(define_predicate "icc_or_fcc_register_operand" 269 (match_code "reg") 270{ 271 if (REGNO (op) == SPARC_ICC_REG) 272 { 273 if (mode != VOIDmode && mode != GET_MODE (op)) 274 return false; 275 if (mode == VOIDmode 276 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) 277 return false; 278 279 return true; 280 } 281 282 return fcc_register_operand (op, mode); 283}) 284 285 286;; Predicates for arithmetic instructions. 287 288;; Return true if OP is a register, or is a constant that is representable 289;; by a 13-bit signed field. This is an acceptable operand for most 290;; 3-address instructions. 291(define_predicate "arith_operand" 292 (ior (match_operand 0 "register_operand") 293 (match_operand 0 "small_int_operand"))) 294 295;; 64-bit: Same as above. 296;; 32-bit: Return true if OP is a register, or is a constant that is 297;; representable by a couple of 13-bit signed fields. This is an 298;; acceptable operand for most 3-address splitters. 299(define_predicate "arith_double_operand" 300 (match_code "const_int,reg,subreg") 301{ 302 bool arith_simple_operand = arith_operand (op, mode); 303 HOST_WIDE_INT m1, m2; 304 305 if (TARGET_ARCH64 || arith_simple_operand) 306 return arith_simple_operand; 307 308 if (GET_CODE (op) != CONST_INT) 309 return false; 310 311 m1 = trunc_int_for_mode (INTVAL (op), SImode); 312 m2 = trunc_int_for_mode (INTVAL (op) >> 32, SImode); 313 314 return SPARC_SIMM13_P (m1) && SPARC_SIMM13_P (m2); 315}) 316 317;; Return true if OP is suitable as second operand for add/sub. 318(define_predicate "arith_add_operand" 319 (ior (match_operand 0 "arith_operand") 320 (match_operand 0 "const_4096_operand"))) 321 322;; Return true if OP is suitable as second double operand for add/sub. 323(define_predicate "arith_double_add_operand" 324 (match_code "const_int,reg,subreg") 325{ 326 if (arith_double_operand (op, mode)) 327 return true; 328 329 return TARGET_ARCH64 && const_4096_operand (op, mode); 330}) 331 332;; Return true if OP is a register, or is a CONST_INT that can fit in a 333;; signed 10-bit immediate field. This is an acceptable SImode operand for 334;; the movrcc instructions. 335(define_predicate "arith10_operand" 336 (ior (match_operand 0 "register_operand") 337 (and (match_code "const_int") 338 (match_test "SPARC_SIMM10_P (INTVAL (op))")))) 339 340;; Return true if OP is a register, or is a CONST_INT that can fit in a 341;; signed 11-bit immediate field. This is an acceptable SImode operand for 342;; the movcc instructions. 343(define_predicate "arith11_operand" 344 (ior (match_operand 0 "register_operand") 345 (and (match_code "const_int") 346 (match_test "SPARC_SIMM11_P (INTVAL (op))")))) 347 348;; Return true if OP is a register or a constant for the umul instruction. 349(define_predicate "uns_arith_operand" 350 (ior (match_operand 0 "register_operand") 351 (match_operand 0 "uns_small_int_operand"))) 352 353;; Return true if OP is a register, or is a CONST_INT that can fit in a 354;; signed 5-bit immediate field. This is an acceptable second operand for 355;; the cbcond instructions. 356(define_predicate "arith5_operand" 357 (ior (match_operand 0 "register_operand") 358 (and (match_code "const_int") 359 (match_test "SPARC_SIMM5_P (INTVAL (op))")))) 360 361 362;; Predicates for miscellaneous instructions. 363 364;; Return true if OP is valid for the lhs of a comparison insn. 365(define_predicate "compare_operand" 366 (match_code "reg,subreg,zero_extract") 367{ 368 if (GET_CODE (op) == ZERO_EXTRACT) 369 return (register_operand (XEXP (op, 0), mode) 370 && small_int_operand (XEXP (op, 1), mode) 371 && small_int_operand (XEXP (op, 2), mode) 372 /* This matches cmp_zero_extract. */ 373 && ((mode == SImode 374 && INTVAL (XEXP (op, 2)) > 19) 375 /* This matches cmp_zero_extract_sp64. */ 376 || (TARGET_ARCH64 377 && mode == DImode 378 && INTVAL (XEXP (op, 2)) > 51))); 379 380 return register_operand (op, mode); 381}) 382 383;; Return true if OP is a valid operand for the source of a move insn. 384(define_predicate "input_operand" 385 (match_code "const_int,const_double,const_vector,reg,subreg,mem") 386{ 387 enum mode_class mclass; 388 389 /* If both modes are non-void they must be the same. */ 390 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) 391 return false; 392 393 mclass = GET_MODE_CLASS (mode); 394 395 /* Allow any 1-instruction integer constant. */ 396 if (mclass == MODE_INT 397 && mode != TImode 398 && (small_int_operand (op, mode) || const_high_operand (op, mode))) 399 return true; 400 401 /* If 32-bit mode and this is a DImode constant, allow it 402 so that the splits can be generated. */ 403 if (TARGET_ARCH32 && mode == DImode && GET_CODE (op) == CONST_INT) 404 return true; 405 406 if (mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE) 407 return true; 408 409 if (mclass == MODE_VECTOR_INT && const_all_ones_operand (op, mode)) 410 return true; 411 412 if (register_or_zero_operand (op, mode)) 413 return true; 414 415 /* If this is a SUBREG, look inside so that we handle paradoxical ones. */ 416 if (GET_CODE (op) == SUBREG) 417 op = SUBREG_REG (op); 418 419 /* Check for valid MEM forms. */ 420 if (GET_CODE (op) == MEM) 421 return memory_address_p (mode, XEXP (op, 0)); 422 423 return false; 424}) 425 426;; Return true if OP is an address suitable for a call insn. 427;; Call insn on SPARC can take a PC-relative constant address 428;; or any regular memory address. 429(define_predicate "call_address_operand" 430 (ior (match_operand 0 "symbolic_operand") 431 (match_test "memory_address_p (Pmode, op)"))) 432 433;; Return true if OP is an operand suitable for a call insn. 434(define_predicate "call_operand" 435 (and (match_code "mem") 436 (match_test "call_address_operand (XEXP (op, 0), mode)"))) 437 438 439(define_predicate "mem_noofs_operand" 440 (and (match_code "mem") 441 (match_code "reg" "0"))) 442 443;; Predicates for operators. 444 445;; Return true if OP is a comparison operator. This allows the use of 446;; MATCH_OPERATOR to recognize all the branch insns. 447(define_predicate "noov_compare_operator" 448 (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu") 449{ 450 enum rtx_code code = GET_CODE (op); 451 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode 452 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 453 /* These are the only branches which work with CC_NOOVmode. */ 454 return (code == EQ || code == NE || code == GE || code == LT); 455 return true; 456}) 457 458;; Return true if OP is a 64-bit comparison operator. This allows the use of 459;; MATCH_OPERATOR to recognize all the branch insns. 460(define_predicate "noov_compare64_operator" 461 (and (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu") 462 (match_test "TARGET_V9")) 463{ 464 enum rtx_code code = GET_CODE (op); 465 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 466 /* These are the only branches which work with CCX_NOOVmode. */ 467 return (code == EQ || code == NE || code == GE || code == LT); 468 return (GET_MODE (XEXP (op, 0)) == CCXmode); 469}) 470 471;; Return true if OP is a comparison operator suitable for use in V9 472;; conditional move or branch on register contents instructions. 473(define_predicate "v9_register_compare_operator" 474 (match_code "eq,ne,ge,lt,le,gt")) 475 476;; Return true if OP is an operator which can set the condition codes 477;; explicitly. We do not include PLUS and MINUS because these 478;; require CC_NOOVmode, which we handle explicitly. 479(define_predicate "cc_arith_operator" 480 (match_code "and,ior,xor")) 481 482;; Return true if OP is an operator which can bitwise complement its 483;; second operand and set the condition codes explicitly. 484;; XOR is not here because combine canonicalizes (xor (not ...) ...) 485;; and (xor ... (not ...)) to (not (xor ...)). */ 486(define_predicate "cc_arith_not_operator" 487 (match_code "and,ior")) 488