1# Check 32bit AVX512{IFMA,VL} instructions 2 3 .allow_index_reg 4 .text 5_start: 6 vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 7 vpmadd52luq %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512{IFMA,VL} 8 vpmadd52luq (%ecx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 9 vpmadd52luq -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 10 vpmadd52luq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 11 vpmadd52luq 2032(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8 12 vpmadd52luq 2048(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 13 vpmadd52luq -2048(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8 14 vpmadd52luq -2064(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 15 vpmadd52luq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8 16 vpmadd52luq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 17 vpmadd52luq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8 18 vpmadd52luq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 19 vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 20 vpmadd52luq %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512{IFMA,VL} 21 vpmadd52luq (%ecx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 22 vpmadd52luq -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 23 vpmadd52luq (%eax){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 24 vpmadd52luq 4064(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8 25 vpmadd52luq 4096(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 26 vpmadd52luq -4096(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8 27 vpmadd52luq -4128(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 28 vpmadd52luq 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8 29 vpmadd52luq 1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 30 vpmadd52luq -1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8 31 vpmadd52luq -1032(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 32 vpmadd52huq %xmm4, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 33 vpmadd52huq %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512{IFMA,VL} 34 vpmadd52huq (%ecx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 35 vpmadd52huq -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 36 vpmadd52huq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 37 vpmadd52huq 2032(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8 38 vpmadd52huq 2048(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 39 vpmadd52huq -2048(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8 40 vpmadd52huq -2064(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 41 vpmadd52huq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8 42 vpmadd52huq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 43 vpmadd52huq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8 44 vpmadd52huq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} 45 vpmadd52huq %ymm4, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 46 vpmadd52huq %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512{IFMA,VL} 47 vpmadd52huq (%ecx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 48 vpmadd52huq -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 49 vpmadd52huq (%eax){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 50 vpmadd52huq 4064(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8 51 vpmadd52huq 4096(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 52 vpmadd52huq -4096(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8 53 vpmadd52huq -4128(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 54 vpmadd52huq 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8 55 vpmadd52huq 1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 56 vpmadd52huq -1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8 57 vpmadd52huq -1032(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} 58 59 .intel_syntax noprefix 60 vpmadd52luq xmm6{k7}, xmm5, xmm4 # AVX512{IFMA,VL} 61 vpmadd52luq xmm6{k7}{z}, xmm5, xmm4 # AVX512{IFMA,VL} 62 vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [ecx] # AVX512{IFMA,VL} 63 vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512{IFMA,VL} 64 vpmadd52luq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{IFMA,VL} 65 vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512{IFMA,VL} Disp8 66 vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [edx+2048] # AVX512{IFMA,VL} 67 vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [edx-2048] # AVX512{IFMA,VL} Disp8 68 vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [edx-2064] # AVX512{IFMA,VL} 69 vpmadd52luq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{IFMA,VL} Disp8 70 vpmadd52luq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{IFMA,VL} 71 vpmadd52luq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{IFMA,VL} Disp8 72 vpmadd52luq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{IFMA,VL} 73 vpmadd52luq ymm6{k7}, ymm5, ymm4 # AVX512{IFMA,VL} 74 vpmadd52luq ymm6{k7}{z}, ymm5, ymm4 # AVX512{IFMA,VL} 75 vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [ecx] # AVX512{IFMA,VL} 76 vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512{IFMA,VL} 77 vpmadd52luq ymm6{k7}, ymm5, [eax]{1to4} # AVX512{IFMA,VL} 78 vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512{IFMA,VL} Disp8 79 vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [edx+4096] # AVX512{IFMA,VL} 80 vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [edx-4096] # AVX512{IFMA,VL} Disp8 81 vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [edx-4128] # AVX512{IFMA,VL} 82 vpmadd52luq ymm6{k7}, ymm5, [edx+1016]{1to4} # AVX512{IFMA,VL} Disp8 83 vpmadd52luq ymm6{k7}, ymm5, [edx+1024]{1to4} # AVX512{IFMA,VL} 84 vpmadd52luq ymm6{k7}, ymm5, [edx-1024]{1to4} # AVX512{IFMA,VL} Disp8 85 vpmadd52luq ymm6{k7}, ymm5, [edx-1032]{1to4} # AVX512{IFMA,VL} 86 vpmadd52huq xmm6{k7}, xmm5, xmm4 # AVX512{IFMA,VL} 87 vpmadd52huq xmm6{k7}{z}, xmm5, xmm4 # AVX512{IFMA,VL} 88 vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [ecx] # AVX512{IFMA,VL} 89 vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512{IFMA,VL} 90 vpmadd52huq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{IFMA,VL} 91 vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512{IFMA,VL} Disp8 92 vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [edx+2048] # AVX512{IFMA,VL} 93 vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [edx-2048] # AVX512{IFMA,VL} Disp8 94 vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [edx-2064] # AVX512{IFMA,VL} 95 vpmadd52huq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{IFMA,VL} Disp8 96 vpmadd52huq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{IFMA,VL} 97 vpmadd52huq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{IFMA,VL} Disp8 98 vpmadd52huq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{IFMA,VL} 99 vpmadd52huq ymm6{k7}, ymm5, ymm4 # AVX512{IFMA,VL} 100 vpmadd52huq ymm6{k7}{z}, ymm5, ymm4 # AVX512{IFMA,VL} 101 vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [ecx] # AVX512{IFMA,VL} 102 vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512{IFMA,VL} 103 vpmadd52huq ymm6{k7}, ymm5, [eax]{1to4} # AVX512{IFMA,VL} 104 vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512{IFMA,VL} Disp8 105 vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [edx+4096] # AVX512{IFMA,VL} 106 vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [edx-4096] # AVX512{IFMA,VL} Disp8 107 vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [edx-4128] # AVX512{IFMA,VL} 108 vpmadd52huq ymm6{k7}, ymm5, [edx+1016]{1to4} # AVX512{IFMA,VL} Disp8 109 vpmadd52huq ymm6{k7}, ymm5, [edx+1024]{1to4} # AVX512{IFMA,VL} 110 vpmadd52huq ymm6{k7}, ymm5, [edx-1024]{1to4} # AVX512{IFMA,VL} Disp8 111 vpmadd52huq ymm6{k7}, ymm5, [edx-1032]{1to4} # AVX512{IFMA,VL} 112