1 /* Basic 80960 instruction formats.
2 
3    Copyright (C) 2001-2016 Free Software Foundation, Inc.
4 
5    This program is free software; you can redistribute it and/or modify
6    it under the terms of the GNU General Public License as published by
7    the Free Software Foundation; either version 3, or (at your option)
8    any later version.
9 
10    This program is distributed in the hope that it will be useful,
11    but WITHOUT ANY WARRANTY; without even the implied warranty of
12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13    GNU General Public License for more details.
14 
15    You should have received a copy of the GNU General Public License
16    along with this program; if not, write to the Free Software
17    Foundation, Inc., 51 Franklin Street - Fifth Floor,
18    Boston, MA 02110-1301, USA.  */
19 
20 /* The 'COJ' instructions are actually COBR instructions with the 'b' in
21    the mnemonic replaced by a 'j';  they are ALWAYS "de-optimized" if
22    necessary: if the displacement will not fit in 13 bits, the assembler will
23    replace them with the corresponding compare and branch instructions.
24 
25    All of the 'MEMn' instructions are the same format; the 'n' in the name
26    indicates the default index scale factor (the size of the datum operated on).
27 
28    The FBRA formats are not actually an instruction format.  They are the
29    "convenience directives" for branching on floating-point comparisons,
30    each of which generates 2 instructions (a 'bno' and one other branch).
31 
32    The CALLJ format is not actually an instruction format.  It indicates that
33    the instruction generated (a CTRL-format 'call') should have its relocation
34    specially flagged for link-time replacement with a 'bal' or 'calls' if
35    appropriate.  */
36 
37 #define CTRL	0
38 #define COBR	1
39 #define COJ	2
40 #define REG	3
41 #define MEM1	4
42 #define MEM2	5
43 #define MEM4	6
44 #define MEM8	7
45 #define MEM12	8
46 #define MEM16	9
47 #define FBRA	10
48 #define CALLJ	11
49 
50 /* Masks for the mode bits in REG format instructions */
51 #define M1		0x0800
52 #define M2		0x1000
53 #define M3		0x2000
54 
55 /* Generate the 12-bit opcode for a REG format instruction by placing the
56  * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
57  * 7-10.
58  */
59 
60 #define REG_OPC(opc)	((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
61 
62 /* Generate a template for a REG format instruction:  place the opcode bits
63  * in the appropriate fields and OR in mode bits for the operands that will not
64  * be used.  I.e.,
65  *		set m1=1, if src1 will not be used
66  *		set m2=1, if src2 will not be used
67  *		set m3=1, if dst  will not be used
68  *
69  * Setting the "unused" mode bits to 1 speeds up instruction execution(!).
70  * The information is also useful to us because some 1-operand REG instructions
71  * use the src1 field, others the dst field; and some 2-operand REG instructions
72  * use src1/src2, others src1/dst.  The set mode bits enable us to distinguish.
73  */
74 #define R_0(opc)	( REG_OPC(opc) | M1 | M2 | M3 )	/* No operands      */
75 #define R_1(opc)	( REG_OPC(opc) | M2 | M3 )	/* 1 operand: src1  */
76 #define R_1D(opc)	( REG_OPC(opc) | M1 | M2 )	/* 1 operand: dst   */
77 #define R_2(opc)	( REG_OPC(opc) | M3 )		/* 2 ops: src1/src2 */
78 #define R_2D(opc)	( REG_OPC(opc) | M2 )		/* 2 ops: src1/dst  */
79 #define R_3(opc)	( REG_OPC(opc) )		/* 3 operands       */
80 
81 /* DESCRIPTOR BYTES FOR REGISTER OPERANDS
82  *
83  * Interpret names as follows:
84  *	R:   global or local register only
85  *	RS:  global, local, or (if target allows) special-function register only
86  *	RL:  global or local register, or integer literal
87  *	RSL: global, local, or (if target allows) special-function register;
88  *		or integer literal
89  *	F:   global, local, or floating-point register
90  *	FL:  global, local, or floating-point register; or literal (including
91  *		floating point)
92  *
93  * A number appended to a name indicates that registers must be aligned,
94  * as follows:
95  *	2: register number must be multiple of 2
96  *	4: register number must be multiple of 4
97  */
98 
99 #define SFR	0x10		/* Mask for the "sfr-OK" bit */
100 #define LIT	0x08		/* Mask for the "literal-OK" bit */
101 #define FP	0x04		/* Mask for "floating-point-OK" bit */
102 
103 /* This macro ors the bits together.  Note that 'align' is a mask
104  * for the low 0, 1, or 2 bits of the register number, as appropriate.
105  */
106 #define OP(align,lit,fp,sfr)	( align | lit | fp | sfr )
107 
108 #define R	OP( 0, 0,   0,  0   )
109 #define RS	OP( 0, 0,   0,  SFR )
110 #define RL	OP( 0, LIT, 0,  0   )
111 #define RSL	OP( 0, LIT, 0,  SFR )
112 #define F	OP( 0, 0,   FP, 0   )
113 #define FL	OP( 0, LIT, FP, 0   )
114 #define R2	OP( 1, 0,   0,  0   )
115 #define RL2	OP( 1, LIT, 0,  0   )
116 #define F2	OP( 1, 0,   FP, 0   )
117 #define FL2	OP( 1, LIT, FP, 0   )
118 #define R4	OP( 3, 0,   0,  0   )
119 #define RL4	OP( 3, LIT, 0,  0   )
120 #define F4	OP( 3, 0,   FP, 0   )
121 #define FL4	OP( 3, LIT, FP, 0   )
122 
123 #define M	0x7f	/* Memory operand (MEMA & MEMB format instructions) */
124 
125 /* Macros to extract info from the register operand descriptor byte 'od'.
126  */
127 #define SFR_OK(od)	(od & SFR)	/* TRUE if sfr operand allowed */
128 #define LIT_OK(od)	(od & LIT)	/* TRUE if literal operand allowed */
129 #define FP_OK(od)	(od & FP)	/* TRUE if floating-point op allowed */
130 #define REG_ALIGN(od,n)	((od & 0x3 & n) == 0)
131 					/* TRUE if reg #n is properly aligned */
132 #define MEMOP(od)	(od == M)	/* TRUE if operand is a memory operand*/
133 
134 /* Description of a single i80960 instruction */
135 struct i960_opcode {
136 	long opcode;	/* 32 bits, constant fields filled in, rest zeroed */
137 	const char *name;	/* Assembler mnemonic				   */
138 	short iclass;	/* Class: see #defines below			   */
139 	char format;	/* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ	   */
140 	char num_ops;	/* Number of operands				   */
141 	char operand[3];/* Operand descriptors; same order as assembler instr */
142 };
143 
144 /* Classes of 960 instructions:
145  *	- each instruction falls into one class.
146  *	- each target architecture supports one or more classes.
147  *
148  * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!:  see targ_has_iclass().
149  */
150 #define I_BASE	0x01	/* 80960 base instruction set	*/
151 #define I_CX	0x02	/* 80960Cx instruction		*/
152 #define I_DEC	0x04	/* Decimal instruction		*/
153 #define I_FP	0x08	/* Floating point instruction	*/
154 #define I_KX	0x10	/* 80960Kx instruction		*/
155 #define I_MIL	0x20	/* Military instruction		*/
156 #define I_CASIM	0x40	/* CA simulator instruction	*/
157 #define I_CX2	0x80	/* Cx/Jx/Hx instructions	*/
158 #define I_JX	0x100	/* Jx/Hx instruction		*/
159 #define I_HX	0x200	/* Hx instructions		*/
160 
161 /******************************************************************************
162  *
163  *		TABLE OF i960 INSTRUCTION DESCRIPTIONS
164  *
165  ******************************************************************************/
166 
167 const struct i960_opcode i960_opcodes[] = {
168 
169 	/* if a CTRL instruction has an operand, it's always a displacement */
170 
171 	/* callj default=='call' */
172 	{ 0x09000000,	"callj",	I_BASE,	CALLJ, 	1, { 0, 0, 0 } },
173 	{ 0x08000000,	"b",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
174 	{ 0x09000000,	"call",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
175 	{ 0x0a000000,	"ret",		I_BASE,	CTRL, 	0, { 0, 0, 0 } },
176 	{ 0x0b000000,	"bal",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
177 	{ 0x10000000,	"bno",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
178 	/* bf same as bno */
179 	{ 0x10000000,	"bf",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
180 	/* bru same as bno */
181 	{ 0x10000000,	"bru",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
182 	{ 0x11000000,	"bg",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
183 	/* brg same as bg */
184 	{ 0x11000000,	"brg",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
185 	{ 0x12000000,	"be",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
186 	/* bre same as be */
187 	{ 0x12000000,	"bre",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
188 	{ 0x13000000,	"bge",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
189 	/* brge same as bge */
190 	{ 0x13000000,	"brge",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
191 	{ 0x14000000,	"bl",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
192 	/* brl same as bl */
193 	{ 0x14000000,	"brl",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
194 	{ 0x15000000,	"bne",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
195 	/* brlg same as bne */
196 	{ 0x15000000,	"brlg",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
197 	{ 0x16000000,	"ble",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
198 	/* brle same as ble */
199 	{ 0x16000000,	"brle",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
200 	{ 0x17000000,	"bo",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
201 	/* bt same as bo */
202 	{ 0x17000000,	"bt",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
203 	/* bro same as bo */
204 	{ 0x17000000,	"bro",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
205 	{ 0x18000000,	"faultno",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
206 	/* faultf same as faultno */
207 	{ 0x18000000,	"faultf",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
208 	{ 0x19000000,	"faultg",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
209 	{ 0x1a000000,	"faulte",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
210 	{ 0x1b000000,	"faultge",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
211 	{ 0x1c000000,	"faultl",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
212 	{ 0x1d000000,	"faultne",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
213 	{ 0x1e000000,	"faultle",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
214 	{ 0x1f000000,	"faulto",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
215 	/* faultt syn for faulto */
216 	{ 0x1f000000,	"faultt",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
217 
218 	{ 0x01000000,	"syscall",	I_CASIM,CTRL, 	0, { 0, 0, 0 } },
219 
220 	/* If a COBR (or COJ) has 3 operands, the last one is always a
221 	 * displacement and does not appear explicitly in the table.
222 	 */
223 
224 	{ 0x20000000,	"testno",	I_BASE,	COBR,	1, { R, 0, 0 }	},
225 	{ 0x21000000,	"testg",	I_BASE,	COBR,	1, { R, 0, 0 }	},
226 	{ 0x22000000,	"teste",	I_BASE,	COBR,	1, { R, 0, 0 }	},
227 	{ 0x23000000,	"testge",	I_BASE,	COBR,	1, { R, 0, 0 }	},
228 	{ 0x24000000,	"testl",	I_BASE,	COBR,	1, { R, 0, 0 }	},
229 	{ 0x25000000,	"testne",	I_BASE,	COBR,	1, { R, 0, 0 }	},
230 	{ 0x26000000,	"testle",	I_BASE,	COBR,	1, { R, 0, 0 }	},
231 	{ 0x27000000,	"testo",	I_BASE,	COBR,	1, { R, 0, 0 }	},
232 	{ 0x30000000,	"bbc",		I_BASE,	COBR,	3, { RL, RS, 0 } },
233 	{ 0x31000000,	"cmpobg",	I_BASE,	COBR,	3, { RL, RS, 0 } },
234 	{ 0x32000000,	"cmpobe",	I_BASE,	COBR,	3, { RL, RS, 0 } },
235 	{ 0x33000000,	"cmpobge",	I_BASE,	COBR,	3, { RL, RS, 0 } },
236 	{ 0x34000000,	"cmpobl",	I_BASE,	COBR,	3, { RL, RS, 0 } },
237 	{ 0x35000000,	"cmpobne",	I_BASE,	COBR,	3, { RL, RS, 0 } },
238 	{ 0x36000000,	"cmpoble",	I_BASE,	COBR,	3, { RL, RS, 0 } },
239 	{ 0x37000000,	"bbs",		I_BASE,	COBR,	3, { RL, RS, 0 } },
240 	{ 0x38000000,	"cmpibno",	I_BASE,	COBR,	3, { RL, RS, 0 } },
241 	{ 0x39000000,	"cmpibg",	I_BASE,	COBR,	3, { RL, RS, 0 } },
242 	{ 0x3a000000,	"cmpibe",	I_BASE,	COBR,	3, { RL, RS, 0 } },
243 	{ 0x3b000000,	"cmpibge",	I_BASE,	COBR,	3, { RL, RS, 0 } },
244 	{ 0x3c000000,	"cmpibl",	I_BASE,	COBR,	3, { RL, RS, 0 } },
245 	{ 0x3d000000,	"cmpibne",	I_BASE,	COBR,	3, { RL, RS, 0 } },
246 	{ 0x3e000000,	"cmpible",	I_BASE,	COBR,	3, { RL, RS, 0 } },
247 	{ 0x3f000000,	"cmpibo",	I_BASE,	COBR,	3, { RL, RS, 0 } },
248 	{ 0x31000000,	"cmpojg",	I_BASE,	COJ,	3, { RL, RS, 0 } },
249 	{ 0x32000000,	"cmpoje",	I_BASE,	COJ,	3, { RL, RS, 0 } },
250 	{ 0x33000000,	"cmpojge",	I_BASE,	COJ,	3, { RL, RS, 0 } },
251 	{ 0x34000000,	"cmpojl",	I_BASE,	COJ,	3, { RL, RS, 0 } },
252 	{ 0x35000000,	"cmpojne",	I_BASE,	COJ,	3, { RL, RS, 0 } },
253 	{ 0x36000000,	"cmpojle",	I_BASE,	COJ,	3, { RL, RS, 0 } },
254 	{ 0x38000000,	"cmpijno",	I_BASE,	COJ,	3, { RL, RS, 0 } },
255 	{ 0x39000000,	"cmpijg",	I_BASE,	COJ,	3, { RL, RS, 0 } },
256 	{ 0x3a000000,	"cmpije",	I_BASE,	COJ,	3, { RL, RS, 0 } },
257 	{ 0x3b000000,	"cmpijge",	I_BASE,	COJ,	3, { RL, RS, 0 } },
258 	{ 0x3c000000,	"cmpijl",	I_BASE,	COJ,	3, { RL, RS, 0 } },
259 	{ 0x3d000000,	"cmpijne",	I_BASE,	COJ,	3, { RL, RS, 0 } },
260 	{ 0x3e000000,	"cmpijle",	I_BASE,	COJ,	3, { RL, RS, 0 } },
261 	{ 0x3f000000,	"cmpijo",	I_BASE,	COJ,	3, { RL, RS, 0 } },
262 
263 	{ 0x80000000,	"ldob",		I_BASE,	MEM1,	2, { M,  R,  0 } },
264 	{ 0x82000000,	"stob",		I_BASE,	MEM1,	2, { R,  M,  0 } },
265 	{ 0x84000000,	"bx",		I_BASE,	MEM1,	1, { M,  0,  0 } },
266 	{ 0x85000000,	"balx",		I_BASE,	MEM1,	2, { M,  R,  0 } },
267 	{ 0x86000000,	"callx",	I_BASE,	MEM1,	1, { M,  0,  0 } },
268 	{ 0x88000000,	"ldos",		I_BASE,	MEM2,	2, { M,  R,  0 } },
269 	{ 0x8a000000,	"stos",		I_BASE,	MEM2,	2, { R,  M,  0 } },
270 	{ 0x8c000000,	"lda",		I_BASE,	MEM1,	2, { M,  R,  0 } },
271 	{ 0x90000000,	"ld",		I_BASE,	MEM4,	2, { M,  R,  0 } },
272 	{ 0x92000000,	"st",		I_BASE,	MEM4,	2, { R,  M,  0 } },
273 	{ 0x98000000,	"ldl",		I_BASE,	MEM8,	2, { M,  R2, 0 } },
274 	{ 0x9a000000,	"stl",		I_BASE,	MEM8,	2, { R2, M,  0 } },
275 	{ 0xa0000000,	"ldt",		I_BASE,	MEM12,	2, { M,  R4, 0 } },
276 	{ 0xa2000000,	"stt",		I_BASE,	MEM12,	2, { R4, M,  0 } },
277 	{ 0xb0000000,	"ldq",		I_BASE,	MEM16,	2, { M,  R4, 0 } },
278 	{ 0xb2000000,	"stq",		I_BASE,	MEM16,	2, { R4, M,  0 } },
279 	{ 0xc0000000,	"ldib",		I_BASE,	MEM1,	2, { M,  R,  0 } },
280 	{ 0xc2000000,	"stib",		I_BASE,	MEM1,	2, { R,  M,  0 } },
281 	{ 0xc8000000,	"ldis",		I_BASE,	MEM2,	2, { M,  R,  0 } },
282 	{ 0xca000000,	"stis",		I_BASE,	MEM2,	2, { R,  M,  0 } },
283 
284 	{ R_3(0x580),	"notbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
285 	{ R_3(0x581),	"and",		I_BASE,	REG,	3, { RSL,RSL,RS } },
286 	{ R_3(0x582),	"andnot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
287 	{ R_3(0x583),	"setbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
288 	{ R_3(0x584),	"notand",	I_BASE,	REG,	3, { RSL,RSL,RS } },
289 	{ R_3(0x586),	"xor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
290 	{ R_3(0x587),	"or",		I_BASE,	REG,	3, { RSL,RSL,RS } },
291 	{ R_3(0x588),	"nor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
292 	{ R_3(0x589),	"xnor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
293 	{ R_2D(0x58a),	"not",		I_BASE,	REG,	2, { RSL,RS, 0 } },
294 	{ R_3(0x58b),	"ornot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
295 	{ R_3(0x58c),	"clrbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
296 	{ R_3(0x58d),	"notor",	I_BASE,	REG,	3, { RSL,RSL,RS } },
297 	{ R_3(0x58e),	"nand",		I_BASE,	REG,	3, { RSL,RSL,RS } },
298 	{ R_3(0x58f),	"alterbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
299 	{ R_3(0x590),	"addo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
300 	{ R_3(0x591),	"addi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
301 	{ R_3(0x592),	"subo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
302 	{ R_3(0x593),	"subi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
303 	{ R_3(0x598),	"shro",		I_BASE,	REG,	3, { RSL,RSL,RS } },
304 	{ R_3(0x59a),	"shrdi",	I_BASE,	REG,	3, { RSL,RSL,RS } },
305 	{ R_3(0x59b),	"shri",		I_BASE,	REG,	3, { RSL,RSL,RS } },
306 	{ R_3(0x59c),	"shlo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
307 	{ R_3(0x59d),	"rotate",	I_BASE,	REG,	3, { RSL,RSL,RS } },
308 	{ R_3(0x59e),	"shli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
309 	{ R_2(0x5a0),	"cmpo",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
310 	{ R_2(0x5a1),	"cmpi",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
311 	{ R_2(0x5a2),	"concmpo",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
312 	{ R_2(0x5a3),	"concmpi",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
313 	{ R_3(0x5a4),	"cmpinco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
314 	{ R_3(0x5a5),	"cmpinci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
315 	{ R_3(0x5a6),	"cmpdeco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
316 	{ R_3(0x5a7),	"cmpdeci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
317 	{ R_2(0x5ac),	"scanbyte",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
318 	{ R_2(0x5ae),	"chkbit",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
319 	{ R_3(0x5b0),	"addc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
320 	{ R_3(0x5b2),	"subc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
321 	{ R_2D(0x5cc),	"mov",		I_BASE,	REG,	2, { RSL,RS, 0 } },
322 	{ R_2D(0x5dc),	"movl",		I_BASE,	REG,	2, { RL2,R2, 0 } },
323 	{ R_2D(0x5ec),	"movt",		I_BASE,	REG,	2, { RL4,R4, 0 } },
324 	{ R_2D(0x5fc),	"movq",		I_BASE,	REG,	2, { RL4,R4, 0 } },
325 	{ R_3(0x610),	"atmod",	I_BASE,	REG,	3, { RS, RSL,R } },
326 	{ R_3(0x612),	"atadd",	I_BASE,	REG,	3, { RS, RSL,RS } },
327 	{ R_2D(0x640),	"spanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
328 	{ R_2D(0x641),	"scanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
329 	{ R_3(0x645),	"modac",	I_BASE,	REG,	3, { RSL,RSL,RS } },
330 	{ R_3(0x650),	"modify",	I_BASE,	REG,	3, { RSL,RSL,R } },
331 	{ R_3(0x651),	"extract",	I_BASE,	REG,	3, { RSL,RSL,R } },
332 	{ R_3(0x654),	"modtc",	I_BASE,	REG,	3, { RSL,RSL,RS } },
333 	{ R_3(0x655),	"modpc",	I_BASE,	REG,	3, { RSL,RSL,R } },
334 	{ R_1(0x660),	"calls",	I_BASE,	REG,	1, { RSL, 0, 0 } },
335 	{ R_0(0x66b),	"mark",		I_BASE,	REG,	0, { 0, 0, 0 }	},
336 	{ R_0(0x66c),	"fmark",	I_BASE,	REG,	0, { 0, 0, 0 }	},
337 	{ R_0(0x66d),	"flushreg",	I_BASE,	REG,	0, { 0, 0, 0 }	},
338 	{ R_0(0x66f),	"syncf",	I_BASE,	REG,	0, { 0, 0, 0 }	},
339 	{ R_3(0x670),	"emul",		I_BASE,	REG,	3, { RSL,RSL,R2 } },
340 	{ R_3(0x671),	"ediv",		I_BASE,	REG,	3, { RSL,RL2,RS } },
341 	{ R_2D(0x672),	"cvtadr",	I_CASIM,REG, 	2, { RL, R2, 0 } },
342 	{ R_3(0x701),	"mulo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
343 	{ R_3(0x708),	"remo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
344 	{ R_3(0x70b),	"divo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
345 	{ R_3(0x741),	"muli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
346 	{ R_3(0x748),	"remi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
347 	{ R_3(0x749),	"modi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
348 	{ R_3(0x74b),	"divi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
349 
350 	/* Floating-point instructions */
351 
352 	{ R_2D(0x674),	"cvtir",	I_FP,	REG,	2, { RL, F, 0 } },
353 	{ R_2D(0x675),	"cvtilr",	I_FP,	REG,	2, { RL, F, 0 } },
354 	{ R_3(0x676),	"scalerl",	I_FP,	REG,	3, { RL, FL2,F2 } },
355 	{ R_3(0x677),	"scaler",	I_FP,	REG,	3, { RL, FL, F } },
356 	{ R_3(0x680),	"atanr",	I_FP,	REG,	3, { FL, FL, F } },
357 	{ R_3(0x681),	"logepr",	I_FP,	REG,	3, { FL, FL, F } },
358 	{ R_3(0x682),	"logr",		I_FP,	REG,	3, { FL, FL, F } },
359 	{ R_3(0x683),	"remr",		I_FP,	REG,	3, { FL, FL, F } },
360 	{ R_2(0x684),	"cmpor",	I_FP,	REG,	2, { FL, FL, 0 } },
361 	{ R_2(0x685),	"cmpr",		I_FP,	REG,	2, { FL, FL, 0 } },
362 	{ R_2D(0x688),	"sqrtr",	I_FP,	REG,	2, { FL, F, 0 } },
363 	{ R_2D(0x689),	"expr",		I_FP,	REG,	2, { FL, F, 0 } },
364 	{ R_2D(0x68a),	"logbnr",	I_FP,	REG,	2, { FL, F, 0 } },
365 	{ R_2D(0x68b),	"roundr",	I_FP,	REG,	2, { FL, F, 0 } },
366 	{ R_2D(0x68c),	"sinr",		I_FP,	REG,	2, { FL, F, 0 } },
367 	{ R_2D(0x68d),	"cosr",		I_FP,	REG,	2, { FL, F, 0 } },
368 	{ R_2D(0x68e),	"tanr",		I_FP,	REG,	2, { FL, F, 0 } },
369 	{ R_1(0x68f),	"classr",	I_FP,	REG,	1, { FL, 0, 0 }	},
370 	{ R_3(0x690),	"atanrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
371 	{ R_3(0x691),	"logeprl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
372 	{ R_3(0x692),	"logrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
373 	{ R_3(0x693),	"remrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
374 	{ R_2(0x694),	"cmporl",	I_FP,	REG,	2, { FL2,FL2, 0 } },
375 	{ R_2(0x695),	"cmprl",	I_FP,	REG,	2, { FL2,FL2, 0 } },
376 	{ R_2D(0x698),	"sqrtrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
377 	{ R_2D(0x699),	"exprl",	I_FP,	REG,	2, { FL2,F2, 0 } },
378 	{ R_2D(0x69a),	"logbnrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
379 	{ R_2D(0x69b),	"roundrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
380 	{ R_2D(0x69c),	"sinrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
381 	{ R_2D(0x69d),	"cosrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
382 	{ R_2D(0x69e),	"tanrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
383 	{ R_1(0x69f),	"classrl",	I_FP,	REG,	1, { FL2, 0, 0 } },
384 	{ R_2D(0x6c0),	"cvtri",	I_FP,	REG,	2, { FL, R, 0 } },
385 	{ R_2D(0x6c1),	"cvtril",	I_FP,	REG,	2, { FL, R2, 0 } },
386 	{ R_2D(0x6c2),	"cvtzri",	I_FP,	REG,	2, { FL, R, 0 } },
387 	{ R_2D(0x6c3),	"cvtzril",	I_FP,	REG,	2, { FL, R2, 0 } },
388 	{ R_2D(0x6c9),	"movr",		I_FP,	REG,	2, { FL, F, 0 } },
389 	{ R_2D(0x6d9),	"movrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
390 	{ R_2D(0x6e1),	"movre",	I_FP,	REG,	2, { FL4,F4, 0 } },
391 	{ R_3(0x6e2),	"cpysre",	I_FP,	REG,	3, { FL4,FL4,F4 } },
392 	{ R_3(0x6e3),	"cpyrsre",	I_FP,	REG,	3, { FL4,FL4,F4 } },
393 	{ R_3(0x78b),	"divr",		I_FP,	REG,	3, { FL, FL, F } },
394 	{ R_3(0x78c),	"mulr",		I_FP,	REG,	3, { FL, FL, F } },
395 	{ R_3(0x78d),	"subr",		I_FP,	REG,	3, { FL, FL, F } },
396 	{ R_3(0x78f),	"addr",		I_FP,	REG,	3, { FL, FL, F } },
397 	{ R_3(0x79b),	"divrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
398 	{ R_3(0x79c),	"mulrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
399 	{ R_3(0x79d),	"subrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
400 	{ R_3(0x79f),	"addrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
401 
402 	/* These are the floating point branch instructions.  Each actually
403 	 * generates 2 branch instructions:  the first a CTRL instruction with
404 	 * the indicated opcode, and the second a 'bno'.
405 	 */
406 
407 	{ 0x12000000,	"brue",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
408 	{ 0x11000000,	"brug",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
409 	{ 0x13000000,	"bruge",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
410 	{ 0x14000000,	"brul",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
411 	{ 0x16000000,	"brule",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
412 	{ 0x15000000,	"brulg",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
413 
414 
415 	/* Decimal instructions */
416 
417 	{ R_3(0x642),	"daddc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
418 	{ R_3(0x643),	"dsubc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
419 	{ R_2D(0x644),	"dmovt",	I_DEC,	REG,	2, { RSL,RS, 0 } },
420 
421 
422 	/* KX extensions */
423 
424 	{ R_2(0x600),	"synmov",	I_KX,	REG,	2, { R,  R, 0 } },
425 	{ R_2(0x601),	"synmovl",	I_KX,	REG,	2, { R,  R, 0 } },
426 	{ R_2(0x602),	"synmovq",	I_KX,	REG,	2, { R,  R, 0 } },
427 	{ R_2D(0x615),	"synld",	I_KX,	REG,	2, { R,  R, 0 } },
428 
429 
430 	/* MC extensions */
431 
432 	{ R_3(0x603),	"cmpstr",	I_MIL,	REG,	3, { R,  R,  RL } },
433 	{ R_3(0x604),	"movqstr",	I_MIL,	REG,	3, { R,  R,  RL } },
434 	{ R_3(0x605),	"movstr",	I_MIL,	REG,	3, { R,  R,  RL } },
435 	{ R_2D(0x613),	"inspacc",	I_MIL,	REG,	2, { R,  R, 0 } },
436 	{ R_2D(0x614),	"ldphy",	I_MIL,	REG,	2, { R,  R, 0 } },
437 	{ R_3(0x617),	"fill",		I_MIL,	REG,	3, { R,  RL, RL } },
438 	{ R_2D(0x646),	"condrec",	I_MIL,	REG,	2, { R,  R, 0 } },
439 	{ R_2D(0x656),	"receive",	I_MIL,	REG,	2, { R,  R, 0 } },
440 	{ R_3(0x662),	"send",		I_MIL,	REG,	3, { R,  RL, R } },
441 	{ R_1(0x663),	"sendserv",	I_MIL,	REG,	1, { R, 0, 0 }	},
442 	{ R_1(0x664),	"resumprcs",	I_MIL,	REG,	1, { R, 0, 0 }	},
443 	{ R_1(0x665),	"schedprcs",	I_MIL,	REG,	1, { R, 0, 0 }	},
444 	{ R_0(0x666),	"saveprcs",	I_MIL,	REG,	0, { 0, 0, 0 }	},
445 	{ R_1(0x668),	"condwait",	I_MIL,	REG,	1, { R, 0, 0 }	},
446 	{ R_1(0x669),	"wait",		I_MIL,	REG,	1, { R, 0, 0 }	},
447 	{ R_1(0x66a),	"signal",	I_MIL,	REG,	1, { R, 0, 0 }	},
448 	{ R_1D(0x673),	"ldtime",	I_MIL,	REG,	1, { R2, 0, 0 }	},
449 
450 
451 	/* CX extensions */
452 
453 	{ R_3(0x5d8),	"eshro",	I_CX2,	REG,	3, { RSL,RSL,RS } },
454 	{ R_3(0x630),	"sdma",		I_CX,	REG,	3, { RSL,RSL,RL } },
455 	{ R_3(0x631),	"udma",		I_CX,	REG,	0, { 0, 0, 0 }	},
456 	{ R_3(0x659),	"sysctl",	I_CX2,	REG,	3, { RSL,RSL,RL } },
457 
458 
459 	/* Jx extensions.  */
460 	{ R_3(0x780),	"addono",	I_JX,	REG,	3, { RSL,RSL,RS } },
461 	{ R_3(0x790),	"addog",	I_JX,	REG,	3, { RSL,RSL,RS } },
462 	{ R_3(0x7a0),	"addoe",	I_JX,	REG,	3, { RSL,RSL,RS } },
463 	{ R_3(0x7b0),	"addoge",	I_JX,	REG,	3, { RSL,RSL,RS } },
464 	{ R_3(0x7c0),	"addol",	I_JX,	REG,	3, { RSL,RSL,RS } },
465 	{ R_3(0x7d0),	"addone",	I_JX,	REG,	3, { RSL,RSL,RS } },
466 	{ R_3(0x7e0),	"addole",	I_JX,	REG,	3, { RSL,RSL,RS } },
467 	{ R_3(0x7f0),	"addoo",	I_JX,	REG,	3, { RSL,RSL,RS } },
468 	{ R_3(0x781),	"addino",	I_JX,	REG,	3, { RSL,RSL,RS } },
469 	{ R_3(0x791),	"addig",	I_JX,	REG,	3, { RSL,RSL,RS } },
470 	{ R_3(0x7a1),	"addie",	I_JX,	REG,	3, { RSL,RSL,RS } },
471 	{ R_3(0x7b1),	"addige",	I_JX,	REG,	3, { RSL,RSL,RS } },
472 	{ R_3(0x7c1),	"addil",	I_JX,	REG,	3, { RSL,RSL,RS } },
473 	{ R_3(0x7d1),	"addine",	I_JX,	REG,	3, { RSL,RSL,RS } },
474 	{ R_3(0x7e1),	"addile",	I_JX,	REG,	3, { RSL,RSL,RS } },
475 	{ R_3(0x7f1),	"addio",	I_JX,	REG,	3, { RSL,RSL,RS } },
476 
477 	{ R_2D(0x5ad),	"bswap",	I_JX,	REG,	2, { RSL, RS, 0 } },
478 
479 	{ R_2(0x594),	"cmpob",	I_JX,	REG,	2, { RSL,RSL, 0 } },
480 	{ R_2(0x595),	"cmpib",	I_JX,	REG,	2, { RSL,RSL, 0 } },
481 	{ R_2(0x596),	"cmpos",	I_JX,	REG,	2, { RSL,RSL, 0 } },
482 	{ R_2(0x597),	"cmpis",	I_JX,	REG,	2, { RSL,RSL, 0 } },
483 
484 	{ R_3(0x784),	"selno",	I_JX,	REG,	3, { RSL,RSL,RS } },
485 	{ R_3(0x794),	"selg",		I_JX,	REG,	3, { RSL,RSL,RS } },
486 	{ R_3(0x7a4),	"sele",		I_JX,	REG,	3, { RSL,RSL,RS } },
487 	{ R_3(0x7b4),	"selge",	I_JX,	REG,	3, { RSL,RSL,RS } },
488 	{ R_3(0x7c4),	"sell",		I_JX,	REG,	3, { RSL,RSL,RS } },
489 	{ R_3(0x7d4),	"selne",	I_JX,	REG,	3, { RSL,RSL,RS } },
490 	{ R_3(0x7e4),	"selle",	I_JX,	REG,	3, { RSL,RSL,RS } },
491 	{ R_3(0x7f4),	"selo",		I_JX,	REG,	3, { RSL,RSL,RS } },
492 
493 	{ R_3(0x782),	"subono",	I_JX,	REG,	3, { RSL,RSL,RS } },
494 	{ R_3(0x792),	"subog",	I_JX,	REG,	3, { RSL,RSL,RS } },
495 	{ R_3(0x7a2),	"suboe",	I_JX,	REG,	3, { RSL,RSL,RS } },
496 	{ R_3(0x7b2),	"suboge",	I_JX,	REG,	3, { RSL,RSL,RS } },
497 	{ R_3(0x7c2),	"subol",	I_JX,	REG,	3, { RSL,RSL,RS } },
498 	{ R_3(0x7d2),	"subone",	I_JX,	REG,	3, { RSL,RSL,RS } },
499 	{ R_3(0x7e2),	"subole",	I_JX,	REG,	3, { RSL,RSL,RS } },
500 	{ R_3(0x7f2),	"suboo",	I_JX,	REG,	3, { RSL,RSL,RS } },
501 	{ R_3(0x783),	"subino",	I_JX,	REG,	3, { RSL,RSL,RS } },
502 	{ R_3(0x793),	"subig",	I_JX,	REG,	3, { RSL,RSL,RS } },
503 	{ R_3(0x7a3),	"subie",	I_JX,	REG,	3, { RSL,RSL,RS } },
504 	{ R_3(0x7b3),	"subige",	I_JX,	REG,	3, { RSL,RSL,RS } },
505 	{ R_3(0x7c3),	"subil",	I_JX,	REG,	3, { RSL,RSL,RS } },
506 	{ R_3(0x7d3),	"subine",	I_JX,	REG,	3, { RSL,RSL,RS } },
507 	{ R_3(0x7e3),	"subile",	I_JX,	REG,	3, { RSL,RSL,RS } },
508 	{ R_3(0x7f3),	"subio",	I_JX,	REG,	3, { RSL,RSL,RS } },
509 
510 	{ R_3(0x65c),	"dcctl",	I_JX,	REG,	3, { RSL,RSL,RL } },
511 	{ R_3(0x65b),	"icctl",	I_JX,	REG,	3, { RSL,RSL,RS } },
512 	{ R_2D(0x658),	"intctl",	I_JX,	REG,	2, { RSL, RS, 0 } },
513 	{ R_0(0x5b4),	"intdis",	I_JX,	REG,	0, {   0,  0, 0 } },
514 	{ R_0(0x5b5),	"inten",	I_JX,	REG,	0, {   0,  0, 0 } },
515 	{ R_0(0x65d),	"halt",		I_JX,	REG,	1, { RSL,  0, 0 } },
516 
517 	/* Hx extensions.  */
518 	{ 0xac000000,	"dcinva",	I_HX,	MEM1,	1, {   M,  0, 0 } },
519 
520 	/* END OF TABLE */
521 
522 	{ 0,		NULL,		0,	0,	0, { 0, 0, 0 }	}
523 };
524 
525  /* end of i960-opcode.h */
526