1 /******************************Module*Header************************************\ 2 * 3 * Module Name: d3dukmdt.h 4 * 5 * Content: Windows Display Driver Model (WDDM) user/kernel mode 6 * shared data type definitions. 7 * 8 * Copyright (c) Microsoft Corporation. 9 * Licensed under the MIT License. 10 * 11 \*******************************************************************************/ 12 #ifndef _D3DUKMDT_H_ 13 #define _D3DUKMDT_H_ 14 #include <winapifamily.h> 15 16 #pragma region Desktop Family 17 #if WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP) 18 19 #if !defined(_D3DKMDT_H) && \ 20 !defined(_D3DKMTHK_H_) && \ 21 !defined(_D3DUMDDI_H_) && \ 22 !defined(__DXGKRNLETW_H__) 23 #error This header should not be included directly! 24 #endif 25 26 #pragma warning(push) 27 #pragma warning(disable:4201) // anonymous unions warning 28 #pragma warning(disable:4214) // nonstandard extension used: bit field types other than int 29 30 31 // 32 // WDDM DDI Interface Version 33 // 34 35 #define DXGKDDI_INTERFACE_VERSION_VISTA 0x1052 36 #define DXGKDDI_INTERFACE_VERSION_VISTA_SP1 0x1053 37 #define DXGKDDI_INTERFACE_VERSION_WIN7 0x2005 38 #define DXGKDDI_INTERFACE_VERSION_WIN8 0x300E 39 #define DXGKDDI_INTERFACE_VERSION_WDDM1_3 0x4002 40 #define DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION 0x4003 41 #define DXGKDDI_INTERFACE_VERSION_WDDM2_0 0x5023 42 #define DXGKDDI_INTERFACE_VERSION_WDDM2_1 0x6003 43 #define DXGKDDI_INTERFACE_VERSION_WDDM2_1_5 0x6010 // Used in RS1.7 for GPU-P 44 #define DXGKDDI_INTERFACE_VERSION_WDDM2_1_6 0x6011 // Used in RS1.8 for GPU-P 45 #define DXGKDDI_INTERFACE_VERSION_WDDM2_2 0x700A 46 #define DXGKDDI_INTERFACE_VERSION_WDDM2_3 0x8001 47 #define DXGKDDI_INTERFACE_VERSION_WDDM2_4 0x9006 48 #define DXGKDDI_INTERFACE_VERSION_WDDM2_5 0xA00B 49 #define DXGKDDI_INTERFACE_VERSION_WDDM2_6 0xB004 50 #define DXGKDDI_INTERFACE_VERSION_WDDM2_7 0xC004 51 #define DXGKDDI_INTERFACE_VERSION_WDDM2_8 0xD001 52 #define DXGKDDI_INTERFACE_VERSION_WDDM2_9 0xE003 53 #define DXGKDDI_INTERFACE_VERSION_WDDM3_0 0xF003 54 55 56 #define IS_OFFICIAL_DDI_INTERFACE_VERSION(version) \ 57 (((version) == DXGKDDI_INTERFACE_VERSION_VISTA) || \ 58 ((version) == DXGKDDI_INTERFACE_VERSION_VISTA_SP1) || \ 59 ((version) == DXGKDDI_INTERFACE_VERSION_WIN7) || \ 60 ((version) == DXGKDDI_INTERFACE_VERSION_WIN8) || \ 61 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM1_3) || \ 62 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION) || \ 63 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_0) || \ 64 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_1) || \ 65 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_1_5) || \ 66 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_1_6) || \ 67 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_2) || \ 68 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_3) || \ 69 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_4) || \ 70 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_5) || \ 71 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_6) || \ 72 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_7) || \ 73 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_8) || \ 74 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM2_9) || \ 75 ((version) == DXGKDDI_INTERFACE_VERSION_WDDM3_0) \ 76 ) 77 78 #if !defined(DXGKDDI_INTERFACE_VERSION) 79 #define DXGKDDI_INTERFACE_VERSION DXGKDDI_INTERFACE_VERSION_WDDM3_0 80 #endif // !defined(DXGKDDI_INTERFACE_VERSION) 81 82 #define D3D_UMD_INTERFACE_VERSION_VISTA 0x000C 83 #define D3D_UMD_INTERFACE_VERSION_WIN7 0x2003 84 #define D3D_UMD_INTERFACE_VERSION_WIN8_M3 0x3001 85 #define D3D_UMD_INTERFACE_VERSION_WIN8_CP 0x3002 86 #define D3D_UMD_INTERFACE_VERSION_WIN8_RC 0x3003 87 #define D3D_UMD_INTERFACE_VERSION_WIN8 0x3004 88 #define D3D_UMD_INTERFACE_VERSION_WDDM1_3 0x4002 89 90 #define D3D_UMD_INTERFACE_VERSION_WDDM2_0_M1 0x5000 91 #define D3D_UMD_INTERFACE_VERSION_WDDM2_0_M1_3 0x5001 92 #define D3D_UMD_INTERFACE_VERSION_WDDM2_0_M2_2 0x5002 93 #define D3D_UMD_INTERFACE_VERSION_WDDM2_0 0x5002 94 95 #define D3D_UMD_INTERFACE_VERSION_WDDM2_1_1 0x6000 96 #define D3D_UMD_INTERFACE_VERSION_WDDM2_1_2 0x6001 97 #define D3D_UMD_INTERFACE_VERSION_WDDM2_1_3 0x6002 98 #define D3D_UMD_INTERFACE_VERSION_WDDM2_1_4 0x6003 99 #define D3D_UMD_INTERFACE_VERSION_WDDM2_1 D3D_UMD_INTERFACE_VERSION_WDDM2_1_4 100 101 #define D3D_UMD_INTERFACE_VERSION_WDDM2_2_1 0x7000 102 #define D3D_UMD_INTERFACE_VERSION_WDDM2_2_2 0x7001 103 #define D3D_UMD_INTERFACE_VERSION_WDDM2_2 D3D_UMD_INTERFACE_VERSION_WDDM2_2_2 104 105 #define D3D_UMD_INTERFACE_VERSION_WDDM2_3_1 0x8000 106 #define D3D_UMD_INTERFACE_VERSION_WDDM2_3_2 0x8001 107 #define D3D_UMD_INTERFACE_VERSION_WDDM2_3 D3D_UMD_INTERFACE_VERSION_WDDM2_3_2 108 109 #define D3D_UMD_INTERFACE_VERSION_WDDM2_4_1 0x9000 110 #define D3D_UMD_INTERFACE_VERSION_WDDM2_4_2 0x9001 111 #define D3D_UMD_INTERFACE_VERSION_WDDM2_4 D3D_UMD_INTERFACE_VERSION_WDDM2_4_2 112 113 #define D3D_UMD_INTERFACE_VERSION_WDDM2_5_1 0xA000 114 #define D3D_UMD_INTERFACE_VERSION_WDDM2_5_2 0xA001 115 #define D3D_UMD_INTERFACE_VERSION_WDDM2_5_3 0xA002 116 #define D3D_UMD_INTERFACE_VERSION_WDDM2_5 D3D_UMD_INTERFACE_VERSION_WDDM2_5_3 117 118 #define D3D_UMD_INTERFACE_VERSION_WDDM2_6_1 0xB000 119 #define D3D_UMD_INTERFACE_VERSION_WDDM2_6_2 0xB001 120 #define D3D_UMD_INTERFACE_VERSION_WDDM2_6_3 0xB002 121 #define D3D_UMD_INTERFACE_VERSION_WDDM2_6_4 0xB003 122 #define D3D_UMD_INTERFACE_VERSION_WDDM2_6 D3D_UMD_INTERFACE_VERSION_WDDM2_6_4 123 124 #define D3D_UMD_INTERFACE_VERSION_WDDM2_7_1 0xC000 125 #define D3D_UMD_INTERFACE_VERSION_WDDM2_7_2 0xC001 126 #define D3D_UMD_INTERFACE_VERSION_WDDM2_7 D3D_UMD_INTERFACE_VERSION_WDDM2_7_2 127 128 #define D3D_UMD_INTERFACE_VERSION_WDDM2_8_1 0xD000 129 #define D3D_UMD_INTERFACE_VERSION_WDDM2_8 D3D_UMD_INTERFACE_VERSION_WDDM2_8_1 130 131 #define D3D_UMD_INTERFACE_VERSION_WDDM2_9_1 0xE000 132 #define D3D_UMD_INTERFACE_VERSION_WDDM2_9 D3D_UMD_INTERFACE_VERSION_WDDM2_9_1 133 134 #define D3D_UMD_INTERFACE_VERSION_WDDM3_0_1 0xF000 135 #define D3D_UMD_INTERFACE_VERSION_WDDM3_0 D3D_UMD_INTERFACE_VERSION_WDDM3_0_1 136 137 // Components which depend on D3D_UMD_INTERFACE_VERSION need to be updated, static assert validation present. 138 // Search for D3D_UMD_INTERFACE_VERSION across all depots to ensure all dependencies are updated. 139 140 #if !defined(D3D_UMD_INTERFACE_VERSION) 141 #define D3D_UMD_INTERFACE_VERSION D3D_UMD_INTERFACE_VERSION_WDDM3_0 142 #endif // !defined(D3D_UMD_INTERFACE_VERSION) 143 144 // 145 // These macros are used to enable non-Windows 32-bit usermode to fill out a fixed-size 146 // structure for D3DKMT structures, so that they can be sent to a 64-bit kernel 147 // without a thunking layer for translation. 148 // 149 // Note that a thunking layer is still used for wchar_t translation, where Windows uses 150 // 16-bit characters and non-Windows uses 32-bit characters. 151 // 152 // If brace initialization is used (e.g. D3DKMT_FOO foo = { a, b, c }), be aware that for 153 // non-Windows, pointers will be unioned such that a 64-bit integer is the member that is 154 // initialized. It is not possible to achieve both type safety and proper zero-initialization 155 // of the high bits of pointers with brace initialization in this model. Use D3DKMT_PTR_INIT(ptr) 156 // to appropriately cast to a 64-bit integer for non-Windows, or to pass the pointer unchanged for 157 // Windows. To maintain type safety, manually assign the fields after zero-initializing the struct. 158 // 159 #ifdef _WIN32 160 // For Windows, don't enforce any unnatural alignment or data sizes/types. 161 // The WOW64 thunking layer will handle translation. 162 #define D3DKMT_ALIGN64 163 #define D3DKMT_PTR_HELPER(Name) 164 #define D3DKMT_PTR(Type, Name) Type Name 165 #define D3DKMT_PTR_INIT(x) (x) 166 typedef SIZE_T D3DKMT_SIZE_T; 167 typedef UINT_PTR D3DKMT_UINT_PTR; 168 typedef ULONG_PTR D3DKMT_ULONG_PTR; 169 typedef HANDLE D3DKMT_PTR_TYPE; 170 #else 171 // For other platforms, struct layout should be fixed-size, x64-compatible 172 #if __cplusplus >= 201103L 173 #define D3DKMT_ALIGN64 alignas(8) 174 #else 175 #define D3DKMT_ALIGN64 __attribute__((aligned(8))) 176 #endif 177 #define D3DKMT_PTR_HELPER(Name) D3DKMT_ALIGN64 UINT64 Name; 178 #define D3DKMT_PTR(Type, Name) \ 179 union D3DKMT_ALIGN64 \ 180 { \ 181 D3DKMT_PTR_HELPER(Name##_Align) \ 182 Type Name; \ 183 } 184 #define D3DKMT_PTR_INIT(x) { (UINT64)(SIZE_T)(x) } 185 typedef UINT64 D3DKMT_SIZE_T, D3DKMT_UINT_PTR, D3DKMT_ULONG_PTR; 186 typedef union _D3DKMT_PTR_TYPE 187 { 188 D3DKMT_PTR_HELPER(Ptr_Align); 189 HANDLE Ptr; 190 } D3DKMT_PTR_TYPE; 191 #endif 192 193 // 194 // Available only for Vista (LONGHORN) and later and for 195 // multiplatform tools such as debugger extensions 196 // 197 #if (NTDDI_VERSION >= NTDDI_LONGHORN) || defined(D3DKMDT_SPECIAL_MULTIPLATFORM_TOOL) 198 199 typedef ULONGLONG D3DGPU_VIRTUAL_ADDRESS; 200 typedef ULONGLONG D3DGPU_SIZE_T; 201 #define D3DGPU_UNIQUE_DRIVER_PROTECTION 0x8000000000000000ULL 202 203 #define DXGK_MAX_PAGE_TABLE_LEVEL_COUNT 6 204 #define DXGK_MIN_PAGE_TABLE_LEVEL_COUNT 2 205 206 // 207 // IOCTL_GPUP_DRIVER_ESCAPE - The user mode emulation DLL calls this IOCTL 208 // to exchange information with the kernel mode driver. 209 // 210 #define IOCTL_GPUP_DRIVER_ESCAPE CTL_CODE(FILE_DEVICE_UNKNOWN, (8 + 0x910), METHOD_BUFFERED, FILE_READ_DATA) 211 typedef struct _GPUP_DRIVER_ESCAPE_INPUT 212 { 213 LUID vfLUID; //LUID that was returned from SET_PARTITION_DETAILS 214 } GPUP_DRIVER_ESCAPE_INPUT, *PGPUP_DRIVER_ESCAPE_INPUT; 215 216 typedef enum _DXGKVGPU_ESCAPE_TYPE 217 { 218 DXGKVGPU_ESCAPE_TYPE_READ_PCI_CONFIG = 0, 219 DXGKVGPU_ESCAPE_TYPE_WRITE_PCI_CONFIG = 1, 220 DXGKVGPU_ESCAPE_TYPE_INITIALIZE = 2, 221 DXGKVGPU_ESCAPE_TYPE_RELEASE = 3, 222 DXGKVGPU_ESCAPE_TYPE_GET_VGPU_TYPE = 4, 223 DXGKVGPU_ESCAPE_TYPE_POWERTRANSITIONCOMPLETE = 5, 224 } DXGKVGPU_ESCAPE_TYPE; 225 226 typedef struct _DXGKVGPU_ESCAPE_HEAD 227 { 228 GPUP_DRIVER_ESCAPE_INPUT Luid; 229 DXGKVGPU_ESCAPE_TYPE Type; 230 } DXGKVGPU_ESCAPE_HEAD; 231 232 typedef struct _DXGKVGPU_ESCAPE_READ_PCI_CONFIG 233 { 234 DXGKVGPU_ESCAPE_HEAD Header; 235 236 UINT Offset; // Offset in bytes in the PCI config space 237 UINT Size; // Size in bytes to read 238 } DXGKVGPU_ESCAPE_READ_PCI_CONFIG; 239 240 typedef struct _DXGKVGPU_ESCAPE_WRITE_PCI_CONFIG 241 { 242 DXGKVGPU_ESCAPE_HEAD Header; 243 244 UINT Offset; // Offset in bytes in the PCI config space 245 UINT Size; // Size in bytes to write 246 // "Size" number of bytes follow 247 } DXGKVGPU_ESCAPE_WRITE_PCI_CONFIG; 248 249 typedef struct _DXGKVGPU_ESCAPE_READ_VGPU_TYPE 250 { 251 DXGKVGPU_ESCAPE_HEAD Header; 252 } DXGKVGPU_ESCAPE_READ_VGPU_TYPE; 253 254 typedef struct _DXGKVGPU_ESCAPE_POWERTRANSITIONCOMPLETE 255 { 256 DXGKVGPU_ESCAPE_HEAD Header; 257 UINT PowerState; 258 } DXGKVGPU_ESCAPE_POWERTRANSITIONCOMPLETE; 259 260 typedef struct _DXGKVGPU_ESCAPE_INITIALIZE 261 { 262 DXGKVGPU_ESCAPE_HEAD Header; 263 GUID VmGuid; 264 } DXGKVGPU_ESCAPE_INITIALIZE; 265 266 typedef struct _DXGKVGPU_ESCAPE_RELEASE 267 { 268 DXGKVGPU_ESCAPE_HEAD Header; 269 } DXGKVGPU_ESCAPE_RELEASE; 270 271 272 typedef enum _DXGK_PTE_PAGE_SIZE 273 { 274 DXGK_PTE_PAGE_TABLE_PAGE_4KB = 0, 275 DXGK_PTE_PAGE_TABLE_PAGE_64KB = 1, 276 } DXGK_PTE_PAGE_SIZE; 277 278 // 279 // Page Table Entry structure. Contains segment/physical address pointing to a page 280 // 281 282 typedef struct _DXGK_PTE 283 { 284 union 285 { 286 struct 287 { 288 ULONGLONG Valid : 1; 289 ULONGLONG Zero : 1; 290 ULONGLONG CacheCoherent : 1; 291 ULONGLONG ReadOnly : 1; 292 ULONGLONG NoExecute : 1; 293 ULONGLONG Segment : 5; 294 ULONGLONG LargePage : 1; 295 ULONGLONG PhysicalAdapterIndex : 6; 296 ULONGLONG PageTablePageSize : 2; // DXGK_PTE_PAGE_SIZE 297 ULONGLONG SystemReserved0 : 1; 298 ULONGLONG Reserved : 44; 299 }; 300 ULONGLONG Flags; 301 }; 302 union 303 { 304 ULONGLONG PageAddress; // High 52 bits of 64 bit physical address. Low 12 bits are zero. 305 ULONGLONG PageTableAddress; // High 52 bits of 64 bit physical address. Low 12 bits are zero. 306 }; 307 } DXGK_PTE; 308 309 #define D3DGPU_NULL 0 310 #define D3DDDI_MAX_WRITTEN_PRIMARIES 16 311 #define D3DDDI_MAX_MPO_PRESENT_DIRTY_RECTS 0xFFF 312 313 typedef struct _D3DGPU_PHYSICAL_ADDRESS 314 { 315 UINT SegmentId; 316 UINT Padding; 317 UINT64 SegmentOffset; 318 } D3DGPU_PHYSICAL_ADDRESS; 319 320 ///////////////////////////////////////////////////////////////////////////////////////////////////////////// 321 // Purpose: Video present source unique identification number descriptor type 322 // 323 324 typedef UINT D3DDDI_VIDEO_PRESENT_SOURCE_ID; 325 326 ///////////////////////////////////////////////////////////////////////////////////////////////////////////// 327 // Purpose: Video present source unique identification number descriptor type. 328 // 329 typedef UINT D3DDDI_VIDEO_PRESENT_TARGET_ID; 330 331 // 332 // DDI level handle that represents a kernel mode object (allocation, device, etc) 333 // 334 typedef UINT D3DKMT_HANDLE; 335 336 ///////////////////////////////////////////////////////////////////////////////////////////////////////////// 337 // Purpose: Video present target mode fractional frequency descriptor type. 338 // 339 // Remarks: Fractional value used to represent vertical and horizontal frequencies of a video mode 340 // (i.e. VSync and HSync). Vertical frequencies are stored in Hz. Horizontal frequencies 341 // are stored in Hz. 342 // The dynamic range of this encoding format, given 10^-7 resolution is {0..(2^32 - 1) / 10^7}, 343 // which translates to {0..428.4967296} [Hz] for vertical frequencies and {0..428.4967296} [Hz] 344 // for horizontal frequencies. This sub-microseconds precision range should be acceptable even 345 // for a pro-video application (error in one microsecond for video signal synchronization would 346 // imply a time drift with a cycle of 10^7/(60*60*24) = 115.741 days. 347 // 348 // If rational number with a finite fractional sequence, use denominator of form 10^(length of fractional sequence). 349 // If rational number without a finite fractional sequence, or a sequence exceeding the precision allowed by the 350 // dynamic range of the denominator, or an irrational number, use an appropriate ratio of integers which best 351 // represents the value. 352 // 353 typedef struct _D3DDDI_RATIONAL 354 { 355 UINT Numerator; 356 UINT Denominator; 357 } D3DDDI_RATIONAL; 358 359 typedef struct _D3DDDI_ALLOCATIONINFO 360 { 361 D3DKMT_HANDLE hAllocation; // out: Private driver data for allocation 362 D3DKMT_PTR(CONST VOID*, pSystemMem); // in: Pointer to pre-allocated sysmem 363 D3DKMT_PTR(VOID*, pPrivateDriverData); // in(out optional): Private data for each allocation 364 UINT PrivateDriverDataSize; // in: Size of the private data 365 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId; // in: VidPN source ID if this is a primary 366 union 367 { 368 struct 369 { 370 UINT Primary : 1; // 0x00000001 371 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) || \ 372 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WIN8)) 373 UINT Stereo : 1; // 0x00000002 374 UINT Reserved :30; // 0xFFFFFFFC 375 #else 376 UINT Reserved :31; // 0xFFFFFFFE 377 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) 378 }; 379 UINT Value; 380 } Flags; 381 } D3DDDI_ALLOCATIONINFO; 382 383 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN7) || \ 384 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WIN7)) 385 386 typedef struct _D3DDDI_ALLOCATIONINFO2 387 { 388 D3DKMT_HANDLE hAllocation; // out: Private driver data for allocation 389 union D3DKMT_ALIGN64 390 { 391 D3DKMT_PTR_HELPER(pSystemMem_hSection_Align) 392 HANDLE hSection; // in: Handle to valid section object 393 CONST VOID* pSystemMem; // in: Pointer to pre-allocated sysmem 394 }; 395 D3DKMT_PTR(VOID*, pPrivateDriverData); // in(out optional): Private data for each allocation 396 UINT PrivateDriverDataSize; // in: Size of the private data 397 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId; // in: VidPN source ID if this is a primary 398 union 399 { 400 struct 401 { 402 UINT Primary : 1; // 0x00000001 403 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) || \ 404 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WIN8)) 405 UINT Stereo : 1; // 0x00000002 406 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2) || \ 407 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_2)) 408 UINT OverridePriority : 1; // 0x00000004 409 UINT Reserved : 29; // 0xFFFFFFF8 410 #else 411 UINT Reserved : 30; // 0xFFFFFFFC 412 #endif 413 #else 414 UINT Reserved :31; // 0xFFFFFFFE 415 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) 416 }; 417 UINT Value; 418 } Flags; 419 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS GpuVirtualAddress; // out: GPU Virtual address of the allocation created. 420 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2) || \ 421 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_2)) 422 union 423 { 424 UINT Priority; // in: priority of allocation 425 D3DKMT_ALIGN64 ULONG_PTR Unused; 426 }; 427 D3DKMT_ALIGN64 ULONG_PTR Reserved[5]; // Reserved 428 #else 429 D3DKMT_ALIGN64 ULONG_PTR Reserved[6]; // Reserved 430 #endif 431 } D3DDDI_ALLOCATIONINFO2; 432 433 #endif 434 435 typedef struct _D3DDDI_OPENALLOCATIONINFO 436 { 437 D3DKMT_HANDLE hAllocation; // in: Handle for this allocation in this process 438 D3DKMT_PTR(CONST VOID*, pPrivateDriverData); // in: Ptr to driver private buffer for this allocations 439 UINT PrivateDriverDataSize; // in: Size in bytes of driver private buffer for this allocations 440 441 } D3DDDI_OPENALLOCATIONINFO; 442 443 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN7) || \ 444 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WIN7)) 445 446 typedef struct _D3DDDI_OPENALLOCATIONINFO2 447 { 448 D3DKMT_HANDLE hAllocation; // in: Handle for this allocation in this process 449 D3DKMT_PTR(CONST VOID*, pPrivateDriverData);// in: Ptr to driver private buffer for this allocations 450 UINT PrivateDriverDataSize; // in: Size in bytes of driver private buffer for this allocations 451 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS GpuVirtualAddress; // out: GPU Virtual address of the allocation opened. 452 D3DKMT_ALIGN64 ULONG_PTR Reserved[6]; // Reserved 453 } D3DDDI_OPENALLOCATIONINFO2; 454 455 #endif 456 457 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) || \ 458 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WIN8)) 459 460 typedef enum _D3DDDI_OFFER_PRIORITY 461 { 462 D3DDDI_OFFER_PRIORITY_NONE=0, // Do not offer 463 D3DDDI_OFFER_PRIORITY_LOW=1, // Content is not useful 464 D3DDDI_OFFER_PRIORITY_NORMAL, // Content is useful but easy to regenerate 465 D3DDDI_OFFER_PRIORITY_HIGH, // Content is useful and difficult to regenerate 466 D3DDDI_OFFER_PRIORITY_AUTO, // Let VidMm decide offer priority based on eviction priority 467 } D3DDDI_OFFER_PRIORITY; 468 469 #endif 470 471 typedef struct _D3DDDI_ALLOCATIONLIST 472 { 473 D3DKMT_HANDLE hAllocation; 474 union 475 { 476 struct 477 { 478 UINT WriteOperation : 1; // 0x00000001 479 UINT DoNotRetireInstance : 1; // 0x00000002 480 481 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) || \ 482 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WIN8)) 483 UINT OfferPriority : 3; // 0x0000001C D3DDDI_OFFER_PRIORITY 484 UINT Reserved :27; // 0xFFFFFFE0 485 #else 486 UINT Reserved :30; // 0xFFFFFFFC 487 #endif 488 }; 489 UINT Value; 490 }; 491 } D3DDDI_ALLOCATIONLIST; 492 493 typedef struct _D3DDDI_PATCHLOCATIONLIST 494 { 495 UINT AllocationIndex; 496 union 497 { 498 struct 499 { 500 UINT SlotId : 24; // 0x00FFFFFF 501 UINT Reserved : 8; // 0xFF000000 502 }; 503 UINT Value; 504 }; 505 UINT DriverId; 506 UINT AllocationOffset; 507 UINT PatchOffset; 508 UINT SplitOffset; 509 } D3DDDI_PATCHLOCATIONLIST; 510 511 typedef struct _D3DDDICB_LOCKFLAGS 512 { 513 union 514 { 515 struct 516 { 517 UINT ReadOnly : 1; // 0x00000001 518 UINT WriteOnly : 1; // 0x00000002 519 UINT DonotWait : 1; // 0x00000004 520 UINT IgnoreSync : 1; // 0x00000008 521 UINT LockEntire : 1; // 0x00000010 522 UINT DonotEvict : 1; // 0x00000020 523 UINT AcquireAperture : 1; // 0x00000040 524 UINT Discard : 1; // 0x00000080 525 UINT NoExistingReference : 1; // 0x00000100 526 UINT UseAlternateVA : 1; // 0x00000200 527 UINT IgnoreReadSync : 1; // 0x00000400 528 UINT Reserved :21; // 0xFFFFF800 529 }; 530 UINT Value; 531 }; 532 } D3DDDICB_LOCKFLAGS; 533 534 typedef struct _D3DDDICB_LOCK2FLAGS 535 { 536 union 537 { 538 struct 539 { 540 UINT Reserved : 32; // 0xFFFFFFFF 541 }; 542 UINT Value; 543 }; 544 } D3DDDICB_LOCK2FLAGS; 545 546 typedef struct _D3DDDICB_DESTROYALLOCATION2FLAGS 547 { 548 union 549 { 550 struct 551 { 552 UINT AssumeNotInUse : 1; // 0x00000001 553 UINT SynchronousDestroy : 1; // 0x00000002 554 UINT Reserved : 29; // 0x7FFFFFFC 555 UINT SystemUseOnly : 1; // 0x80000000 // Should not be set by the UMD 556 }; 557 UINT Value; 558 }; 559 } D3DDDICB_DESTROYALLOCATION2FLAGS; 560 561 typedef struct _D3DDDI_ESCAPEFLAGS 562 { 563 union 564 { 565 struct 566 { 567 UINT HardwareAccess : 1; // 0x00000001 568 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3) || \ 569 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM1_3)) 570 UINT DeviceStatusQuery : 1; // 0x00000002 571 UINT ChangeFrameLatency : 1; // 0x00000004 572 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) 573 UINT NoAdapterSynchronization : 1; // 0x00000008 574 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2) 575 UINT Reserved : 1; // 0x00000010 Used internally by DisplayOnly present 576 UINT VirtualMachineData : 1; // 0x00000020 Cannot be set from user mode 577 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5) 578 UINT DriverKnownEscape : 1; // 0x00000040 // Driver private data points to a well known structure 579 UINT DriverCommonEscape : 1; // 0x00000080 // Private data points runtime defined structure 580 UINT Reserved2 :24; // 0xFFFFFF00 581 #else // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5) 582 UINT Reserved2 :26; // 0xFFFFFFC0 583 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5) 584 #else 585 UINT Reserved :28; // 0xFFFFFFF0 586 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2) 587 #else 588 UINT Reserved :29; // 0xFFFFFFF8 589 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) 590 #else 591 UINT Reserved :31; // 0xFFFFFFFE 592 #endif // WDDM1_3 593 }; 594 UINT Value; 595 }; 596 } D3DDDI_ESCAPEFLAGS; 597 598 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5) 599 600 typedef enum _D3DDDI_DRIVERESCAPETYPE 601 { 602 D3DDDI_DRIVERESCAPETYPE_TRANSLATEALLOCATIONHANDLE = 0, 603 D3DDDI_DRIVERESCAPETYPE_TRANSLATERESOURCEHANDLE = 1, 604 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM3_0) 605 D3DDDI_DRIVERESCAPETYPE_CPUEVENTUSAGE = 2, 606 #endif 607 D3DDDI_DRIVERESCAPETYPE_MAX, 608 } D3DDDI_DRIVERESCAPETYPE; 609 610 typedef struct _D3DDDI_DRIVERESCAPE_TRANSLATEALLOCATIONEHANDLE 611 { 612 D3DDDI_DRIVERESCAPETYPE EscapeType; 613 D3DKMT_HANDLE hAllocation; 614 } D3DDDI_DRIVERESCAPE_TRANSLATEALLOCATIONEHANDLE; 615 616 typedef struct _D3DDDI_DRIVERESCAPE_TRANSLATERESOURCEHANDLE 617 { 618 D3DDDI_DRIVERESCAPETYPE EscapeType; 619 D3DKMT_HANDLE hResource; 620 } D3DDDI_DRIVERESCAPE_TRANSLATERESOURCEHANDLE; 621 622 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5) 623 624 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM3_0) 625 626 typedef struct _D3DDDI_DRIVERESCAPE_CPUEVENTUSAGE 627 { 628 D3DDDI_DRIVERESCAPETYPE EscapeType; 629 D3DKMT_HANDLE hSyncObject; 630 D3DKMT_ALIGN64 UINT64 hKmdCpuEvent; 631 UINT Usage[8]; 632 } D3DDDI_DRIVERESCAPE_CPUEVENTUSAGE; 633 634 #endif 635 636 typedef struct _D3DDDI_CREATECONTEXTFLAGS 637 { 638 union 639 { 640 struct 641 { 642 UINT NullRendering : 1; // 0x00000001 643 UINT InitialData : 1; // 0x00000002 644 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) || \ 645 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_0)) 646 UINT DisableGpuTimeout : 1; // 0x00000004 647 UINT SynchronizationOnly : 1; // 0x00000008 648 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_3) || \ 649 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_3_1)) 650 UINT HwQueueSupported : 1; // 0x00000010 651 UINT NoKmdAccess : 1; // 0x00000020 652 UINT Reserved :26; // 0xFFFFFFC0 653 #else 654 UINT Reserved :28; // 0xFFFFFFF0 655 #endif // DXGKDDI_INTERFACE_VERSION 656 657 #else 658 UINT Reserved :30; // 0xFFFFFFFC 659 #endif // DXGKDDI_INTERFACE_VERSION 660 }; 661 UINT Value; 662 }; 663 } D3DDDI_CREATECONTEXTFLAGS; 664 665 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2) || \ 666 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_2_1)) 667 668 typedef struct _D3DDDI_CREATEHWCONTEXTFLAGS 669 { 670 union 671 { 672 struct 673 { 674 UINT Reserved :32; // 0xFFFFFFFF 675 }; 676 UINT Value; 677 }; 678 } D3DDDI_CREATEHWCONTEXTFLAGS; 679 680 typedef struct _D3DDDI_CREATEHWQUEUEFLAGS 681 { 682 union 683 { 684 struct 685 { 686 UINT DisableGpuTimeout : 1; // 0x00000001 687 UINT NoBroadcastSignal : 1; // 0x00000002 688 UINT NoBroadcastWait : 1; // 0x00000004 689 UINT NoKmdAccess : 1; // 0x00000008 690 UINT Reserved :28; // 0xFFFFFFF0 691 }; 692 UINT Value; 693 }; 694 } D3DDDI_CREATEHWQUEUEFLAGS; 695 696 #endif // ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2) 697 698 typedef struct _D3DDDI_SEGMENTPREFERENCE 699 { 700 union 701 { 702 struct 703 { 704 UINT SegmentId0 : 5; // 0x0000001F 705 UINT Direction0 : 1; // 0x00000020 706 UINT SegmentId1 : 5; // 0x000007C0 707 UINT Direction1 : 1; // 0x00000800 708 UINT SegmentId2 : 5; // 0x0001F000 709 UINT Direction2 : 1; // 0x00020000 710 UINT SegmentId3 : 5; // 0x007C0000 711 UINT Direction3 : 1; // 0x00800000 712 UINT SegmentId4 : 5; // 0x1F000000 713 UINT Direction4 : 1; // 0x20000000 714 UINT Reserved : 2; // 0xC0000000 715 }; 716 UINT Value; 717 }; 718 } D3DDDI_SEGMENTPREFERENCE; 719 720 /* Formats 721 * Most of these names have the following convention: 722 * A = Alpha 723 * R = Red 724 * G = Green 725 * B = Blue 726 * X = Unused Bits 727 * P = Palette 728 * L = Luminance 729 * U = dU coordinate for BumpMap 730 * V = dV coordinate for BumpMap 731 * S = Stencil 732 * D = Depth (e.g. Z or W buffer) 733 * C = Computed from other channels (typically on certain read operations) 734 * 735 * Further, the order of the pieces are from MSB first; hence 736 * D3DFMT_A8L8 indicates that the high byte of this two byte 737 * format is alpha. 738 * 739 * D16 indicates: 740 * - An integer 16-bit value. 741 * - An app-lockable surface. 742 * 743 * All Depth/Stencil formats except D3DFMT_D16_LOCKABLE indicate: 744 * - no particular bit ordering per pixel, and 745 * - are not app lockable, and 746 * - the driver is allowed to consume more than the indicated 747 * number of bits per Depth channel (but not Stencil channel). 748 */ 749 #ifndef MAKEFOURCC 750 #define MAKEFOURCC(ch0, ch1, ch2, ch3) \ 751 ((DWORD)(BYTE)(ch0) | ((DWORD)(BYTE)(ch1) << 8) | \ 752 ((DWORD)(BYTE)(ch2) << 16) | ((DWORD)(BYTE)(ch3) << 24 )) 753 #endif /* defined(MAKEFOURCC) */ 754 755 756 typedef enum _D3DDDIFORMAT 757 { 758 759 D3DDDIFMT_UNKNOWN = 0, 760 761 D3DDDIFMT_R8G8B8 = 20, 762 D3DDDIFMT_A8R8G8B8 = 21, 763 D3DDDIFMT_X8R8G8B8 = 22, 764 D3DDDIFMT_R5G6B5 = 23, 765 D3DDDIFMT_X1R5G5B5 = 24, 766 D3DDDIFMT_A1R5G5B5 = 25, 767 D3DDDIFMT_A4R4G4B4 = 26, 768 D3DDDIFMT_R3G3B2 = 27, 769 D3DDDIFMT_A8 = 28, 770 D3DDDIFMT_A8R3G3B2 = 29, 771 D3DDDIFMT_X4R4G4B4 = 30, 772 D3DDDIFMT_A2B10G10R10 = 31, 773 D3DDDIFMT_A8B8G8R8 = 32, 774 D3DDDIFMT_X8B8G8R8 = 33, 775 D3DDDIFMT_G16R16 = 34, 776 D3DDDIFMT_A2R10G10B10 = 35, 777 D3DDDIFMT_A16B16G16R16 = 36, 778 779 D3DDDIFMT_A8P8 = 40, 780 D3DDDIFMT_P8 = 41, 781 782 D3DDDIFMT_L8 = 50, 783 D3DDDIFMT_A8L8 = 51, 784 D3DDDIFMT_A4L4 = 52, 785 786 D3DDDIFMT_V8U8 = 60, 787 D3DDDIFMT_L6V5U5 = 61, 788 D3DDDIFMT_X8L8V8U8 = 62, 789 D3DDDIFMT_Q8W8V8U8 = 63, 790 D3DDDIFMT_V16U16 = 64, 791 D3DDDIFMT_W11V11U10 = 65, 792 D3DDDIFMT_A2W10V10U10 = 67, 793 794 D3DDDIFMT_UYVY = MAKEFOURCC('U', 'Y', 'V', 'Y'), 795 D3DDDIFMT_R8G8_B8G8 = MAKEFOURCC('R', 'G', 'B', 'G'), 796 D3DDDIFMT_YUY2 = MAKEFOURCC('Y', 'U', 'Y', '2'), 797 D3DDDIFMT_G8R8_G8B8 = MAKEFOURCC('G', 'R', 'G', 'B'), 798 D3DDDIFMT_DXT1 = MAKEFOURCC('D', 'X', 'T', '1'), 799 D3DDDIFMT_DXT2 = MAKEFOURCC('D', 'X', 'T', '2'), 800 D3DDDIFMT_DXT3 = MAKEFOURCC('D', 'X', 'T', '3'), 801 D3DDDIFMT_DXT4 = MAKEFOURCC('D', 'X', 'T', '4'), 802 D3DDDIFMT_DXT5 = MAKEFOURCC('D', 'X', 'T', '5'), 803 804 D3DDDIFMT_D16_LOCKABLE = 70, 805 D3DDDIFMT_D32 = 71, 806 D3DDDIFMT_D15S1 = 73, 807 D3DDDIFMT_D24S8 = 75, 808 D3DDDIFMT_D24X8 = 77, 809 D3DDDIFMT_D24X4S4 = 79, 810 D3DDDIFMT_D16 = 80, 811 812 D3DDDIFMT_D32F_LOCKABLE = 82, 813 D3DDDIFMT_D24FS8 = 83, 814 815 D3DDDIFMT_D32_LOCKABLE = 84, 816 D3DDDIFMT_S8_LOCKABLE = 85, 817 818 D3DDDIFMT_S1D15 = 72, 819 D3DDDIFMT_S8D24 = 74, 820 D3DDDIFMT_X8D24 = 76, 821 D3DDDIFMT_X4S4D24 = 78, 822 823 D3DDDIFMT_L16 = 81, 824 #if (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM1_3) // M1 825 D3DDDIFMT_G8R8 = 91, 826 D3DDDIFMT_R8 = 92, 827 #endif 828 829 D3DDDIFMT_VERTEXDATA =100, 830 D3DDDIFMT_INDEX16 =101, 831 D3DDDIFMT_INDEX32 =102, 832 833 D3DDDIFMT_Q16W16V16U16 =110, 834 835 D3DDDIFMT_MULTI2_ARGB8 = MAKEFOURCC('M','E','T','1'), 836 837 // Floating point surface formats 838 839 // s10e5 formats (16-bits per channel) 840 D3DDDIFMT_R16F = 111, 841 D3DDDIFMT_G16R16F = 112, 842 D3DDDIFMT_A16B16G16R16F = 113, 843 844 // IEEE s23e8 formats (32-bits per channel) 845 D3DDDIFMT_R32F = 114, 846 D3DDDIFMT_G32R32F = 115, 847 D3DDDIFMT_A32B32G32R32F = 116, 848 849 D3DDDIFMT_CxV8U8 = 117, 850 851 // Monochrome 1 bit per pixel format 852 D3DDDIFMT_A1 = 118, 853 854 // 2.8 biased fixed point 855 D3DDDIFMT_A2B10G10R10_XR_BIAS = 119, 856 857 // Decode compressed buffer formats 858 D3DDDIFMT_DXVACOMPBUFFER_BASE = 150, 859 D3DDDIFMT_PICTUREPARAMSDATA = D3DDDIFMT_DXVACOMPBUFFER_BASE+0, // 150 860 D3DDDIFMT_MACROBLOCKDATA = D3DDDIFMT_DXVACOMPBUFFER_BASE+1, // 151 861 D3DDDIFMT_RESIDUALDIFFERENCEDATA = D3DDDIFMT_DXVACOMPBUFFER_BASE+2, // 152 862 D3DDDIFMT_DEBLOCKINGDATA = D3DDDIFMT_DXVACOMPBUFFER_BASE+3, // 153 863 D3DDDIFMT_INVERSEQUANTIZATIONDATA = D3DDDIFMT_DXVACOMPBUFFER_BASE+4, // 154 864 D3DDDIFMT_SLICECONTROLDATA = D3DDDIFMT_DXVACOMPBUFFER_BASE+5, // 155 865 D3DDDIFMT_BITSTREAMDATA = D3DDDIFMT_DXVACOMPBUFFER_BASE+6, // 156 866 D3DDDIFMT_MOTIONVECTORBUFFER = D3DDDIFMT_DXVACOMPBUFFER_BASE+7, // 157 867 D3DDDIFMT_FILMGRAINBUFFER = D3DDDIFMT_DXVACOMPBUFFER_BASE+8, // 158 868 D3DDDIFMT_DXVA_RESERVED9 = D3DDDIFMT_DXVACOMPBUFFER_BASE+9, // 159 869 D3DDDIFMT_DXVA_RESERVED10 = D3DDDIFMT_DXVACOMPBUFFER_BASE+10, // 160 870 D3DDDIFMT_DXVA_RESERVED11 = D3DDDIFMT_DXVACOMPBUFFER_BASE+11, // 161 871 D3DDDIFMT_DXVA_RESERVED12 = D3DDDIFMT_DXVACOMPBUFFER_BASE+12, // 162 872 D3DDDIFMT_DXVA_RESERVED13 = D3DDDIFMT_DXVACOMPBUFFER_BASE+13, // 163 873 D3DDDIFMT_DXVA_RESERVED14 = D3DDDIFMT_DXVACOMPBUFFER_BASE+14, // 164 874 D3DDDIFMT_DXVA_RESERVED15 = D3DDDIFMT_DXVACOMPBUFFER_BASE+15, // 165 875 D3DDDIFMT_DXVA_RESERVED16 = D3DDDIFMT_DXVACOMPBUFFER_BASE+16, // 166 876 D3DDDIFMT_DXVA_RESERVED17 = D3DDDIFMT_DXVACOMPBUFFER_BASE+17, // 167 877 D3DDDIFMT_DXVA_RESERVED18 = D3DDDIFMT_DXVACOMPBUFFER_BASE+18, // 168 878 D3DDDIFMT_DXVA_RESERVED19 = D3DDDIFMT_DXVACOMPBUFFER_BASE+19, // 169 879 D3DDDIFMT_DXVA_RESERVED20 = D3DDDIFMT_DXVACOMPBUFFER_BASE+20, // 170 880 D3DDDIFMT_DXVA_RESERVED21 = D3DDDIFMT_DXVACOMPBUFFER_BASE+21, // 171 881 D3DDDIFMT_DXVA_RESERVED22 = D3DDDIFMT_DXVACOMPBUFFER_BASE+22, // 172 882 D3DDDIFMT_DXVA_RESERVED23 = D3DDDIFMT_DXVACOMPBUFFER_BASE+23, // 173 883 D3DDDIFMT_DXVA_RESERVED24 = D3DDDIFMT_DXVACOMPBUFFER_BASE+24, // 174 884 D3DDDIFMT_DXVA_RESERVED25 = D3DDDIFMT_DXVACOMPBUFFER_BASE+25, // 175 885 D3DDDIFMT_DXVA_RESERVED26 = D3DDDIFMT_DXVACOMPBUFFER_BASE+26, // 176 886 D3DDDIFMT_DXVA_RESERVED27 = D3DDDIFMT_DXVACOMPBUFFER_BASE+27, // 177 887 D3DDDIFMT_DXVA_RESERVED28 = D3DDDIFMT_DXVACOMPBUFFER_BASE+28, // 178 888 D3DDDIFMT_DXVA_RESERVED29 = D3DDDIFMT_DXVACOMPBUFFER_BASE+29, // 179 889 D3DDDIFMT_DXVA_RESERVED30 = D3DDDIFMT_DXVACOMPBUFFER_BASE+30, // 180 890 D3DDDIFMT_DXVA_RESERVED31 = D3DDDIFMT_DXVACOMPBUFFER_BASE+31, // 181 891 D3DDDIFMT_DXVACOMPBUFFER_MAX = D3DDDIFMT_DXVA_RESERVED31, 892 893 D3DDDIFMT_BINARYBUFFER = 199, 894 895 D3DDDIFMT_FORCE_UINT =0x7fffffff 896 } D3DDDIFORMAT; 897 898 typedef enum D3DDDI_COLOR_SPACE_TYPE 899 { 900 D3DDDI_COLOR_SPACE_RGB_FULL_G22_NONE_P709 = 0, 901 D3DDDI_COLOR_SPACE_RGB_FULL_G10_NONE_P709 = 1, 902 D3DDDI_COLOR_SPACE_RGB_STUDIO_G22_NONE_P709 = 2, 903 D3DDDI_COLOR_SPACE_RGB_STUDIO_G22_NONE_P2020 = 3, 904 D3DDDI_COLOR_SPACE_RESERVED = 4, 905 D3DDDI_COLOR_SPACE_YCBCR_FULL_G22_NONE_P709_X601 = 5, 906 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_G22_LEFT_P601 = 6, 907 D3DDDI_COLOR_SPACE_YCBCR_FULL_G22_LEFT_P601 = 7, 908 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_G22_LEFT_P709 = 8, 909 D3DDDI_COLOR_SPACE_YCBCR_FULL_G22_LEFT_P709 = 9, 910 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_G22_LEFT_P2020 = 10, 911 D3DDDI_COLOR_SPACE_YCBCR_FULL_G22_LEFT_P2020 = 11, 912 D3DDDI_COLOR_SPACE_RGB_FULL_G2084_NONE_P2020 = 12, 913 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_G2084_LEFT_P2020 = 13, 914 D3DDDI_COLOR_SPACE_RGB_STUDIO_G2084_NONE_P2020 = 14, 915 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_G22_TOPLEFT_P2020 = 15, 916 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_G2084_TOPLEFT_P2020 = 16, 917 D3DDDI_COLOR_SPACE_RGB_FULL_G22_NONE_P2020 = 17, 918 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_GHLG_TOPLEFT_P2020 = 18, 919 D3DDDI_COLOR_SPACE_YCBCR_FULL_GHLG_TOPLEFT_P2020 = 19, 920 D3DDDI_COLOR_SPACE_RGB_STUDIO_G24_NONE_P709 = 20, 921 D3DDDI_COLOR_SPACE_RGB_STUDIO_G24_NONE_P2020 = 21, 922 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_G24_LEFT_P709 = 22, 923 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_G24_LEFT_P2020 = 23, 924 D3DDDI_COLOR_SPACE_YCBCR_STUDIO_G24_TOPLEFT_P2020 = 24, 925 D3DDDI_COLOR_SPACE_CUSTOM = 0xFFFFFFFF 926 } D3DDDI_COLOR_SPACE_TYPE; 927 928 // 929 // Note: This enum is intended to specify the final wire signaling 930 // colorspace values. Do not mix it with enum values defined in 931 // D3DDDI_COLOR_SPACE_TYPE which are used to specify 932 // input colorspace for MPOs and other surfaces. 933 // 934 typedef enum _D3DDDI_OUTPUT_WIRE_COLOR_SPACE_TYPE 935 { 936 // We are using the same values for these first two enums for 937 // backward compatibility to WDDM2.2 drivers which used 938 // to get these 2 values from D3DDDI_COLOR_SPACE_TYPE 939 D3DDDI_OUTPUT_WIRE_COLOR_SPACE_G22_P709 = 0, 940 D3DDDI_OUTPUT_WIRE_COLOR_SPACE_RESERVED = 4, 941 D3DDDI_OUTPUT_WIRE_COLOR_SPACE_G2084_P2020 = 12, 942 943 // We are starting the new enum value at 30 just to make sure it 944 // is not confused with the existing D3DDDI_COLOR_SPACE_TYPE 945 // in the short term 946 D3DDDI_OUTPUT_WIRE_COLOR_SPACE_G22_P709_WCG = 30, 947 948 // OS only intend to use the _G22_P2020 value in future, 949 // for now graphics drivers should not expect it. 950 D3DDDI_OUTPUT_WIRE_COLOR_SPACE_G22_P2020 = 31, 951 952 // OS only intend to use the _G2084_P2020_HDR10PLUS value in future, 953 // for now graphics drivers should not expect it. 954 D3DDDI_OUTPUT_WIRE_COLOR_SPACE_G2084_P2020_HDR10PLUS = 32, 955 956 // OS only intend to use the _G2084_P2020_DVLL value in future, 957 // for now graphics drivers should not expect it. 958 D3DDDI_OUTPUT_WIRE_COLOR_SPACE_G2084_P2020_DVLL = 33, 959 } D3DDDI_OUTPUT_WIRE_COLOR_SPACE_TYPE; 960 961 typedef struct _D3DDDIRECT 962 { 963 LONG left; 964 LONG top; 965 LONG right; 966 LONG bottom; 967 } D3DDDIRECT; 968 969 typedef struct _D3DDDI_KERNELOVERLAYINFO 970 { 971 D3DKMT_HANDLE hAllocation; // in: Allocation to be displayed 972 D3DDDIRECT DstRect; // in: Dest rect 973 D3DDDIRECT SrcRect; // in: Source rect 974 D3DKMT_PTR(VOID*, pPrivateDriverData); // in: Private driver data 975 UINT PrivateDriverDataSize; // in: Size of private driver data 976 } D3DDDI_KERNELOVERLAYINFO; 977 978 typedef enum _D3DDDI_GAMMARAMP_TYPE 979 { 980 D3DDDI_GAMMARAMP_UNINITIALIZED = 0, 981 D3DDDI_GAMMARAMP_DEFAULT = 1, 982 D3DDDI_GAMMARAMP_RGB256x3x16 = 2, 983 D3DDDI_GAMMARAMP_DXGI_1 = 3, 984 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_3) 985 D3DDDI_GAMMARAMP_MATRIX_3x4 = 4, 986 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_3) 987 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_6) 988 D3DDDI_GAMMARAMP_MATRIX_V2 = 5, 989 #endif // DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_6 990 } D3DDDI_GAMMARAMP_TYPE; 991 992 typedef struct _D3DDDI_GAMMA_RAMP_RGB256x3x16 993 { 994 USHORT Red[256]; 995 USHORT Green[256]; 996 USHORT Blue[256]; 997 } D3DDDI_GAMMA_RAMP_RGB256x3x16; 998 999 typedef struct D3DDDI_DXGI_RGB 1000 { 1001 float Red; 1002 float Green; 1003 float Blue; 1004 } D3DDDI_DXGI_RGB; 1005 1006 typedef struct _D3DDDI_GAMMA_RAMP_DXGI_1 1007 { 1008 D3DDDI_DXGI_RGB Scale; 1009 D3DDDI_DXGI_RGB Offset; 1010 D3DDDI_DXGI_RGB GammaCurve[1025]; 1011 } D3DDDI_GAMMA_RAMP_DXGI_1; 1012 1013 typedef struct _D3DKMDT_3X4_COLORSPACE_TRANSFORM 1014 { 1015 float ColorMatrix3x4[3][4]; 1016 float ScalarMultiplier; 1017 D3DDDI_DXGI_RGB LookupTable1D[4096]; 1018 } D3DKMDT_3x4_COLORSPACE_TRANSFORM, *PD3DDDI_3x4_COLORSPACE_TRANSFORM; 1019 1020 typedef enum _D3DKMDT_COLORSPACE_TRANSFORM_STAGE_CONTROL 1021 { 1022 D3DKMDT_COLORSPACE_TRANSFORM_STAGE_CONTROL_NO_CHANGE = 0, 1023 D3DKMDT_COLORSPACE_TRANSFORM_STAGE_CONTROL_ENABLE = 1, 1024 D3DKMDT_COLORSPACE_TRANSFORM_STAGE_CONTROL_BYPASS = 2, 1025 }D3DKMDT_COLORSPACE_TRANSFORM_STAGE_CONTROL, *PD3DKMDT_COLORSPACE_TRANSFORM_STAGE_CONTROL; 1026 1027 typedef struct _D3DKMDT_COLORSPACE_TRANSFORM_MATRIX_V2 1028 { 1029 // stage of 1D Degamma. 1030 D3DKMDT_COLORSPACE_TRANSFORM_STAGE_CONTROL StageControlLookupTable1DDegamma; 1031 D3DDDI_DXGI_RGB LookupTable1DDegamma[4096]; 1032 1033 // stage of 3x3 matrix 1034 D3DKMDT_COLORSPACE_TRANSFORM_STAGE_CONTROL StageControlColorMatrix3x3; 1035 float ColorMatrix3x3[3][3]; 1036 1037 // stage of 1D Regamma. 1038 D3DKMDT_COLORSPACE_TRANSFORM_STAGE_CONTROL StageControlLookupTable1DRegamma; 1039 D3DDDI_DXGI_RGB LookupTable1DRegamma[4096]; 1040 } D3DKMDT_COLORSPACE_TRANSFORM_MATRIX_V2, *PD3DKMDT_COLORSPACE_TRANSFORM_MATRIX_V2; 1041 1042 typedef enum _D3DDDI_HDR_METADATA_TYPE 1043 { 1044 D3DDDI_HDR_METADATA_TYPE_NONE = 0, 1045 D3DDDI_HDR_METADATA_TYPE_HDR10 = 1, 1046 D3DDDI_HDR_METADATA_TYPE_HDR10PLUS = 2, 1047 } D3DDDI_HDR_METADATA_TYPE; 1048 1049 typedef struct _D3DDDI_HDR_METADATA_HDR10 1050 { 1051 // Color gamut 1052 UINT16 RedPrimary[2]; 1053 UINT16 GreenPrimary[2]; 1054 UINT16 BluePrimary[2]; 1055 UINT16 WhitePoint[2]; 1056 1057 // Luminance 1058 UINT MaxMasteringLuminance; 1059 UINT MinMasteringLuminance; 1060 UINT16 MaxContentLightLevel; 1061 UINT16 MaxFrameAverageLightLevel; 1062 } D3DDDI_HDR_METADATA_HDR10; 1063 1064 typedef struct D3DDDI_HDR_METADATA_HDR10PLUS 1065 { 1066 BYTE Data[72]; 1067 } D3DDDI_HDR_METADATA_HDR10PLUS; 1068 1069 // Used as a value for D3DDDI_VIDEO_PRESENT_SOURCE_ID and D3DDDI_VIDEO_PRESENT_TARGET_ID types to specify 1070 // that the respective video present source/target ID hasn't been initialized. 1071 #define D3DDDI_ID_UNINITIALIZED (UINT)(~0) 1072 1073 // TODO:[mmilirud] Define this as (UINT)(~1) to avoid collision with valid source ID equal to 0. 1074 // 1075 // Used as a value for D3DDDI_VIDEO_PRESENT_SOURCE_ID and D3DDDI_VIDEO_PRESENT_TARGET_ID types to specify 1076 // that the respective video present source/target ID isn't applicable for the given execution context. 1077 #define D3DDDI_ID_NOTAPPLICABLE (UINT)(0) 1078 1079 // Indicates that a resource can be associated with "any" VidPn source, even none at all. 1080 #define D3DDDI_ID_ANY (UINT)(~1) 1081 1082 // Used as a value for D3DDDI_VIDEO_PRESENT_SOURCE_ID and D3DDDI_VIDEO_PRESENT_TARGET_ID types to specify 1083 // that the respective video present source/target ID describes every VidPN source/target in question. 1084 #define D3DDDI_ID_ALL (UINT)(~2) 1085 1086 // 1087 // Hardcoded VidPnSource count 1088 // 1089 #define D3DKMDT_MAX_VIDPN_SOURCES_BITCOUNT 4 1090 #define D3DKMDT_MAX_VIDPN_SOURCES (1 << D3DKMDT_MAX_VIDPN_SOURCES_BITCOUNT) 1091 1092 1093 ///////////////////////////////////////////////////////////////////////////////////////////////////////////// 1094 // Purpose: Multi-sampling method descriptor type. 1095 // 1096 // Remarks: Driver is free to partition its quality levels for a given multi-sampling method into as many 1097 // increments as it likes, with the condition that each incremental step does noticably improve 1098 // quality of the presented image. 1099 // 1100 typedef struct _D3DDDI_MULTISAMPLINGMETHOD 1101 { 1102 // Number of sub-pixels employed in this multi-sampling method (e.g. 2 for 2x and 8 for 8x multi-sampling) 1103 UINT NumSamples; 1104 1105 // Upper bound on the quality range supported for this multi-sampling method. The range starts from 0 1106 // and goes upto and including the reported maximum quality setting. 1107 UINT NumQualityLevels; 1108 } 1109 D3DDDI_MULTISAMPLINGMETHOD; 1110 1111 1112 ///////////////////////////////////////////////////////////////////////////////////////////////////////////// 1113 // Purpose: Video signal scan line ordering descriptor type. 1114 // 1115 // Remarks: Scan-line ordering of the video mode, specifies whether each field contains the entire 1116 // content of a frame, or only half of it (i.e. even/odd lines interchangeably). 1117 // Note that while for standard interlaced modes, what field comes first can be inferred 1118 // from the mode, specifying this characteristic explicitly with an enum both frees up the 1119 // client from having to maintain mode-based look-up tables and is extensible for future 1120 // standard modes not listed in the D3DKMDT_VIDEO_SIGNAL_STANDARD enum. 1121 // 1122 typedef enum _D3DDDI_VIDEO_SIGNAL_SCANLINE_ORDERING 1123 { 1124 D3DDDI_VSSLO_UNINITIALIZED = 0, 1125 D3DDDI_VSSLO_PROGRESSIVE = 1, 1126 D3DDDI_VSSLO_INTERLACED_UPPERFIELDFIRST = 2, 1127 D3DDDI_VSSLO_INTERLACED_LOWERFIELDFIRST = 3, 1128 D3DDDI_VSSLO_OTHER = 255 1129 } 1130 D3DDDI_VIDEO_SIGNAL_SCANLINE_ORDERING; 1131 1132 1133 typedef enum D3DDDI_FLIPINTERVAL_TYPE 1134 { 1135 D3DDDI_FLIPINTERVAL_IMMEDIATE = 0, 1136 D3DDDI_FLIPINTERVAL_ONE = 1, 1137 D3DDDI_FLIPINTERVAL_TWO = 2, 1138 D3DDDI_FLIPINTERVAL_THREE = 3, 1139 D3DDDI_FLIPINTERVAL_FOUR = 4, 1140 1141 // This value is only valid for the D3D9 runtime PresentCb SyncIntervalOverride field. 1142 // For this field, IMMEDIATE means the API semantic of sync interval 0, where 1143 // IMMEDIATE_ALLOW_TEARING is equivalent to the addition of the DXGI ALLOW_TEARING API flags. 1144 D3DDDI_FLIPINTERVAL_IMMEDIATE_ALLOW_TEARING = 5, 1145 } D3DDDI_FLIPINTERVAL_TYPE; 1146 1147 1148 typedef enum _D3DDDI_POOL 1149 { 1150 D3DDDIPOOL_SYSTEMMEM = 1, 1151 D3DDDIPOOL_VIDEOMEMORY = 2, 1152 D3DDDIPOOL_LOCALVIDMEM = 3, 1153 D3DDDIPOOL_NONLOCALVIDMEM = 4, 1154 #if (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM1_3) // M1 1155 D3DDDIPOOL_STAGINGMEM = 5, 1156 #endif 1157 } D3DDDI_POOL; 1158 1159 1160 typedef enum _D3DDDIMULTISAMPLE_TYPE 1161 { 1162 D3DDDIMULTISAMPLE_NONE = 0, 1163 D3DDDIMULTISAMPLE_NONMASKABLE = 1, 1164 D3DDDIMULTISAMPLE_2_SAMPLES = 2, 1165 D3DDDIMULTISAMPLE_3_SAMPLES = 3, 1166 D3DDDIMULTISAMPLE_4_SAMPLES = 4, 1167 D3DDDIMULTISAMPLE_5_SAMPLES = 5, 1168 D3DDDIMULTISAMPLE_6_SAMPLES = 6, 1169 D3DDDIMULTISAMPLE_7_SAMPLES = 7, 1170 D3DDDIMULTISAMPLE_8_SAMPLES = 8, 1171 D3DDDIMULTISAMPLE_9_SAMPLES = 9, 1172 D3DDDIMULTISAMPLE_10_SAMPLES = 10, 1173 D3DDDIMULTISAMPLE_11_SAMPLES = 11, 1174 D3DDDIMULTISAMPLE_12_SAMPLES = 12, 1175 D3DDDIMULTISAMPLE_13_SAMPLES = 13, 1176 D3DDDIMULTISAMPLE_14_SAMPLES = 14, 1177 D3DDDIMULTISAMPLE_15_SAMPLES = 15, 1178 D3DDDIMULTISAMPLE_16_SAMPLES = 16, 1179 1180 D3DDDIMULTISAMPLE_FORCE_UINT = 0x7fffffff 1181 } D3DDDIMULTISAMPLE_TYPE; 1182 1183 typedef struct _D3DDDI_RESOURCEFLAGS 1184 { 1185 union 1186 { 1187 struct 1188 { 1189 UINT RenderTarget : 1; // 0x00000001 1190 UINT ZBuffer : 1; // 0x00000002 1191 UINT Dynamic : 1; // 0x00000004 1192 UINT HintStatic : 1; // 0x00000008 1193 UINT AutogenMipmap : 1; // 0x00000010 1194 UINT DMap : 1; // 0x00000020 1195 UINT WriteOnly : 1; // 0x00000040 1196 UINT NotLockable : 1; // 0x00000080 1197 UINT Points : 1; // 0x00000100 1198 UINT RtPatches : 1; // 0x00000200 1199 UINT NPatches : 1; // 0x00000400 1200 UINT SharedResource : 1; // 0x00000800 1201 UINT DiscardRenderTarget : 1; // 0x00001000 1202 UINT Video : 1; // 0x00002000 1203 UINT CaptureBuffer : 1; // 0x00004000 1204 UINT Primary : 1; // 0x00008000 1205 UINT Texture : 1; // 0x00010000 1206 UINT CubeMap : 1; // 0x00020000 1207 UINT Volume : 1; // 0x00040000 1208 UINT VertexBuffer : 1; // 0x00080000 1209 UINT IndexBuffer : 1; // 0x00100000 1210 UINT DecodeRenderTarget : 1; // 0x00200000 1211 UINT DecodeCompressedBuffer : 1; // 0x00400000 1212 UINT VideoProcessRenderTarget: 1; // 0x00800000 1213 UINT CpuOptimized : 1; // 0x01000000 1214 UINT MightDrawFromLocked : 1; // 0x02000000 1215 UINT Overlay : 1; // 0x04000000 1216 UINT MatchGdiPrimary : 1; // 0x08000000 1217 UINT InterlacedRefresh : 1; // 0x10000000 1218 UINT TextApi : 1; // 0x20000000 1219 UINT RestrictedContent : 1; // 0x40000000 1220 UINT RestrictSharedAccess : 1; // 0x80000000 1221 }; 1222 UINT Value; 1223 }; 1224 } D3DDDI_RESOURCEFLAGS; 1225 1226 typedef struct _D3DDDI_SURFACEINFO 1227 { 1228 UINT Width; // in: For linear, surface and volume 1229 UINT Height; // in: For surface and volume 1230 UINT Depth; // in: For volume 1231 CONST VOID* pSysMem; 1232 UINT SysMemPitch; 1233 UINT SysMemSlicePitch; 1234 } D3DDDI_SURFACEINFO; 1235 1236 typedef enum _D3DDDI_ROTATION 1237 { 1238 D3DDDI_ROTATION_IDENTITY = 1, // No rotation. 1239 D3DDDI_ROTATION_90 = 2, // Rotated 90 degrees. 1240 D3DDDI_ROTATION_180 = 3, // Rotated 180 degrees. 1241 D3DDDI_ROTATION_270 = 4 // Rotated 270 degrees. 1242 } D3DDDI_ROTATION; 1243 1244 typedef enum D3DDDI_SCANLINEORDERING 1245 { 1246 D3DDDI_SCANLINEORDERING_UNKNOWN = 0, 1247 D3DDDI_SCANLINEORDERING_PROGRESSIVE = 1, 1248 D3DDDI_SCANLINEORDERING_INTERLACED = 2, 1249 } D3DDDI_SCANLINEORDERING; 1250 1251 typedef struct _D3DDDIARG_CREATERESOURCE 1252 { 1253 D3DDDIFORMAT Format; 1254 D3DDDI_POOL Pool; 1255 D3DDDIMULTISAMPLE_TYPE MultisampleType; 1256 UINT MultisampleQuality; 1257 CONST D3DDDI_SURFACEINFO* pSurfList; // in: List of sub resource objects to create 1258 UINT SurfCount; // in: Number of sub resource objects 1259 UINT MipLevels; 1260 UINT Fvf; // in: FVF format for vertex buffers 1261 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId; // in: VidPnSourceId on which the primary surface is created 1262 D3DDDI_RATIONAL RefreshRate; // in: RefreshRate that this primary surface is to be used with 1263 HANDLE hResource; // in/out: D3D runtime handle/UM driver handle 1264 D3DDDI_RESOURCEFLAGS Flags; 1265 D3DDDI_ROTATION Rotation; // in: The orientation of the resource. (0, 90, 180, 270) 1266 } D3DDDIARG_CREATERESOURCE; 1267 1268 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) || \ 1269 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WIN8)) 1270 1271 typedef struct _D3DDDI_RESOURCEFLAGS2 1272 { 1273 union 1274 { 1275 struct 1276 { 1277 UINT VideoEncoder : 1; // 0x00000001 1278 UINT UserMemory : 1; // 0x00000002 1279 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3) || \ 1280 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM1_3)) // M1 1281 UINT CrossAdapter : 1; // 0x00000004 1282 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) || \ 1283 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_0)) 1284 UINT IsDisplayable : 1; // 0x00000008 1285 UINT Reserved : 28; 1286 #else 1287 UINT Reserved : 29; 1288 #endif 1289 #else 1290 UINT Reserved : 30; 1291 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3) 1292 }; 1293 UINT Value; 1294 }; 1295 } D3DDDI_RESOURCEFLAGS2; 1296 1297 1298 typedef struct _D3DDDIARG_CREATERESOURCE2 1299 { 1300 D3DDDIFORMAT Format; 1301 D3DDDI_POOL Pool; 1302 D3DDDIMULTISAMPLE_TYPE MultisampleType; 1303 UINT MultisampleQuality; 1304 CONST D3DDDI_SURFACEINFO* pSurfList; // in: List of sub resource objects to create 1305 UINT SurfCount; // in: Number of sub resource objects 1306 UINT MipLevels; 1307 UINT Fvf; // in: FVF format for vertex buffers 1308 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId; // in: VidPnSourceId on which the primary surface is created 1309 D3DDDI_RATIONAL RefreshRate; // in: RefreshRate that this primary surface is to be used with 1310 HANDLE hResource; // in/out: D3D runtime handle/UM driver handle 1311 D3DDDI_RESOURCEFLAGS Flags; 1312 D3DDDI_ROTATION Rotation; // in: The orientation of the resource. (0, 90, 180, 270) 1313 D3DDDI_RESOURCEFLAGS2 Flags2; 1314 } D3DDDIARG_CREATERESOURCE2; 1315 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) 1316 1317 typedef struct _D3DDDICB_SIGNALFLAGS 1318 { 1319 union 1320 { 1321 struct 1322 { 1323 UINT SignalAtSubmission : 1; 1324 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) 1325 UINT EnqueueCpuEvent : 1; 1326 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) 1327 UINT AllowFenceRewind : 1; 1328 UINT Reserved : 28; 1329 UINT DXGK_SIGNAL_FLAG_INTERNAL0 : 1; 1330 #else 1331 UINT Reserved : 30; 1332 #endif 1333 #else 1334 UINT Reserved : 31; 1335 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8) 1336 }; 1337 UINT Value; 1338 }; 1339 } D3DDDICB_SIGNALFLAGS; 1340 1341 #define D3DDDI_MAX_OBJECT_WAITED_ON 32 1342 #define D3DDDI_MAX_OBJECT_SIGNALED 32 1343 1344 typedef enum _D3DDDI_SYNCHRONIZATIONOBJECT_TYPE 1345 { 1346 D3DDDI_SYNCHRONIZATION_MUTEX = 1, 1347 D3DDDI_SEMAPHORE = 2, 1348 D3DDDI_FENCE = 3, 1349 D3DDDI_CPU_NOTIFICATION = 4, 1350 1351 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) || \ 1352 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_0)) 1353 D3DDDI_MONITORED_FENCE = 5, 1354 #endif // DXGKDDI_INTERFACE_VERSION 1355 1356 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2) || \ 1357 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_2)) 1358 D3DDDI_PERIODIC_MONITORED_FENCE = 6, 1359 #endif // DXGKDDI_INTERFACE_VERSION 1360 1361 D3DDDI_SYNCHRONIZATION_TYPE_LIMIT 1362 1363 } D3DDDI_SYNCHRONIZATIONOBJECT_TYPE; 1364 1365 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) || \ 1366 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_0)) 1367 1368 #define D3DDDI_SYNC_OBJECT_WAIT 0x1 1369 #define D3DDDI_SYNC_OBJECT_SIGNAL 0x2 1370 #define D3DDDI_SYNC_OBJECT_ALL_ACCESS (STANDARD_RIGHTS_REQUIRED | SYNCHRONIZE | D3DDDI_SYNC_OBJECT_WAIT | D3DDDI_SYNC_OBJECT_SIGNAL) 1371 1372 #endif // DXGKDDI_INTERFACE_VERSION 1373 1374 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3) 1375 1376 typedef union 1377 { 1378 struct 1379 { 1380 UINT64 FrameNumber : 40; 1381 UINT64 PartNumber : 24; 1382 }; 1383 UINT64 Value; 1384 }DXGK_MIRACAST_CHUNK_ID; 1385 1386 typedef enum _DXGK_MIRACAST_CHUNK_TYPE 1387 { 1388 DXGK_MIRACAST_CHUNK_TYPE_UNKNOWN = 0, 1389 DXGK_MIRACAST_CHUNK_TYPE_COLOR_CONVERT_COMPLETE = 1, 1390 DXGK_MIRACAST_CHUNK_TYPE_ENCODE_COMPLETE = 2, 1391 DXGK_MIRACAST_CHUNK_TYPE_FRAME_START = 3, 1392 DXGK_MIRACAST_CHUNK_TYPE_FRAME_DROPPED = 4, 1393 DXGK_MIRACAST_CHUNK_TYPE_ENCODE_DRIVER_DEFINED_1 = 0x80000000, 1394 DXGK_MIRACAST_CHUNK_TYPE_ENCODE_DRIVER_DEFINED_2 = 0x80000001, 1395 } DXGK_MIRACAST_CHUNK_TYPE; 1396 1397 typedef struct 1398 { 1399 DXGK_MIRACAST_CHUNK_TYPE ChunkType; // Type of chunk info 1400 DXGK_MIRACAST_CHUNK_ID ChunkId; // Identifier for this chunk 1401 UINT ProcessingTime; // Time the process took to complete in microsecond 1402 UINT EncodeRate; // Encode bitrate driver reported for the chunk, kilobits per second 1403 } DXGK_MIRACAST_CHUNK_INFO; 1404 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3) 1405 1406 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) || \ 1407 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_0)) 1408 1409 typedef enum D3DDDI_PAGINGQUEUE_PRIORITY 1410 { 1411 D3DDDI_PAGINGQUEUE_PRIORITY_BELOW_NORMAL = -1, 1412 D3DDDI_PAGINGQUEUE_PRIORITY_NORMAL = 0, 1413 D3DDDI_PAGINGQUEUE_PRIORITY_ABOVE_NORMAL = 1, 1414 } D3DDDI_PAGINGQUEUE_PRIORITY; 1415 1416 typedef struct D3DDDI_MAKERESIDENT_FLAGS 1417 { 1418 union 1419 { 1420 struct 1421 { 1422 UINT CantTrimFurther : 1; // When set, MakeResidentCb will succeed even if the request puts the application over the current budget. 1423 // MakeResidentCb will still fail if the request puts the application over the maximum budget. 1424 UINT MustSucceed : 1; // When set, instructs MakeResidentCb to put the device in error if the resource cannot be made resident. 1425 UINT Reserved : 30; 1426 }; 1427 UINT Value; 1428 }; 1429 } D3DDDI_MAKERESIDENT_FLAGS; 1430 1431 typedef struct D3DDDI_MAKERESIDENT 1432 { 1433 D3DKMT_HANDLE hPagingQueue; // [in] Handle to the paging queue used to synchronize paging operations for this call. 1434 UINT NumAllocations; // [in/out] On input, the number of allocation handles om the AllocationList array. On output, 1435 // the number of allocations successfully made resident. 1436 D3DKMT_PTR(_Field_size_(NumAllocations) 1437 CONST D3DKMT_HANDLE*, AllocationList); // [in] An array of NumAllocations allocation handles 1438 D3DKMT_PTR(CONST UINT*, PriorityList); // [in] Residency priority array for each of the allocations in the resource or allocation list 1439 D3DDDI_MAKERESIDENT_FLAGS Flags; // [in] Residency flags 1440 D3DKMT_ALIGN64 UINT64 PagingFenceValue; // [out] Paging fence value to synchronize on before submitting the command 1441 // that uses above resources to the GPU. This value applies to the monitored fence 1442 // synchronization object associated with hPagingQueue. 1443 D3DKMT_ALIGN64 UINT64 NumBytesToTrim; // [out] When MakeResident fails due to being over budget, this value 1444 // indicates how much to trim in order for the call to succeed on a retry. 1445 } D3DDDI_MAKERESIDENT; 1446 1447 typedef struct D3DDDI_EVICT_FLAGS 1448 { 1449 union 1450 { 1451 struct 1452 { 1453 UINT EvictOnlyIfNecessary : 1; 1454 UINT NotWrittenTo : 1; 1455 UINT Reserved : 30; 1456 }; 1457 UINT Value; 1458 }; 1459 } D3DDDI_EVICT_FLAGS; 1460 1461 typedef struct D3DDDI_TRIMRESIDENCYSET_FLAGS 1462 { 1463 union 1464 { 1465 struct 1466 { 1467 UINT PeriodicTrim : 1; // When PeriodicTrim flag is set, the driver is required to performed the following operations: 1468 // a) trim all allocations that were not referenced since the previous periodic trim request 1469 // by comparing the allocation last referenced fence with the last periodic trim context fence 1470 // b) Refresh the last periodic trim context fence with the last completed context fence. 1471 UINT RestartPeriodicTrim : 1; // May not be set together with PeriodicTrim flag. 1472 // Reset the last periodic trim context fence to the last completed context fence. 1473 UINT TrimToBudget : 1; // Indicates that the application usage is over the memory budget, 1474 // and NumBytesToTrim bytes should be trimmed to fit in the new memory budget. 1475 UINT Reserved : 29; 1476 }; 1477 UINT Value; 1478 }; 1479 } D3DDDI_TRIMRESIDENCYSET_FLAGS; 1480 1481 typedef struct _D3DDDIGPUVIRTUALADDRESS_PROTECTION_TYPE 1482 { 1483 union 1484 { 1485 struct 1486 { 1487 UINT64 Write : 1; 1488 UINT64 Execute : 1; 1489 UINT64 Zero : 1; 1490 UINT64 NoAccess : 1; 1491 UINT64 SystemUseOnly : 1; // Should not be set by the UMD 1492 UINT64 Reserved : 59; 1493 }; 1494 D3DKMT_ALIGN64 UINT64 Value; 1495 }; 1496 } D3DDDIGPUVIRTUALADDRESS_PROTECTION_TYPE; 1497 1498 typedef enum _D3DDDI_UPDATEGPUVIRTUALADDRESS_OPERATION_TYPE 1499 { 1500 D3DDDI_UPDATEGPUVIRTUALADDRESS_MAP = 0, 1501 D3DDDI_UPDATEGPUVIRTUALADDRESS_UNMAP = 1, 1502 D3DDDI_UPDATEGPUVIRTUALADDRESS_COPY = 2, 1503 D3DDDI_UPDATEGPUVIRTUALADDRESS_MAP_PROTECT = 3, 1504 } D3DDDI_UPDATEGPUVIRTUALADDRESS_OPERATION_TYPE; 1505 1506 typedef struct _D3DDDI_UPDATEGPUVIRTUALADDRESS_OPERATION 1507 { 1508 D3DDDI_UPDATEGPUVIRTUALADDRESS_OPERATION_TYPE OperationType; 1509 union 1510 { 1511 struct 1512 { 1513 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS BaseAddress; 1514 D3DKMT_ALIGN64 D3DGPU_SIZE_T SizeInBytes; 1515 D3DKMT_HANDLE hAllocation; 1516 D3DKMT_ALIGN64 D3DGPU_SIZE_T AllocationOffsetInBytes; 1517 D3DKMT_ALIGN64 D3DGPU_SIZE_T AllocationSizeInBytes; 1518 } Map; 1519 struct 1520 { 1521 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS BaseAddress; 1522 D3DKMT_ALIGN64 D3DGPU_SIZE_T SizeInBytes; 1523 D3DKMT_HANDLE hAllocation; 1524 D3DKMT_ALIGN64 D3DGPU_SIZE_T AllocationOffsetInBytes; 1525 D3DKMT_ALIGN64 D3DGPU_SIZE_T AllocationSizeInBytes; 1526 D3DDDIGPUVIRTUALADDRESS_PROTECTION_TYPE Protection; 1527 D3DKMT_ALIGN64 UINT64 DriverProtection; 1528 } MapProtect; 1529 struct 1530 { 1531 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS BaseAddress; 1532 D3DKMT_ALIGN64 D3DGPU_SIZE_T SizeInBytes; 1533 D3DDDIGPUVIRTUALADDRESS_PROTECTION_TYPE Protection; 1534 } Unmap; // Used for UNMAP_NOACCESS as well 1535 struct 1536 { 1537 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS SourceAddress; 1538 D3DKMT_ALIGN64 D3DGPU_SIZE_T SizeInBytes; 1539 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS DestAddress; 1540 } Copy; 1541 }; 1542 } D3DDDI_UPDATEGPUVIRTUALADDRESS_OPERATION; 1543 1544 typedef enum _D3DDDIGPUVIRTUALADDRESS_RESERVATION_TYPE 1545 { 1546 D3DDDIGPUVIRTUALADDRESS_RESERVE_NO_ACCESS = 0, 1547 D3DDDIGPUVIRTUALADDRESS_RESERVE_ZERO = 1, 1548 D3DDDIGPUVIRTUALADDRESS_RESERVE_NO_COMMIT = 2 // Reserved for system use 1549 } D3DDDIGPUVIRTUALADDRESS_RESERVATION_TYPE; 1550 1551 typedef struct D3DDDI_MAPGPUVIRTUALADDRESS 1552 { 1553 D3DKMT_HANDLE hPagingQueue; // in: Paging queue to synchronize the operation on. 1554 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS BaseAddress; // in_opt: Base virtual address to map 1555 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS MinimumAddress; // in_opt: Minimum virtual address 1556 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS MaximumAddress; // in_opt: Maximum virtual address 1557 D3DKMT_HANDLE hAllocation; // in: Allocation handle to map 1558 D3DKMT_ALIGN64 D3DGPU_SIZE_T OffsetInPages; // in: Offset in 4 KB pages from the start of the allocation 1559 D3DKMT_ALIGN64 D3DGPU_SIZE_T SizeInPages; // in: Size in 4 KB pages to map 1560 D3DDDIGPUVIRTUALADDRESS_PROTECTION_TYPE Protection; // in: Virtual address protection 1561 D3DKMT_ALIGN64 UINT64 DriverProtection; // in: Driver specific protection 1562 UINT Reserved0; // in: 1563 D3DKMT_ALIGN64 UINT64 Reserved1; // in: 1564 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS VirtualAddress; // out: Virtual address 1565 D3DKMT_ALIGN64 UINT64 PagingFenceValue; // out: Paging fence Id for synchronization 1566 } D3DDDI_MAPGPUVIRTUALADDRESS; 1567 1568 typedef struct D3DDDI_RESERVEGPUVIRTUALADDRESS 1569 { 1570 union 1571 { 1572 D3DKMT_HANDLE hPagingQueue; // in: Paging queue to synchronize the operation on. 1573 D3DKMT_HANDLE hAdapter; // in: DXG adapter handle. (M2) 1574 }; 1575 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS BaseAddress; // in_opt: Base virtual address to map 1576 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS MinimumAddress; // in_opt: Minimum virtual address 1577 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS MaximumAddress; // in_opt: Maximum virtual address 1578 D3DKMT_ALIGN64 D3DGPU_SIZE_T Size; // in: Size to reserve in bytes 1579 union 1580 { 1581 D3DDDIGPUVIRTUALADDRESS_RESERVATION_TYPE ReservationType; // in: Reservation type 1582 UINT Reserved0; // M2 1583 }; 1584 union 1585 { 1586 D3DKMT_ALIGN64 UINT64 DriverProtection;// in: Driver specific protection 1587 D3DKMT_ALIGN64 UINT64 Reserved1; // M2 1588 }; 1589 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS VirtualAddress; // out: Virtual address 1590 union 1591 { 1592 D3DKMT_ALIGN64 UINT64 PagingFenceValue;// out: Paging fence Id for synchronization 1593 D3DKMT_ALIGN64 UINT64 Reserved2; // M2 1594 }; 1595 } D3DDDI_RESERVEGPUVIRTUALADDRESS; 1596 1597 typedef struct _D3DDDI_GETRESOURCEPRESENTPRIVATEDRIVERDATA 1598 { 1599 D3DKMT_HANDLE hResource; 1600 UINT PrivateDriverDataSize; 1601 D3DKMT_PTR(PVOID, pPrivateDriverData); 1602 } D3DDDI_GETRESOURCEPRESENTPRIVATEDRIVERDATA; 1603 1604 typedef struct D3DDDI_DESTROYPAGINGQUEUE 1605 { 1606 D3DKMT_HANDLE hPagingQueue; // in: handle to the paging queue to destroy 1607 } D3DDDI_DESTROYPAGINGQUEUE; 1608 1609 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) 1610 1611 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1) || \ 1612 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_1_1)) 1613 1614 typedef struct D3DDDI_UPDATEALLOCPROPERTY_FLAGS 1615 { 1616 union 1617 { 1618 struct 1619 { 1620 UINT AccessedPhysically : 1; // The new value for AccessedPhysically on an allocation 1621 UINT Unmoveable : 1; // Indicates an allocation cannot be moved while pinned in a memory segment 1622 UINT Reserved : 30; 1623 }; 1624 UINT Value; 1625 }; 1626 } D3DDDI_UPDATEALLOCPROPERTY_FLAGS; 1627 1628 typedef struct D3DDDI_UPDATEALLOCPROPERTY 1629 { 1630 D3DKMT_HANDLE hPagingQueue; // [in] Handle to the paging queue used to synchronize paging operations for this call. 1631 D3DKMT_HANDLE hAllocation; // [in] Handle to the allocation to be updated. 1632 UINT SupportedSegmentSet; // [in] New supported segment set, ignored if the same. 1633 D3DDDI_SEGMENTPREFERENCE PreferredSegment; // [in] New preferred segment set, ignored if the same. 1634 D3DDDI_UPDATEALLOCPROPERTY_FLAGS Flags; // [in] Flags to set on the allocation, ignored if the same. 1635 D3DKMT_ALIGN64 UINT64 PagingFenceValue; // [out] Paging fence value to synchronize on before using the above allocation. 1636 // This value applies to the monitored fence synchronization 1637 // object associated with hPagingQueue. 1638 union 1639 { 1640 struct 1641 { 1642 UINT SetAccessedPhysically : 1; // [in] When set to 1, will set AccessedPhysically to new value 1643 UINT SetSupportedSegmentSet : 1; // [in] When set to 1, will set SupportedSegmentSet to new value 1644 UINT SetPreferredSegment : 1; // [in] When set to 1, will set PreferredSegment to new value 1645 UINT SetUnmoveable : 1; // [in] When set to 1, will set Unmoveable to new value 1646 UINT Reserved : 28; 1647 }; 1648 UINT PropertyMaskValue; 1649 }; 1650 } D3DDDI_UPDATEALLOCPROPERTY; 1651 1652 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1) 1653 1654 #if(D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_1_1) 1655 1656 typedef struct D3DDDI_OFFER_FLAGS 1657 { 1658 union 1659 { 1660 struct 1661 { 1662 UINT AllowDecommit : 1; 1663 UINT Reserved : 31; 1664 }; 1665 UINT Value; 1666 }; 1667 } D3DDDI_OFFER_FLAGS; 1668 1669 #endif // (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_1_1) 1670 1671 #if(DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1 || \ 1672 D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_1) 1673 1674 typedef enum _D3DDDI_RECLAIM_RESULT 1675 { 1676 D3DDDI_RECLAIM_RESULT_OK = 0, 1677 D3DDDI_RECLAIM_RESULT_DISCARDED = 1, 1678 D3DDDI_RECLAIM_RESULT_NOT_COMMITTED = 2, 1679 } D3DDDI_RECLAIM_RESULT; 1680 1681 #endif 1682 1683 typedef struct _D3DDDI_SYNCHRONIZATIONOBJECTINFO 1684 { 1685 D3DDDI_SYNCHRONIZATIONOBJECT_TYPE Type; // in: Type of synchronization object to create. 1686 union 1687 { 1688 struct 1689 { 1690 BOOL InitialState; // in: Initial state of a synchronization mutex. 1691 } SynchronizationMutex; 1692 1693 struct 1694 { 1695 UINT MaxCount; // in: Max count of the semaphore. 1696 UINT InitialCount; // in: Initial count of the semaphore. 1697 } Semaphore; 1698 1699 1700 struct 1701 { 1702 UINT Reserved[16]; // Reserved for future use. 1703 } Reserved; 1704 }; 1705 } D3DDDI_SYNCHRONIZATIONOBJECTINFO; 1706 1707 #ifndef D3DDDI_SYNCHRONIZATIONOBJECT_FLAGS_EXT 1708 #define D3DDDI_SYNCHRONIZATIONOBJECT_FLAGS_EXT 1709 #define D3DDDI_SYNCHRONIZATIONOBJECT_FLAGS_RESERVED0 Reserved0 1710 #endif 1711 1712 typedef struct _D3DDDI_SYNCHRONIZATIONOBJECT_FLAGS 1713 { 1714 union 1715 { 1716 struct 1717 { 1718 UINT Shared : 1; 1719 UINT NtSecuritySharing : 1; 1720 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3) || \ 1721 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM1_3)) // M1 1722 1723 UINT CrossAdapter : 1; 1724 1725 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) || \ 1726 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_0)) 1727 1728 // When set, the sync object is signaled as soon as the contents of command buffers preceding it 1729 // is entirely copied to the GPU pipeline, but not necessarily completed execution. 1730 // This flag can be set in order to start reusing command buffers as soon as possible. 1731 UINT TopOfPipeline : 1; 1732 1733 // When set, the device this sync object is created or opened on 1734 // can only submit wait commands for it. 1735 UINT NoSignal : 1; 1736 1737 // When set, the device this sync object is created or opened on 1738 // can only submit signal commands for it. This flag cannot be set 1739 // simultaneously with NoSignal. 1740 UINT NoWait : 1; 1741 1742 // When set, instructs the GPU scheduler to bypass signaling of the monitored fence 1743 // to the maximum value when the device is affected by the GPU reset. 1744 UINT NoSignalMaxValueOnTdr : 1; 1745 1746 // When set, the fence will not be mapped into the GPU virtual address space. 1747 // Only packet-based signal/wait operations are supported 1748 // When this is set, the fence is always stored as a 64-bit value (regardless of adapter caps) 1749 UINT NoGPUAccess : 1; 1750 1751 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM3_0) 1752 // When set, the fence can be signaled by KMD. 1753 // The flag can be used only with D3DDDI_CPU_NOTIFICATION objects. 1754 UINT SignalByKmd : 1; 1755 UINT Reserved : 22; 1756 #else 1757 UINT Reserved : 23; 1758 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM3_0) 1759 1760 #else 1761 UINT Reserved : 28; 1762 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) 1763 1764 #else 1765 UINT Reserved : 29; 1766 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3) 1767 UINT D3DDDI_SYNCHRONIZATIONOBJECT_FLAGS_RESERVED0 : 1; 1768 }; 1769 UINT Value; 1770 }; 1771 } D3DDDI_SYNCHRONIZATIONOBJECT_FLAGS; 1772 1773 typedef struct _D3DDDI_SYNCHRONIZATIONOBJECTINFO2 1774 { 1775 D3DDDI_SYNCHRONIZATIONOBJECT_TYPE Type; // in: Type of synchronization object to create. 1776 D3DDDI_SYNCHRONIZATIONOBJECT_FLAGS Flags; // in: flags. 1777 union 1778 { 1779 struct 1780 { 1781 BOOL InitialState; // in: Initial state of a synchronization mutex. 1782 } SynchronizationMutex; 1783 1784 struct 1785 { 1786 UINT MaxCount; // in: Max count of the semaphore. 1787 UINT InitialCount; // in: Initial count of the semaphore. 1788 } Semaphore; 1789 1790 struct 1791 { 1792 D3DKMT_ALIGN64 UINT64 FenceValue; // in: inital fence value. 1793 } Fence; 1794 1795 struct 1796 { 1797 D3DKMT_PTR(HANDLE, Event); // in: Handle to the event 1798 } CPUNotification; 1799 1800 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) || \ 1801 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_0)) 1802 struct 1803 { 1804 D3DKMT_ALIGN64 UINT64 InitialFenceValue; // in: inital fence value. 1805 D3DKMT_PTR(VOID*, FenceValueCPUVirtualAddress); // out: Read-only mapping of the fence value for the CPU 1806 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS FenceValueGPUVirtualAddress; // out: Read/write mapping of the fence value for the GPU 1807 UINT EngineAffinity; // in: Defines physical adapters where the GPU VA will be mapped 1808 UINT Padding; 1809 } MonitoredFence; 1810 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) 1811 1812 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2) || \ 1813 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_2)) 1814 struct 1815 { 1816 D3DKMT_HANDLE hAdapter; // in: A handle to the adapter associated with VidPnTargetId 1817 D3DDDI_VIDEO_PRESENT_TARGET_ID VidPnTargetId; // in: The output that the compositor wishes to receive notifications for 1818 D3DKMT_ALIGN64 UINT64 Time; // in: Represents an offset before the VSync. 1819 // The Time value may not be longer than a VSync interval. In units of 100ns. 1820 D3DKMT_PTR(VOID*, FenceValueCPUVirtualAddress); // out: Read-only mapping of the fence value for the CPU 1821 D3DKMT_ALIGN64 D3DGPU_VIRTUAL_ADDRESS FenceValueGPUVirtualAddress; // out: Read-only mapping of the fence value for the GPU 1822 UINT EngineAffinity; // in: Defines physical adapters where the GPU VA will be mapped 1823 UINT Padding; 1824 } PeriodicMonitoredFence; 1825 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2) 1826 1827 1828 struct 1829 { 1830 D3DKMT_ALIGN64 UINT64 Reserved[8]; // Reserved for future use. 1831 } Reserved; 1832 }; 1833 1834 D3DKMT_HANDLE SharedHandle; // out: global shared handle (when requested to be shared) 1835 1836 } D3DDDI_SYNCHRONIZATIONOBJECTINFO2; 1837 1838 #if ((DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) || \ 1839 (D3D_UMD_INTERFACE_VERSION >= D3D_UMD_INTERFACE_VERSION_WDDM2_0)) 1840 1841 typedef struct _D3DDDI_WAITFORSYNCHRONIZATIONOBJECTFROMCPU_FLAGS 1842 { 1843 union 1844 { 1845 struct 1846 { 1847 UINT WaitAny : 1; // when waiting for multiple objects, signal the wait event if any 1848 // of the wait array conditions is satisfied as opposed to all conditions. 1849 UINT Reserved : 31; 1850 }; 1851 UINT Value; 1852 }; 1853 } D3DDDI_WAITFORSYNCHRONIZATIONOBJECTFROMCPU_FLAGS; 1854 1855 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0) 1856 1857 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4) 1858 1859 typedef struct _D3DDDI_QUERYREGISTRY_FLAGS 1860 { 1861 union 1862 { 1863 struct 1864 { 1865 UINT TranslatePath : 1; 1866 UINT MutableValue : 1; 1867 UINT Reserved : 30; 1868 }; 1869 UINT Value; 1870 }; 1871 } D3DDDI_QUERYREGISTRY_FLAGS; 1872 1873 typedef enum _D3DDDI_QUERYREGISTRY_TYPE 1874 { 1875 D3DDDI_QUERYREGISTRY_SERVICEKEY = 0, 1876 D3DDDI_QUERYREGISTRY_ADAPTERKEY = 1, 1877 D3DDDI_QUERYREGISTRY_DRIVERSTOREPATH = 2, 1878 D3DDDI_QUERYREGISTRY_DRIVERIMAGEPATH = 3, 1879 D3DDDI_QUERYREGISTRY_MAX, 1880 } D3DDDI_QUERYREGISTRY_TYPE; 1881 1882 typedef enum _D3DDDI_QUERYREGISTRY_STATUS 1883 { 1884 D3DDDI_QUERYREGISTRY_STATUS_SUCCESS = 0, 1885 D3DDDI_QUERYREGISTRY_STATUS_BUFFER_OVERFLOW = 1, 1886 D3DDDI_QUERYREGISTRY_STATUS_FAIL = 2, 1887 D3DDDI_QUERYREGISTRY_STATUS_MAX, 1888 } D3DDDI_QUERYREGISTRY_STATUS; 1889 1890 // 1891 // Output data value follows this structure. 1892 // PrivateDriverSize must be sizeof(D3DDDI_QUERYREGISTRY_INFO) + (size of the the key value in bytes) 1893 // 1894 typedef struct _D3DDDI_QUERYREGISTRY_INFO 1895 { 1896 D3DDDI_QUERYREGISTRY_TYPE QueryType; // In 1897 D3DDDI_QUERYREGISTRY_FLAGS QueryFlags; // In 1898 WCHAR ValueName[MAX_PATH]; // In 1899 ULONG ValueType; // In 1900 ULONG PhysicalAdapterIndex; // In 1901 ULONG OutputValueSize; // Out. Number of bytes written to the output value or required in case of D3DDDI_QUERYREGISTRY_STATUS_BUFFER_OVERFLOW. 1902 D3DDDI_QUERYREGISTRY_STATUS Status; // Out 1903 union { 1904 DWORD OutputDword; // Out 1905 D3DKMT_ALIGN64 UINT64 OutputQword; // Out 1906 WCHAR OutputString[1]; // Out. Dynamic array 1907 BYTE OutputBinary[1]; // Out. Dynamic array 1908 }; 1909 } D3DDDI_QUERYREGISTRY_INFO; 1910 1911 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4) 1912 1913 // 1914 // Defines the maximum number of context a particular command buffer can 1915 // be broadcast to. 1916 // 1917 #define D3DDDI_MAX_BROADCAST_CONTEXT 64 1918 1919 // 1920 // Allocation priorities. 1921 // 1922 #define D3DDDI_ALLOCATIONPRIORITY_MINIMUM 0x28000000 1923 #define D3DDDI_ALLOCATIONPRIORITY_LOW 0x50000000 1924 #define D3DDDI_ALLOCATIONPRIORITY_NORMAL 0x78000000 1925 #define D3DDDI_ALLOCATIONPRIORITY_HIGH 0xa0000000 1926 #define D3DDDI_ALLOCATIONPRIORITY_MAXIMUM 0xc8000000 1927 1928 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3) 1929 1930 // Cross adapter resource pitch alignment in bytes. 1931 // Must be power of 2. 1932 // 1933 #define D3DKMT_CROSS_ADAPTER_RESOURCE_PITCH_ALIGNMENT 128 1934 1935 // Cross adapter resource height alignment in rows. 1936 // 1937 #define D3DKMT_CROSS_ADAPTER_RESOURCE_HEIGHT_ALIGNMENT 4 1938 1939 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3) 1940 1941 #endif // (NTDDI_VERSION >= NTDDI_LONGHORN) || defined(D3DKMDT_SPECIAL_MULTIPLATFORM_TOOL) 1942 1943 #pragma warning(pop) 1944 1945 1946 #endif /* WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP) */ 1947 #pragma endregion 1948 1949 #endif /* _D3DUKMDT_H_ */ 1950 1951