1 /**************************************************************************//**
2  * @file     cmsis_armclang_ltm.h
3  * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
4  * @version  V1.0.1
5  * @date     19. March 2019
6  ******************************************************************************/
7 /*
8  * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
26 
27 #ifndef __CMSIS_ARMCLANG_H
28 #define __CMSIS_ARMCLANG_H
29 
30 #pragma clang system_header   /* treat file as system include file */
31 
32 #ifndef __ARM_COMPAT_H
33 #include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
34 #endif
35 
36 /* CMSIS compiler specific defines */
37 #ifndef   __ASM
38   #define __ASM                                  __asm
39 #endif
40 #ifndef   __INLINE
41   #define __INLINE                               __inline
42 #endif
43 #ifndef   __STATIC_INLINE
44   #define __STATIC_INLINE                        static __inline
45 #endif
46 #ifndef   __STATIC_FORCEINLINE
47   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
48 #endif
49 #ifndef   __NO_RETURN
50   #define __NO_RETURN                            __attribute__((__noreturn__))
51 #endif
52 #ifndef   __USED
53   #define __USED                                 __attribute__((used))
54 #endif
55 #ifndef   __WEAK
56   #define __WEAK                                 __attribute__((weak))
57 #endif
58 #ifndef   __PACKED
59   #define __PACKED                               __attribute__((packed, aligned(1)))
60 #endif
61 #ifndef   __PACKED_STRUCT
62   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
63 #endif
64 #ifndef   __PACKED_UNION
65   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
66 #endif
67 #ifndef   __UNALIGNED_UINT32        /* deprecated */
68   #pragma clang diagnostic push
69   #pragma clang diagnostic ignored "-Wpacked"
70 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
71   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
72   #pragma clang diagnostic pop
73   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
74 #endif
75 #ifndef   __UNALIGNED_UINT16_WRITE
76   #pragma clang diagnostic push
77   #pragma clang diagnostic ignored "-Wpacked"
78 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
79   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
80   #pragma clang diagnostic pop
81   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
82 #endif
83 #ifndef   __UNALIGNED_UINT16_READ
84   #pragma clang diagnostic push
85   #pragma clang diagnostic ignored "-Wpacked"
86 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
87   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
88   #pragma clang diagnostic pop
89   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
90 #endif
91 #ifndef   __UNALIGNED_UINT32_WRITE
92   #pragma clang diagnostic push
93   #pragma clang diagnostic ignored "-Wpacked"
94 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
95   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
96   #pragma clang diagnostic pop
97   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
98 #endif
99 #ifndef   __UNALIGNED_UINT32_READ
100   #pragma clang diagnostic push
101   #pragma clang diagnostic ignored "-Wpacked"
102 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
103   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
104   #pragma clang diagnostic pop
105   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
106 #endif
107 #ifndef   __ALIGNED
108   #define __ALIGNED(x)                           __attribute__((aligned(x)))
109 #endif
110 #ifndef   __RESTRICT
111   #define __RESTRICT                             __restrict
112 #endif
113 
114 
115 /* ###########################  Core Function Access  ########################### */
116 /** \ingroup  CMSIS_Core_FunctionInterface
117     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
118   @{
119  */
120 
121 /**
122   \brief   Enable IRQ Interrupts
123   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
124            Can only be executed in Privileged modes.
125  */
126 /* intrinsic void __enable_irq();  see arm_compat.h */
127 
128 
129 /**
130   \brief   Disable IRQ Interrupts
131   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
132            Can only be executed in Privileged modes.
133  */
134 /* intrinsic void __disable_irq();  see arm_compat.h */
135 
136 
137 /**
138   \brief   Get Control Register
139   \details Returns the content of the Control Register.
140   \return               Control Register value
141  */
__get_CONTROL(void)142 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
143 {
144   uint32_t result;
145 
146   __ASM volatile ("MRS %0, control" : "=r" (result) );
147   return(result);
148 }
149 
150 
151 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
152 /**
153   \brief   Get Control Register (non-secure)
154   \details Returns the content of the non-secure Control Register when in secure mode.
155   \return               non-secure Control Register value
156  */
__TZ_get_CONTROL_NS(void)157 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
158 {
159   uint32_t result;
160 
161   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
162   return(result);
163 }
164 #endif
165 
166 
167 /**
168   \brief   Set Control Register
169   \details Writes the given value to the Control Register.
170   \param [in]    control  Control Register value to set
171  */
__set_CONTROL(uint32_t control)172 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
173 {
174   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
175 }
176 
177 
178 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
179 /**
180   \brief   Set Control Register (non-secure)
181   \details Writes the given value to the non-secure Control Register when in secure state.
182   \param [in]    control  Control Register value to set
183  */
__TZ_set_CONTROL_NS(uint32_t control)184 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
185 {
186   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
187 }
188 #endif
189 
190 
191 /**
192   \brief   Get IPSR Register
193   \details Returns the content of the IPSR Register.
194   \return               IPSR Register value
195  */
__get_IPSR(void)196 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
197 {
198   uint32_t result;
199 
200   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
201   return(result);
202 }
203 
204 
205 /**
206   \brief   Get APSR Register
207   \details Returns the content of the APSR Register.
208   \return               APSR Register value
209  */
__get_APSR(void)210 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
211 {
212   uint32_t result;
213 
214   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
215   return(result);
216 }
217 
218 
219 /**
220   \brief   Get xPSR Register
221   \details Returns the content of the xPSR Register.
222   \return               xPSR Register value
223  */
__get_xPSR(void)224 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
225 {
226   uint32_t result;
227 
228   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
229   return(result);
230 }
231 
232 
233 /**
234   \brief   Get Process Stack Pointer
235   \details Returns the current value of the Process Stack Pointer (PSP).
236   \return               PSP Register value
237  */
__get_PSP(void)238 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
239 {
240   uint32_t result;
241 
242   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
243   return(result);
244 }
245 
246 
247 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
248 /**
249   \brief   Get Process Stack Pointer (non-secure)
250   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
251   \return               PSP Register value
252  */
__TZ_get_PSP_NS(void)253 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
254 {
255   uint32_t result;
256 
257   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
258   return(result);
259 }
260 #endif
261 
262 
263 /**
264   \brief   Set Process Stack Pointer
265   \details Assigns the given value to the Process Stack Pointer (PSP).
266   \param [in]    topOfProcStack  Process Stack Pointer value to set
267  */
__set_PSP(uint32_t topOfProcStack)268 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
269 {
270   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
271 }
272 
273 
274 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
275 /**
276   \brief   Set Process Stack Pointer (non-secure)
277   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
278   \param [in]    topOfProcStack  Process Stack Pointer value to set
279  */
__TZ_set_PSP_NS(uint32_t topOfProcStack)280 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
281 {
282   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
283 }
284 #endif
285 
286 
287 /**
288   \brief   Get Main Stack Pointer
289   \details Returns the current value of the Main Stack Pointer (MSP).
290   \return               MSP Register value
291  */
__get_MSP(void)292 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
293 {
294   uint32_t result;
295 
296   __ASM volatile ("MRS %0, msp" : "=r" (result) );
297   return(result);
298 }
299 
300 
301 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
302 /**
303   \brief   Get Main Stack Pointer (non-secure)
304   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
305   \return               MSP Register value
306  */
__TZ_get_MSP_NS(void)307 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
308 {
309   uint32_t result;
310 
311   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
312   return(result);
313 }
314 #endif
315 
316 
317 /**
318   \brief   Set Main Stack Pointer
319   \details Assigns the given value to the Main Stack Pointer (MSP).
320   \param [in]    topOfMainStack  Main Stack Pointer value to set
321  */
__set_MSP(uint32_t topOfMainStack)322 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
323 {
324   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
325 }
326 
327 
328 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
329 /**
330   \brief   Set Main Stack Pointer (non-secure)
331   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
332   \param [in]    topOfMainStack  Main Stack Pointer value to set
333  */
__TZ_set_MSP_NS(uint32_t topOfMainStack)334 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
335 {
336   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
337 }
338 #endif
339 
340 
341 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
342 /**
343   \brief   Get Stack Pointer (non-secure)
344   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
345   \return               SP Register value
346  */
__TZ_get_SP_NS(void)347 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
348 {
349   uint32_t result;
350 
351   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
352   return(result);
353 }
354 
355 
356 /**
357   \brief   Set Stack Pointer (non-secure)
358   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
359   \param [in]    topOfStack  Stack Pointer value to set
360  */
__TZ_set_SP_NS(uint32_t topOfStack)361 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
362 {
363   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
364 }
365 #endif
366 
367 
368 /**
369   \brief   Get Priority Mask
370   \details Returns the current state of the priority mask bit from the Priority Mask Register.
371   \return               Priority Mask value
372  */
__get_PRIMASK(void)373 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
374 {
375   uint32_t result;
376 
377   __ASM volatile ("MRS %0, primask" : "=r" (result) );
378   return(result);
379 }
380 
381 
382 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
383 /**
384   \brief   Get Priority Mask (non-secure)
385   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
386   \return               Priority Mask value
387  */
__TZ_get_PRIMASK_NS(void)388 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
389 {
390   uint32_t result;
391 
392   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
393   return(result);
394 }
395 #endif
396 
397 
398 /**
399   \brief   Set Priority Mask
400   \details Assigns the given value to the Priority Mask Register.
401   \param [in]    priMask  Priority Mask
402  */
__set_PRIMASK(uint32_t priMask)403 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
404 {
405   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
406 }
407 
408 
409 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
410 /**
411   \brief   Set Priority Mask (non-secure)
412   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
413   \param [in]    priMask  Priority Mask
414  */
__TZ_set_PRIMASK_NS(uint32_t priMask)415 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
416 {
417   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
418 }
419 #endif
420 
421 
422 #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
423      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
424      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
425 /**
426   \brief   Enable FIQ
427   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
428            Can only be executed in Privileged modes.
429  */
430 #define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
431 
432 
433 /**
434   \brief   Disable FIQ
435   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
436            Can only be executed in Privileged modes.
437  */
438 #define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
439 
440 
441 /**
442   \brief   Get Base Priority
443   \details Returns the current value of the Base Priority register.
444   \return               Base Priority register value
445  */
__get_BASEPRI(void)446 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
447 {
448   uint32_t result;
449 
450   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
451   return(result);
452 }
453 
454 
455 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
456 /**
457   \brief   Get Base Priority (non-secure)
458   \details Returns the current value of the non-secure Base Priority register when in secure state.
459   \return               Base Priority register value
460  */
__TZ_get_BASEPRI_NS(void)461 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
462 {
463   uint32_t result;
464 
465   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
466   return(result);
467 }
468 #endif
469 
470 
471 /**
472   \brief   Set Base Priority
473   \details Assigns the given value to the Base Priority register.
474   \param [in]    basePri  Base Priority value to set
475  */
__set_BASEPRI(uint32_t basePri)476 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
477 {
478   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
479 }
480 
481 
482 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
483 /**
484   \brief   Set Base Priority (non-secure)
485   \details Assigns the given value to the non-secure Base Priority register when in secure state.
486   \param [in]    basePri  Base Priority value to set
487  */
__TZ_set_BASEPRI_NS(uint32_t basePri)488 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
489 {
490   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
491 }
492 #endif
493 
494 
495 /**
496   \brief   Set Base Priority with condition
497   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
498            or the new value increases the BASEPRI priority level.
499   \param [in]    basePri  Base Priority value to set
500  */
__set_BASEPRI_MAX(uint32_t basePri)501 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
502 {
503   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
504 }
505 
506 
507 /**
508   \brief   Get Fault Mask
509   \details Returns the current value of the Fault Mask register.
510   \return               Fault Mask register value
511  */
__get_FAULTMASK(void)512 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
513 {
514   uint32_t result;
515 
516   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
517   return(result);
518 }
519 
520 
521 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
522 /**
523   \brief   Get Fault Mask (non-secure)
524   \details Returns the current value of the non-secure Fault Mask register when in secure state.
525   \return               Fault Mask register value
526  */
__TZ_get_FAULTMASK_NS(void)527 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
528 {
529   uint32_t result;
530 
531   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
532   return(result);
533 }
534 #endif
535 
536 
537 /**
538   \brief   Set Fault Mask
539   \details Assigns the given value to the Fault Mask register.
540   \param [in]    faultMask  Fault Mask value to set
541  */
__set_FAULTMASK(uint32_t faultMask)542 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
543 {
544   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
545 }
546 
547 
548 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
549 /**
550   \brief   Set Fault Mask (non-secure)
551   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
552   \param [in]    faultMask  Fault Mask value to set
553  */
__TZ_set_FAULTMASK_NS(uint32_t faultMask)554 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
555 {
556   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
557 }
558 #endif
559 
560 #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
561            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
562            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
563 
564 
565 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
566      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
567 
568 /**
569   \brief   Get Process Stack Pointer Limit
570   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
571   Stack Pointer Limit register hence zero is returned always in non-secure
572   mode.
573 
574   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
575   \return               PSPLIM Register value
576  */
__get_PSPLIM(void)577 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
578 {
579 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
580     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
581     // without main extensions, the non-secure PSPLIM is RAZ/WI
582   return 0U;
583 #else
584   uint32_t result;
585   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
586   return result;
587 #endif
588 }
589 
590 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
591 /**
592   \brief   Get Process Stack Pointer Limit (non-secure)
593   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
594   Stack Pointer Limit register hence zero is returned always in non-secure
595   mode.
596 
597   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
598   \return               PSPLIM Register value
599  */
__TZ_get_PSPLIM_NS(void)600 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
601 {
602 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
603   // without main extensions, the non-secure PSPLIM is RAZ/WI
604   return 0U;
605 #else
606   uint32_t result;
607   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
608   return result;
609 #endif
610 }
611 #endif
612 
613 
614 /**
615   \brief   Set Process Stack Pointer Limit
616   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
617   Stack Pointer Limit register hence the write is silently ignored in non-secure
618   mode.
619 
620   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
621   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
622  */
__set_PSPLIM(uint32_t ProcStackPtrLimit)623 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
624 {
625 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
626     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
627   // without main extensions, the non-secure PSPLIM is RAZ/WI
628   (void)ProcStackPtrLimit;
629 #else
630   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
631 #endif
632 }
633 
634 
635 #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
636 /**
637   \brief   Set Process Stack Pointer (non-secure)
638   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
639   Stack Pointer Limit register hence the write is silently ignored in non-secure
640   mode.
641 
642   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
643   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
644  */
__TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)645 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
646 {
647 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
648   // without main extensions, the non-secure PSPLIM is RAZ/WI
649   (void)ProcStackPtrLimit;
650 #else
651   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
652 #endif
653 }
654 #endif
655 
656 
657 /**
658   \brief   Get Main Stack Pointer Limit
659   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
660   Stack Pointer Limit register hence zero is returned always.
661 
662   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
663   \return               MSPLIM Register value
664  */
__get_MSPLIM(void)665 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
666 {
667 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
668     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
669   // without main extensions, the non-secure MSPLIM is RAZ/WI
670   return 0U;
671 #else
672   uint32_t result;
673   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
674   return result;
675 #endif
676 }
677 
678 
679 #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
680 /**
681   \brief   Get Main Stack Pointer Limit (non-secure)
682   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
683   Stack Pointer Limit register hence zero is returned always.
684 
685   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
686   \return               MSPLIM Register value
687  */
__TZ_get_MSPLIM_NS(void)688 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
689 {
690 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
691   // without main extensions, the non-secure MSPLIM is RAZ/WI
692   return 0U;
693 #else
694   uint32_t result;
695   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
696   return result;
697 #endif
698 }
699 #endif
700 
701 
702 /**
703   \brief   Set Main Stack Pointer Limit
704   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
705   Stack Pointer Limit register hence the write is silently ignored.
706 
707   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
708   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
709  */
__set_MSPLIM(uint32_t MainStackPtrLimit)710 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
711 {
712 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
713     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
714   // without main extensions, the non-secure MSPLIM is RAZ/WI
715   (void)MainStackPtrLimit;
716 #else
717   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
718 #endif
719 }
720 
721 
722 #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
723 /**
724   \brief   Set Main Stack Pointer Limit (non-secure)
725   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
726   Stack Pointer Limit register hence the write is silently ignored.
727 
728   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
729   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
730  */
__TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)731 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
732 {
733 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
734   // without main extensions, the non-secure MSPLIM is RAZ/WI
735   (void)MainStackPtrLimit;
736 #else
737   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
738 #endif
739 }
740 #endif
741 
742 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
743            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
744 
745 /**
746   \brief   Get FPSCR
747   \details Returns the current value of the Floating Point Status/Control register.
748   \return               Floating Point Status/Control register value
749  */
750 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
751      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
752 #define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
753 #else
754 #define __get_FPSCR()      ((uint32_t)0U)
755 #endif
756 
757 /**
758   \brief   Set FPSCR
759   \details Assigns the given value to the Floating Point Status/Control register.
760   \param [in]    fpscr  Floating Point Status/Control value to set
761  */
762 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
763      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
764 #define __set_FPSCR      __builtin_arm_set_fpscr
765 #else
766 #define __set_FPSCR(x)      ((void)(x))
767 #endif
768 
769 
770 /*@} end of CMSIS_Core_RegAccFunctions */
771 
772 
773 /* ##########################  Core Instruction Access  ######################### */
774 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
775   Access to dedicated instructions
776   @{
777 */
778 
779 /* Define macros for porting to both thumb1 and thumb2.
780  * For thumb1, use low register (r0-r7), specified by constraint "l"
781  * Otherwise, use general registers, specified by constraint "r" */
782 #if defined (__thumb__) && !defined (__thumb2__)
783 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
784 #define __CMSIS_GCC_USE_REG(r) "l" (r)
785 #else
786 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
787 #define __CMSIS_GCC_USE_REG(r) "r" (r)
788 #endif
789 
790 /**
791   \brief   No Operation
792   \details No Operation does nothing. This instruction can be used for code alignment purposes.
793  */
794 #define __NOP          __builtin_arm_nop
795 
796 /**
797   \brief   Wait For Interrupt
798   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
799  */
800 #define __WFI          __builtin_arm_wfi
801 
802 
803 /**
804   \brief   Wait For Event
805   \details Wait For Event is a hint instruction that permits the processor to enter
806            a low-power state until one of a number of events occurs.
807  */
808 #define __WFE          __builtin_arm_wfe
809 
810 
811 /**
812   \brief   Send Event
813   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
814  */
815 #define __SEV          __builtin_arm_sev
816 
817 
818 /**
819   \brief   Instruction Synchronization Barrier
820   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
821            so that all instructions following the ISB are fetched from cache or memory,
822            after the instruction has been completed.
823  */
824 #define __ISB()        __builtin_arm_isb(0xF)
825 
826 /**
827   \brief   Data Synchronization Barrier
828   \details Acts as a special kind of Data Memory Barrier.
829            It completes when all explicit memory accesses before this instruction complete.
830  */
831 #define __DSB()        __builtin_arm_dsb(0xF)
832 
833 
834 /**
835   \brief   Data Memory Barrier
836   \details Ensures the apparent order of the explicit memory operations before
837            and after the instruction, without ensuring their completion.
838  */
839 #define __DMB()        __builtin_arm_dmb(0xF)
840 
841 
842 /**
843   \brief   Reverse byte order (32 bit)
844   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
845   \param [in]    value  Value to reverse
846   \return               Reversed value
847  */
848 #define __REV(value)   __builtin_bswap32(value)
849 
850 
851 /**
852   \brief   Reverse byte order (16 bit)
853   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
854   \param [in]    value  Value to reverse
855   \return               Reversed value
856  */
857 #define __REV16(value) __ROR(__REV(value), 16)
858 
859 
860 /**
861   \brief   Reverse byte order (16 bit)
862   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
863   \param [in]    value  Value to reverse
864   \return               Reversed value
865  */
866 #define __REVSH(value) (int16_t)__builtin_bswap16(value)
867 
868 
869 /**
870   \brief   Rotate Right in unsigned value (32 bit)
871   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
872   \param [in]    op1  Value to rotate
873   \param [in]    op2  Number of Bits to rotate
874   \return               Rotated value
875  */
__ROR(uint32_t op1,uint32_t op2)876 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
877 {
878   op2 %= 32U;
879   if (op2 == 0U)
880   {
881     return op1;
882   }
883   return (op1 >> op2) | (op1 << (32U - op2));
884 }
885 
886 
887 /**
888   \brief   Breakpoint
889   \details Causes the processor to enter Debug state.
890            Debug tools can use this to investigate system state when the instruction at a particular address is reached.
891   \param [in]    value  is ignored by the processor.
892                  If required, a debugger can use it to store additional information about the breakpoint.
893  */
894 #define __BKPT(value)     __ASM volatile ("bkpt "#value)
895 
896 
897 /**
898   \brief   Reverse bit order of value
899   \details Reverses the bit order of the given value.
900   \param [in]    value  Value to reverse
901   \return               Reversed value
902  */
903 #define __RBIT            __builtin_arm_rbit
904 
905 /**
906   \brief   Count leading zeros
907   \details Counts the number of leading zeros of a data value.
908   \param [in]  value  Value to count the leading zeros
909   \return             number of leading zeros in value
910  */
__CLZ(uint32_t value)911 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
912 {
913   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
914      __builtin_clz(0) is undefined behaviour, so handle this case specially.
915      This guarantees ARM-compatible results if happening to compile on a non-ARM
916      target, and ensures the compiler doesn't decide to activate any
917      optimisations using the logic "value was passed to __builtin_clz, so it
918      is non-zero".
919      ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
920      single CLZ instruction.
921    */
922   if (value == 0U)
923   {
924     return 32U;
925   }
926   return __builtin_clz(value);
927 }
928 
929 
930 #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
931      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
932      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
933      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
934 /**
935   \brief   LDR Exclusive (8 bit)
936   \details Executes a exclusive LDR instruction for 8 bit value.
937   \param [in]    ptr  Pointer to data
938   \return             value of type uint8_t at (*ptr)
939  */
940 #define __LDREXB        (uint8_t)__builtin_arm_ldrex
941 
942 
943 /**
944   \brief   LDR Exclusive (16 bit)
945   \details Executes a exclusive LDR instruction for 16 bit values.
946   \param [in]    ptr  Pointer to data
947   \return        value of type uint16_t at (*ptr)
948  */
949 #define __LDREXH        (uint16_t)__builtin_arm_ldrex
950 
951 
952 /**
953   \brief   LDR Exclusive (32 bit)
954   \details Executes a exclusive LDR instruction for 32 bit values.
955   \param [in]    ptr  Pointer to data
956   \return        value of type uint32_t at (*ptr)
957  */
958 #define __LDREXW        (uint32_t)__builtin_arm_ldrex
959 
960 
961 /**
962   \brief   STR Exclusive (8 bit)
963   \details Executes a exclusive STR instruction for 8 bit values.
964   \param [in]  value  Value to store
965   \param [in]    ptr  Pointer to location
966   \return          0  Function succeeded
967   \return          1  Function failed
968  */
969 #define __STREXB        (uint32_t)__builtin_arm_strex
970 
971 
972 /**
973   \brief   STR Exclusive (16 bit)
974   \details Executes a exclusive STR instruction for 16 bit values.
975   \param [in]  value  Value to store
976   \param [in]    ptr  Pointer to location
977   \return          0  Function succeeded
978   \return          1  Function failed
979  */
980 #define __STREXH        (uint32_t)__builtin_arm_strex
981 
982 
983 /**
984   \brief   STR Exclusive (32 bit)
985   \details Executes a exclusive STR instruction for 32 bit values.
986   \param [in]  value  Value to store
987   \param [in]    ptr  Pointer to location
988   \return          0  Function succeeded
989   \return          1  Function failed
990  */
991 #define __STREXW        (uint32_t)__builtin_arm_strex
992 
993 
994 /**
995   \brief   Remove the exclusive lock
996   \details Removes the exclusive lock which is created by LDREX.
997  */
998 #define __CLREX             __builtin_arm_clrex
999 
1000 #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
1001            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
1002            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1003            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
1004 
1005 
1006 #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
1007      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
1008      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
1009 
1010 /**
1011   \brief   Signed Saturate
1012   \details Saturates a signed value.
1013   \param [in]  value  Value to be saturated
1014   \param [in]    sat  Bit position to saturate to (1..32)
1015   \return             Saturated value
1016  */
1017 #define __SSAT             __builtin_arm_ssat
1018 
1019 
1020 /**
1021   \brief   Unsigned Saturate
1022   \details Saturates an unsigned value.
1023   \param [in]  value  Value to be saturated
1024   \param [in]    sat  Bit position to saturate to (0..31)
1025   \return             Saturated value
1026  */
1027 #define __USAT             __builtin_arm_usat
1028 
1029 
1030 /**
1031   \brief   Rotate Right with Extend (32 bit)
1032   \details Moves each bit of a bitstring right by one bit.
1033            The carry input is shifted in at the left end of the bitstring.
1034   \param [in]    value  Value to rotate
1035   \return               Rotated value
1036  */
__RRX(uint32_t value)1037 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
1038 {
1039   uint32_t result;
1040 
1041   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1042   return(result);
1043 }
1044 
1045 
1046 /**
1047   \brief   LDRT Unprivileged (8 bit)
1048   \details Executes a Unprivileged LDRT instruction for 8 bit value.
1049   \param [in]    ptr  Pointer to data
1050   \return             value of type uint8_t at (*ptr)
1051  */
__LDRBT(volatile uint8_t * ptr)1052 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
1053 {
1054   uint32_t result;
1055 
1056   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
1057   return ((uint8_t) result);    /* Add explicit type cast here */
1058 }
1059 
1060 
1061 /**
1062   \brief   LDRT Unprivileged (16 bit)
1063   \details Executes a Unprivileged LDRT instruction for 16 bit values.
1064   \param [in]    ptr  Pointer to data
1065   \return        value of type uint16_t at (*ptr)
1066  */
__LDRHT(volatile uint16_t * ptr)1067 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
1068 {
1069   uint32_t result;
1070 
1071   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
1072   return ((uint16_t) result);    /* Add explicit type cast here */
1073 }
1074 
1075 
1076 /**
1077   \brief   LDRT Unprivileged (32 bit)
1078   \details Executes a Unprivileged LDRT instruction for 32 bit values.
1079   \param [in]    ptr  Pointer to data
1080   \return        value of type uint32_t at (*ptr)
1081  */
__LDRT(volatile uint32_t * ptr)1082 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
1083 {
1084   uint32_t result;
1085 
1086   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
1087   return(result);
1088 }
1089 
1090 
1091 /**
1092   \brief   STRT Unprivileged (8 bit)
1093   \details Executes a Unprivileged STRT instruction for 8 bit values.
1094   \param [in]  value  Value to store
1095   \param [in]    ptr  Pointer to location
1096  */
__STRBT(uint8_t value,volatile uint8_t * ptr)1097 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
1098 {
1099   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1100 }
1101 
1102 
1103 /**
1104   \brief   STRT Unprivileged (16 bit)
1105   \details Executes a Unprivileged STRT instruction for 16 bit values.
1106   \param [in]  value  Value to store
1107   \param [in]    ptr  Pointer to location
1108  */
__STRHT(uint16_t value,volatile uint16_t * ptr)1109 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
1110 {
1111   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1112 }
1113 
1114 
1115 /**
1116   \brief   STRT Unprivileged (32 bit)
1117   \details Executes a Unprivileged STRT instruction for 32 bit values.
1118   \param [in]  value  Value to store
1119   \param [in]    ptr  Pointer to location
1120  */
__STRT(uint32_t value,volatile uint32_t * ptr)1121 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
1122 {
1123   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
1124 }
1125 
1126 #else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
1127            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
1128            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
1129 
1130 /**
1131   \brief   Signed Saturate
1132   \details Saturates a signed value.
1133   \param [in]  value  Value to be saturated
1134   \param [in]    sat  Bit position to saturate to (1..32)
1135   \return             Saturated value
1136  */
__SSAT(int32_t val,uint32_t sat)1137 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
1138 {
1139   if ((sat >= 1U) && (sat <= 32U))
1140   {
1141     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
1142     const int32_t min = -1 - max ;
1143     if (val > max)
1144     {
1145       return max;
1146     }
1147     else if (val < min)
1148     {
1149       return min;
1150     }
1151   }
1152   return val;
1153 }
1154 
1155 /**
1156   \brief   Unsigned Saturate
1157   \details Saturates an unsigned value.
1158   \param [in]  value  Value to be saturated
1159   \param [in]    sat  Bit position to saturate to (0..31)
1160   \return             Saturated value
1161  */
__USAT(int32_t val,uint32_t sat)1162 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
1163 {
1164   if (sat <= 31U)
1165   {
1166     const uint32_t max = ((1U << sat) - 1U);
1167     if (val > (int32_t)max)
1168     {
1169       return max;
1170     }
1171     else if (val < 0)
1172     {
1173       return 0U;
1174     }
1175   }
1176   return (uint32_t)val;
1177 }
1178 
1179 #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
1180            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
1181            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
1182 
1183 
1184 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1185      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
1186 /**
1187   \brief   Load-Acquire (8 bit)
1188   \details Executes a LDAB instruction for 8 bit value.
1189   \param [in]    ptr  Pointer to data
1190   \return             value of type uint8_t at (*ptr)
1191  */
__LDAB(volatile uint8_t * ptr)1192 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
1193 {
1194   uint32_t result;
1195 
1196   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
1197   return ((uint8_t) result);
1198 }
1199 
1200 
1201 /**
1202   \brief   Load-Acquire (16 bit)
1203   \details Executes a LDAH instruction for 16 bit values.
1204   \param [in]    ptr  Pointer to data
1205   \return        value of type uint16_t at (*ptr)
1206  */
__LDAH(volatile uint16_t * ptr)1207 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
1208 {
1209   uint32_t result;
1210 
1211   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
1212   return ((uint16_t) result);
1213 }
1214 
1215 
1216 /**
1217   \brief   Load-Acquire (32 bit)
1218   \details Executes a LDA instruction for 32 bit values.
1219   \param [in]    ptr  Pointer to data
1220   \return        value of type uint32_t at (*ptr)
1221  */
__LDA(volatile uint32_t * ptr)1222 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
1223 {
1224   uint32_t result;
1225 
1226   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
1227   return(result);
1228 }
1229 
1230 
1231 /**
1232   \brief   Store-Release (8 bit)
1233   \details Executes a STLB instruction for 8 bit values.
1234   \param [in]  value  Value to store
1235   \param [in]    ptr  Pointer to location
1236  */
__STLB(uint8_t value,volatile uint8_t * ptr)1237 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
1238 {
1239   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1240 }
1241 
1242 
1243 /**
1244   \brief   Store-Release (16 bit)
1245   \details Executes a STLH instruction for 16 bit values.
1246   \param [in]  value  Value to store
1247   \param [in]    ptr  Pointer to location
1248  */
__STLH(uint16_t value,volatile uint16_t * ptr)1249 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
1250 {
1251   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1252 }
1253 
1254 
1255 /**
1256   \brief   Store-Release (32 bit)
1257   \details Executes a STL instruction for 32 bit values.
1258   \param [in]  value  Value to store
1259   \param [in]    ptr  Pointer to location
1260  */
__STL(uint32_t value,volatile uint32_t * ptr)1261 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
1262 {
1263   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1264 }
1265 
1266 
1267 /**
1268   \brief   Load-Acquire Exclusive (8 bit)
1269   \details Executes a LDAB exclusive instruction for 8 bit value.
1270   \param [in]    ptr  Pointer to data
1271   \return             value of type uint8_t at (*ptr)
1272  */
1273 #define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
1274 
1275 
1276 /**
1277   \brief   Load-Acquire Exclusive (16 bit)
1278   \details Executes a LDAH exclusive instruction for 16 bit values.
1279   \param [in]    ptr  Pointer to data
1280   \return        value of type uint16_t at (*ptr)
1281  */
1282 #define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
1283 
1284 
1285 /**
1286   \brief   Load-Acquire Exclusive (32 bit)
1287   \details Executes a LDA exclusive instruction for 32 bit values.
1288   \param [in]    ptr  Pointer to data
1289   \return        value of type uint32_t at (*ptr)
1290  */
1291 #define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
1292 
1293 
1294 /**
1295   \brief   Store-Release Exclusive (8 bit)
1296   \details Executes a STLB exclusive instruction for 8 bit values.
1297   \param [in]  value  Value to store
1298   \param [in]    ptr  Pointer to location
1299   \return          0  Function succeeded
1300   \return          1  Function failed
1301  */
1302 #define     __STLEXB                 (uint32_t)__builtin_arm_stlex
1303 
1304 
1305 /**
1306   \brief   Store-Release Exclusive (16 bit)
1307   \details Executes a STLH exclusive instruction for 16 bit values.
1308   \param [in]  value  Value to store
1309   \param [in]    ptr  Pointer to location
1310   \return          0  Function succeeded
1311   \return          1  Function failed
1312  */
1313 #define     __STLEXH                 (uint32_t)__builtin_arm_stlex
1314 
1315 
1316 /**
1317   \brief   Store-Release Exclusive (32 bit)
1318   \details Executes a STL exclusive instruction for 32 bit values.
1319   \param [in]  value  Value to store
1320   \param [in]    ptr  Pointer to location
1321   \return          0  Function succeeded
1322   \return          1  Function failed
1323  */
1324 #define     __STLEX                  (uint32_t)__builtin_arm_stlex
1325 
1326 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1327            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
1328 
1329 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
1330 
1331 
1332 /* ###################  Compiler specific Intrinsics  ########################### */
1333 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1334   Access to dedicated SIMD instructions
1335   @{
1336 */
1337 
1338 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1339 
__SADD8(uint32_t op1,uint32_t op2)1340 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
1341 {
1342   uint32_t result;
1343 
1344   __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1345   return(result);
1346 }
1347 
__QADD8(uint32_t op1,uint32_t op2)1348 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
1349 {
1350   uint32_t result;
1351 
1352   __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1353   return(result);
1354 }
1355 
__SHADD8(uint32_t op1,uint32_t op2)1356 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
1357 {
1358   uint32_t result;
1359 
1360   __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1361   return(result);
1362 }
1363 
__UADD8(uint32_t op1,uint32_t op2)1364 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
1365 {
1366   uint32_t result;
1367 
1368   __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1369   return(result);
1370 }
1371 
__UQADD8(uint32_t op1,uint32_t op2)1372 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
1373 {
1374   uint32_t result;
1375 
1376   __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1377   return(result);
1378 }
1379 
__UHADD8(uint32_t op1,uint32_t op2)1380 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
1381 {
1382   uint32_t result;
1383 
1384   __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1385   return(result);
1386 }
1387 
1388 
__SSUB8(uint32_t op1,uint32_t op2)1389 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
1390 {
1391   uint32_t result;
1392 
1393   __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1394   return(result);
1395 }
1396 
__QSUB8(uint32_t op1,uint32_t op2)1397 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
1398 {
1399   uint32_t result;
1400 
1401   __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1402   return(result);
1403 }
1404 
__SHSUB8(uint32_t op1,uint32_t op2)1405 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
1406 {
1407   uint32_t result;
1408 
1409   __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1410   return(result);
1411 }
1412 
__USUB8(uint32_t op1,uint32_t op2)1413 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
1414 {
1415   uint32_t result;
1416 
1417   __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1418   return(result);
1419 }
1420 
__UQSUB8(uint32_t op1,uint32_t op2)1421 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
1422 {
1423   uint32_t result;
1424 
1425   __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1426   return(result);
1427 }
1428 
__UHSUB8(uint32_t op1,uint32_t op2)1429 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
1430 {
1431   uint32_t result;
1432 
1433   __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1434   return(result);
1435 }
1436 
1437 
__SADD16(uint32_t op1,uint32_t op2)1438 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
1439 {
1440   uint32_t result;
1441 
1442   __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1443   return(result);
1444 }
1445 
__QADD16(uint32_t op1,uint32_t op2)1446 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
1447 {
1448   uint32_t result;
1449 
1450   __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1451   return(result);
1452 }
1453 
__SHADD16(uint32_t op1,uint32_t op2)1454 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
1455 {
1456   uint32_t result;
1457 
1458   __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1459   return(result);
1460 }
1461 
__UADD16(uint32_t op1,uint32_t op2)1462 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
1463 {
1464   uint32_t result;
1465 
1466   __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1467   return(result);
1468 }
1469 
__UQADD16(uint32_t op1,uint32_t op2)1470 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
1471 {
1472   uint32_t result;
1473 
1474   __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1475   return(result);
1476 }
1477 
__UHADD16(uint32_t op1,uint32_t op2)1478 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
1479 {
1480   uint32_t result;
1481 
1482   __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1483   return(result);
1484 }
1485 
__SSUB16(uint32_t op1,uint32_t op2)1486 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
1487 {
1488   uint32_t result;
1489 
1490   __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1491   return(result);
1492 }
1493 
__QSUB16(uint32_t op1,uint32_t op2)1494 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
1495 {
1496   uint32_t result;
1497 
1498   __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1499   return(result);
1500 }
1501 
__SHSUB16(uint32_t op1,uint32_t op2)1502 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
1503 {
1504   uint32_t result;
1505 
1506   __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1507   return(result);
1508 }
1509 
__USUB16(uint32_t op1,uint32_t op2)1510 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
1511 {
1512   uint32_t result;
1513 
1514   __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1515   return(result);
1516 }
1517 
__UQSUB16(uint32_t op1,uint32_t op2)1518 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
1519 {
1520   uint32_t result;
1521 
1522   __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1523   return(result);
1524 }
1525 
__UHSUB16(uint32_t op1,uint32_t op2)1526 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
1527 {
1528   uint32_t result;
1529 
1530   __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1531   return(result);
1532 }
1533 
__SASX(uint32_t op1,uint32_t op2)1534 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
1535 {
1536   uint32_t result;
1537 
1538   __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1539   return(result);
1540 }
1541 
__QASX(uint32_t op1,uint32_t op2)1542 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
1543 {
1544   uint32_t result;
1545 
1546   __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1547   return(result);
1548 }
1549 
__SHASX(uint32_t op1,uint32_t op2)1550 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
1551 {
1552   uint32_t result;
1553 
1554   __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1555   return(result);
1556 }
1557 
__UASX(uint32_t op1,uint32_t op2)1558 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
1559 {
1560   uint32_t result;
1561 
1562   __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1563   return(result);
1564 }
1565 
__UQASX(uint32_t op1,uint32_t op2)1566 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
1567 {
1568   uint32_t result;
1569 
1570   __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1571   return(result);
1572 }
1573 
__UHASX(uint32_t op1,uint32_t op2)1574 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
1575 {
1576   uint32_t result;
1577 
1578   __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1579   return(result);
1580 }
1581 
__SSAX(uint32_t op1,uint32_t op2)1582 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
1583 {
1584   uint32_t result;
1585 
1586   __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1587   return(result);
1588 }
1589 
__QSAX(uint32_t op1,uint32_t op2)1590 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
1591 {
1592   uint32_t result;
1593 
1594   __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1595   return(result);
1596 }
1597 
__SHSAX(uint32_t op1,uint32_t op2)1598 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
1599 {
1600   uint32_t result;
1601 
1602   __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1603   return(result);
1604 }
1605 
__USAX(uint32_t op1,uint32_t op2)1606 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
1607 {
1608   uint32_t result;
1609 
1610   __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1611   return(result);
1612 }
1613 
__UQSAX(uint32_t op1,uint32_t op2)1614 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
1615 {
1616   uint32_t result;
1617 
1618   __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1619   return(result);
1620 }
1621 
__UHSAX(uint32_t op1,uint32_t op2)1622 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
1623 {
1624   uint32_t result;
1625 
1626   __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1627   return(result);
1628 }
1629 
__USAD8(uint32_t op1,uint32_t op2)1630 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
1631 {
1632   uint32_t result;
1633 
1634   __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1635   return(result);
1636 }
1637 
__USADA8(uint32_t op1,uint32_t op2,uint32_t op3)1638 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
1639 {
1640   uint32_t result;
1641 
1642   __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1643   return(result);
1644 }
1645 
1646 #define __SSAT16(ARG1,ARG2) \
1647 ({                          \
1648   int32_t __RES, __ARG1 = (ARG1); \
1649   __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
1650   __RES; \
1651  })
1652 
1653 #define __USAT16(ARG1,ARG2) \
1654 ({                          \
1655   uint32_t __RES, __ARG1 = (ARG1); \
1656   __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
1657   __RES; \
1658  })
1659 
__UXTB16(uint32_t op1)1660 __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
1661 {
1662   uint32_t result;
1663 
1664   __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
1665   return(result);
1666 }
1667 
__UXTAB16(uint32_t op1,uint32_t op2)1668 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
1669 {
1670   uint32_t result;
1671 
1672   __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1673   return(result);
1674 }
1675 
__SXTB16(uint32_t op1)1676 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
1677 {
1678   uint32_t result;
1679 
1680   __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
1681   return(result);
1682 }
1683 
__SXTAB16(uint32_t op1,uint32_t op2)1684 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
1685 {
1686   uint32_t result;
1687 
1688   __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1689   return(result);
1690 }
1691 
__SMUAD(uint32_t op1,uint32_t op2)1692 __STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
1693 {
1694   uint32_t result;
1695 
1696   __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1697   return(result);
1698 }
1699 
__SMUADX(uint32_t op1,uint32_t op2)1700 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
1701 {
1702   uint32_t result;
1703 
1704   __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1705   return(result);
1706 }
1707 
__SMLAD(uint32_t op1,uint32_t op2,uint32_t op3)1708 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
1709 {
1710   uint32_t result;
1711 
1712   __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1713   return(result);
1714 }
1715 
__SMLADX(uint32_t op1,uint32_t op2,uint32_t op3)1716 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
1717 {
1718   uint32_t result;
1719 
1720   __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1721   return(result);
1722 }
1723 
__SMLALD(uint32_t op1,uint32_t op2,uint64_t acc)1724 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
1725 {
1726   union llreg_u{
1727     uint32_t w32[2];
1728     uint64_t w64;
1729   } llr;
1730   llr.w64 = acc;
1731 
1732 #ifndef __ARMEB__   /* Little endian */
1733   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1734 #else               /* Big endian */
1735   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1736 #endif
1737 
1738   return(llr.w64);
1739 }
1740 
__SMLALDX(uint32_t op1,uint32_t op2,uint64_t acc)1741 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
1742 {
1743   union llreg_u{
1744     uint32_t w32[2];
1745     uint64_t w64;
1746   } llr;
1747   llr.w64 = acc;
1748 
1749 #ifndef __ARMEB__   /* Little endian */
1750   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1751 #else               /* Big endian */
1752   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1753 #endif
1754 
1755   return(llr.w64);
1756 }
1757 
__SMUSD(uint32_t op1,uint32_t op2)1758 __STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
1759 {
1760   uint32_t result;
1761 
1762   __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1763   return(result);
1764 }
1765 
__SMUSDX(uint32_t op1,uint32_t op2)1766 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
1767 {
1768   uint32_t result;
1769 
1770   __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1771   return(result);
1772 }
1773 
__SMLSD(uint32_t op1,uint32_t op2,uint32_t op3)1774 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
1775 {
1776   uint32_t result;
1777 
1778   __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1779   return(result);
1780 }
1781 
__SMLSDX(uint32_t op1,uint32_t op2,uint32_t op3)1782 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
1783 {
1784   uint32_t result;
1785 
1786   __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1787   return(result);
1788 }
1789 
__SMLSLD(uint32_t op1,uint32_t op2,uint64_t acc)1790 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
1791 {
1792   union llreg_u{
1793     uint32_t w32[2];
1794     uint64_t w64;
1795   } llr;
1796   llr.w64 = acc;
1797 
1798 #ifndef __ARMEB__   /* Little endian */
1799   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1800 #else               /* Big endian */
1801   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1802 #endif
1803 
1804   return(llr.w64);
1805 }
1806 
__SMLSLDX(uint32_t op1,uint32_t op2,uint64_t acc)1807 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
1808 {
1809   union llreg_u{
1810     uint32_t w32[2];
1811     uint64_t w64;
1812   } llr;
1813   llr.w64 = acc;
1814 
1815 #ifndef __ARMEB__   /* Little endian */
1816   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1817 #else               /* Big endian */
1818   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1819 #endif
1820 
1821   return(llr.w64);
1822 }
1823 
__SEL(uint32_t op1,uint32_t op2)1824 __STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
1825 {
1826   uint32_t result;
1827 
1828   __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1829   return(result);
1830 }
1831 
__QADD(int32_t op1,int32_t op2)1832 __STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
1833 {
1834   int32_t result;
1835 
1836   __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1837   return(result);
1838 }
1839 
__QSUB(int32_t op1,int32_t op2)1840 __STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
1841 {
1842   int32_t result;
1843 
1844   __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1845   return(result);
1846 }
1847 
1848 #define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
1849                                            ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
1850 
1851 #define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
1852                                            ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
1853 
__SMMLA(int32_t op1,int32_t op2,int32_t op3)1854 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1855 {
1856   int32_t result;
1857 
1858   __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
1859   return(result);
1860 }
1861 
1862 #endif /* (__ARM_FEATURE_DSP == 1) */
1863 /*@} end of group CMSIS_SIMD_intrinsics */
1864 
1865 
1866 #endif /* __CMSIS_ARMCLANG_H */
1867