1# powerpc cpu description file 2# this file is read by genmdesc to pruduce a table with all the relevant information 3# about the cpu instructions that may be used by the regsiter allocator, the scheduler 4# and other parts of the arch-dependent part of mini. 5# 6# An opcode name is followed by a colon and optional specifiers. 7# A specifier has a name, a colon and a value. Specifiers are separated by white space. 8# Here is a description of the specifiers valid for this file and their possible values. 9# 10# dest:register describes the destination register of an instruction 11# src1:register describes the first source register of an instruction 12# src2:register describes the second source register of an instruction 13# 14# register may have the following values: 15# i integer register 16# a r3 register (output from calls) 17# b base register (used in address references) 18# f floating point register 19# 20# len:number describe the maximun length in bytes of the instruction 21# number is a positive integer 22# 23# cost:number describe how many cycles are needed to complete the instruction (unused) 24# 25# clob:spec describe if the instruction clobbers registers or has special needs 26# 27# spec can be one of the following characters: 28# c clobbers caller-save registers 29# r 'reserves' the destination register until a later instruction unreserves it 30# used mostly to set output registers in function calls 31# 32# flags:spec describe if the instruction uses or sets the flags (unused) 33# 34# spec can be one of the following chars: 35# s sets the flags 36# u uses the flags 37# m uses and modifies the flags 38# 39# res:spec describe what units are used in the processor (unused) 40# 41# delay: describe delay slots (unused) 42# 43# the required specifiers are: len, clob (if registers are clobbered), the registers 44# specifiers if the registers are actually used, flags (when scheduling is implemented). 45# 46# See the code in mini-x86.c for more details on how the specifiers are used. 47# 48memory_barrier: len:4 49nop: len:4 50relaxed_nop: len:4 51break: len:32 52seq_point: len:24 53il_seq_point: len:0 54jmp: len:108 55tailcall: len:120 clob:c 56call: dest:a clob:c len:16 57br: len:4 58throw: src1:i len:20 59rethrow: src1:i len:20 60ckfinite: dest:f src1:f 61ppc_check_finite: src1:i len:16 62add_ovf_carry: dest:i src1:i src2:i len:16 63sub_ovf_carry: dest:i src1:i src2:i len:16 64add_ovf_un_carry: dest:i src1:i src2:i len:16 65sub_ovf_un_carry: dest:i src1:i src2:i len:16 66start_handler: len:32 67endfinally: len:28 68ceq: dest:i len:12 69cgt: dest:i len:12 70cgt.un: dest:i len:12 71clt: dest:i len:12 72clt.un: dest:i len:12 73localloc: dest:i src1:i len:60 74compare: src1:i src2:i len:4 75compare_imm: src1:i len:12 76fcompare: src1:f src2:f len:12 77oparglist: src1:i len:12 78setlret: src1:i src2:i len:12 79checkthis: src1:b len:4 80voidcall: len:16 clob:c 81voidcall_reg: src1:i len:16 clob:c 82voidcall_membase: src1:b len:16 clob:c 83fcall: dest:g len:16 clob:c 84fcall_reg: dest:g src1:i len:16 clob:c 85fcall_membase: dest:g src1:b len:16 clob:c 86lcall: dest:l len:16 clob:c 87lcall_reg: dest:l src1:i len:16 clob:c 88lcall_membase: dest:l src1:b len:16 clob:c 89vcall: len:16 clob:c 90vcall_reg: src1:i len:16 clob:c 91vcall_membase: src1:b len:16 clob:c 92call_reg: dest:a src1:i len:16 clob:c 93call_membase: dest:a src1:b len:16 clob:c 94iconst: dest:i len:8 95r4const: dest:f len:12 96r8const: dest:f len:24 97label: len:0 98store_membase_reg: dest:b src1:i len:12 99storei1_membase_reg: dest:b src1:i len:12 100storei2_membase_reg: dest:b src1:i len:12 101storei4_membase_reg: dest:b src1:i len:12 102storer4_membase_reg: dest:b src1:f len:16 103storer8_membase_reg: dest:b src1:f len:12 104load_membase: dest:i src1:b len:12 105loadi1_membase: dest:i src1:b len:16 106loadu1_membase: dest:i src1:b len:12 107loadi2_membase: dest:i src1:b len:12 108loadu2_membase: dest:i src1:b len:12 109loadi4_membase: dest:i src1:b len:12 110loadu4_membase: dest:i src1:b len:12 111loadr4_membase: dest:f src1:b len:12 112loadr8_membase: dest:f src1:b len:12 113load_memindex: dest:i src1:b src2:i len:4 114loadi1_memindex: dest:i src1:b src2:i len:8 115loadu1_memindex: dest:i src1:b src2:i len:4 116loadi2_memindex: dest:i src1:b src2:i len:4 117loadu2_memindex: dest:i src1:b src2:i len:4 118loadi4_memindex: dest:i src1:b src2:i len:4 119loadu4_memindex: dest:i src1:b src2:i len:4 120loadr4_memindex: dest:f src1:b src2:i len:4 121loadr8_memindex: dest:f src1:b src2:i len:4 122store_memindex: dest:b src1:i src2:i len:4 123storei1_memindex: dest:b src1:i src2:i len:4 124storei2_memindex: dest:b src1:i src2:i len:4 125storei4_memindex: dest:b src1:i src2:i len:4 126storer4_memindex: dest:b src1:i src2:i len:8 127storer8_memindex: dest:b src1:i src2:i len:4 128loadu4_mem: dest:i len:8 129move: dest:i src1:i len:4 130fmove: dest:f src1:f len:4 131move_f_to_i4: dest:i src1:f len:8 132move_i4_to_f: dest:f src1:i len:8 133add_imm: dest:i src1:i len:4 134sub_imm: dest:i src1:i len:4 135mul_imm: dest:i src1:i len:4 136# there is no actual support for division or reminder by immediate 137# we simulate them, though (but we need to change the burg rules 138# to allocate a symbolic reg for src2) 139div_imm: dest:i src1:i src2:i len:20 140div_un_imm: dest:i src1:i src2:i len:12 141rem_imm: dest:i src1:i src2:i len:28 142rem_un_imm: dest:i src1:i src2:i len:16 143and_imm: dest:i src1:i len:4 144or_imm: dest:i src1:i len:4 145xor_imm: dest:i src1:i len:4 146shl_imm: dest:i src1:i len:4 147shr_imm: dest:i src1:i len:4 148shr_un_imm: dest:i src1:i len:4 149cond_exc_eq: len:8 150cond_exc_ne_un: len:8 151cond_exc_lt: len:8 152cond_exc_lt_un: len:8 153cond_exc_gt: len:8 154cond_exc_gt_un: len:8 155cond_exc_ge: len:8 156cond_exc_ge_un: len:8 157cond_exc_le: len:8 158cond_exc_le_un: len:8 159cond_exc_ov: len:12 160cond_exc_no: len:8 161cond_exc_c: len:12 162cond_exc_nc: len:8 163long_conv_to_ovf_i: dest:i src1:i src2:i len:32 164long_mul_ovf: 165long_conv_to_r_un: dest:f src1:i src2:i len:37 166float_beq: len:8 167float_bne_un: len:8 168float_blt: len:8 169float_blt_un: len:8 170float_bgt: len:8 171float_bgt_un: len:8 172float_bge: len:8 173float_bge_un: len:8 174float_ble: len:8 175float_ble_un: len:8 176float_add: dest:f src1:f src2:f len:4 177float_sub: dest:f src1:f src2:f len:4 178float_mul: dest:f src1:f src2:f len:4 179float_div: dest:f src1:f src2:f len:4 180float_div_un: dest:f src1:f src2:f len:4 181float_rem: dest:f src1:f src2:f len:16 182float_rem_un: dest:f src1:f src2:f len:16 183float_neg: dest:f src1:f len:4 184float_not: dest:f src1:f len:4 185float_conv_to_i1: dest:i src1:f len:40 186float_conv_to_i2: dest:i src1:f len:40 187float_conv_to_i4: dest:i src1:f len:40 188float_conv_to_i8: dest:l src1:f len:40 189float_conv_to_r4: dest:f src1:f len:4 190float_conv_to_u4: dest:i src1:f len:40 191float_conv_to_u8: dest:l src1:f len:40 192float_conv_to_u2: dest:i src1:f len:40 193float_conv_to_u1: dest:i src1:f len:40 194float_conv_to_i: dest:i src1:f len:40 195float_ceq: dest:i src1:f src2:f len:16 196float_cgt: dest:i src1:f src2:f len:16 197float_cgt_un: dest:i src1:f src2:f len:20 198float_clt: dest:i src1:f src2:f len:16 199float_clt_un: dest:i src1:f src2:f len:20 200float_conv_to_u: dest:i src1:f len:36 201float_cneq: dest:i src1:f src2:f len:16 202float_cge: dest:i src1:f src2:f len:16 203float_cle: dest:i src1:f src2:f len:16 204call_handler: len:12 clob:c 205endfilter: src1:i len:32 206aot_const: dest:i len:8 207load_gotaddr: dest:i len:32 208got_entry: dest:i src1:b len:32 209sqrt: dest:f src1:f len:4 210adc: dest:i src1:i src2:i len:4 211addcc: dest:i src1:i src2:i len:4 212subcc: dest:i src1:i src2:i len:4 213addcc_imm: dest:i src1:i len:4 214sbb: dest:i src1:i src2:i len:4 215br_reg: src1:i len:8 216ppc_subfic: dest:i src1:i len:4 217ppc_subfze: dest:i src1:i len:4 218bigmul: len:12 dest:l src1:i src2:i 219bigmul_un: len:12 dest:l src1:i src2:i 220 221# Linear IR opcodes 222dummy_use: src1:i len:0 223dummy_store: len:0 224not_reached: len:0 225not_null: src1:i len:0 226 227# 32 bit opcodes 228int_add: dest:i src1:i src2:i len:4 229int_sub: dest:i src1:i src2:i len:4 230int_mul: dest:i src1:i src2:i len:4 231int_div: dest:i src1:i src2:i len:40 232int_div_un: dest:i src1:i src2:i len:16 233int_rem: dest:i src1:i src2:i len:48 234int_rem_un: dest:i src1:i src2:i len:24 235int_and: dest:i src1:i src2:i len:4 236int_or: dest:i src1:i src2:i len:4 237int_xor: dest:i src1:i src2:i len:4 238int_shl: dest:i src1:i src2:i len:4 239int_shr: dest:i src1:i src2:i len:4 240int_shr_un: dest:i src1:i src2:i len:4 241int_neg: dest:i src1:i len:4 242int_not: dest:i src1:i len:4 243int_conv_to_i1: dest:i src1:i len:8 244int_conv_to_i2: dest:i src1:i len:8 245int_conv_to_i4: dest:i src1:i len:4 246int_conv_to_r4: dest:f src1:i len:36 247int_conv_to_r8: dest:f src1:i len:36 248int_conv_to_u4: dest:i src1:i 249int_conv_to_u2: dest:i src1:i len:8 250int_conv_to_u1: dest:i src1:i len:4 251int_beq: len:8 252int_bge: len:8 253int_bgt: len:8 254int_ble: len:8 255int_blt: len:8 256int_bne_un: len:8 257int_bge_un: len:8 258int_bgt_un: len:8 259int_ble_un: len:8 260int_blt_un: len:8 261int_add_ovf: dest:i src1:i src2:i len:16 262int_add_ovf_un: dest:i src1:i src2:i len:16 263int_mul_ovf: dest:i src1:i src2:i len:16 264int_mul_ovf_un: dest:i src1:i src2:i len:16 265int_sub_ovf: dest:i src1:i src2:i len:16 266int_sub_ovf_un: dest:i src1:i src2:i len:16 267 268int_adc: dest:i src1:i src2:i len:4 269int_addcc: dest:i src1:i src2:i len:4 270int_subcc: dest:i src1:i src2:i len:4 271int_sbb: dest:i src1:i src2:i len:4 272int_adc_imm: dest:i src1:i len:12 273int_sbb_imm: dest:i src1:i len:12 274 275int_add_imm: dest:i src1:i len:12 276int_sub_imm: dest:i src1:i len:12 277int_mul_imm: dest:i src1:i len:12 278int_div_imm: dest:i src1:i len:20 279int_div_un_imm: dest:i src1:i len:12 280int_rem_imm: dest:i src1:i len:28 281int_rem_un_imm: dest:i src1:i len:16 282int_and_imm: dest:i src1:i len:12 283int_or_imm: dest:i src1:i len:12 284int_xor_imm: dest:i src1:i len:12 285int_shl_imm: dest:i src1:i len:8 286int_shr_imm: dest:i src1:i len:8 287int_shr_un_imm: dest:i src1:i len:8 288 289int_ceq: dest:i len:12 290int_cgt: dest:i len:12 291int_cgt_un: dest:i len:12 292int_clt: dest:i len:12 293int_clt_un: dest:i len:12 294 295int_cneq: dest:i len:12 296int_cge: dest:i len:12 297int_cle: dest:i len:12 298int_cge_un: dest:i len:12 299int_cle_un: dest:i len:12 300 301cond_exc_ieq: len:8 302cond_exc_ine_un: len:8 303cond_exc_ilt: len:8 304cond_exc_ilt_un: len:8 305cond_exc_igt: len:8 306cond_exc_igt_un: len:8 307cond_exc_ige: len:8 308cond_exc_ige_un: len:8 309cond_exc_ile: len:8 310cond_exc_ile_un: len:8 311cond_exc_iov: len:12 312cond_exc_ino: len:8 313cond_exc_ic: len:12 314cond_exc_inc: len:8 315 316icompare: src1:i src2:i len:4 317icompare_imm: src1:i len:12 318 319long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:32 320 321vcall2: len:20 clob:c 322vcall2_reg: src1:i len:8 clob:c 323vcall2_membase: src1:b len:16 clob:c 324 325jump_table: dest:i len:8 326 327atomic_add_i4: src1:b src2:i dest:i len:28 328atomic_cas_i4: src1:b src2:i src3:i dest:i len:38 329 330gc_safe_point: len:0 331