1 //===-- DNBArchImpl.cpp -----------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Created by Greg Clayton on 6/25/07.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
14
15 #include "MacOSX/arm/DNBArchImpl.h"
16 #include "ARM_DWARF_Registers.h"
17 #include "ARM_ehframe_Registers.h"
18 #include "DNB.h"
19 #include "DNBBreakpoint.h"
20 #include "DNBLog.h"
21 #include "DNBRegisterInfo.h"
22 #include "MacOSX/MachProcess.h"
23 #include "MacOSX/MachThread.h"
24
25 #include <cinttypes>
26 #include <sys/sysctl.h>
27
28 // BCR address match type
29 #define BCR_M_IMVA_MATCH ((uint32_t)(0u << 21))
30 #define BCR_M_CONTEXT_ID_MATCH ((uint32_t)(1u << 21))
31 #define BCR_M_IMVA_MISMATCH ((uint32_t)(2u << 21))
32 #define BCR_M_RESERVED ((uint32_t)(3u << 21))
33
34 // Link a BVR/BCR or WVR/WCR pair to another
35 #define E_ENABLE_LINKING ((uint32_t)(1u << 20))
36
37 // Byte Address Select
38 #define BAS_IMVA_PLUS_0 ((uint32_t)(1u << 5))
39 #define BAS_IMVA_PLUS_1 ((uint32_t)(1u << 6))
40 #define BAS_IMVA_PLUS_2 ((uint32_t)(1u << 7))
41 #define BAS_IMVA_PLUS_3 ((uint32_t)(1u << 8))
42 #define BAS_IMVA_0_1 ((uint32_t)(3u << 5))
43 #define BAS_IMVA_2_3 ((uint32_t)(3u << 7))
44 #define BAS_IMVA_ALL ((uint32_t)(0xfu << 5))
45
46 // Break only in privileged or user mode
47 #define S_RSVD ((uint32_t)(0u << 1))
48 #define S_PRIV ((uint32_t)(1u << 1))
49 #define S_USER ((uint32_t)(2u << 1))
50 #define S_PRIV_USER ((S_PRIV) | (S_USER))
51
52 #define BCR_ENABLE ((uint32_t)(1u))
53 #define WCR_ENABLE ((uint32_t)(1u))
54
55 // Watchpoint load/store
56 #define WCR_LOAD ((uint32_t)(1u << 3))
57 #define WCR_STORE ((uint32_t)(1u << 4))
58
59 // Definitions for the Debug Status and Control Register fields:
60 // [5:2] => Method of debug entry
61 //#define WATCHPOINT_OCCURRED ((uint32_t)(2u))
62 // I'm seeing this, instead.
63 #define WATCHPOINT_OCCURRED ((uint32_t)(10u))
64
65 // 0xE120BE70
66 static const uint8_t g_arm_breakpoint_opcode[] = {0x70, 0xBE, 0x20, 0xE1};
67 static const uint8_t g_thumb_breakpoint_opcode[] = {0x70, 0xBE};
68
69 // A watchpoint may need to be implemented using two watchpoint registers.
70 // e.g. watching an 8-byte region when the device can only watch 4-bytes.
71 //
72 // This stores the lo->hi mappings. It's safe to initialize to all 0's
73 // since hi > lo and therefore LoHi[i] cannot be 0.
74 static uint32_t LoHi[16] = {0};
75
76 // ARM constants used during decoding
77 #define REG_RD 0
78 #define LDM_REGLIST 1
79 #define PC_REG 15
80 #define PC_REGLIST_BIT 0x8000
81
82 // ARM conditions
83 #define COND_EQ 0x0
84 #define COND_NE 0x1
85 #define COND_CS 0x2
86 #define COND_HS 0x2
87 #define COND_CC 0x3
88 #define COND_LO 0x3
89 #define COND_MI 0x4
90 #define COND_PL 0x5
91 #define COND_VS 0x6
92 #define COND_VC 0x7
93 #define COND_HI 0x8
94 #define COND_LS 0x9
95 #define COND_GE 0xA
96 #define COND_LT 0xB
97 #define COND_GT 0xC
98 #define COND_LE 0xD
99 #define COND_AL 0xE
100 #define COND_UNCOND 0xF
101
102 #define MASK_CPSR_T (1u << 5)
103 #define MASK_CPSR_J (1u << 24)
104
105 #define MNEMONIC_STRING_SIZE 32
106 #define OPERAND_STRING_SIZE 128
107
108 #if !defined(__arm64__) && !defined(__aarch64__)
109 // Returns true if the first 16 bit opcode of a thumb instruction indicates
110 // the instruction will be a 32 bit thumb opcode
IsThumb32Opcode(uint16_t opcode)111 static bool IsThumb32Opcode(uint16_t opcode) {
112 if (((opcode & 0xE000) == 0xE000) && (opcode & 0x1800))
113 return true;
114 return false;
115 }
116 #endif
117
Initialize()118 void DNBArchMachARM::Initialize() {
119 DNBArchPluginInfo arch_plugin_info = {
120 CPU_TYPE_ARM, DNBArchMachARM::Create, DNBArchMachARM::GetRegisterSetInfo,
121 DNBArchMachARM::SoftwareBreakpointOpcode};
122
123 // Register this arch plug-in with the main protocol class
124 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info);
125 }
126
Create(MachThread * thread)127 DNBArchProtocol *DNBArchMachARM::Create(MachThread *thread) {
128 DNBArchMachARM *obj = new DNBArchMachARM(thread);
129 return obj;
130 }
131
SoftwareBreakpointOpcode(nub_size_t byte_size)132 const uint8_t *DNBArchMachARM::SoftwareBreakpointOpcode(nub_size_t byte_size) {
133 switch (byte_size) {
134 case 2:
135 return g_thumb_breakpoint_opcode;
136 case 4:
137 return g_arm_breakpoint_opcode;
138 }
139 return NULL;
140 }
141
GetCPUType()142 uint32_t DNBArchMachARM::GetCPUType() { return CPU_TYPE_ARM; }
143
GetPC(uint64_t failValue)144 uint64_t DNBArchMachARM::GetPC(uint64_t failValue) {
145 // Get program counter
146 if (GetGPRState(false) == KERN_SUCCESS)
147 return m_state.context.gpr.__pc;
148 return failValue;
149 }
150
SetPC(uint64_t value)151 kern_return_t DNBArchMachARM::SetPC(uint64_t value) {
152 // Get program counter
153 kern_return_t err = GetGPRState(false);
154 if (err == KERN_SUCCESS) {
155 m_state.context.gpr.__pc = (uint32_t)value;
156 err = SetGPRState();
157 }
158 return err == KERN_SUCCESS;
159 }
160
GetSP(uint64_t failValue)161 uint64_t DNBArchMachARM::GetSP(uint64_t failValue) {
162 // Get stack pointer
163 if (GetGPRState(false) == KERN_SUCCESS)
164 return m_state.context.gpr.__sp;
165 return failValue;
166 }
167
GetGPRState(bool force)168 kern_return_t DNBArchMachARM::GetGPRState(bool force) {
169 int set = e_regSetGPR;
170 // Check if we have valid cached registers
171 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
172 return KERN_SUCCESS;
173
174 // Read the registers from our thread
175 mach_msg_type_number_t count = ARM_THREAD_STATE_COUNT;
176 kern_return_t kret =
177 ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE,
178 (thread_state_t)&m_state.context.gpr, &count);
179 uint32_t *r = &m_state.context.gpr.__r[0];
180 DNBLogThreadedIf(
181 LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = "
182 "%u) regs r0=%8.8x r1=%8.8x r2=%8.8x r3=%8.8x r4=%8.8x "
183 "r5=%8.8x r6=%8.8x r7=%8.8x r8=%8.8x r9=%8.8x r10=%8.8x "
184 "r11=%8.8x s12=%8.8x sp=%8.8x lr=%8.8x pc=%8.8x cpsr=%8.8x",
185 m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT,
186 kret, count, r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7], r[8], r[9],
187 r[10], r[11], r[12], r[13], r[14], r[15], r[16]);
188 m_state.SetError(set, Read, kret);
189 return kret;
190 }
191
GetVFPState(bool force)192 kern_return_t DNBArchMachARM::GetVFPState(bool force) {
193 int set = e_regSetVFP;
194 // Check if we have valid cached registers
195 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
196 return KERN_SUCCESS;
197
198 kern_return_t kret;
199
200 #if defined(__arm64__) || defined(__aarch64__)
201 // Read the registers from our thread
202 mach_msg_type_number_t count = ARM_NEON_STATE_COUNT;
203 kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE,
204 (thread_state_t)&m_state.context.vfp, &count);
205 if (DNBLogEnabledForAny(LOG_THREAD)) {
206 DNBLogThreaded(
207 "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
208 "\n q0 = 0x%16.16llx%16.16llx"
209 "\n q1 = 0x%16.16llx%16.16llx"
210 "\n q2 = 0x%16.16llx%16.16llx"
211 "\n q3 = 0x%16.16llx%16.16llx"
212 "\n q4 = 0x%16.16llx%16.16llx"
213 "\n q5 = 0x%16.16llx%16.16llx"
214 "\n q6 = 0x%16.16llx%16.16llx"
215 "\n q7 = 0x%16.16llx%16.16llx"
216 "\n q8 = 0x%16.16llx%16.16llx"
217 "\n q9 = 0x%16.16llx%16.16llx"
218 "\n q10 = 0x%16.16llx%16.16llx"
219 "\n q11 = 0x%16.16llx%16.16llx"
220 "\n q12 = 0x%16.16llx%16.16llx"
221 "\n q13 = 0x%16.16llx%16.16llx"
222 "\n q14 = 0x%16.16llx%16.16llx"
223 "\n q15 = 0x%16.16llx%16.16llx"
224 "\n fpsr = 0x%8.8x"
225 "\n fpcr = 0x%8.8x\n\n",
226 m_thread->MachPortNumber(), ARM_NEON_STATE, ARM_NEON_STATE_COUNT, kret,
227 count, ((uint64_t *)&m_state.context.vfp.__v[0])[0],
228 ((uint64_t *)&m_state.context.vfp.__v[0])[1],
229 ((uint64_t *)&m_state.context.vfp.__v[1])[0],
230 ((uint64_t *)&m_state.context.vfp.__v[1])[1],
231 ((uint64_t *)&m_state.context.vfp.__v[2])[0],
232 ((uint64_t *)&m_state.context.vfp.__v[2])[1],
233 ((uint64_t *)&m_state.context.vfp.__v[3])[0],
234 ((uint64_t *)&m_state.context.vfp.__v[3])[1],
235 ((uint64_t *)&m_state.context.vfp.__v[4])[0],
236 ((uint64_t *)&m_state.context.vfp.__v[4])[1],
237 ((uint64_t *)&m_state.context.vfp.__v[5])[0],
238 ((uint64_t *)&m_state.context.vfp.__v[5])[1],
239 ((uint64_t *)&m_state.context.vfp.__v[6])[0],
240 ((uint64_t *)&m_state.context.vfp.__v[6])[1],
241 ((uint64_t *)&m_state.context.vfp.__v[7])[0],
242 ((uint64_t *)&m_state.context.vfp.__v[7])[1],
243 ((uint64_t *)&m_state.context.vfp.__v[8])[0],
244 ((uint64_t *)&m_state.context.vfp.__v[8])[1],
245 ((uint64_t *)&m_state.context.vfp.__v[9])[0],
246 ((uint64_t *)&m_state.context.vfp.__v[9])[1],
247 ((uint64_t *)&m_state.context.vfp.__v[10])[0],
248 ((uint64_t *)&m_state.context.vfp.__v[10])[1],
249 ((uint64_t *)&m_state.context.vfp.__v[11])[0],
250 ((uint64_t *)&m_state.context.vfp.__v[11])[1],
251 ((uint64_t *)&m_state.context.vfp.__v[12])[0],
252 ((uint64_t *)&m_state.context.vfp.__v[12])[1],
253 ((uint64_t *)&m_state.context.vfp.__v[13])[0],
254 ((uint64_t *)&m_state.context.vfp.__v[13])[1],
255 ((uint64_t *)&m_state.context.vfp.__v[14])[0],
256 ((uint64_t *)&m_state.context.vfp.__v[14])[1],
257 ((uint64_t *)&m_state.context.vfp.__v[15])[0],
258 ((uint64_t *)&m_state.context.vfp.__v[15])[1],
259 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr);
260 }
261 #else
262 // Read the registers from our thread
263 mach_msg_type_number_t count = ARM_VFP_STATE_COUNT;
264 kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_VFP_STATE,
265 (thread_state_t)&m_state.context.vfp, &count);
266
267 if (DNBLogEnabledForAny(LOG_THREAD)) {
268 uint32_t *r = &m_state.context.vfp.__r[0];
269 DNBLogThreaded(
270 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)",
271 m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT,
272 kret, count);
273 DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x "
274 "s5=%8.8x s6=%8.8x s7=%8.8x",
275 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
276 DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x "
277 "s13=%8.8x s14=%8.8x s15=%8.8x",
278 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
279 DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x "
280 "s21=%8.8x s22=%8.8x s23=%8.8x",
281 r[16], r[17], r[18], r[19], r[20], r[21], r[22], r[23]);
282 DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x "
283 "s29=%8.8x s30=%8.8x s31=%8.8x",
284 r[24], r[25], r[26], r[27], r[28], r[29], r[30], r[31]);
285 DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x "
286 "s37=%8.8x s38=%8.8x s39=%8.8x",
287 r[32], r[33], r[34], r[35], r[36], r[37], r[38], r[39]);
288 DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x "
289 "s45=%8.8x s46=%8.8x s47=%8.8x",
290 r[40], r[41], r[42], r[43], r[44], r[45], r[46], r[47]);
291 DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x "
292 "s53=%8.8x s54=%8.8x s55=%8.8x",
293 r[48], r[49], r[50], r[51], r[52], r[53], r[54], r[55]);
294 DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x "
295 "s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x",
296 r[56], r[57], r[58], r[59], r[60], r[61], r[62], r[63],
297 r[64]);
298 }
299
300 #endif
301 m_state.SetError(set, Read, kret);
302 return kret;
303 }
304
GetEXCState(bool force)305 kern_return_t DNBArchMachARM::GetEXCState(bool force) {
306 int set = e_regSetEXC;
307 // Check if we have valid cached registers
308 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
309 return KERN_SUCCESS;
310
311 // Read the registers from our thread
312 mach_msg_type_number_t count = ARM_EXCEPTION_STATE_COUNT;
313 kern_return_t kret =
314 ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE,
315 (thread_state_t)&m_state.context.exc, &count);
316 m_state.SetError(set, Read, kret);
317 return kret;
318 }
319
320 #if 0
321 static void DumpDBGState(const DNBArchMachARM::DBG &dbg) {
322 uint32_t i = 0;
323 for (i = 0; i < 16; i++) {
324 DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } "
325 "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }",
326 i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i],
327 dbg.__wcr[i]);
328 }
329 }
330 #endif
331
GetDBGState(bool force)332 kern_return_t DNBArchMachARM::GetDBGState(bool force) {
333 int set = e_regSetDBG;
334
335 // Check if we have valid cached registers
336 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
337 return KERN_SUCCESS;
338
339 // Read the registers from our thread
340 #if defined(ARM_DEBUG_STATE32) && (defined(__arm64__) || defined(__aarch64__))
341 mach_msg_type_number_t count = ARM_DEBUG_STATE32_COUNT;
342 kern_return_t kret =
343 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE32,
344 (thread_state_t)&m_state.dbg, &count);
345 #else
346 mach_msg_type_number_t count = ARM_DEBUG_STATE_COUNT;
347 kern_return_t kret =
348 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE,
349 (thread_state_t)&m_state.dbg, &count);
350 #endif
351 m_state.SetError(set, Read, kret);
352
353 return kret;
354 }
355
SetGPRState()356 kern_return_t DNBArchMachARM::SetGPRState() {
357 int set = e_regSetGPR;
358 kern_return_t kret = ::thread_set_state(
359 m_thread->MachPortNumber(), ARM_THREAD_STATE,
360 (thread_state_t)&m_state.context.gpr, ARM_THREAD_STATE_COUNT);
361 m_state.SetError(set, Write,
362 kret); // Set the current write error for this register set
363 m_state.InvalidateRegisterSetState(set); // Invalidate the current register
364 // state in case registers are read
365 // back differently
366 return kret; // Return the error code
367 }
368
SetVFPState()369 kern_return_t DNBArchMachARM::SetVFPState() {
370 int set = e_regSetVFP;
371 kern_return_t kret;
372 mach_msg_type_number_t count;
373
374 #if defined(__arm64__) || defined(__aarch64__)
375 count = ARM_NEON_STATE_COUNT;
376 kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_NEON_STATE,
377 (thread_state_t)&m_state.context.vfp, count);
378 #else
379 count = ARM_VFP_STATE_COUNT;
380 kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_VFP_STATE,
381 (thread_state_t)&m_state.context.vfp, count);
382 #endif
383
384 #if defined(__arm64__) || defined(__aarch64__)
385 if (DNBLogEnabledForAny(LOG_THREAD)) {
386 DNBLogThreaded(
387 "thread_set_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
388 "\n q0 = 0x%16.16llx%16.16llx"
389 "\n q1 = 0x%16.16llx%16.16llx"
390 "\n q2 = 0x%16.16llx%16.16llx"
391 "\n q3 = 0x%16.16llx%16.16llx"
392 "\n q4 = 0x%16.16llx%16.16llx"
393 "\n q5 = 0x%16.16llx%16.16llx"
394 "\n q6 = 0x%16.16llx%16.16llx"
395 "\n q7 = 0x%16.16llx%16.16llx"
396 "\n q8 = 0x%16.16llx%16.16llx"
397 "\n q9 = 0x%16.16llx%16.16llx"
398 "\n q10 = 0x%16.16llx%16.16llx"
399 "\n q11 = 0x%16.16llx%16.16llx"
400 "\n q12 = 0x%16.16llx%16.16llx"
401 "\n q13 = 0x%16.16llx%16.16llx"
402 "\n q14 = 0x%16.16llx%16.16llx"
403 "\n q15 = 0x%16.16llx%16.16llx"
404 "\n fpsr = 0x%8.8x"
405 "\n fpcr = 0x%8.8x\n\n",
406 m_thread->MachPortNumber(), ARM_NEON_STATE, ARM_NEON_STATE_COUNT, kret,
407 count, ((uint64_t *)&m_state.context.vfp.__v[0])[0],
408 ((uint64_t *)&m_state.context.vfp.__v[0])[1],
409 ((uint64_t *)&m_state.context.vfp.__v[1])[0],
410 ((uint64_t *)&m_state.context.vfp.__v[1])[1],
411 ((uint64_t *)&m_state.context.vfp.__v[2])[0],
412 ((uint64_t *)&m_state.context.vfp.__v[2])[1],
413 ((uint64_t *)&m_state.context.vfp.__v[3])[0],
414 ((uint64_t *)&m_state.context.vfp.__v[3])[1],
415 ((uint64_t *)&m_state.context.vfp.__v[4])[0],
416 ((uint64_t *)&m_state.context.vfp.__v[4])[1],
417 ((uint64_t *)&m_state.context.vfp.__v[5])[0],
418 ((uint64_t *)&m_state.context.vfp.__v[5])[1],
419 ((uint64_t *)&m_state.context.vfp.__v[6])[0],
420 ((uint64_t *)&m_state.context.vfp.__v[6])[1],
421 ((uint64_t *)&m_state.context.vfp.__v[7])[0],
422 ((uint64_t *)&m_state.context.vfp.__v[7])[1],
423 ((uint64_t *)&m_state.context.vfp.__v[8])[0],
424 ((uint64_t *)&m_state.context.vfp.__v[8])[1],
425 ((uint64_t *)&m_state.context.vfp.__v[9])[0],
426 ((uint64_t *)&m_state.context.vfp.__v[9])[1],
427 ((uint64_t *)&m_state.context.vfp.__v[10])[0],
428 ((uint64_t *)&m_state.context.vfp.__v[10])[1],
429 ((uint64_t *)&m_state.context.vfp.__v[11])[0],
430 ((uint64_t *)&m_state.context.vfp.__v[11])[1],
431 ((uint64_t *)&m_state.context.vfp.__v[12])[0],
432 ((uint64_t *)&m_state.context.vfp.__v[12])[1],
433 ((uint64_t *)&m_state.context.vfp.__v[13])[0],
434 ((uint64_t *)&m_state.context.vfp.__v[13])[1],
435 ((uint64_t *)&m_state.context.vfp.__v[14])[0],
436 ((uint64_t *)&m_state.context.vfp.__v[14])[1],
437 ((uint64_t *)&m_state.context.vfp.__v[15])[0],
438 ((uint64_t *)&m_state.context.vfp.__v[15])[1],
439 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr);
440 }
441 #else
442 if (DNBLogEnabledForAny(LOG_THREAD)) {
443 uint32_t *r = &m_state.context.vfp.__r[0];
444 DNBLogThreaded(
445 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)",
446 m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT,
447 kret, count);
448 DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x "
449 "s5=%8.8x s6=%8.8x s7=%8.8x",
450 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
451 DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x "
452 "s13=%8.8x s14=%8.8x s15=%8.8x",
453 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
454 DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x "
455 "s21=%8.8x s22=%8.8x s23=%8.8x",
456 r[16], r[17], r[18], r[19], r[20], r[21], r[22], r[23]);
457 DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x "
458 "s29=%8.8x s30=%8.8x s31=%8.8x",
459 r[24], r[25], r[26], r[27], r[28], r[29], r[30], r[31]);
460 DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x "
461 "s37=%8.8x s38=%8.8x s39=%8.8x",
462 r[32], r[33], r[34], r[35], r[36], r[37], r[38], r[39]);
463 DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x "
464 "s45=%8.8x s46=%8.8x s47=%8.8x",
465 r[40], r[41], r[42], r[43], r[44], r[45], r[46], r[47]);
466 DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x "
467 "s53=%8.8x s54=%8.8x s55=%8.8x",
468 r[48], r[49], r[50], r[51], r[52], r[53], r[54], r[55]);
469 DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x "
470 "s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x",
471 r[56], r[57], r[58], r[59], r[60], r[61], r[62], r[63],
472 r[64]);
473 }
474 #endif
475
476 m_state.SetError(set, Write,
477 kret); // Set the current write error for this register set
478 m_state.InvalidateRegisterSetState(set); // Invalidate the current register
479 // state in case registers are read
480 // back differently
481 return kret; // Return the error code
482 }
483
SetEXCState()484 kern_return_t DNBArchMachARM::SetEXCState() {
485 int set = e_regSetEXC;
486 kern_return_t kret = ::thread_set_state(
487 m_thread->MachPortNumber(), ARM_EXCEPTION_STATE,
488 (thread_state_t)&m_state.context.exc, ARM_EXCEPTION_STATE_COUNT);
489 m_state.SetError(set, Write,
490 kret); // Set the current write error for this register set
491 m_state.InvalidateRegisterSetState(set); // Invalidate the current register
492 // state in case registers are read
493 // back differently
494 return kret; // Return the error code
495 }
496
SetDBGState(bool also_set_on_task)497 kern_return_t DNBArchMachARM::SetDBGState(bool also_set_on_task) {
498 int set = e_regSetDBG;
499 #if defined(ARM_DEBUG_STATE32) && (defined(__arm64__) || defined(__aarch64__))
500 kern_return_t kret =
501 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE32,
502 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT);
503 if (also_set_on_task) {
504 kern_return_t task_kret = ::task_set_state(
505 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE32,
506 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT);
507 if (task_kret != KERN_SUCCESS)
508 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to "
509 "set debug control register state: "
510 "0x%8.8x.",
511 kret);
512 }
513 #else
514 kern_return_t kret =
515 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE,
516 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT);
517 if (also_set_on_task) {
518 kern_return_t task_kret = ::task_set_state(
519 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE,
520 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT);
521 if (task_kret != KERN_SUCCESS)
522 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to "
523 "set debug control register state: "
524 "0x%8.8x.",
525 kret);
526 }
527 #endif
528
529 m_state.SetError(set, Write,
530 kret); // Set the current write error for this register set
531 m_state.InvalidateRegisterSetState(set); // Invalidate the current register
532 // state in case registers are read
533 // back differently
534 return kret; // Return the error code
535 }
536
ThreadWillResume()537 void DNBArchMachARM::ThreadWillResume() {
538 // Do we need to step this thread? If so, let the mach thread tell us so.
539 if (m_thread->IsStepping()) {
540 // This is the primary thread, let the arch do anything it needs
541 if (NumSupportedHardwareBreakpoints() > 0) {
542 if (EnableHardwareSingleStep(true) != KERN_SUCCESS) {
543 DNBLogThreaded("DNBArchMachARM::ThreadWillResume() failed to enable "
544 "hardware single step");
545 }
546 }
547 }
548
549 // Disable the triggered watchpoint temporarily before we resume.
550 // Plus, we try to enable hardware single step to execute past the instruction
551 // which triggered our watchpoint.
552 if (m_watchpoint_did_occur) {
553 if (m_watchpoint_hw_index >= 0) {
554 kern_return_t kret = GetDBGState(false);
555 if (kret == KERN_SUCCESS &&
556 !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) {
557 // The watchpoint might have been disabled by the user. We don't need
558 // to do anything at all
559 // to enable hardware single stepping.
560 m_watchpoint_did_occur = false;
561 m_watchpoint_hw_index = -1;
562 return;
563 }
564
565 DisableHardwareWatchpoint(m_watchpoint_hw_index, false);
566 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() "
567 "DisableHardwareWatchpoint(%d) called",
568 m_watchpoint_hw_index);
569
570 // Enable hardware single step to move past the watchpoint-triggering
571 // instruction.
572 m_watchpoint_resume_single_step_enabled =
573 (EnableHardwareSingleStep(true) == KERN_SUCCESS);
574
575 // If we are not able to enable single step to move past the
576 // watchpoint-triggering instruction,
577 // at least we should reset the two watchpoint member variables so that
578 // the next time around
579 // this callback function is invoked, the enclosing logical branch is
580 // skipped.
581 if (!m_watchpoint_resume_single_step_enabled) {
582 // Reset the two watchpoint member variables.
583 m_watchpoint_did_occur = false;
584 m_watchpoint_hw_index = -1;
585 DNBLogThreadedIf(
586 LOG_WATCHPOINTS,
587 "DNBArchMachARM::ThreadWillResume() failed to enable single step");
588 } else
589 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() "
590 "succeeded to enable single step");
591 }
592 }
593 }
594
ThreadDidStop()595 bool DNBArchMachARM::ThreadDidStop() {
596 bool success = true;
597
598 m_state.InvalidateRegisterSetState(e_regSetALL);
599
600 if (m_watchpoint_resume_single_step_enabled) {
601 // Great! We now disable the hardware single step as well as re-enable the
602 // hardware watchpoint.
603 // See also ThreadWillResume().
604 if (EnableHardwareSingleStep(false) == KERN_SUCCESS) {
605 if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) {
606 ReenableHardwareWatchpoint(m_watchpoint_hw_index);
607 m_watchpoint_resume_single_step_enabled = false;
608 m_watchpoint_did_occur = false;
609 m_watchpoint_hw_index = -1;
610 } else {
611 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled "
612 "is true but (m_watchpoint_did_occur && "
613 "m_watchpoint_hw_index >= 0) does not hold!");
614 }
615 } else {
616 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled "
617 "is true but unable to disable single step!");
618 }
619 }
620
621 // Are we stepping a single instruction?
622 if (GetGPRState(true) == KERN_SUCCESS) {
623 // We are single stepping, was this the primary thread?
624 if (m_thread->IsStepping()) {
625 success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
626 } else {
627 // The MachThread will automatically restore the suspend count
628 // in ThreadDidStop(), so we don't need to do anything here if
629 // we weren't the primary thread the last time
630 }
631 }
632 return success;
633 }
634
NotifyException(MachException::Data & exc)635 bool DNBArchMachARM::NotifyException(MachException::Data &exc) {
636 switch (exc.exc_type) {
637 default:
638 break;
639 case EXC_BREAKPOINT:
640 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) {
641 // The data break address is passed as exc_data[1].
642 nub_addr_t addr = exc.exc_data[1];
643 // Find the hardware index with the side effect of possibly massaging the
644 // addr to return the starting address as seen from the debugger side.
645 uint32_t hw_index = GetHardwareWatchpointHit(addr);
646 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException "
647 "watchpoint %d was hit on address "
648 "0x%llx",
649 hw_index, (uint64_t)addr);
650 const uint32_t num_watchpoints = NumSupportedHardwareWatchpoints();
651 for (uint32_t i = 0; i < num_watchpoints; i++) {
652 if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i &&
653 GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) {
654 addr = GetWatchpointAddressByIndex(i);
655 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException "
656 "It is a linked watchpoint; "
657 "rewritten to index %d addr 0x%llx",
658 LoHi[i], (uint64_t)addr);
659 }
660 }
661 if (hw_index != INVALID_NUB_HW_INDEX) {
662 m_watchpoint_did_occur = true;
663 m_watchpoint_hw_index = hw_index;
664 exc.exc_data[1] = addr;
665 // Piggyback the hw_index in the exc.data.
666 exc.exc_data.push_back(hw_index);
667 }
668
669 return true;
670 }
671 break;
672 }
673 return false;
674 }
675
StepNotComplete()676 bool DNBArchMachARM::StepNotComplete() {
677 if (m_hw_single_chained_step_addr != INVALID_NUB_ADDRESS) {
678 kern_return_t kret = KERN_INVALID_ARGUMENT;
679 kret = GetGPRState(false);
680 if (kret == KERN_SUCCESS) {
681 if (m_state.context.gpr.__pc == m_hw_single_chained_step_addr) {
682 DNBLogThreadedIf(LOG_STEP, "Need to step some more at 0x%8.8llx",
683 (uint64_t)m_hw_single_chained_step_addr);
684 return true;
685 }
686 }
687 }
688
689 m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS;
690 return false;
691 }
692
693 // Set the single step bit in the processor status register.
EnableHardwareSingleStep(bool enable)694 kern_return_t DNBArchMachARM::EnableHardwareSingleStep(bool enable) {
695 DNBError err;
696 DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable);
697
698 err = GetGPRState(false);
699
700 if (err.Fail()) {
701 err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__);
702 return err.Status();
703 }
704
705 err = GetDBGState(false);
706
707 if (err.Fail()) {
708 err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__);
709 return err.Status();
710 }
711
712 // The use of __arm64__ here is not ideal. If debugserver is running on
713 // an armv8 device, regardless of whether it was built for arch arm or arch
714 // arm64,
715 // it needs to use the MDSCR_EL1 SS bit to single instruction step.
716
717 #if defined(__arm64__) || defined(__aarch64__)
718 if (enable) {
719 DNBLogThreadedIf(LOG_STEP,
720 "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx",
721 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc);
722 m_state.dbg.__mdscr_el1 |=
723 1; // Set bit 0 (single step, SS) in the MDSCR_EL1.
724 } else {
725 DNBLogThreadedIf(LOG_STEP,
726 "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx",
727 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc);
728 m_state.dbg.__mdscr_el1 &=
729 ~(1ULL); // Clear bit 0 (single step, SS) in the MDSCR_EL1.
730 }
731 #else
732 const uint32_t i = 0;
733 if (enable) {
734 m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS;
735
736 // Save our previous state
737 m_dbg_save = m_state.dbg;
738 // Set a breakpoint that will stop when the PC doesn't match the current
739 // one!
740 m_state.dbg.__bvr[i] =
741 m_state.context.gpr.__pc &
742 0xFFFFFFFCu; // Set the current PC as the breakpoint address
743 m_state.dbg.__bcr[i] = BCR_M_IMVA_MISMATCH | // Stop on address mismatch
744 S_USER | // Stop only in user mode
745 BCR_ENABLE; // Enable this breakpoint
746 if (m_state.context.gpr.__cpsr & 0x20) {
747 // Thumb breakpoint
748 if (m_state.context.gpr.__pc & 2)
749 m_state.dbg.__bcr[i] |= BAS_IMVA_2_3;
750 else
751 m_state.dbg.__bcr[i] |= BAS_IMVA_0_1;
752
753 uint16_t opcode;
754 if (sizeof(opcode) ==
755 m_thread->Process()->Task().ReadMemory(m_state.context.gpr.__pc,
756 sizeof(opcode), &opcode)) {
757 if (IsThumb32Opcode(opcode)) {
758 // 32 bit thumb opcode...
759 if (m_state.context.gpr.__pc & 2) {
760 // We can't take care of a 32 bit thumb instruction single step
761 // with just IVA mismatching. We will need to chain an extra
762 // hardware single step in order to complete this single step...
763 m_hw_single_chained_step_addr = m_state.context.gpr.__pc + 2;
764 } else {
765 // Extend the number of bits to ignore for the mismatch
766 m_state.dbg.__bcr[i] |= BAS_IMVA_ALL;
767 }
768 }
769 }
770 } else {
771 // ARM breakpoint
772 m_state.dbg.__bcr[i] |= BAS_IMVA_ALL; // Stop when any address bits change
773 }
774
775 DNBLogThreadedIf(LOG_STEP, "%s: BVR%u=0x%8.8x BCR%u=0x%8.8x", __FUNCTION__,
776 i, m_state.dbg.__bvr[i], i, m_state.dbg.__bcr[i]);
777
778 for (uint32_t j = i + 1; j < 16; ++j) {
779 // Disable all others
780 m_state.dbg.__bvr[j] = 0;
781 m_state.dbg.__bcr[j] = 0;
782 }
783 } else {
784 // Just restore the state we had before we did single stepping
785 m_state.dbg = m_dbg_save;
786 }
787 #endif
788
789 return SetDBGState(false);
790 }
791
792 // return 1 if bit "BIT" is set in "value"
bit(uint32_t value,uint32_t bit)793 static inline uint32_t bit(uint32_t value, uint32_t bit) {
794 return (value >> bit) & 1u;
795 }
796
797 // return the bitfield "value[msbit:lsbit]".
bits(uint32_t value,uint32_t msbit,uint32_t lsbit)798 static inline uint32_t bits(uint32_t value, uint32_t msbit, uint32_t lsbit) {
799 assert(msbit >= lsbit);
800 uint32_t shift_left = sizeof(value) * 8 - 1 - msbit;
801 value <<=
802 shift_left; // shift anything above the msbit off of the unsigned edge
803 value >>= (shift_left + lsbit); // shift it back again down to the lsbit
804 // (including undoing any shift from above)
805 return value; // return our result
806 }
807
ConditionPassed(uint8_t condition,uint32_t cpsr)808 bool DNBArchMachARM::ConditionPassed(uint8_t condition, uint32_t cpsr) {
809 uint32_t cpsr_n = bit(cpsr, 31); // Negative condition code flag
810 uint32_t cpsr_z = bit(cpsr, 30); // Zero condition code flag
811 uint32_t cpsr_c = bit(cpsr, 29); // Carry condition code flag
812 uint32_t cpsr_v = bit(cpsr, 28); // Overflow condition code flag
813
814 switch (condition) {
815 case COND_EQ: // (0x0)
816 if (cpsr_z == 1)
817 return true;
818 break;
819 case COND_NE: // (0x1)
820 if (cpsr_z == 0)
821 return true;
822 break;
823 case COND_CS: // (0x2)
824 if (cpsr_c == 1)
825 return true;
826 break;
827 case COND_CC: // (0x3)
828 if (cpsr_c == 0)
829 return true;
830 break;
831 case COND_MI: // (0x4)
832 if (cpsr_n == 1)
833 return true;
834 break;
835 case COND_PL: // (0x5)
836 if (cpsr_n == 0)
837 return true;
838 break;
839 case COND_VS: // (0x6)
840 if (cpsr_v == 1)
841 return true;
842 break;
843 case COND_VC: // (0x7)
844 if (cpsr_v == 0)
845 return true;
846 break;
847 case COND_HI: // (0x8)
848 if ((cpsr_c == 1) && (cpsr_z == 0))
849 return true;
850 break;
851 case COND_LS: // (0x9)
852 if ((cpsr_c == 0) || (cpsr_z == 1))
853 return true;
854 break;
855 case COND_GE: // (0xA)
856 if (cpsr_n == cpsr_v)
857 return true;
858 break;
859 case COND_LT: // (0xB)
860 if (cpsr_n != cpsr_v)
861 return true;
862 break;
863 case COND_GT: // (0xC)
864 if ((cpsr_z == 0) && (cpsr_n == cpsr_v))
865 return true;
866 break;
867 case COND_LE: // (0xD)
868 if ((cpsr_z == 1) || (cpsr_n != cpsr_v))
869 return true;
870 break;
871 default:
872 return true;
873 break;
874 }
875
876 return false;
877 }
878
NumSupportedHardwareBreakpoints()879 uint32_t DNBArchMachARM::NumSupportedHardwareBreakpoints() {
880 // Set the init value to something that will let us know that we need to
881 // autodetect how many breakpoints are supported dynamically...
882 static uint32_t g_num_supported_hw_breakpoints = UINT_MAX;
883 if (g_num_supported_hw_breakpoints == UINT_MAX) {
884 // Set this to zero in case we can't tell if there are any HW breakpoints
885 g_num_supported_hw_breakpoints = 0;
886
887 size_t len;
888 uint32_t n = 0;
889 len = sizeof(n);
890 if (::sysctlbyname("hw.optional.breakpoint", &n, &len, NULL, 0) == 0) {
891 g_num_supported_hw_breakpoints = n;
892 DNBLogThreadedIf(LOG_THREAD, "hw.optional.breakpoint=%u", n);
893 } else {
894 #if !defined(__arm64__) && !defined(__aarch64__)
895 // Read the DBGDIDR to get the number of available hardware breakpoints
896 // However, in some of our current armv7 processors, hardware
897 // breakpoints/watchpoints were not properly connected. So detect those
898 // cases using a field in a sysctl. For now we are using "hw.cpusubtype"
899 // field to distinguish CPU architectures. This is a hack until we can
900 // get <rdar://problem/6372672> fixed, at which point we will switch to
901 // using a different sysctl string that will tell us how many BRPs
902 // are available to us directly without having to read DBGDIDR.
903 uint32_t register_DBGDIDR;
904
905 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
906 uint32_t numBRPs = bits(register_DBGDIDR, 27, 24);
907 // Zero is reserved for the BRP count, so don't increment it if it is zero
908 if (numBRPs > 0)
909 numBRPs++;
910 DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number BRP pairs = %u)",
911 register_DBGDIDR, numBRPs);
912
913 if (numBRPs > 0) {
914 uint32_t cpusubtype;
915 len = sizeof(cpusubtype);
916 // TODO: remove this hack and change to using hw.optional.xx when
917 // implmented
918 if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0) {
919 DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=%d", cpusubtype);
920 if (cpusubtype == CPU_SUBTYPE_ARM_V7)
921 DNBLogThreadedIf(LOG_THREAD, "Hardware breakpoints disabled for "
922 "armv7 (rdar://problem/6372672)");
923 else
924 g_num_supported_hw_breakpoints = numBRPs;
925 }
926 }
927 #endif
928 }
929 }
930 return g_num_supported_hw_breakpoints;
931 }
932
NumSupportedHardwareWatchpoints()933 uint32_t DNBArchMachARM::NumSupportedHardwareWatchpoints() {
934 // Set the init value to something that will let us know that we need to
935 // autodetect how many watchpoints are supported dynamically...
936 static uint32_t g_num_supported_hw_watchpoints = UINT_MAX;
937 if (g_num_supported_hw_watchpoints == UINT_MAX) {
938 // Set this to zero in case we can't tell if there are any HW breakpoints
939 g_num_supported_hw_watchpoints = 0;
940
941 size_t len;
942 uint32_t n = 0;
943 len = sizeof(n);
944 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) {
945 g_num_supported_hw_watchpoints = n;
946 DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n);
947 } else {
948 #if !defined(__arm64__) && !defined(__aarch64__)
949 // Read the DBGDIDR to get the number of available hardware breakpoints
950 // However, in some of our current armv7 processors, hardware
951 // breakpoints/watchpoints were not properly connected. So detect those
952 // cases using a field in a sysctl. For now we are using "hw.cpusubtype"
953 // field to distinguish CPU architectures. This is a hack until we can
954 // get <rdar://problem/6372672> fixed, at which point we will switch to
955 // using a different sysctl string that will tell us how many WRPs
956 // are available to us directly without having to read DBGDIDR.
957
958 uint32_t register_DBGDIDR;
959 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
960 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28) + 1;
961 DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number WRP pairs = %u)",
962 register_DBGDIDR, numWRPs);
963
964 if (numWRPs > 0) {
965 uint32_t cpusubtype;
966 size_t len;
967 len = sizeof(cpusubtype);
968 // TODO: remove this hack and change to using hw.optional.xx when
969 // implmented
970 if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0) {
971 DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=0x%d", cpusubtype);
972
973 if (cpusubtype == CPU_SUBTYPE_ARM_V7)
974 DNBLogThreadedIf(LOG_THREAD, "Hardware watchpoints disabled for "
975 "armv7 (rdar://problem/6372672)");
976 else
977 g_num_supported_hw_watchpoints = numWRPs;
978 }
979 }
980 #endif
981 }
982 }
983 return g_num_supported_hw_watchpoints;
984 }
985
EnableHardwareBreakpoint(nub_addr_t addr,nub_size_t size,bool also_set_on_task)986 uint32_t DNBArchMachARM::EnableHardwareBreakpoint(nub_addr_t addr,
987 nub_size_t size,
988 bool also_set_on_task) {
989 // Make sure our address isn't bogus
990 if (addr & 1)
991 return INVALID_NUB_HW_INDEX;
992
993 kern_return_t kret = GetDBGState(false);
994
995 if (kret == KERN_SUCCESS) {
996 const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints();
997 uint32_t i;
998 for (i = 0; i < num_hw_breakpoints; ++i) {
999 if ((m_state.dbg.__bcr[i] & BCR_ENABLE) == 0)
1000 break; // We found an available hw breakpoint slot (in i)
1001 }
1002
1003 // See if we found an available hw breakpoint slot above
1004 if (i < num_hw_breakpoints) {
1005 // Make sure bits 1:0 are clear in our address
1006 m_state.dbg.__bvr[i] = addr & ~((nub_addr_t)3);
1007
1008 if (size == 2 || addr & 2) {
1009 uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1;
1010
1011 // We have a thumb breakpoint
1012 // We have an ARM breakpoint
1013 m_state.dbg.__bcr[i] =
1014 BCR_M_IMVA_MATCH | // Stop on address mismatch
1015 byte_addr_select | // Set the correct byte address select so we only
1016 // trigger on the correct opcode
1017 S_USER | // Which modes should this breakpoint stop in?
1018 BCR_ENABLE; // Enable this hardware breakpoint
1019 DNBLogThreadedIf(LOG_BREAKPOINTS,
1020 "DNBArchMachARM::EnableHardwareBreakpoint( addr = "
1021 "0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / "
1022 "0x%8.8x (Thumb)",
1023 (uint64_t)addr, (uint64_t)size, i, i,
1024 m_state.dbg.__bvr[i], m_state.dbg.__bcr[i]);
1025 } else if (size == 4) {
1026 // We have an ARM breakpoint
1027 m_state.dbg.__bcr[i] =
1028 BCR_M_IMVA_MATCH | // Stop on address mismatch
1029 BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA
1030 S_USER | // Which modes should this breakpoint stop in?
1031 BCR_ENABLE; // Enable this hardware breakpoint
1032 DNBLogThreadedIf(LOG_BREAKPOINTS,
1033 "DNBArchMachARM::EnableHardwareBreakpoint( addr = "
1034 "0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / "
1035 "0x%8.8x (ARM)",
1036 (uint64_t)addr, (uint64_t)size, i, i,
1037 m_state.dbg.__bvr[i], m_state.dbg.__bcr[i]);
1038 }
1039
1040 kret = SetDBGState(false);
1041 DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::"
1042 "EnableHardwareBreakpoint() "
1043 "SetDBGState() => 0x%8.8x.",
1044 kret);
1045
1046 if (kret == KERN_SUCCESS)
1047 return i;
1048 } else {
1049 DNBLogThreadedIf(LOG_BREAKPOINTS,
1050 "DNBArchMachARM::EnableHardwareBreakpoint(addr = "
1051 "0x%8.8llx, size = %llu) => all hardware breakpoint "
1052 "resources are being used.",
1053 (uint64_t)addr, (uint64_t)size);
1054 }
1055 }
1056
1057 return INVALID_NUB_HW_INDEX;
1058 }
1059
DisableHardwareBreakpoint(uint32_t hw_index,bool also_set_on_task)1060 bool DNBArchMachARM::DisableHardwareBreakpoint(uint32_t hw_index,
1061 bool also_set_on_task) {
1062 kern_return_t kret = GetDBGState(false);
1063
1064 const uint32_t num_hw_points = NumSupportedHardwareBreakpoints();
1065 if (kret == KERN_SUCCESS) {
1066 if (hw_index < num_hw_points) {
1067 m_state.dbg.__bcr[hw_index] = 0;
1068 DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::SetHardwareBreakpoint("
1069 " %u ) - BVR%u = 0x%8.8x BCR%u = "
1070 "0x%8.8x",
1071 hw_index, hw_index, m_state.dbg.__bvr[hw_index],
1072 hw_index, m_state.dbg.__bcr[hw_index]);
1073
1074 kret = SetDBGState(false);
1075
1076 if (kret == KERN_SUCCESS)
1077 return true;
1078 }
1079 }
1080 return false;
1081 }
1082
1083 // ARM v7 watchpoints may be either word-size or double-word-size.
1084 // It's implementation defined which they can handle. It looks like on an
1085 // armv8 device, armv7 processes can watch dwords. But on a genuine armv7
1086 // device I tried, only word watchpoints are supported.
1087
1088 #if defined(__arm64__) || defined(__aarch64__)
1089 #define WATCHPOINTS_ARE_DWORD 1
1090 #else
1091 #undef WATCHPOINTS_ARE_DWORD
1092 #endif
1093
EnableHardwareWatchpoint(nub_addr_t addr,nub_size_t size,bool read,bool write,bool also_set_on_task)1094 uint32_t DNBArchMachARM::EnableHardwareWatchpoint(nub_addr_t addr,
1095 nub_size_t size, bool read,
1096 bool write,
1097 bool also_set_on_task) {
1098
1099 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint("
1100 "addr = 0x%8.8llx, size = %zu, read = %u, "
1101 "write = %u)",
1102 (uint64_t)addr, size, read, write);
1103
1104 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
1105
1106 // Can't watch zero bytes
1107 if (size == 0)
1108 return INVALID_NUB_HW_INDEX;
1109
1110 // We must watch for either read or write
1111 if (read == false && write == false)
1112 return INVALID_NUB_HW_INDEX;
1113
1114 // Otherwise, can't watch more than 8 bytes per WVR/WCR pair
1115 if (size > 8)
1116 return INVALID_NUB_HW_INDEX;
1117
1118 // Treat arm watchpoints as having an 8-byte alignment requirement. You can put
1119 // a watchpoint on a 4-byte
1120 // offset address but you can only watch 4 bytes with that watchpoint.
1121
1122 // arm watchpoints on an 8-byte (double word) aligned addr can watch any bytes
1123 // in that
1124 // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 3rd
1125 // byte, etc, or any
1126 // combination therein by setting the bits in the BAS [12:5] (Byte Address
1127 // Select) field of
1128 // the DBGWCRn_EL1 reg for the watchpoint.
1129
1130 // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to
1131 // monitor a larger region
1132 // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield
1133 // then selects a larger
1134 // range of bytes, instead of individual bytes. See the ARMv8 Debug
1135 // Architecture manual for details.
1136 // This implementation does not currently use the MASK bits; the largest single
1137 // region watched by a single
1138 // watchpoint right now is 8-bytes.
1139
1140 #if defined(WATCHPOINTS_ARE_DWORD)
1141 nub_addr_t aligned_wp_address = addr & ~0x7;
1142 uint32_t addr_dword_offset = addr & 0x7;
1143 const int max_watchpoint_size = 8;
1144 #else
1145 nub_addr_t aligned_wp_address = addr & ~0x3;
1146 uint32_t addr_dword_offset = addr & 0x3;
1147 const int max_watchpoint_size = 4;
1148 #endif
1149
1150 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint "
1151 "aligned_wp_address is 0x%llx and "
1152 "addr_dword_offset is 0x%x",
1153 (uint64_t)aligned_wp_address, addr_dword_offset);
1154
1155 // Do we need to split up this logical watchpoint into two hardware watchpoint
1156 // registers?
1157 // e.g. a watchpoint of length 4 on address 6. We need do this with
1158 // one watchpoint on address 0 with bytes 6 & 7 being monitored
1159 // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored
1160
1161 if (addr_dword_offset + size > max_watchpoint_size) {
1162 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
1163 "EnableHardwareWatchpoint(addr = "
1164 "0x%8.8llx, size = %zu) needs two "
1165 "hardware watchpoints slots to monitor",
1166 (uint64_t)addr, size);
1167 int low_watchpoint_size = max_watchpoint_size - addr_dword_offset;
1168 int high_watchpoint_size = addr_dword_offset + size - max_watchpoint_size;
1169
1170 uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read,
1171 write, also_set_on_task);
1172 if (lo == INVALID_NUB_HW_INDEX)
1173 return INVALID_NUB_HW_INDEX;
1174 uint32_t hi = EnableHardwareWatchpoint(
1175 aligned_wp_address + max_watchpoint_size, high_watchpoint_size, read,
1176 write, also_set_on_task);
1177 if (hi == INVALID_NUB_HW_INDEX) {
1178 DisableHardwareWatchpoint(lo, also_set_on_task);
1179 return INVALID_NUB_HW_INDEX;
1180 }
1181 // Tag this lo->hi mapping in our database.
1182 LoHi[lo] = hi;
1183 return lo;
1184 }
1185
1186 // At this point
1187 // 1 aligned_wp_address is the requested address rounded down to 8-byte
1188 // alignment
1189 // 2 addr_dword_offset is the offset into that double word (8-byte) region
1190 // that we are watching
1191 // 3 size is the number of bytes within that 8-byte region that we are
1192 // watching
1193
1194 // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the
1195 // above.
1196 // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4,
1197 // etc, up to 0b11111111 for 8.
1198 // then we shift those bits left by the offset into this dword that we are
1199 // interested in.
1200 // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of
1201 // 0b11110000.
1202 uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset;
1203
1204 // Read the debug state
1205 kern_return_t kret = GetDBGState(true);
1206
1207 if (kret == KERN_SUCCESS) {
1208 // Check to make sure we have the needed hardware support
1209 uint32_t i = 0;
1210
1211 for (i = 0; i < num_hw_watchpoints; ++i) {
1212 if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0)
1213 break; // We found an available hw watchpoint slot (in i)
1214 }
1215
1216 // See if we found an available hw watchpoint slot above
1217 if (i < num_hw_watchpoints) {
1218 // DumpDBGState(m_state.dbg);
1219
1220 // Clear any previous LoHi joined-watchpoint that may have been in use
1221 LoHi[i] = 0;
1222
1223 // shift our Byte Address Select bits up to the correct bit range for the
1224 // DBGWCRn_EL1
1225 byte_address_select = byte_address_select << 5;
1226
1227 // Make sure bits 1:0 are clear in our address
1228 m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address)
1229 m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow
1230 // the DVA that we will watch
1231 S_USER | // Stop only in user mode
1232 (read ? WCR_LOAD : 0) | // Stop on read access?
1233 (write ? WCR_STORE : 0) | // Stop on write access?
1234 WCR_ENABLE; // Enable this watchpoint;
1235
1236 DNBLogThreadedIf(
1237 LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint() adding "
1238 "watchpoint on address 0x%llx with control register "
1239 "value 0x%x",
1240 (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]);
1241
1242 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
1243 // automatically, don't need to do it here.
1244
1245 kret = SetDBGState(also_set_on_task);
1246 // DumpDBGState(m_state.dbg);
1247
1248 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
1249 "EnableHardwareWatchpoint() "
1250 "SetDBGState() => 0x%8.8x.",
1251 kret);
1252
1253 if (kret == KERN_SUCCESS)
1254 return i;
1255 } else {
1256 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
1257 "EnableHardwareWatchpoint(): All "
1258 "hardware resources (%u) are in use.",
1259 num_hw_watchpoints);
1260 }
1261 }
1262 return INVALID_NUB_HW_INDEX;
1263 }
1264
ReenableHardwareWatchpoint(uint32_t hw_index)1265 bool DNBArchMachARM::ReenableHardwareWatchpoint(uint32_t hw_index) {
1266 // If this logical watchpoint # is actually implemented using
1267 // two hardware watchpoint registers, re-enable both of them.
1268
1269 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) {
1270 return ReenableHardwareWatchpoint_helper(hw_index) &&
1271 ReenableHardwareWatchpoint_helper(LoHi[hw_index]);
1272 } else {
1273 return ReenableHardwareWatchpoint_helper(hw_index);
1274 }
1275 }
1276
ReenableHardwareWatchpoint_helper(uint32_t hw_index)1277 bool DNBArchMachARM::ReenableHardwareWatchpoint_helper(uint32_t hw_index) {
1278 kern_return_t kret = GetDBGState(false);
1279 if (kret != KERN_SUCCESS)
1280 return false;
1281 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1282 if (hw_index >= num_hw_points)
1283 return false;
1284
1285 m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr;
1286 m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control;
1287
1288 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint( "
1289 "%u ) - WVR%u = 0x%8.8llx WCR%u = "
1290 "0x%8.8llx",
1291 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index],
1292 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]);
1293
1294 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
1295 // automatically, don't need to do it here.
1296
1297 kret = SetDBGState(false);
1298
1299 return (kret == KERN_SUCCESS);
1300 }
1301
DisableHardwareWatchpoint(uint32_t hw_index,bool also_set_on_task)1302 bool DNBArchMachARM::DisableHardwareWatchpoint(uint32_t hw_index,
1303 bool also_set_on_task) {
1304 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) {
1305 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) &&
1306 DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task);
1307 } else {
1308 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task);
1309 }
1310 }
1311
DisableHardwareWatchpoint_helper(uint32_t hw_index,bool also_set_on_task)1312 bool DNBArchMachARM::DisableHardwareWatchpoint_helper(uint32_t hw_index,
1313 bool also_set_on_task) {
1314 kern_return_t kret = GetDBGState(false);
1315 if (kret != KERN_SUCCESS)
1316 return false;
1317
1318 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1319 if (hw_index >= num_hw_points)
1320 return false;
1321
1322 m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index];
1323 m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index];
1324
1325 m_state.dbg.__wvr[hw_index] = 0;
1326 m_state.dbg.__wcr[hw_index] = 0;
1327 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::DisableHardwareWatchpoint("
1328 " %u ) - WVR%u = 0x%8.8llx WCR%u = "
1329 "0x%8.8llx",
1330 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index],
1331 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]);
1332
1333 kret = SetDBGState(also_set_on_task);
1334
1335 return (kret == KERN_SUCCESS);
1336 }
1337
1338 // Returns -1 if the trailing bit patterns are not one of:
1339 // { 0b???1, 0b??10, 0b?100, 0b1000 }.
LowestBitSet(uint32_t val)1340 static inline int32_t LowestBitSet(uint32_t val) {
1341 for (unsigned i = 0; i < 4; ++i) {
1342 if (bit(val, i))
1343 return i;
1344 }
1345 return -1;
1346 }
1347
1348 // Iterate through the debug registers; return the index of the first watchpoint
1349 // whose address matches.
1350 // As a side effect, the starting address as understood by the debugger is
1351 // returned which could be
1352 // different from 'addr' passed as an in/out argument.
GetHardwareWatchpointHit(nub_addr_t & addr)1353 uint32_t DNBArchMachARM::GetHardwareWatchpointHit(nub_addr_t &addr) {
1354 // Read the debug state
1355 kern_return_t kret = GetDBGState(true);
1356 // DumpDBGState(m_state.dbg);
1357 DNBLogThreadedIf(
1358 LOG_WATCHPOINTS,
1359 "DNBArchMachARM::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.",
1360 kret);
1361 DNBLogThreadedIf(LOG_WATCHPOINTS,
1362 "DNBArchMachARM::GetHardwareWatchpointHit() addr = 0x%llx",
1363 (uint64_t)addr);
1364
1365 // This is the watchpoint value to match against, i.e., word address.
1366 #if defined(WATCHPOINTS_ARE_DWORD)
1367 nub_addr_t wp_val = addr & ~((nub_addr_t)7);
1368 #else
1369 nub_addr_t wp_val = addr & ~((nub_addr_t)3);
1370 #endif
1371 if (kret == KERN_SUCCESS) {
1372 DBG &debug_state = m_state.dbg;
1373 uint32_t i, num = NumSupportedHardwareWatchpoints();
1374 for (i = 0; i < num; ++i) {
1375 nub_addr_t wp_addr = GetWatchAddress(debug_state, i);
1376 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
1377 "GetHardwareWatchpointHit() slot: %u "
1378 "(addr = 0x%llx).",
1379 i, (uint64_t)wp_addr);
1380 if (wp_val == wp_addr) {
1381 #if defined(WATCHPOINTS_ARE_DWORD)
1382 uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5);
1383 #else
1384 uint32_t byte_mask = bits(debug_state.__wcr[i], 8, 5);
1385 #endif
1386
1387 // Sanity check the byte_mask, first.
1388 if (LowestBitSet(byte_mask) < 0)
1389 continue;
1390
1391 // Compute the starting address (from the point of view of the
1392 // debugger).
1393 addr = wp_addr + LowestBitSet(byte_mask);
1394 return i;
1395 }
1396 }
1397 }
1398 return INVALID_NUB_HW_INDEX;
1399 }
1400
GetWatchpointAddressByIndex(uint32_t hw_index)1401 nub_addr_t DNBArchMachARM::GetWatchpointAddressByIndex(uint32_t hw_index) {
1402 kern_return_t kret = GetDBGState(true);
1403 if (kret != KERN_SUCCESS)
1404 return INVALID_NUB_ADDRESS;
1405 const uint32_t num = NumSupportedHardwareWatchpoints();
1406 if (hw_index >= num)
1407 return INVALID_NUB_ADDRESS;
1408 if (IsWatchpointEnabled(m_state.dbg, hw_index))
1409 return GetWatchAddress(m_state.dbg, hw_index);
1410 return INVALID_NUB_ADDRESS;
1411 }
1412
IsWatchpointEnabled(const DBG & debug_state,uint32_t hw_index)1413 bool DNBArchMachARM::IsWatchpointEnabled(const DBG &debug_state,
1414 uint32_t hw_index) {
1415 // Watchpoint Control Registers, bitfield definitions
1416 // ...
1417 // Bits Value Description
1418 // [0] 0 Watchpoint disabled
1419 // 1 Watchpoint enabled.
1420 return (debug_state.__wcr[hw_index] & 1u);
1421 }
1422
GetWatchAddress(const DBG & debug_state,uint32_t hw_index)1423 nub_addr_t DNBArchMachARM::GetWatchAddress(const DBG &debug_state,
1424 uint32_t hw_index) {
1425 // Watchpoint Value Registers, bitfield definitions
1426 // Bits Description
1427 // [31:2] Watchpoint value (word address, i.e., 4-byte aligned)
1428 // [1:0] RAZ/SBZP
1429 return bits(debug_state.__wvr[hw_index], 31, 0);
1430 }
1431
1432 // Register information definitions for 32 bit ARMV7.
1433 enum gpr_regnums {
1434 gpr_r0 = 0,
1435 gpr_r1,
1436 gpr_r2,
1437 gpr_r3,
1438 gpr_r4,
1439 gpr_r5,
1440 gpr_r6,
1441 gpr_r7,
1442 gpr_r8,
1443 gpr_r9,
1444 gpr_r10,
1445 gpr_r11,
1446 gpr_r12,
1447 gpr_sp,
1448 gpr_lr,
1449 gpr_pc,
1450 gpr_cpsr
1451 };
1452
1453 enum {
1454 vfp_s0 = 0,
1455 vfp_s1,
1456 vfp_s2,
1457 vfp_s3,
1458 vfp_s4,
1459 vfp_s5,
1460 vfp_s6,
1461 vfp_s7,
1462 vfp_s8,
1463 vfp_s9,
1464 vfp_s10,
1465 vfp_s11,
1466 vfp_s12,
1467 vfp_s13,
1468 vfp_s14,
1469 vfp_s15,
1470 vfp_s16,
1471 vfp_s17,
1472 vfp_s18,
1473 vfp_s19,
1474 vfp_s20,
1475 vfp_s21,
1476 vfp_s22,
1477 vfp_s23,
1478 vfp_s24,
1479 vfp_s25,
1480 vfp_s26,
1481 vfp_s27,
1482 vfp_s28,
1483 vfp_s29,
1484 vfp_s30,
1485 vfp_s31,
1486 vfp_d0,
1487 vfp_d1,
1488 vfp_d2,
1489 vfp_d3,
1490 vfp_d4,
1491 vfp_d5,
1492 vfp_d6,
1493 vfp_d7,
1494 vfp_d8,
1495 vfp_d9,
1496 vfp_d10,
1497 vfp_d11,
1498 vfp_d12,
1499 vfp_d13,
1500 vfp_d14,
1501 vfp_d15,
1502 vfp_d16,
1503 vfp_d17,
1504 vfp_d18,
1505 vfp_d19,
1506 vfp_d20,
1507 vfp_d21,
1508 vfp_d22,
1509 vfp_d23,
1510 vfp_d24,
1511 vfp_d25,
1512 vfp_d26,
1513 vfp_d27,
1514 vfp_d28,
1515 vfp_d29,
1516 vfp_d30,
1517 vfp_d31,
1518 vfp_q0,
1519 vfp_q1,
1520 vfp_q2,
1521 vfp_q3,
1522 vfp_q4,
1523 vfp_q5,
1524 vfp_q6,
1525 vfp_q7,
1526 vfp_q8,
1527 vfp_q9,
1528 vfp_q10,
1529 vfp_q11,
1530 vfp_q12,
1531 vfp_q13,
1532 vfp_q14,
1533 vfp_q15,
1534 #if defined(__arm64__) || defined(__aarch64__)
1535 vfp_fpsr,
1536 vfp_fpcr,
1537 #else
1538 vfp_fpscr
1539 #endif
1540 };
1541
1542 enum {
1543 exc_exception,
1544 exc_fsr,
1545 exc_far,
1546 };
1547
1548 #define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM::GPR, __r[idx]))
1549 #define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM::GPR, __##reg))
1550
1551 #define EXC_OFFSET(reg) \
1552 (offsetof(DNBArchMachARM::EXC, __##reg) + \
1553 offsetof(DNBArchMachARM::Context, exc))
1554
1555 // These macros will auto define the register name, alt name, register size,
1556 // register offset, encoding, format and native register. This ensures that
1557 // the register state structures are defined correctly and have the correct
1558 // sizes and offsets.
1559 #define DEFINE_GPR_IDX(idx, reg, alt, gen) \
1560 { \
1561 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_IDX(idx), \
1562 ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, NULL \
1563 }
1564 #define DEFINE_GPR_NAME(reg, alt, gen, inval) \
1565 { \
1566 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_NAME(reg), \
1567 ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, inval \
1568 }
1569
1570 // In case we are debugging to a debug target that the ability to
1571 // change into the protected modes with folded registers (ABT, IRQ,
1572 // FIQ, SYS, USR, etc..), we should invalidate r8-r14 if the CPSR
1573 // gets modified.
1574
1575 const char *g_invalidate_cpsr[] = {"r8", "r9", "r10", "r11",
1576 "r12", "sp", "lr", NULL};
1577
1578 // General purpose registers
1579 const DNBRegisterInfo DNBArchMachARM::g_gpr_registers[] = {
1580 DEFINE_GPR_IDX(0, r0, "arg1", GENERIC_REGNUM_ARG1),
1581 DEFINE_GPR_IDX(1, r1, "arg2", GENERIC_REGNUM_ARG2),
1582 DEFINE_GPR_IDX(2, r2, "arg3", GENERIC_REGNUM_ARG3),
1583 DEFINE_GPR_IDX(3, r3, "arg4", GENERIC_REGNUM_ARG4),
1584 DEFINE_GPR_IDX(4, r4, NULL, INVALID_NUB_REGNUM),
1585 DEFINE_GPR_IDX(5, r5, NULL, INVALID_NUB_REGNUM),
1586 DEFINE_GPR_IDX(6, r6, NULL, INVALID_NUB_REGNUM),
1587 DEFINE_GPR_IDX(7, r7, "fp", GENERIC_REGNUM_FP),
1588 DEFINE_GPR_IDX(8, r8, NULL, INVALID_NUB_REGNUM),
1589 DEFINE_GPR_IDX(9, r9, NULL, INVALID_NUB_REGNUM),
1590 DEFINE_GPR_IDX(10, r10, NULL, INVALID_NUB_REGNUM),
1591 DEFINE_GPR_IDX(11, r11, NULL, INVALID_NUB_REGNUM),
1592 DEFINE_GPR_IDX(12, r12, NULL, INVALID_NUB_REGNUM),
1593 DEFINE_GPR_NAME(sp, "r13", GENERIC_REGNUM_SP, NULL),
1594 DEFINE_GPR_NAME(lr, "r14", GENERIC_REGNUM_RA, NULL),
1595 DEFINE_GPR_NAME(pc, "r15", GENERIC_REGNUM_PC, NULL),
1596 DEFINE_GPR_NAME(cpsr, "flags", GENERIC_REGNUM_FLAGS, g_invalidate_cpsr)};
1597
1598 const char *g_contained_q0[]{"q0", NULL};
1599 const char *g_contained_q1[]{"q1", NULL};
1600 const char *g_contained_q2[]{"q2", NULL};
1601 const char *g_contained_q3[]{"q3", NULL};
1602 const char *g_contained_q4[]{"q4", NULL};
1603 const char *g_contained_q5[]{"q5", NULL};
1604 const char *g_contained_q6[]{"q6", NULL};
1605 const char *g_contained_q7[]{"q7", NULL};
1606 const char *g_contained_q8[]{"q8", NULL};
1607 const char *g_contained_q9[]{"q9", NULL};
1608 const char *g_contained_q10[]{"q10", NULL};
1609 const char *g_contained_q11[]{"q11", NULL};
1610 const char *g_contained_q12[]{"q12", NULL};
1611 const char *g_contained_q13[]{"q13", NULL};
1612 const char *g_contained_q14[]{"q14", NULL};
1613 const char *g_contained_q15[]{"q15", NULL};
1614
1615 const char *g_invalidate_q0[]{"q0", "d0", "d1", "s0", "s1", "s2", "s3", NULL};
1616 const char *g_invalidate_q1[]{"q1", "d2", "d3", "s4", "s5", "s6", "s7", NULL};
1617 const char *g_invalidate_q2[]{"q2", "d4", "d5", "s8", "s9", "s10", "s11", NULL};
1618 const char *g_invalidate_q3[]{"q3", "d6", "d7", "s12",
1619 "s13", "s14", "s15", NULL};
1620 const char *g_invalidate_q4[]{"q4", "d8", "d9", "s16",
1621 "s17", "s18", "s19", NULL};
1622 const char *g_invalidate_q5[]{"q5", "d10", "d11", "s20",
1623 "s21", "s22", "s23", NULL};
1624 const char *g_invalidate_q6[]{"q6", "d12", "d13", "s24",
1625 "s25", "s26", "s27", NULL};
1626 const char *g_invalidate_q7[]{"q7", "d14", "d15", "s28",
1627 "s29", "s30", "s31", NULL};
1628 const char *g_invalidate_q8[]{"q8", "d16", "d17", NULL};
1629 const char *g_invalidate_q9[]{"q9", "d18", "d19", NULL};
1630 const char *g_invalidate_q10[]{"q10", "d20", "d21", NULL};
1631 const char *g_invalidate_q11[]{"q11", "d22", "d23", NULL};
1632 const char *g_invalidate_q12[]{"q12", "d24", "d25", NULL};
1633 const char *g_invalidate_q13[]{"q13", "d26", "d27", NULL};
1634 const char *g_invalidate_q14[]{"q14", "d28", "d29", NULL};
1635 const char *g_invalidate_q15[]{"q15", "d30", "d31", NULL};
1636
1637 #define VFP_S_OFFSET_IDX(idx) \
1638 (((idx) % 4) * 4) // offset into q reg: 0, 4, 8, 12
1639 #define VFP_D_OFFSET_IDX(idx) (((idx) % 2) * 8) // offset into q reg: 0, 8
1640 #define VFP_Q_OFFSET_IDX(idx) (VFP_S_OFFSET_IDX((idx)*4))
1641
1642 #define VFP_OFFSET_NAME(reg) \
1643 (offsetof(DNBArchMachARM::FPU, __##reg) + \
1644 offsetof(DNBArchMachARM::Context, vfp))
1645
1646 #define FLOAT_FORMAT Float
1647
1648 #define DEFINE_VFP_S_IDX(idx) \
1649 e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, FLOAT_FORMAT, 4, \
1650 VFP_S_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_s##idx, \
1651 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
1652 #define DEFINE_VFP_D_IDX(idx) \
1653 e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, FLOAT_FORMAT, 8, \
1654 VFP_D_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_d##idx, \
1655 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
1656 #define DEFINE_VFP_Q_IDX(idx) \
1657 e_regSetVFP, vfp_q##idx, "q" #idx, NULL, Vector, VectorOfUInt8, 16, \
1658 VFP_Q_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_q##idx, \
1659 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
1660
1661 // Floating point registers
1662 const DNBRegisterInfo DNBArchMachARM::g_vfp_registers[] = {
1663 {DEFINE_VFP_S_IDX(0), g_contained_q0, g_invalidate_q0},
1664 {DEFINE_VFP_S_IDX(1), g_contained_q0, g_invalidate_q0},
1665 {DEFINE_VFP_S_IDX(2), g_contained_q0, g_invalidate_q0},
1666 {DEFINE_VFP_S_IDX(3), g_contained_q0, g_invalidate_q0},
1667 {DEFINE_VFP_S_IDX(4), g_contained_q1, g_invalidate_q1},
1668 {DEFINE_VFP_S_IDX(5), g_contained_q1, g_invalidate_q1},
1669 {DEFINE_VFP_S_IDX(6), g_contained_q1, g_invalidate_q1},
1670 {DEFINE_VFP_S_IDX(7), g_contained_q1, g_invalidate_q1},
1671 {DEFINE_VFP_S_IDX(8), g_contained_q2, g_invalidate_q2},
1672 {DEFINE_VFP_S_IDX(9), g_contained_q2, g_invalidate_q2},
1673 {DEFINE_VFP_S_IDX(10), g_contained_q2, g_invalidate_q2},
1674 {DEFINE_VFP_S_IDX(11), g_contained_q2, g_invalidate_q2},
1675 {DEFINE_VFP_S_IDX(12), g_contained_q3, g_invalidate_q3},
1676 {DEFINE_VFP_S_IDX(13), g_contained_q3, g_invalidate_q3},
1677 {DEFINE_VFP_S_IDX(14), g_contained_q3, g_invalidate_q3},
1678 {DEFINE_VFP_S_IDX(15), g_contained_q3, g_invalidate_q3},
1679 {DEFINE_VFP_S_IDX(16), g_contained_q4, g_invalidate_q4},
1680 {DEFINE_VFP_S_IDX(17), g_contained_q4, g_invalidate_q4},
1681 {DEFINE_VFP_S_IDX(18), g_contained_q4, g_invalidate_q4},
1682 {DEFINE_VFP_S_IDX(19), g_contained_q4, g_invalidate_q4},
1683 {DEFINE_VFP_S_IDX(20), g_contained_q5, g_invalidate_q5},
1684 {DEFINE_VFP_S_IDX(21), g_contained_q5, g_invalidate_q5},
1685 {DEFINE_VFP_S_IDX(22), g_contained_q5, g_invalidate_q5},
1686 {DEFINE_VFP_S_IDX(23), g_contained_q5, g_invalidate_q5},
1687 {DEFINE_VFP_S_IDX(24), g_contained_q6, g_invalidate_q6},
1688 {DEFINE_VFP_S_IDX(25), g_contained_q6, g_invalidate_q6},
1689 {DEFINE_VFP_S_IDX(26), g_contained_q6, g_invalidate_q6},
1690 {DEFINE_VFP_S_IDX(27), g_contained_q6, g_invalidate_q6},
1691 {DEFINE_VFP_S_IDX(28), g_contained_q7, g_invalidate_q7},
1692 {DEFINE_VFP_S_IDX(29), g_contained_q7, g_invalidate_q7},
1693 {DEFINE_VFP_S_IDX(30), g_contained_q7, g_invalidate_q7},
1694 {DEFINE_VFP_S_IDX(31), g_contained_q7, g_invalidate_q7},
1695
1696 {DEFINE_VFP_D_IDX(0), g_contained_q0, g_invalidate_q0},
1697 {DEFINE_VFP_D_IDX(1), g_contained_q0, g_invalidate_q0},
1698 {DEFINE_VFP_D_IDX(2), g_contained_q1, g_invalidate_q1},
1699 {DEFINE_VFP_D_IDX(3), g_contained_q1, g_invalidate_q1},
1700 {DEFINE_VFP_D_IDX(4), g_contained_q2, g_invalidate_q2},
1701 {DEFINE_VFP_D_IDX(5), g_contained_q2, g_invalidate_q2},
1702 {DEFINE_VFP_D_IDX(6), g_contained_q3, g_invalidate_q3},
1703 {DEFINE_VFP_D_IDX(7), g_contained_q3, g_invalidate_q3},
1704 {DEFINE_VFP_D_IDX(8), g_contained_q4, g_invalidate_q4},
1705 {DEFINE_VFP_D_IDX(9), g_contained_q4, g_invalidate_q4},
1706 {DEFINE_VFP_D_IDX(10), g_contained_q5, g_invalidate_q5},
1707 {DEFINE_VFP_D_IDX(11), g_contained_q5, g_invalidate_q5},
1708 {DEFINE_VFP_D_IDX(12), g_contained_q6, g_invalidate_q6},
1709 {DEFINE_VFP_D_IDX(13), g_contained_q6, g_invalidate_q6},
1710 {DEFINE_VFP_D_IDX(14), g_contained_q7, g_invalidate_q7},
1711 {DEFINE_VFP_D_IDX(15), g_contained_q7, g_invalidate_q7},
1712 {DEFINE_VFP_D_IDX(16), g_contained_q8, g_invalidate_q8},
1713 {DEFINE_VFP_D_IDX(17), g_contained_q8, g_invalidate_q8},
1714 {DEFINE_VFP_D_IDX(18), g_contained_q9, g_invalidate_q9},
1715 {DEFINE_VFP_D_IDX(19), g_contained_q9, g_invalidate_q9},
1716 {DEFINE_VFP_D_IDX(20), g_contained_q10, g_invalidate_q10},
1717 {DEFINE_VFP_D_IDX(21), g_contained_q10, g_invalidate_q10},
1718 {DEFINE_VFP_D_IDX(22), g_contained_q11, g_invalidate_q11},
1719 {DEFINE_VFP_D_IDX(23), g_contained_q11, g_invalidate_q11},
1720 {DEFINE_VFP_D_IDX(24), g_contained_q12, g_invalidate_q12},
1721 {DEFINE_VFP_D_IDX(25), g_contained_q12, g_invalidate_q12},
1722 {DEFINE_VFP_D_IDX(26), g_contained_q13, g_invalidate_q13},
1723 {DEFINE_VFP_D_IDX(27), g_contained_q13, g_invalidate_q13},
1724 {DEFINE_VFP_D_IDX(28), g_contained_q14, g_invalidate_q14},
1725 {DEFINE_VFP_D_IDX(29), g_contained_q14, g_invalidate_q14},
1726 {DEFINE_VFP_D_IDX(30), g_contained_q15, g_invalidate_q15},
1727 {DEFINE_VFP_D_IDX(31), g_contained_q15, g_invalidate_q15},
1728
1729 {DEFINE_VFP_Q_IDX(0), NULL, g_invalidate_q0},
1730 {DEFINE_VFP_Q_IDX(1), NULL, g_invalidate_q1},
1731 {DEFINE_VFP_Q_IDX(2), NULL, g_invalidate_q2},
1732 {DEFINE_VFP_Q_IDX(3), NULL, g_invalidate_q3},
1733 {DEFINE_VFP_Q_IDX(4), NULL, g_invalidate_q4},
1734 {DEFINE_VFP_Q_IDX(5), NULL, g_invalidate_q5},
1735 {DEFINE_VFP_Q_IDX(6), NULL, g_invalidate_q6},
1736 {DEFINE_VFP_Q_IDX(7), NULL, g_invalidate_q7},
1737 {DEFINE_VFP_Q_IDX(8), NULL, g_invalidate_q8},
1738 {DEFINE_VFP_Q_IDX(9), NULL, g_invalidate_q9},
1739 {DEFINE_VFP_Q_IDX(10), NULL, g_invalidate_q10},
1740 {DEFINE_VFP_Q_IDX(11), NULL, g_invalidate_q11},
1741 {DEFINE_VFP_Q_IDX(12), NULL, g_invalidate_q12},
1742 {DEFINE_VFP_Q_IDX(13), NULL, g_invalidate_q13},
1743 {DEFINE_VFP_Q_IDX(14), NULL, g_invalidate_q14},
1744 {DEFINE_VFP_Q_IDX(15), NULL, g_invalidate_q15},
1745
1746 #if defined(__arm64__) || defined(__aarch64__)
1747 {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpsr),
1748 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1749 INVALID_NUB_REGNUM, NULL, NULL},
1750 {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpcr),
1751 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1752 INVALID_NUB_REGNUM, NULL, NULL}
1753 #else
1754 {e_regSetVFP, vfp_fpscr, "fpscr", NULL, Uint, Hex, 4,
1755 VFP_OFFSET_NAME(fpscr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1756 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}
1757 #endif
1758 };
1759
1760 // Exception registers
1761
1762 const DNBRegisterInfo DNBArchMachARM::g_exc_registers[] = {
1763 {e_regSetVFP, exc_exception, "exception", NULL, Uint, Hex, 4,
1764 EXC_OFFSET(exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1765 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1766 {e_regSetVFP, exc_fsr, "fsr", NULL, Uint, Hex, 4, EXC_OFFSET(fsr),
1767 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1768 INVALID_NUB_REGNUM, NULL, NULL},
1769 {e_regSetVFP, exc_far, "far", NULL, Uint, Hex, 4, EXC_OFFSET(far),
1770 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1771 INVALID_NUB_REGNUM, NULL, NULL}};
1772
1773 // Number of registers in each register set
1774 const size_t DNBArchMachARM::k_num_gpr_registers =
1775 sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo);
1776 const size_t DNBArchMachARM::k_num_vfp_registers =
1777 sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo);
1778 const size_t DNBArchMachARM::k_num_exc_registers =
1779 sizeof(g_exc_registers) / sizeof(DNBRegisterInfo);
1780 const size_t DNBArchMachARM::k_num_all_registers =
1781 k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers;
1782
1783 // Register set definitions. The first definitions at register set index
1784 // of zero is for all registers, followed by other registers sets. The
1785 // register information for the all register set need not be filled in.
1786 const DNBRegisterSetInfo DNBArchMachARM::g_reg_sets[] = {
1787 {"ARM Registers", NULL, k_num_all_registers},
1788 {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
1789 {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers},
1790 {"Exception State Registers", g_exc_registers, k_num_exc_registers}};
1791 // Total number of register sets for this architecture
1792 const size_t DNBArchMachARM::k_num_register_sets =
1793 sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo);
1794
1795 const DNBRegisterSetInfo *
GetRegisterSetInfo(nub_size_t * num_reg_sets)1796 DNBArchMachARM::GetRegisterSetInfo(nub_size_t *num_reg_sets) {
1797 *num_reg_sets = k_num_register_sets;
1798 return g_reg_sets;
1799 }
1800
GetRegisterValue(uint32_t set,uint32_t reg,DNBRegisterValue * value)1801 bool DNBArchMachARM::GetRegisterValue(uint32_t set, uint32_t reg,
1802 DNBRegisterValue *value) {
1803 if (set == REGISTER_SET_GENERIC) {
1804 switch (reg) {
1805 case GENERIC_REGNUM_PC: // Program Counter
1806 set = e_regSetGPR;
1807 reg = gpr_pc;
1808 break;
1809
1810 case GENERIC_REGNUM_SP: // Stack Pointer
1811 set = e_regSetGPR;
1812 reg = gpr_sp;
1813 break;
1814
1815 case GENERIC_REGNUM_FP: // Frame Pointer
1816 set = e_regSetGPR;
1817 reg = gpr_r7; // is this the right reg?
1818 break;
1819
1820 case GENERIC_REGNUM_RA: // Return Address
1821 set = e_regSetGPR;
1822 reg = gpr_lr;
1823 break;
1824
1825 case GENERIC_REGNUM_FLAGS: // Processor flags register
1826 set = e_regSetGPR;
1827 reg = gpr_cpsr;
1828 break;
1829
1830 default:
1831 return false;
1832 }
1833 }
1834
1835 if (GetRegisterState(set, false) != KERN_SUCCESS)
1836 return false;
1837
1838 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
1839 if (regInfo) {
1840 value->info = *regInfo;
1841 switch (set) {
1842 case e_regSetGPR:
1843 if (reg < k_num_gpr_registers) {
1844 value->value.uint32 = m_state.context.gpr.__r[reg];
1845 return true;
1846 }
1847 break;
1848
1849 case e_regSetVFP:
1850 // "reg" is an index into the floating point register set at this point.
1851 // We need to translate it up so entry 0 in the fp reg set is the same as
1852 // vfp_s0
1853 // in the enumerated values for case statement below.
1854 if (reg >= vfp_s0 && reg <= vfp_s31) {
1855 #if defined(__arm64__) || defined(__aarch64__)
1856 uint32_t *s_reg =
1857 ((uint32_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_s0);
1858 memcpy(&value->value.v_uint8, s_reg, 4);
1859 #else
1860 value->value.uint32 = m_state.context.vfp.__r[reg];
1861 #endif
1862 return true;
1863 } else if (reg >= vfp_d0 && reg <= vfp_d31) {
1864 #if defined(__arm64__) || defined(__aarch64__)
1865 uint64_t *d_reg =
1866 ((uint64_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_d0);
1867 memcpy(&value->value.v_uint8, d_reg, 8);
1868 #else
1869 uint32_t d_reg_idx = reg - vfp_d0;
1870 uint32_t s_reg_idx = d_reg_idx * 2;
1871 value->value.v_sint32[0] = m_state.context.vfp.__r[s_reg_idx + 0];
1872 value->value.v_sint32[1] = m_state.context.vfp.__r[s_reg_idx + 1];
1873 #endif
1874 return true;
1875 } else if (reg >= vfp_q0 && reg <= vfp_q15) {
1876 #if defined(__arm64__) || defined(__aarch64__)
1877 memcpy(&value->value.v_uint8,
1878 (uint8_t *)&m_state.context.vfp.__v[reg - vfp_q0], 16);
1879 #else
1880 uint32_t s_reg_idx = (reg - vfp_q0) * 4;
1881 memcpy(&value->value.v_uint8,
1882 (uint8_t *)&m_state.context.vfp.__r[s_reg_idx], 16);
1883 #endif
1884 return true;
1885 }
1886 #if defined(__arm64__) || defined(__aarch64__)
1887 else if (reg == vfp_fpsr) {
1888 value->value.uint32 = m_state.context.vfp.__fpsr;
1889 return true;
1890 } else if (reg == vfp_fpcr) {
1891 value->value.uint32 = m_state.context.vfp.__fpcr;
1892 return true;
1893 }
1894 #else
1895 else if (reg == vfp_fpscr) {
1896 value->value.uint32 = m_state.context.vfp.__fpscr;
1897 return true;
1898 }
1899 #endif
1900 break;
1901
1902 case e_regSetEXC:
1903 if (reg < k_num_exc_registers) {
1904 value->value.uint32 = (&m_state.context.exc.__exception)[reg];
1905 return true;
1906 }
1907 break;
1908 }
1909 }
1910 return false;
1911 }
1912
SetRegisterValue(uint32_t set,uint32_t reg,const DNBRegisterValue * value)1913 bool DNBArchMachARM::SetRegisterValue(uint32_t set, uint32_t reg,
1914 const DNBRegisterValue *value) {
1915 if (set == REGISTER_SET_GENERIC) {
1916 switch (reg) {
1917 case GENERIC_REGNUM_PC: // Program Counter
1918 set = e_regSetGPR;
1919 reg = gpr_pc;
1920 break;
1921
1922 case GENERIC_REGNUM_SP: // Stack Pointer
1923 set = e_regSetGPR;
1924 reg = gpr_sp;
1925 break;
1926
1927 case GENERIC_REGNUM_FP: // Frame Pointer
1928 set = e_regSetGPR;
1929 reg = gpr_r7;
1930 break;
1931
1932 case GENERIC_REGNUM_RA: // Return Address
1933 set = e_regSetGPR;
1934 reg = gpr_lr;
1935 break;
1936
1937 case GENERIC_REGNUM_FLAGS: // Processor flags register
1938 set = e_regSetGPR;
1939 reg = gpr_cpsr;
1940 break;
1941
1942 default:
1943 return false;
1944 }
1945 }
1946
1947 if (GetRegisterState(set, false) != KERN_SUCCESS)
1948 return false;
1949
1950 bool success = false;
1951 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
1952 if (regInfo) {
1953 switch (set) {
1954 case e_regSetGPR:
1955 if (reg < k_num_gpr_registers) {
1956 m_state.context.gpr.__r[reg] = value->value.uint32;
1957 success = true;
1958 }
1959 break;
1960
1961 case e_regSetVFP:
1962 // "reg" is an index into the floating point register set at this point.
1963 // We need to translate it up so entry 0 in the fp reg set is the same as
1964 // vfp_s0
1965 // in the enumerated values for case statement below.
1966 if (reg >= vfp_s0 && reg <= vfp_s31) {
1967 #if defined(__arm64__) || defined(__aarch64__)
1968 uint32_t *s_reg =
1969 ((uint32_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_s0);
1970 memcpy(s_reg, &value->value.v_uint8, 4);
1971 #else
1972 m_state.context.vfp.__r[reg] = value->value.uint32;
1973 #endif
1974 success = true;
1975 } else if (reg >= vfp_d0 && reg <= vfp_d31) {
1976 #if defined(__arm64__) || defined(__aarch64__)
1977 uint64_t *d_reg =
1978 ((uint64_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_d0);
1979 memcpy(d_reg, &value->value.v_uint8, 8);
1980 #else
1981 uint32_t d_reg_idx = reg - vfp_d0;
1982 uint32_t s_reg_idx = d_reg_idx * 2;
1983 m_state.context.vfp.__r[s_reg_idx + 0] = value->value.v_sint32[0];
1984 m_state.context.vfp.__r[s_reg_idx + 1] = value->value.v_sint32[1];
1985 #endif
1986 success = true;
1987 } else if (reg >= vfp_q0 && reg <= vfp_q15) {
1988 #if defined(__arm64__) || defined(__aarch64__)
1989 memcpy((uint8_t *)&m_state.context.vfp.__v[reg - vfp_q0],
1990 &value->value.v_uint8, 16);
1991 #else
1992 uint32_t s_reg_idx = (reg - vfp_q0) * 4;
1993 memcpy((uint8_t *)&m_state.context.vfp.__r[s_reg_idx],
1994 &value->value.v_uint8, 16);
1995 #endif
1996 success = true;
1997 }
1998 #if defined(__arm64__) || defined(__aarch64__)
1999 else if (reg == vfp_fpsr) {
2000 m_state.context.vfp.__fpsr = value->value.uint32;
2001 success = true;
2002 } else if (reg == vfp_fpcr) {
2003 m_state.context.vfp.__fpcr = value->value.uint32;
2004 success = true;
2005 }
2006 #else
2007 else if (reg == vfp_fpscr) {
2008 m_state.context.vfp.__fpscr = value->value.uint32;
2009 success = true;
2010 }
2011 #endif
2012 break;
2013
2014 case e_regSetEXC:
2015 if (reg < k_num_exc_registers) {
2016 (&m_state.context.exc.__exception)[reg] = value->value.uint32;
2017 success = true;
2018 }
2019 break;
2020 }
2021 }
2022 if (success)
2023 return SetRegisterState(set) == KERN_SUCCESS;
2024 return false;
2025 }
2026
GetRegisterState(int set,bool force)2027 kern_return_t DNBArchMachARM::GetRegisterState(int set, bool force) {
2028 switch (set) {
2029 case e_regSetALL:
2030 return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) |
2031 GetDBGState(force);
2032 case e_regSetGPR:
2033 return GetGPRState(force);
2034 case e_regSetVFP:
2035 return GetVFPState(force);
2036 case e_regSetEXC:
2037 return GetEXCState(force);
2038 case e_regSetDBG:
2039 return GetDBGState(force);
2040 default:
2041 break;
2042 }
2043 return KERN_INVALID_ARGUMENT;
2044 }
2045
SetRegisterState(int set)2046 kern_return_t DNBArchMachARM::SetRegisterState(int set) {
2047 // Make sure we have a valid context to set.
2048 kern_return_t err = GetRegisterState(set, false);
2049 if (err != KERN_SUCCESS)
2050 return err;
2051
2052 switch (set) {
2053 case e_regSetALL:
2054 return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false);
2055 case e_regSetGPR:
2056 return SetGPRState();
2057 case e_regSetVFP:
2058 return SetVFPState();
2059 case e_regSetEXC:
2060 return SetEXCState();
2061 case e_regSetDBG:
2062 return SetDBGState(false);
2063 default:
2064 break;
2065 }
2066 return KERN_INVALID_ARGUMENT;
2067 }
2068
RegisterSetStateIsValid(int set) const2069 bool DNBArchMachARM::RegisterSetStateIsValid(int set) const {
2070 return m_state.RegsAreValid(set);
2071 }
2072
GetRegisterContext(void * buf,nub_size_t buf_len)2073 nub_size_t DNBArchMachARM::GetRegisterContext(void *buf, nub_size_t buf_len) {
2074 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) +
2075 sizeof(m_state.context.exc);
2076
2077 if (buf && buf_len) {
2078 if (size > buf_len)
2079 size = buf_len;
2080
2081 bool force = false;
2082 if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force))
2083 return 0;
2084
2085 // Copy each struct individually to avoid any padding that might be between
2086 // the structs in m_state.context
2087 uint8_t *p = (uint8_t *)buf;
2088 ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr));
2089 p += sizeof(m_state.context.gpr);
2090 ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp));
2091 p += sizeof(m_state.context.vfp);
2092 ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc));
2093 p += sizeof(m_state.context.exc);
2094
2095 size_t bytes_written = p - (uint8_t *)buf;
2096 UNUSED_IF_ASSERT_DISABLED(bytes_written);
2097 assert(bytes_written == size);
2098 }
2099 DNBLogThreadedIf(
2100 LOG_THREAD,
2101 "DNBArchMachARM::GetRegisterContext (buf = %p, len = %llu) => %llu", buf,
2102 (uint64_t)buf_len, (uint64_t)size);
2103 // Return the size of the register context even if NULL was passed in
2104 return size;
2105 }
2106
SetRegisterContext(const void * buf,nub_size_t buf_len)2107 nub_size_t DNBArchMachARM::SetRegisterContext(const void *buf,
2108 nub_size_t buf_len) {
2109 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) +
2110 sizeof(m_state.context.exc);
2111
2112 if (buf == NULL || buf_len == 0)
2113 size = 0;
2114
2115 if (size) {
2116 if (size > buf_len)
2117 size = buf_len;
2118
2119 // Copy each struct individually to avoid any padding that might be between
2120 // the structs in m_state.context
2121 uint8_t *p = const_cast<uint8_t*>(reinterpret_cast<const uint8_t *>(buf));
2122 ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr));
2123 p += sizeof(m_state.context.gpr);
2124 ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp));
2125 p += sizeof(m_state.context.vfp);
2126 ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc));
2127 p += sizeof(m_state.context.exc);
2128
2129 size_t bytes_written = p - reinterpret_cast<const uint8_t *>(buf);
2130 UNUSED_IF_ASSERT_DISABLED(bytes_written);
2131 assert(bytes_written == size);
2132
2133 if (SetGPRState() | SetVFPState() | SetEXCState())
2134 return 0;
2135 }
2136 DNBLogThreadedIf(
2137 LOG_THREAD,
2138 "DNBArchMachARM::SetRegisterContext (buf = %p, len = %llu) => %llu", buf,
2139 (uint64_t)buf_len, (uint64_t)size);
2140 return size;
2141 }
2142
SaveRegisterState()2143 uint32_t DNBArchMachARM::SaveRegisterState() {
2144 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
2145 DNBLogThreadedIf(
2146 LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u "
2147 "(SetGPRState() for stop_count = %u)",
2148 m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
2149
2150 // Always re-read the registers because above we call thread_abort_safely();
2151 bool force = true;
2152
2153 if ((kret = GetGPRState(force)) != KERN_SUCCESS) {
2154 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: "
2155 "GPR regs failed to read: %u ",
2156 kret);
2157 } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) {
2158 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: "
2159 "%s regs failed to read: %u",
2160 "VFP", kret);
2161 } else {
2162 const uint32_t save_id = GetNextRegisterStateSaveID();
2163 m_saved_register_states[save_id] = m_state.context;
2164 return save_id;
2165 }
2166 return UINT32_MAX;
2167 }
2168
RestoreRegisterState(uint32_t save_id)2169 bool DNBArchMachARM::RestoreRegisterState(uint32_t save_id) {
2170 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id);
2171 if (pos != m_saved_register_states.end()) {
2172 m_state.context.gpr = pos->second.gpr;
2173 m_state.context.vfp = pos->second.vfp;
2174 kern_return_t kret;
2175 bool success = true;
2176 if ((kret = SetGPRState()) != KERN_SUCCESS) {
2177 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::RestoreRegisterState "
2178 "(save_id = %u) error: GPR regs failed to "
2179 "write: %u",
2180 save_id, kret);
2181 success = false;
2182 } else if ((kret = SetVFPState()) != KERN_SUCCESS) {
2183 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::RestoreRegisterState "
2184 "(save_id = %u) error: %s regs failed to "
2185 "write: %u",
2186 save_id, "VFP", kret);
2187 success = false;
2188 }
2189 m_saved_register_states.erase(pos);
2190 return success;
2191 }
2192 return false;
2193 }
2194
2195 #endif // #if defined (__arm__)
2196