1 /*--------------------------------------------------------------------------
2 P89LPC932.H
3 (English)
4 This header allows to use the microcontroler Philips P89LPC932
5 with the compiler SDCC.
6 
7 Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com.
8 
9    This library is free software; you can redistribute it and/or
10    modify it under the terms of the GNU Lesser General Public
11    License as published by the Free Software Foundation; either
12    version 2.1 of the License, or (at your option) any later version.
13 
14    This library is distributed in the hope that it will be useful,
15    but WITHOUT ANY WARRANTY; without even the implied warranty of
16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17    Lesser General Public License for more details.
18 
19    You should have received a copy of the GNU Lesser General Public
20    License along with this library; if not, write to the Free Software
21    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
22 
23 (Spanish-Espa�ol)
24 Archivo encabezador para el ucontrolador Philips P89LPC932.
25 Derechos de copy (DC) 2005.  OMAR ESPINOSA P.  E-mail: opiedrahita2003 AT yahoo.com
26 Uso libre
27 --------------------------------------------------------------------------*/
28 #ifndef __REG932_H__
29 #define __REG932_H__
30 
31 /*  BYTE Registers  */
32 __sfr __at (0x80) P0     ;
33 __sfr __at (0x90) P1     ;
34 __sfr __at (0xA0) P2     ;
35 __sfr __at (0xB0) P3     ;
36 __sfr __at (0xD0) PSW    ;
37 __sfr __at (0xE0) ACC    ;
38 __sfr __at (0xF0) B      ;
39 __sfr __at (0x81) SP     ;
40 __sfr __at (0x82) DPL    ;
41 __sfr __at (0x83) DPH    ;
42 __sfr __at (0x87) PCON   ;
43 __sfr __at (0x88) TCON   ;
44 __sfr __at (0x89) TMOD   ;
45 __sfr __at (0x8A) TL0    ;
46 __sfr __at (0x8B) TL1    ;
47 __sfr __at (0x8C) TH0    ;
48 __sfr __at (0x8D) TH1    ;
49 __sfr __at (0xA8) IEN0   ;
50 __sfr __at (0xB8) IP0    ;
51 __sfr __at (0x98) SCON   ;
52 __sfr __at (0x99) SBUF   ;
53 
54 
55 __sfr __at (0xA2) AUXR1  ;
56 __sfr __at (0xA9) SADDR  ;
57 __sfr __at (0xB9) SADEN  ;
58 __sfr __at (0xCC) TL2    ;
59 __sfr __at (0xCD) TH2    ;
60 __sfr __at (0xBE) BRGR0  ;
61 __sfr __at (0xBF) BRGR1  ;
62 __sfr __at (0xBD) BRGCON ;
63 __sfr __at (0xEA) CCCRA  ;
64 __sfr __at (0xEB) CCCRB  ;
65 __sfr __at (0xEC) CCCRC  ;
66 __sfr __at (0xED) CCCRD  ;
67 __sfr __at (0xAC) CMP1   ;
68 __sfr __at (0xAD) CMP2   ;
69 __sfr __at (0xF1) DEECON ;
70 __sfr __at (0xF2) DEEDAT ;
71 __sfr __at (0xF3) DEEADR ;
72 __sfr __at (0x95) DIVM   ;
73 __sfr __at (0xDB) I2ADR  ;
74 __sfr __at (0xD8) I2CON  ;
75 __sfr __at (0xDA) I2DAT  ;
76 __sfr __at (0xDD) I2SCLH ;
77 __sfr __at (0xDC) I2SCLL ;
78 __sfr __at (0xD9) I2STAT ;
79 __sfr __at (0xAB) ICRAH  ;
80 __sfr __at (0xAA) ICRAL  ;
81 __sfr __at (0xAF) ICRBH  ;
82 __sfr __at (0xAE) ICRBL  ;
83 __sfr __at (0xE8) IEN1   ;
84 __sfr __at (0xF8) IP1    ;
85 __sfr __at (0xF7) IP1H   ;
86 __sfr __at (0x94) KBCON  ;
87 __sfr __at (0x86) KBMASK ;
88 __sfr __at (0x93) KBPATN ;
89 __sfr __at (0xEF) OCRAH  ;
90 __sfr __at (0xEE) OCRAL  ;
91 __sfr __at (0xFB) OCRBH  ;
92 __sfr __at (0xFA) OCRBL  ;
93 __sfr __at (0xFD) OCRCH  ;
94 __sfr __at (0xFC) OCRCL  ;
95 __sfr __at (0xFF) OCRDH  ;
96 __sfr __at (0xFE) OCRDL  ;
97 __sfr __at (0x84) P0M1   ;
98 __sfr __at (0x85) P0M2   ;
99 __sfr __at (0x91) P1M1   ;
100 __sfr __at (0x92) P1M2   ;
101 __sfr __at (0xA4) P2M1   ;
102 __sfr __at (0xA5) P2M2   ;
103 __sfr __at (0xB1) P3M1   ;
104 __sfr __at (0xB2) P3M2   ;
105 __sfr __at (0xB5) PCONA  ;
106 __sfr __at (0xF6) PT0AD  ;
107 __sfr __at (0xDF) RSTSRC ;
108 __sfr __at (0xD1) RTCCON ;
109 __sfr __at (0xD2) RTCH   ;
110 __sfr __at (0xD3) RTCL   ;
111 __sfr __at (0xBA) SSTAT  ;
112 __sfr __at (0xE2) SPCTL  ;
113 __sfr __at (0xE1) SPSTAT ;
114 __sfr __at (0xE3) SPDAT  ;
115 __sfr __at (0x8F) TAMOD  ;
116 __sfr __at (0xC8) TCR20  ;
117 __sfr __at (0xF9) TCR21  ;
118 __sfr __at (0xC9) TICR2  ;
119 __sfr __at (0xE9) TIFR2  ;
120 __sfr __at (0xDE) TISE2  ;
121 __sfr __at (0xCF) TOR2H  ;
122 __sfr __at (0xCE) TOR2L  ;
123 __sfr __at (0xCB) TPCR2H ;
124 __sfr __at (0xCA) TPCR2L ;
125 __sfr __at (0x96) TRIM   ;
126 __sfr __at (0xA7) WDCON  ;
127 __sfr __at (0xC1) WDL    ;
128 __sfr __at (0xC2) WFEED1 ;
129 __sfr __at (0xC3) WFEED2 ;
130 __sfr __at (0xB7) IP0H   ;
131 
132 /*  BIT Registers  */
133 /*  PSW   */
134 __sbit __at (0xD7)    PSW_7;
135 __sbit __at (0xD6)    PSW_6;
136 __sbit __at (0xD5)    PSW_5;
137 __sbit __at (0xD4)    PSW_4;
138 __sbit __at (0xD3)    PSW_3;
139 __sbit __at (0xD2)    PSW_2;
140 __sbit __at (0xD1)    PSW_1;
141 __sbit __at (0xD0)    PSW_0;
142 
143 #define CY      PSW_7
144 #define AC      PSW_6
145 #define F0      PSW_5
146 #define RS1     PSW_4
147 #define RS0     PSW_3
148 #define OV      PSW_2
149 #define F1      PSW_1
150 #define P       PSW_0
151 
152 /*  TCON  */
153 __sbit __at (0x8F)    TCON_7;
154 __sbit __at (0x8E)    TCON_6;
155 __sbit __at (0x8D)    TCON_5;
156 __sbit __at (0x8C)    TCON_4;
157 __sbit __at (0x8B)    TCON_3;
158 __sbit __at (0x8A)    TCON_2;
159 __sbit __at (0x89)    TCON_1;
160 __sbit __at (0x88)    TCON_0;
161 
162 #define  TF1    TCON_7
163 #define  TR1    TCON_6
164 #define  TF0    TCON_5
165 #define  TR0    TCON_4
166 #define  IE1    TCON_3
167 #define  IT1    TCON_2
168 #define  IE0    TCON_1
169 #define  IT0    TCON_0
170 
171 /*  IEN0   */
172 __sbit __at (0xAF)    IEN0_7;
173 __sbit __at (0xAE)    IEN0_6;
174 __sbit __at (0xAD)    IEN0_5;
175 __sbit __at (0xAC)    IEN0_4; // alternatively "ESR"
176 __sbit __at (0xAC)    IEN0_4;
177 __sbit __at (0xAB)    IEN0_3;
178 __sbit __at (0xAA)    IEN0_2;
179 __sbit __at (0xA9)    IEN0_1;
180 __sbit __at (0xA8)    IEN0_0;
181 
182 #define  EA	IEN0_7
183 #define  EWDRT  IEN0_6
184 #define  EBO    IEN0_5
185 #define  ES     IEN0_4  // alternatively "ESR"
186 #define  ESR    IEN0_4
187 #define  ET1    IEN0_3
188 #define  EX1    IEN0_2
189 #define  ET0    IEN0_1
190 #define  EX0    IEN0_0
191 
192 /*  IEN1   */
193 __sbit __at (0xEF)   IEN1_7;
194 __sbit __at (0xEE)   IEN1_6;
195 __sbit __at (0xEC)   IEN1_4;
196 __sbit __at (0xEB)   IEN1_3;
197 __sbit __at (0xEA)   IEN1_2;
198 __sbit __at (0xE9)   IEN1_1;
199 __sbit __at (0xE8)   IEN1_0;
200 
201 #define  EIEE   IEN1_7
202 #define  EST    IEN1_6
203 #define  ECCU   IEN1_4
204 #define  ESPI   IEN1_3
205 #define  EC     IEN1_2
206 #define  EKBI   IEN1_1
207 #define  EI2C   IEN1_0
208 
209 /*  IP0   */
210 __sbit __at (0xBE)    IP0_6;
211 __sbit __at (0xBD)    IP0_5;
212 __sbit __at (0xBC)    IP0_4; // alternatively "PSR"
213 __sbit __at (0xBC)    IP0_4;
214 __sbit __at (0xBB)    IP0_3;
215 __sbit __at (0xBA)    IP0_2;
216 __sbit __at (0xB9)    IP0_1;
217 __sbit __at (0xB8)    IP0_0;
218 
219 #define  PWDRT  IP0_6
220 #define  PB0    IP0_5
221 #define  PS     IP0_4 // alternatively "PSR"
222 #define  PSR    IP0_4
223 #define  PT1    IP0_3
224 #define  PX1    IP0_2
225 #define  PT0    IP0_1
226 #define  PX0    IP0_0
227 
228 /*  SCON  */
229 __sbit __at (0x9F)    SCON_7; // alternatively "FE"
230 __sbit __at (0x9E)    SCON_6;
231 __sbit __at (0x9D)    SCON_5;
232 __sbit __at (0x9C)    SCON_4;
233 __sbit __at (0x9B)    SCON_3;
234 __sbit __at (0x9A)    SCON_2;
235 __sbit __at (0x99)    SCON_1;
236 __sbit __at (0x98)    SCON_0;
237 
238 #define  SM0    SCON_7 // alternatively "FE"
239 #define  FE     SCON_7
240 #define  SM1    SCON_6
241 #define  SM2    SCON_5
242 #define  REN    SCON_4
243 #define  TB8    SCON_3
244 #define  RB8    SCON_2
245 #define  TI     SCON_1
246 #define  RI     SCON_0
247 
248 /*  I2CON  */
249 __sbit __at (0xDE)    I2CON_6;
250 __sbit __at (0xDD)    I2CON_5;
251 __sbit __at (0xDC)    I2CON_4;
252 __sbit __at (0xDB)    I2CON_3;
253 __sbit __at (0xDA)    I2CON_2;
254 __sbit __at (0xD8)    I2CON_0;
255 
256 #define  I2EN   I2CON_6;
257 #define  STA    I2CON_5;
258 #define  STO    I2CON_4;
259 #define  SI     I2CON_3;
260 #define  AA     I2CON_2;
261 #define  CRSEL  I2CON_0;
262 
263 /*  P0  */
264 __sbit __at (0x87)    P0_7;
265 __sbit __at (0x86)    P0_6; // alternatively "CMP1"
266 __sbit __at (0x85)    P0_5;
267 __sbit __at (0x84)    P0_4;
268 __sbit __at (0x83)    P0_3;
269 __sbit __at (0x82)    P0_2;
270 __sbit __at (0x81)    P0_1;
271 __sbit __at (0x80)    P0_0; // alternatively "CMP2"
272 
273 #define  KB7    P0_7  // alternatively "T1"
274 #define  T1     P0_7
275 #define  KB6    P0_6  // alternatively "CMP_1"
276 #define  CMP_1  P0_6
277 #define  KB5    P0_5
278 #define  KB4    P0_4
279 #define  KB3    P0_3
280 #define  KB2    P0_2
281 #define  KB1    P0_1
282 #define  KB0    P0_0  // alternatively "CMP_2"
283 #define  CMP_2  P0_0
284 
285 /*  P1  */
286 __sbit __at (0x97)    P1_7;
287 __sbit __at (0x96)    P1_6;
288 __sbit __at (0x95)    P1_5;
289 __sbit __at (0x94)    P1_4;
290 __sbit __at (0x93)    P1_3;
291 __sbit __at (0x92)    P1_2;
292 __sbit __at (0x91)    P1_1;
293 __sbit __at (0x90)    P1_0;
294 
295 #define  OCC    P1_7
296 #define  OCB    P1_6
297 #define  RST    P1_5
298 #define  INT1   P1_4
299 #define  INT0   P1_3 // alternatively "SDA"
300 #define  SDA    P1_3
301 #define  T0     P1_2 // alternatively "SCL"
302 #define  SCL    P1_2
303 #define  RxD    P1_1
304 #define  TxD    P1_0
305 
306 /*  P2  */
307 __sbit __at (0xA7)    P2_7;
308 __sbit __at (0xA6)    P2_6;
309 __sbit __at (0xA5)    P2_5;
310 __sbit __at (0xA4)    P2_4;
311 __sbit __at (0xA3)    P2_3;
312 __sbit __at (0xA2)    P2_2;
313 __sbit __at (0xA1)    P2_1;
314 __sbit __at (0xA0)    P2_0;
315 
316 #define  ICA    P2_7
317 #define  OCA    P2_6
318 #define  SPICLK P2_5
319 #define  SS     P2_4
320 #define  MISO   P2_3
321 #define  MOSI   P2_2
322 #define  OCD    P2_1
323 #define  ICB    P2_0
324 
325 /*  P3  */
326 __sbit __at (0xB1)    P3_1;
327 __sbit __at (0xB0)    P3_0;
328 
329 #define  XTAL1  P3_1
330 #define  XTAL2  P3_0
331 
332 /* TCR20 */
333 __sbit __at (0xCF)    TCR20_7;
334 __sbit __at (0xCE)    TCR20_6;
335 __sbit __at (0xCD)    TCR20_5;
336 __sbit __at (0xCC)    TCR20_4;
337 __sbit __at (0xCB)    TCR20_3;
338 __sbit __at (0xCA)    TCR20_2;
339 __sbit __at (0xC9)    TCR20_1;
340 __sbit __at (0xC8)    TCR20_0;
341 
342 #define  PLLEN  TCR20_7
343 #define  HLTRN  TCR20_6
344 #define  HLTEN  TCR20_5
345 #define  ALTCD  TCR20_4
346 #define  ALTAB  TCR20_3
347 #define  TDIR2  TCR20_2
348 #define  TMOD21 TCR20_1
349 #define  TMOD20 TCR20_0
350 
351 #endif
352