1 /*------------------------------------------------------------------------- 2 at89c51ed2.h: Register Declarations for the Atmel AT89C51RD2/ED2 Processor 3 4 Copyright (C) 2005, Jesus Calvino-Fraga / jesusc at ece.ubc.ca 5 6 This library is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the 8 Free Software Foundation; either version 2, or (at your option) any 9 later version. 10 11 This library is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this library; see the file COPYING. If not, write to the 18 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19 MA 02110-1301, USA. 20 21 As a special exception, if you link this library with other files, 22 some of which are compiled with SDCC, to produce an executable, 23 this library does not by itself cause the resulting executable to 24 be covered by the GNU General Public License. This exception does 25 not however invalidate any other reasons why the executable file 26 might be covered by the GNU General Public License. 27 -------------------------------------------------------------------------*/ 28 29 #ifndef REG_AT89C51ED2_H 30 #define REG_AT89C51ED2_H 31 32 #include <8052.h> // Load definitions for the 8052 33 34 #ifdef REG8052_H 35 #undef REG8052_H 36 #endif 37 38 // Define AT89C51RD2/ED2 specific registers only 39 40 __sfr __at (0x8E) AUXR; //Auxiliary function register 41 #define DPU 0x80 //'1'=Disables weak pull-up 42 #define M0 0x20 //'1'=Strechs MOVX control signals 43 #define XRS2 0x10 // XRAM select bit 2 44 #define XRS1 0x08 // XRAM select bit 1 45 #define XRS0 0x04 // XRAM select bit 0 46 // XRS2 XRS1 XRS2 XRAM Size 47 // 0 0 0 256 bytes 48 // 0 0 1 512 bytes 49 // 0 1 0 768 bytes (default) 50 // 0 1 1 1024 bytes 51 // 1 0 0 1792 bytes 52 #define EXTRAM 0x02 //'0'=uses internal XRAM. 53 #define AO 0x01 //'1'=Disables ALE generation. 54 55 __sfr __at (0xA2) AUXR1; //Auxiliary function register 1 56 #define ENBOOT 0x20 //'0'=Disables boot ROM 57 #define GF3 0x08 //General purpose user-defined flag. 58 #define DPS 0x01 //Data pointer select. 59 60 __sfr __at (0x97) CKRL; //Clock Reload Register 61 __sfr __at (0x8F) CKCON0; //Clock control Register 0 62 #define WDTX2 0x40 //Watch Dog Clock speed '1'=12 ck/cy, '0'=6 ck/cy 63 #define PCAX2 0x20 //Programmable Counter Array Clock speed '1'=12 ck/cy, '0'=6 ck/cy 64 #define SIX2 0x10 //Enhanced UART Clock (Mode 0 and 2) speed '1'=12 ck/cy, '0'=6 ck/cy 65 #define T2X2 0x08 //Timer2 Clock speed '1'=12 ck/cy, '0'=6 ck/cy 66 #define T1X2 0x04 //Timer1 Clock speed '1'=12 ck/cy, '0'=6 ck/cy 67 #define T0X2 0x02 //Timer0 Clock speed '1'=12 ck/cy, '0'=6 ck/cy 68 #define X2 0x01 //CPU Clock '0'=12 ck/cy, '1'=6 ck/cy 69 __sfr __at (0xAF) CKCON1; //Clock control Register 1 70 #define XPIX2 0x01 //SPI Clock speed '1'=12 ck/cy, '0'=6 ck/cy 71 72 __sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH. 73 __sfr __at (0xFB) CCAP1H; //Module 1 Capture HIGH. 74 __sfr __at (0xFC) CCAP2H; //Module 2 Capture HIGH. 75 __sfr __at (0xFD) CCAP3H; //Module 3 Capture HIGH. 76 __sfr __at (0xFE) CCAP4H; //Module 4 Capture HIGH. 77 __sfr __at (0xEA) CCAP0L; //Module 0 Capture LOW. 78 __sfr __at (0xEB) CCAP1L; //Module 1 Capture LOW. 79 __sfr __at (0xEC) CCAP2L; //Module 2 Capture LOW. 80 __sfr __at (0xED) CCAP3L; //Module 3 Capture LOW. 81 __sfr __at (0xEE) CCAP4L; //Module 4 Capture LOW. 82 83 __sfr __at (0xDA) CCAPM0; //Module 0 Mode. 84 __sfr __at (0xDB) CCAPM1; //Module 1 Mode. 85 __sfr __at (0xDC) CCAPM2; //Module 2 Mode. 86 __sfr __at (0xDD) CCAPM3; //Module 3 Mode. 87 __sfr __at (0xDE) CCAPM4; //Module 4 Mode. 88 //The preceding five registers have the following bits: 89 #define ECOM 0x40 //Enable Comparator. 90 #define CAPP 0x20 //1=enables positive edge capture. 91 #define CAPN 0x10 //1=enables negative edge capture. 92 #define MAT 0x08 //When counter matches sets CCF_n bit causing and interrupt. 93 #define TOG 0x04 //Toggle output on match. 94 #define PWM 0x02 //Pulse width modulation mode. 95 #define ECCF 0x01 //Enable CCF interrupt. 96 97 __sfr __at (0xD8) CCON; //PCA Counter Control 98 __sbit __at (0xDF) CF; //PCA Counter overflow flag. 99 __sbit __at (0xDE) CR ; //PCA Counter Run Control Bit. 1=counter on. 0=counter off. 100 __sbit __at (0xDC) CCF4;//PCA Module 4 Interrupt Flag. 101 __sbit __at (0xDB) CCF3;//PCA Module 3 Interrupt Flag. 102 __sbit __at (0xDA) CCF2;//PCA Module 2 Interrupt Flag. 103 __sbit __at (0xD9) CCF1;//PCA Module 1 Interrupt Flag. 104 __sbit __at (0xD8) CCF0;//PCA Module 0 Interrupt Flag. 105 106 __sfr __at (0xF9) CH; //PCA Counter HIGH. 107 __sfr __at (0xE9) CL; //PCA Counter LOW. 108 109 __sfr __at (0xD9) CMOD; //PCA Counter Mode. 110 #define CIDL 0x80 //CIDL=0 program the PCA counter to work during idle mode. 111 #define WDTE 0x40 //Watchdog Timer Enable. 112 #define CPS1 0x04 //PCA Count Pulse Select bit 1. 113 #define CPS0 0x02 //PCA Count Pulse Select bit 0. 114 //00=Internal clock, Fosc/6 115 //01=Internal clock, Fosc/6 116 //10=Timer 0 overflow 117 //11=External clock at ECI/P1.2 pin (max rate=Fosc/4) 118 #define ECF 0x01 //PCA Enable Counter Overflow Interrupt. 119 120 //Attention IEN0 is the same as register IE found in <8051.h> only bit EC added here. 121 __sfr __at (0xA8) IEN0; //Interrupt Enable 1. 122 __sbit __at (0xAE) EC; //PCA Interrupt Enable bit. 123 124 __sfr __at (0xB1) IEN1; //Interrupt Enable 1 125 #define ESPI 0x04 //SPA Interrupt Enable bit. 126 #define KBD 0x01 //Keyboard Interrupt Enable bit. 127 128 //Attention IPL0 is the same as register IP found in <8051.h> 129 __sfr __at (0xB8) IPL0; //Interrupt Priority 0 LOW 130 __sbit __at (0xBE) PPCL;//PCA Interrupt Priority low bit. 131 __sbit __at (0xBD) PT2L;//Timer 2 Interrupt Priority Low Bit. 132 __sbit __at (0xBC) PSL; //Serial Port Interrupt Priority Low Bit. 133 __sbit __at (0xBB) PT1L;//Timer 1 Interrupt Priority Low Bit. 134 __sbit __at (0xBA) PX1L;//External Interrupt 1 Priority Low Bit. 135 __sbit __at (0xB9) PT0L;//Timer 0 Interrupt Priority Low Bit. 136 __sbit __at (0xB8) PX0L;//External Interrupt 0 Priority Low Bit. 137 138 __sfr __at (0xB7) IPH0; //Interrupt Priority 0 HIGH 139 #define PPCH 0x40 //PCA Interrupt Priority High Bit. 140 #define PT2H 0x20 //Timer 2 Interrupt Priority High Bit. 141 #define PSH 0x10 //Serial Port Interrupt Priority High Bit. 142 #define PT1H 0x08 //Timer 1 Interrupt Priority High Bit. 143 #define PX1H 0x04 //External Interrupt 1 Priority High Bit. 144 #define PT0H 0x02 //Timer 0 Interrupt Priority High Bit. 145 #define PX0H 0x01 //External Interrupt 0 Priority High Bit. 146 147 __sfr __at (0xB2) IPL1; //Interrupt Priority 1 LOW. 148 #define SPIL 0x04 //SPI Priority Low Bit 149 #define KBDL 0x01 //Keyboard Priority Low Bit 150 151 __sfr __at (0xB3) IPH1; //Interrupt Priority 1 HIGH. 152 #define SPIH 0x04 //SPI Priority High Bit 153 #define KBDH 0x01 //Keyboard Priority High Bit 154 155 __sfr __at (0xC0) P4; //8-bit port 4 156 __sbit __at (0xC0) P4_0 ; 157 __sbit __at (0xC1) P4_1 ; 158 __sbit __at (0xC2) P4_2 ; 159 __sbit __at (0xC3) P4_3 ; 160 __sbit __at (0xC4) P4_4 ; 161 __sbit __at (0xC5) P4_5 ; 162 __sbit __at (0xC6) P4_6 ; 163 __sbit __at (0xC7) P4_7 ; 164 165 // S. Qu 12/30/2008 4:23PM 166 __sfr __at (0xE8) P5; //8-bit port 5 167 __sbit __at (0xE8) P5_0 ; 168 __sbit __at (0xE9) P5_1 ; 169 __sbit __at (0xEA) P5_2 ; 170 __sbit __at (0xEB) P5_3 ; 171 __sbit __at (0xEC) P5_4 ; 172 __sbit __at (0xED) P5_5 ; 173 __sbit __at (0xEE) P5_6 ; 174 __sbit __at (0xEF) P5_7 ; 175 176 __sfr __at (0xA6) WDTRST; //WatchDog Timer Reset 177 __sfr __at (0xA7) WDTPRG; //WatchDog Timer Program 178 #define WTO2 0x04 //WDT Time-out select bit 2 179 #define WTO1 0x02 //WDT Time-out select bit 1 180 #define WTO0 0x01 //WDT Time-out select bit 0 181 //This names appear also in the datasheet: 182 #define S2 0x04 //WDT Time-out select bit 2 183 #define S1 0x02 //WDT Time-out select bit 1 184 #define S0 0x01 //WDT Time-out select bit 0 185 //S2 S1 S0 Selected Time-out 186 //0 0 0 (2^14 - 1) machine cycles, 16.3 ms @ FOSCA=12 MHz 187 //0 0 1 (2^15 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz 188 //0 1 0 (2^16 - 1) machine cycles, 65.5 ms @ FOSCA=12 MHz 189 //0 1 1 (2^17 - 1) machine cycles, 131 ms @ FOSCA=12 MHz 190 //1 0 0 (2^18 - 1) machine cycles, 262 ms @ FOSCA=12 MHz 191 //1 0 1 (2^19 - 1) machine cycles, 542 ms @ FOSCA=12 MHz 192 //1 1 0 (2^20 - 1) machine cycles, 1.05 s @ FOSCA=12 MHz 193 //1 1 1 (2^21 - 1) machine cycles, 2.09 s @ FOSCA=12 MHz 194 195 __sfr __at (0xA9) SADDR; //Serial Port Address Register. 196 __sfr __at (0xB9) SADEN; //Serial Port Address Enable. 197 198 __sfr __at (0xC3) SPCON; //SPI Control Register 199 #define SPR2 0x80 //SPI Clork Rate select bit 2. 200 #define SPEN 0x40 //SPI enable bit. When set enables SPI. 201 #define SSDIS 0x20 //Cleared to enable SS in both Master and Slave modes. 202 #define MSTR 0x10 //1=master mode. 0=slave mode. 203 #define CPOL 0x08 //1=SCK is high when idle (active low), 0=SCK is low when idle (active high). 204 #define CPHA 0x04 //1=shift triggered on the trailing edge of SCK. 0=shift trig. on leading edge. 205 #define SPR1 0x02 //SPI Clork Rate select bit 1. 206 #define SPR0 0x01 //SPI Clork Rate select bit 0. 207 //SPR2 SPR1 SPR0 Baud Rate Divisor 208 // 0 0 0 2 209 // 0 0 1 4 210 // 0 1 0 8 211 // 0 1 1 16 212 // 1 0 0 32 213 // 1 0 1 64 214 // 1 1 0 128 215 // 1 1 1 Invalid: Don't Use 216 217 __sfr __at (0xC4) SPSTA; //Serial Peripheral Status register 218 #define SPIF 0x80 //Serial Peripheral Data Transfer Flag 219 #define WCOL 0x40 //Write collision Flag. 220 #define SSERR 0x20 //Synchronous Serial Slave Error Flag 221 #define MODF 0x10 //Mode Fault Flag 222 223 __sfr __at (0xC5) SPDAT; //SPI Data 224 225 __sfr __at (0xC9) T2MOD; //Timer 2 mode control 226 #define T2OE 0x02 //Timer 2 Output Enable bit. 227 #define DCEN 0x01 //Down count enable 228 229 __sfr __at (0x9B) BDRCON; //Baud Rate Control 230 #define BRR 0x10 //Baud Rate Run Control bit. '1'=enable 231 #define TBCK 0x08 //Transmission Baud rate Generator Selection bit for UART 232 #define RBCK 0x04 //Reception Baud Rate Generator Selection bit for UART 233 #define SPD 0x02 //Baud Rate Speed Control bit for UART 234 #define SRC 0x01 //Baud Rate Source select bit in Mode 0 for UART 235 236 __sfr __at (0x9A) BRL; //Baud Rate Reload 237 238 __sfr __at (0x9C) KBLS; //Keyboard level Selector 239 __sfr __at (0x9D) KBE; //Keyboard Input Enable 240 __sfr __at (0x9E) KBF; //Keyboard Flag Register 241 242 __sfr __at (0xD2) EECON; //EEPROM Data Control 243 #define EEE 0x02 //EEPROM Enable. '1'=use EEPROM, '0'=use XRAM 244 #define EEBUSY 0x01 //EEPROM Busy. '1'=EEPROM is busy programming 245 246 // PCON bit definitions 247 #define SMOD1 0x80 248 #define SMOD0 0x40 249 #define POF 0x10 250 251 /* Interrupt numbers: address = (number * 8) + 3 */ 252 #define TF2_VECTOR 5 /* 0x2b timer 2 */ 253 #define PCA_VECTOR 6 /* 0x33 Programmable Counter Array */ 254 #define KBD_VECTOR 7 /* 0x3b Keyboard Interface */ 255 #define SPI_VECTOR 9 /* 0x4b Serial Port Interface */ 256 257 #endif /*REG_AT89C51ED2_H*/ 258